Semiconductor device with modified access and associated methods and systems

Abstract

The present application relates to a semiconductor device with modified access and associated methods and systems. A memory device, a system including a memory device, and a method of operating a memory device are described, wherein a host device can access a group of memory cells (e.g., a portion of an array that can be configured to store ECC parity bits), the group of memory cells originally reserved for the ECC function of the memory device. The memory device may include a register for indicating whether its ECC function is enabled or disabled. When the register indicates that the ECC function is disabled, the memory device can increase the storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device can store metadata associated with various operational aspects of the memory device in the group of memory cells.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to a semiconductor device with modified access and associated methods and systems. Background Art

[0002] Memory devices are widely used to store information related to various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Memory devices are usually provided in the form of internal semiconductor integrated circuits in computers or other electronic devices and / or external removable devices. There are many different types of memory, including volatile memory and non-volatile memory. Volatile memory including random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM) requires the application of power to maintain its data. In contrast, non-volatile memory can retain its stored data even without the use of external power. Non-volatile memory can be used in a variety of technologies, including flash memory (e.g., NAND and NOR), phase change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM) and magnetic random access memory (MRAM). Improving memory devices can generally include increasing memory cell density, increasing read / write speed or otherwise reducing operation latency, increasing reliability, increasing data retention, reducing power consumption or reducing manufacturing costs, and other metrics. Summary of the invention

[0003] In one aspect, the present application relates to a method comprising: receiving signaling at a mode register of a memory device indicating whether an error correction code (ECC) mode of the memory device is enabled or disabled; selecting a burst length for data transmission from the memory device to a host device based at least in part on whether the mode register indicates that the ECC mode is enabled or disabled; and transmitting data having the selected burst length from the memory device to the host device.

[0004] On the other hand, the present application relates to an apparatus, comprising: a register configured to indicate whether an error checking and correction (ECC) function is enabled or disabled; a memory array, the memory array comprising a plurality of memory cells, the plurality of memory cells comprising a first subset and a second subset, the first subset being configured to store first user-accessible data, the second subset being configured to: store second user-accessible data, metadata associated with the apparatus, or both when the register indicates that the ECC function is disabled, and store ECC data when the register indicates that the ECC function is enabled; and a circuit system, the circuit system being configured to: communicate with a host device for a first burst length when the register indicates that the ECC function is enabled, the first burst length being used to transmit the first user-accessible data in the first subset, and communicate with the host device for a second burst length when the register indicates that the ECC function is disabled, the second burst length being used to transmit the first user-accessible data in the first subset and the second user-accessible data or the metadata in the second subset.

[0005] On the other hand, the present application relates to a method, comprising: transmitting signaling to a mode register of a memory device indicating whether an error correction code (ECC) mode of the memory device is enabled or disabled; transmitting a read command to the memory device; and receiving data in response to the read command, wherein a burst length of the data is at least partially based on whether the ECC mode is enabled or disabled, as indicated by the mode register. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a block diagram schematically illustrating a memory device according to an embodiment of the present technology.

[0007] Figure 2 is a block diagram schematically illustrating a memory device according to an embodiment of the present technology.

[0008] Figure 3 is a flow chart showing a general overview of a method of operating a memory device according to an embodiment of the present technology.

[0009] Figure 4 is a block diagram schematically illustrating a memory system according to an embodiment of the present technology.

[0010] Figure 5 and 6 is a flowchart illustrating a method of operating a memory device according to an embodiment of the present technology. DETAILED DESCRIPTION

[0011] A memory device may include an error checking and correction (ECC) function for providing reliable data, for example, an on-die ECC function. Arithmetic, program, or circuitry that performs the ECC function may be referred to as or include aspects of an error-correcting code (which may also be referred to as an error-correction code). Such a memory device may include an ECC circuit and a group of memory cells (e.g., a portion of a memory array configured to store ECC parity bits, an ECC array) that supports the on-die ECC function. In some embodiments, the group of memory cells may be reserved to internally store (e.g., inaccessible to a user) ECC data, and the specified storage capacity of the memory device may not include the ECC array capacity. In some instances, the ECC array capacity may occupy a significant portion of the memory array of the memory device, for example, approximately 6% of the total memory array space. Some memory systems may include a host device that is coupled to a memory device that includes an on-die ECC function, and the host device (or memory system) may perform the ECC function of the host device itself without relying on the on-die ECC function. Thus, the set of memory cells reserved to support on-die ECC functionality may be employed to provide additional features that may otherwise be available - for example, additional storage capacity beyond the specified storage capacity indicated as available to a user of the memory device.

[0012] Several embodiments of the present technology relate to a memory device, a system including a memory device, and a method of operating a memory device, wherein when an ECC function is disabled, for example, by a host device, the host device can access a set of memory cells reserved for the ECC function in the memory device. In one embodiment, the memory device includes a register for indicating whether the ECC function is enabled or disabled. When the ECC function is disabled, the memory device can configure the set of memory cells to store user data, metadata, or both. Therefore, the memory device can increase the storage capacity available to the host device, for example, by increasing the bit output by approximately 6%.

[0013] Metadata in a memory device may refer to various data associated with other data (e.g., data transmitted or received) or operational aspects of the memory device (e.g., operating temperature, latency settings, data transmission parameters). In some embodiments, the memory device may store the metadata in one or more registers that are accessed by an output circuit of the memory device. In some embodiments, the memory device may store the metadata in a memory array (including the set of memory cells reserved for the ECC function when the ECC function is disabled). After the memory device stores the metadata in the memory array, the metadata may be considered part of the user data for future access. In this way, the memory device may output the metadata (when stored in the memory array) without utilizing a separate command (e.g., a mode register read (MRR) command for reading metadata stored in one or more registers) as part of an access command (e.g., a read command).

[0014] In addition, when the register indicates that the on-die ECC function is disabled, the memory device can modify the burst length to accommodate additional information to be stored in the group of memory cells (e.g., additional user data) or additional information to be read from the group of memory cells (e.g., additional user data or metadata). For example, when the register indicates that the on-die ECC function is enabled, the memory device can use a first burst length (e.g., BL32, which corresponds to sixteen (16) clock cycles under a double data rate (DDR) scheme). However, when the register indicates that the on-die ECC function is disabled, the memory device can use a second burst length (e.g., BL34, which corresponds to seventeen (17) clock cycles under a DDR scheme) to combine additional data (e.g., user data or metadata associated with the group of memory cells that were originally reserved for the ECC function) amount.

[0015] refer to Figure 1 A memory device supporting embodiments of the present invention is described. Figure 2 A more detailed description of the memory device is provided. Figure 3 Various operational aspects of memory devices according to embodiments of the present technology are further presented. Figure 4 A memory system supporting embodiments of the present invention is described. Figure 5 and 6 A flow chart illustrating a method of operating a memory device is described.

[0016] Figure 11 is a block diagram schematically illustrating a memory device 100 according to an embodiment of the present technology. The memory device 100 may include an array of memory cells, such as a memory array 150. The memory array 150 may include a plurality of groups (e.g., Figure 1 1-15 in the example of ), and each group may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells (e.g., m×n memory cells) arranged at the intersection of the word lines (e.g., m word lines, which may also be referred to as rows) and the bit lines (e.g., n bit lines, which may also be referred to as columns). The memory cells may include any of a plurality of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, etc. In some embodiments, a portion of the memory array 150 (e.g., an ECC plane) may be configured to store ECC parity bits. That is, the memory array 150 may include a first subset of memory cells and a second subset of memory cells (e.g., ECC parity bits), the first subset being configured to store user accessible data, and the second subset being configured to store different kinds of data—e.g., storing ECC data when the ECC function is enabled and storing non-ECC data when the ECC function is disabled. The selection of the word line WL may be performed by a row decoder 140, and the selection of the bit line BL may be performed by a column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit line BL, and the sense amplifier may be connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) through a transmission gate (TG) that may act as a switch. The memory array 150 may also include plate lines and corresponding circuitry for managing the operation of the plate lines.

[0017] In some embodiments, the memory array 150 includes a memory array including a group of memory cells. The group of memory cells may include a first subset of memory cells, the first subset being configured to store user accessible data (e.g., data from a host device). In addition, the group of memory cells may include a second subset of memory cells, the second subset being reserved to store ECC data to support the ECC function of the memory device 100. Therefore, when the ECC function is enabled, the host device may not directly access the second subset of memory cells. However, when the ECC function is disabled, the memory device 100 may configure the second subset of memory cells to store additional user accessible data (e.g., allowing access from the host device), metadata associated with the memory device 100, or both. In some embodiments, the memory device 100 may configure the second subset of memory cells to store additional user accessible data (e.g., the entire memory array 150 is configured to store user accessible data) and store the metadata elsewhere—e.g., one or more registers of the memory device 100. Further, the memory device 100 may include a register (eg, a mode register) configured to indicate whether the ECC function is enabled or disabled.

[0018] The memory device 100 may employ a plurality of external terminals, including a command terminal and an address terminal coupled to a command bus and an address bus to receive a command signal CMD and an address signal ADDR, respectively. The memory device may further include a chip select terminal for receiving a chip select signal CS; a clock terminal for receiving clock signals CK and CKF; a data clock terminal for receiving data clock signals WCK and WCKF; data terminals DQ, RDQS, DBI (for data bus inversion function) and DMI (for data mask inversion function); power supply terminals VDD, VSS, VDDQ and VSSQ.

[0019] The address signal and the group address signal may be supplied to the command terminal and the address terminal from the outside. The address signal and the group address signal supplied to the address terminal may be transmitted to the address decoder 110 through the command / address input circuit 105. The address decoder 110 may receive the address signal and supply the decoded row address signal (XADD) to the row decoder 140 and supply the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive the group address portion of the ADDR input and supply the decoded group address signal (BADD) to both the row decoder 140 and the column decoder 145.

[0020] A command signal CMD, an address signal ADDR, and a chip select signal CS may be supplied from a memory controller to the command terminal and the address terminal. The command signal may represent various memory commands (e.g., including access commands, which may include read commands and write commands) from the memory controller. The chip select signal CS may be used to select the memory device 100 to respond to commands and addresses provided to the command terminal and the address terminal. When an activation CS signal is provided to the memory device 100, the commands and addresses may be decoded and memory operations may be performed. The command signal CMD may be provided to the command decoder 115 in the form of an internal command signal ICMD through the command / address input circuit 105. The command decoder 115 may include a circuit for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as a row command signal for selecting a word line and a column command signal for selecting a bit line. The internal command signal may also include an output activation command and an input activation command, such as a timing command CMDCK ( Figure 1 not shown).

[0021] In some embodiments, the command decoder 115 may further include one or more registers 118 for tracking various counts or values ​​(e.g., counts of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100). In some embodiments, a subset of the registers 118 may be referred to as mode registers and configured to store user-defined variables to provide flexibility in executing various functions, features, and modes (e.g., ECC modes). For example, the memory device 100 may receive signaling from a host device at a mode register that indicates whether the ECC mode of the memory device is enabled or disabled—e.g., indicating whether the ECC function of the memory device 100 is enabled or disabled. Based on the indication stored at the mode register, the memory device 100 may access the ECC parity bits of the memory array 150 and perform various operations—e.g., perform ECC functions using the ECC parity bits, store / retrieve user-accessible data or metadata at / from the ECC parity bits.

[0022] When a read command is issued to a group with an open row and a column address is supplied in time as part of a read designation, read data can be read from a memory cell in the memory array 150 specified by the row address (which may have been provided in the form of a part of an activation command identifying an open row) and the column address. The read command can be received by a command decoder 115, which can provide an internal command to the input / output circuit 160 so that the read data can be output from the data terminals DQ, RDQS, DBI, and DMI through the read / write amplifier 155 and the input / output circuit 160 according to the RDQS clock signal. The read data can be provided at a time defined by read latency information RL that can be programmed in the memory device 100, such as in a mode register (e.g., register 118). The read latency information RL can be defined according to a clock cycle of a CK clock signal. For example, when the associated read data is provided, the read latency information RL can be a plurality of clock cycles of the CK signal after the read command is received by the memory device 100.

[0023] When a write command is issued to a group with an open row and a column address is supplied in time as part of the write command, write data can be supplied to data terminals DQ, DBI and DMI according to WCK and WCKF clock signals. The write command can be received by a command decoder 115, which can provide an internal command to the input / output circuit 160 so that the write data can be received by a data receiver in the input / output circuit 160 and supplied to the memory array 150 through the input / output circuit 160 and the read / write amplifier 155. The write data can be written in a memory cell specified by the row address and the column address. The write data can be provided to the data terminal at a time defined by the write wait time WL information. The write wait time WL information can be programmed in the memory device 100, such as in a mode register (e.g., register 118). The write delay WL information can be defined according to the clock cycle of the CK clock signal. For example, when the associated write data is received, the write wait time information WL can be a plurality of clock cycles of the CK signal after the write command is received by the memory device 100.

[0024] Under the DDR scheme, a data burst with a burst length of 2N (e.g., eight (8), sixteen (16), thirty-two (32)) includes 2N bits of data transmitted to each output pin (e.g., each data terminal DQ) of the memory device during N (e.g., four (4), eight (8), sixteen (16)) clock cycles. In some embodiments, the input / output circuit 160 can be configured to communicate with the host device (e.g., transmit or receive data through the data terminal DQ) for a first burst length when a register (e.g., a mode register) indicates that the ECC function is enabled. For example, the first burst length can be thirty-two (32), which corresponds to sixteen (16) clock cycles (e.g., WCK and WCKF clock cycles) under the DDR scheme. The first burst length can be determined to transmit (e.g., transmit or receive) user-accessible data in a first subset of memory cells within the data burst. In some embodiments, when the ECC function is enabled, the input / output circuit 160 may output metadata (e.g., metadata stored on one or more registers) during one or more additional data bursts (i.e., one or more data bursts outside the first burst length).

[0025] In addition, the input / output circuit 160 can be configured to communicate with the host device for a second burst length when a register (e.g., a mode register) indicates that the ECC function is disabled. For example, the first burst length can be thirty-four (34), which corresponds to seventeen (17) clock cycles under the DDR scheme. The second burst length can be determined to transmit user accessible data in the first subset of memory cells and additional user accessible data or metadata in the second subset of memory cells within the data burst. In some embodiments, the metadata can be stored elsewhere (e.g., register 180 accessed by the input / output circuit 160) and not stored in the second subset of memory cells (or the first subset of memory cells). In some embodiments, the second burst length (e.g., a longer data burst) can be longer than the first burst length (e.g., a shorter data burst) by more than one (1) clock cycle - for example, two (2) clock cycles longer, three (3) clock cycles longer, or even more.

[0026] In some embodiments, the memory device 100 may receive signaling at a register 118 (e.g., a mode register) indicating whether an ECC mode (e.g., an ECC function) of the memory device 100 is enabled or disabled. The memory device 100 may select a burst length for data transmission to the host device based on whether the mode register indicates that the ECC mode is enabled or disabled in response to receiving the signaling. Subsequently, the memory device 100 may transmit data having the selected burst length to the host device. In some embodiments, the memory device 100 may determine that the ECC mode is disabled and select a burst length from a first burst length and a second burst length, wherein the second burst length contains more bits than the first burst length. The memory device 100 may transmit data having the selected burst length (e.g., the second burst length).

[0027] The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in a sense amplifier included in the memory array 150, and the internal potential VPERI may be used in many other circuit blocks.

[0028] A power supply potential VDDQ may also be supplied to the power supply terminal. The power supply potential VDDQ may be supplied to the input / output circuit 160 together with the power supply potential VSS. In an embodiment of the present technology, the potential of the power supply potential VDDQ may be the same as the potential of the power supply potential VDD. In another embodiment of the present technology, the potential of the power supply potential VDDQ may be different from the potential of the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 does not propagate to other circuit blocks.

[0029] An external clock signal and a complementary external clock signal can be supplied to the clock terminal and the data clock terminal. The external clock signals CK, CKF, WCK, and WCKF can be supplied to the clock input circuit 120. The CK signal and the CKF signal can be complementary, and the WCK signal and the WCKF signal can also be complementary. The complementary clock signals can have opposite clock levels and transition between opposite clock levels at the same time. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal changes from a low clock level to a high clock level, the complementary clock signal changes from a high clock level to a low clock level, and when the clock signal changes from a high clock level to a low clock level, the complementary clock signal changes from a low clock level to a high clock level.

[0030] The input buffer included in the clock input circuit 120 can receive an external clock signal. For example, when enabled by the CKE signal from the command decoder 115, the input buffer can receive the CK signal and the CKF signal and the WCK signal and the WCKF signal. The clock input circuit 120 can receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to the internal clock circuit 130. The internal clock circuit 130 can provide various phase and frequency controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from the command decoder 115. For example, the internal clock circuit 130 can include a clock path ( Figure 1 100 and 100. The clock path of the memory device 100 may be a clock path (not shown) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 160 and may be used as a timing signal for determining the output timing of read data and the input timing of write data. The IO clock signal may be provided at multiple clock frequencies so that data may be output from and input to the memory device 100 at different data rates. When high memory speeds are desired, higher clock frequencies may be desirable. When lower power consumption is desired, lower clock frequencies may be desirable. The internal clock signal ICLK may also be supplied to the timing generator 135, and various internal clock signals may be generated accordingly.

[0031] The memory device 100 can be connected to any electronic device or component thereof among a plurality of electronic devices capable of using the memory for temporary or permanent storage of information. For example, the host device of the memory device 100 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player) or a component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device can be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio and / or video, a vehicle, an appliance, a toy, or any of a variety of other products. In one embodiment, the host device can be directly connected to the memory device 100, but in other embodiments, the host device can be indirectly connected to the memory device (e.g., via a networking connection or via an intermediate device).

[0032] Figure 2 2 is a block diagram schematically illustrating a memory device 200 according to an embodiment of the present technology. The memory device 200 may be a reference Figure 1 The memory device 100 described herein may include various aspects of a memory device. The memory device 200 may include a peripheral circuit 270, a register 275, an ECC circuit 280, and a memory array 250. The peripheral circuit 270 may include a reference Figure 1 For example, the peripheral circuit 270 may include aspects of the command / address input circuit 105, the address decoder 110, the command decoder 115, and the input / output circuit 160. In addition, the memory array 250 may be a reference Figure 1 Examples of memory array 150 are described or may include aspects of a memory array.

[0033] Register 275 (which may also be referred to as a mode register) may be configured to indicate whether an ECC function (e.g., an on-die ECC function) of memory device 200 is enabled or disabled. In some embodiments, a host device coupled to memory device 200 may perform an ECC function without relying on the on-die ECC function of memory device 200. In such cases, register 275 may indicate that the on-die ECC function is disabled (e.g., by the host device) so that memory device 200 may modify certain operational aspects to provide additional features to the host device.

[0034] The memory array 250 may include a group of memory cells, the group of memory cells including a first subset 260 and a second subset 265. The first subset 260 may be configured to store first user accessible data - for example, data from a host device. In some embodiments, the first subset 260 may occupy a major portion of the storage capacity of the memory array 250 - for example, greater than 90% of the storage capacity. The first subset 260 may represent a portion of the memory array 250 that can be accessed by the host device, regardless of whether the on-die ECC function is enabled or disabled. In some embodiments, the second subset 265 may be configured to store ECC data supporting the on-die ECC function of the memory device 200 when the ECC function is enabled - therefore, the second subset 265 may also be referred to as ECC parity bits or parity planes. The second subset 265 may occupy a relatively small but significant portion of the storage capacity of the memory array 250 - for example, approximately 5% to 10% of the storage capacity. In some embodiments, the second subset 265 may not be accessible by the host device when the ECC function is enabled. In other embodiments, the second subset 265 may be accessible by a host device when the ECC function is enabled, so that the host device may access the ECC data.

[0035] However, when the ECC function is disabled, the second subset 265 can be configured to store second user-accessible data (e.g., data from the host device), metadata associated with the memory device 200, or both. When the second subset 265 is configured to store the second user-accessible data, the memory device 200 can provide the host device with increased storage capacity, for example, nearly 100% of the entire storage capacity (i.e., the entire storage capacity corresponds to the first subset 260 and the second subset 265). That is, in addition to the storage capacity corresponding to the first subset 260 (which can be referred to as the designated storage capacity of the memory device), the memory device 200 can provide the host device with additional storage capacity (i.e., the storage capacity corresponding to the second subset 265). In addition, the first subset 260 and the second subset 265 can provide the first user-accessible data and the second user-accessible data that are not corrected by the ECC function of the memory device 200. Such uncorrected user-accessible data can provide the host device with an opportunity to optimize and / or modify its ECC routine in the event that the error characteristics and / or features change.

[0036] Additionally or alternatively, the second subset 265 may be configured to store metadata including information related to an operating mode of the memory device 200, such as an operating temperature, a wait time setting associated with an access command, parameters for data transfer, a test mode, or a combination thereof. In this manner, the memory device 200 may provide metadata as part of an access operation (e.g., a read command directed to the first subset 260) without having to invoke a command (e.g., an MRR command) for retrieving metadata that may otherwise be stored in various registers (e.g., a mode register) of the memory device 200. Such commands to retrieve metadata from registers may introduce undesirable delays to the memory device 200 because the commands may place the memory device 200 in a particular mode (e.g., a "status" mode) that results in the memory array 250 being in a certain state (e.g., an "idle" state). As a result, the use of such commands may be limited, and the visibility of the metadata to a host device may also be limited.

[0037] In some embodiments, the second subset 265 can be organized to be physically adjacent to (or very close to) the first subset 260, so that certain components of the memory device 200 that support the first subset 260 and the second subset 265 (e.g., row decoder 140, column decoder 145, read / write amplifier 155, sense amplifier (SAMP)) can be shared or efficiently laid out. In other embodiments, the second subset 265 can be organized to be separate from the first subset 260, so that the first subset 260 and the second subset 265 can operate relatively independently of each other-for example, the first subset and the second subset have separate power domains, separate routing for control and / or data paths.

[0038] When the ECC function is enabled, the ECC circuit 280 provides the ECC function for the memory device 200. The ECC circuit can be coupled to the second subset 265 and perform the ECC function on the first user accessible data stored in the first subset 260 using the ECC data stored in the second subset 265. In some embodiments, the ECC circuit 280 can be configured to detect two or more errors in the first user accessible data and / or correct one or more errors in the first user accessible data. For example, the ECC circuit 280 can detect two errors in the first user accessible data and correct one error in the first user accessible data. In some embodiments, the ECC circuit 280 can be configured to indicate that the first user accessible data contains an amount of errors that is greater than its detection and correction capabilities.

[0039] The peripheral circuit 270 may be configured to communicate with the host device for a first burst length (e.g., BL32) when the register 275 indicates that the ECC function is enabled, wherein the first burst length is used to transmit the first user-accessible data in the first subset 260. Additionally, the peripheral circuit 270 may be configured to communicate with the host device for a second burst length (e.g., BL34, BL36, BL38, BL40) when the register 275 indicates that the ECC function is disabled, wherein the second burst length is used to transmit the first user-accessible data in the first subset 260 and the second user-accessible data or metadata in the second subset 265. In some embodiments, the peripheral circuit 270 may include a logic circuit (e.g., a first logic circuit) coupled to the memory array 250 (and thus to the first subset 260 and the second subset 265). The first logic circuit may be configured to combine the first user-accessible data with the second user-accessible data or metadata for transmission to the host device when the register 275 indicates that the ECC function is disabled.

[0040] In some embodiments, when the ECC function is enabled, the memory device 200 (e.g., the peripheral circuit 270) can be configured to provide the ECC data stored at the second subset 265 (e.g., ECC data associated with the user-accessible data stored at the first subset 260) to the host device. In such embodiments, the burst length can be modified (e.g., increased from BL32 to BL34) when the memory device 200 transmits the user-accessible data stored at the first subset 260 and the ECC data stored at the second subset 265. In other embodiments, when the ECC function is disabled, the memory device 200 (e.g., the peripheral circuit 270) can be configured to communicate with the host device (e.g., retrieve and transmit the user-accessible data stored at the first subset 260, retrieve and store the user-accessible data at the first subset 260) without modifying the burst length - for example, using a single burst length (e.g., BL32) to transmit (or receive) user-accessible data to (from) the host device, regardless of whether the ECC function is enabled or disabled. In such embodiments, the user accessible data may not be corrected by the ECC functionality of the memory device 200 .

[0041] In some embodiments, an access command (e.g., a read command, a write command) may be directed to the first subset 260 or both the first subset 260 and the second subset 265. In such embodiments, the memory device (e.g., the peripheral circuit 270) may operate based on whether the ECC function is enabled or disabled and / or whether the access command is directed to the first subset 260 or both the first subset 260 and the second subset 265. For example, when the ECC function is enabled and when the access command is directed to the first subset 260, the memory device 200 may communicate with the host device for a first burst length (e.g., BL32) corresponding to the first user-accessible data at the first subset 260. In another example, when the ECC function is enabled and when the access command is directed to both the first subset 260 and the second subset 265, the memory device 200 may communicate with the host device for a second burst length (e.g., BL34), the second burst length corresponding to the first user-accessible data at the first subset 260 and the ECC data at the second subset 265.

[0042] In yet another example, when the ECC function is disabled and when the access command is directed to both the first subset 260 and the second subset 265, the memory device 200 can communicate with the host device for a second burst length (e.g., BL34), the second burst length corresponding to the first user-accessible data at the first subset 260 and the second user-accessible data or metadata at the second subset 265. In yet another example, when the ECC function is disabled and when the access command is directed to the first subset 260, the memory device 200 can communicate with the host device for a first burst length (e.g., BL32) corresponding to the first user-accessible data in the first subset 260. In some embodiments, the memory device 200 can include an additional register 276 ( Figure 2 ), the additional register is configured to indicate whether an access command (e.g., a read command, a write command) is directed to the first subset 260 or both the first subset 260 and the second subset 265. In such embodiments, the memory device 200 (e.g., the peripheral circuit 270) can operate based on the register 275 (e.g., indicating whether the ECC function is enabled or disabled) and the additional register 276 (e.g., indicating whether the access command is directed to the first subset 260 or both the first subset 260 and the second subset 265).

[0043] Although a memory array having a first subset occupying more than 90% of the storage capacity of the memory device and a second subset occupying less than 10% of the storage capacity of the memory device has been described and illustrated in the foregoing example embodiments, in other embodiments, a memory array having a different capacity allocation may be provided to the memory device. For example, a first subset having less than 90% of the storage capacity (e.g., 75%, 66%, or even 50% or less) may be provided.

[0044] Figure 3 3 is a flowchart 300 showing a general overview of a method of operating a memory device according to an embodiment of the present technology. Flowchart 300 may be an example of a method that may be performed by memory device 200 (or peripheral circuit 270 of memory device 200) or include aspects of the method. Such a memory device (e.g., memory device 100 or 200) may include a memory array (e.g., memory array 150 or 250) having a set of memory cells, wherein the set of memory cells includes a first subset (e.g., first subset 260) configured to store first user-accessible data and a second subset (e.g., second subset 265) configured to store ECC data. Further, the memory device may maintain a register (e.g., register 275) configured to indicate whether the ECC function is enabled or disabled.

[0045] In some cases, at step 305, the memory device (e.g., peripheral circuit 270 of memory device 200) may determine that the ECC function is enabled based on checking registers (e.g., register 275). Subsequently, at step 310, the memory device may activate the ECC circuit (e.g., ECC circuit 280).

[0046] At step 315, the memory device may retrieve the first user-accessible data from the first subset upon receiving a read command from the host device. As described above, the memory device may, for example, have performed an ECC function using the ECC circuit 280 based on the ECC data stored in the second subset 265. In some embodiments, the memory device may detect at least one error in the first user-accessible data stored in the first subset using the ECC data stored in the second subset 265. Further, the memory device may correct the at least one error in the first user-accessible data before outputting the first user-accessible data to the host device. In this manner, one or more errors in the first user-accessible data may have been corrected before transmitting the first user-accessible data to the host device. At step 320, the memory device may communicate with the host device (e.g., transmit the first user-accessible data to the host device) for a first burst length (e.g., BL32).

[0047] Alternatively, at step 325, when the ECC function is enabled, the memory device may receive the first user accessible data from the host device for the first burst length upon receiving a write command from the host device. Subsequently, the memory device may generate ECC data (e.g., ECC parity bits) associated with the first user accessible data. At step 330, the memory device may store the first user accessible data in the first subset and store the ECC data associated with the first user accessible data in the second subset.

[0048] In other cases, referring to step 305, the memory device (e.g., peripheral circuit 270 of memory device 200) can determine that the ECC function is disabled based on checking registers (e.g., register 275). Subsequently, at step 340, the memory device can bypass the ECC circuit (e.g., ECC circuit 280).

[0049] At step 345, the memory device may retrieve the first user accessible data in the first subset and the second user accessible data or metadata in the second subset upon receiving a read command from the host device, wherein the second subset may be further configured to store the second user accessible data, metadata, or both when the ECC function is disabled. In some embodiments, the memory device may simultaneously access the first subset and the second subset of the set of memory cells when the ECC function is disabled. In some embodiments, the memory device may combine the first user accessible data with the second user accessible data or metadata for transmission to the host device.

[0050] In some embodiments, the memory device may determine a second burst length during which the memory device transmits first user accessible data and second user accessible data or metadata. The memory device may determine a second burst length (e.g., BL34) based on the amount of second user accessible data or the amount of metadata, wherein the second burst length is greater than the first burst length. Further, the memory device may determine the second burst length by incrementing the first burst length by an even number of bursts. For example, the memory device may determine BL34 from BL32 by incrementing two bursts corresponding to one clock cycle under the DDR scheme. In other instances, the memory device may determine BL36 from BL32 (by incrementing four bursts corresponding to two clock cycles), BL38 (by incrementing six bursts corresponding to three clock cycles), or BL40 (by incrementing eight bursts corresponding to four clock cycles).

[0051] At step 350, the memory device may communicate (e.g., transmit) the first user accessible data and the second user accessible data or metadata to the host device for a second burst length (e.g., BL34). Alternatively, at step 355, the memory device may receive the first user accessible data and the second user accessible data from the host device for the second burst length upon receiving a write command from the host device. Subsequently, at step 360, the memory device may store the first user accessible data in the first subset and the second user accessible data in the second subset.

[0052] Figure 4 4 is a block diagram of a system 401 having a memory device 400 configured in accordance with an embodiment of the present technology. The memory device 400 may be a reference Figure 1 and 2 1 and 200. Memory devices 400 and 406 are examples of memory devices 100 and 200 described herein or include aspects of the memory devices described herein. As shown, memory device 400 includes main memory 402 (e.g., DRAM, NAND flash, NAND flash, FeRAM, PCM, etc.) and control circuitry 406, which is operably coupled to a host device 408 (e.g., an upstream central processing unit (CPU)). Main memory 402 may be a reference Figure 1 and 2 Examples of memory arrays 150 or 250 described herein or including aspects of the described methods. Further, control circuitry 406 may be referenced Figure 2 Instances of the peripheral circuits 270 described herein or aspects thereof. The main memory 402 includes a plurality of memory cells 420, each of which includes a plurality of memory cells. The memory cells 420 may be separate memory dies, memory planes in a single memory die, memory die stacks vertically connected to through silicon vias (TSVs), and the like. For example, in one embodiment, each memory cell in the memory cells 420 may be formed by a semiconductor die and arranged in a single device package with other memory cell dies. In other embodiments, the plurality of memory cells 420 may be co-located on a single die and / or distributed across a plurality of device packages. In some embodiments, the memory cells 420 may also be subdivided into memory regions 428 (e.g., groups, columns, channels, blocks, pages, etc.).

[0053] The memory cell may include, for example, a floating gate storage element, a charge trapping storage element, a phase change storage element, a capacitive storage element, a ferroelectric storage element, a magnetoresistive storage element, and / or other suitable storage elements configured to store data permanently or semi-permanently. The main memory 402 and / or the separate memory unit 420 may also include other circuit components for accessing and / or programming (e.g., writing) the memory cells and other functions, such as for processing information and / or communicating with the control circuit system 406 or the host device 408, such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, etc. Although shown as having a certain number of memory cells, rows, columns, regions, and memory cells in the illustrated embodiment for illustrative purposes, the number of memory cells, rows, columns, regions, and memory cells may vary, and in other embodiments, the dimensions may be greater or less than the dimensions shown in the illustrated examples. For example, in some embodiments, the memory device 400 may include only one memory cell 420. Alternatively, the memory device 400 may include two, three, four, eight, ten or more (eg, 16, 32, 64 or more) memory cells 420. Figure 4 Memory cells 420 are shown as each including four memory regions 428, but in other embodiments, each memory cell 420 may include one, two, three, eight, or more (e.g., 16, 32, 64, 100, 128, 256, or more) memory regions.

[0054] In one embodiment, control circuitry 406 may be disposed on the same die as main memory 402 (e.g., including command / address / clock input circuitry, decoders, voltage generators and timing generators, input / output circuitry, etc.). In another embodiment, control circuitry 406 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), control circuitry on a memory die, etc.), or other suitable processor. In one embodiment, control circuitry 406 may include a processor configured to execute instructions stored in memory to perform various processes, logic flows, and routines for controlling the operation of memory device 400, including managing main memory 402 and handling communications between memory device 400 and host device 408. In some embodiments, control circuitry 406 may include embedded memory having memory registers for storing, for example, row counters, group counters, memory pointers, fetched data, etc. In another embodiment of the present technology, memory device 400 may not include control circuitry, but may rely on external control (eg, provided by host device 408, or by a processor or controller separate from memory device 400).

[0055] The host device 408 can be any electronic device or component thereof among a plurality of electronic devices that can utilize memory to temporarily or permanently store information. For example, the host device 408 can be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or a component thereof (e.g., a central processing unit, a coprocessor, a dedicated memory controller, etc.). The host device 408 can be a networked device (e.g., a switch, a router, etc.) or a recorder of digital images, audio, and / or video, a vehicle, an appliance, a toy, or any of a variety of other products. In one embodiment, the host device 408 can be directly connected to the memory device 400, but in other embodiments, the host device 408 can be indirectly connected to the memory device (e.g., via a networked connection or via an intermediate device).

[0056] In operation, the control circuit system 406 can directly write or otherwise program (e.g., erase) various memory areas of the main memory 402. The control circuit system 406 communicates with the host device 408 via a host device bus or interface 410. In some embodiments, the host device bus or interface 410 can be configured to carry data bursts with variable burst lengths. For example, the host device bus or interface 410 can carry data bursts with a first burst length (e.g., BL32) or a second burst length (e.g., BL34, BL36, BL38, BL40) based on whether the ECC function of the memory device 400 is enabled (e.g., BL32) or disabled (e.g., BL34, BL36, BL38, BL40). In some embodiments, the host device 408 and the control circuit system 406 can communicate via a dedicated memory bus (e.g., a DRAM bus). In other embodiments, host device 408 and control circuit system 406 may communicate via a serial interface (e.g., a serially attached SCSI (SAS), a serial AT attachment (SATA) interface, a peripheral component interconnect express (PCIe)), or other suitable interface (e.g., a parallel interface). Host device 408 may send various requests (e.g., in the form of packets or packet streams) to control circuit system 406. The requests may include commands for reading, writing, erasing, returning information, and / or commands for performing specific operations (e.g., refresh operations, TRIM operations, precharge operations, activation operations, wear leveling operations, garbage collection operations, etc.).

[0057] In some embodiments, the control circuit system 406 may be configured to track operations (e.g., read operations, write operations, erase operations, activate operations, etc.) performed in the main memory 402 (e.g., in a register or table in an embedded memory of the control circuit system 406) in the plurality of memory cells 420 to facilitate the execution of refresh operations on an as-needed basis. In this regard, the control circuit system 406 may be configured to compare the number or rate of operations experienced by different memory cells 420, and perform or schedule refresh operations on the memory cells 420 based on the comparison between the number or rate of operations experienced by the memory cells 420. Alternatively, the control circuit system 406 may be configured to perform or schedule refresh operations on the memory cells 420 based on a comparison of each memory cell 420 to one or more predetermined thresholds (e.g., a threshold number of operations, a threshold rate of operations, etc.). Therefore, due to the freedom that different cells 420 can experience out-of-order refresh operations, a memory cell 420 that is the target of operations exceeding the threshold number or rate may be refreshed more frequently than another cell 420.

[0058] In some embodiments, the memory device 400 includes a register configured to indicate whether the ECC function is enabled or disabled (e.g., reference Figure 2 275 described). Further, the main memory 402 may include a group of memory cells, wherein the group of memory cells includes a first subset and a second subset. The first subset may be configured to store first user-accessible data. In addition, the second subset may be configured to store ECC data when the register indicates that the ECC function is enabled, and to store second user-accessible data, metadata, or both when the register indicates that the ECC function is disabled. In some embodiments, the host device 408 and the memory device 400 are configured to communicate for a first burst length (e.g., BL32) when the register indicates that the ECC function is enabled, wherein the first burst length is determined for transmitting the first user-accessible data in the first subset. Additionally or alternatively, the host device 408 and the memory device 400 are configured to communicate for a second burst length (e.g., BL34, BL36, BL38, BL40) when the register indicates that the ECC function is disabled, wherein the second burst length is determined for transmitting the first user-accessible data in the first subset and the second user-accessible data or metadata in the second subset.

[0059] In some embodiments, the host device 408 may transmit signaling to a mode register of the memory device 400 indicating whether the ECC mode of the memory device 400 is enabled or disabled. Further, the host device 408 may transmit a read command to the memory device 400. Subsequently, the host device 408 may receive data in response to the read command, wherein the burst length of the data is based on whether the ECC mode is enabled or disabled, as indicated by the mode register.

[0060] In some embodiments, when the ECC function is disabled, the host device 408 can be configured to transmit an access command to the memory device 400, wherein the access command (e.g., a read command, a write command) includes a set of address bits that simultaneously identify a first subset and a second subset of the group of memory cells. Upon receiving a read command from the host device 408, the memory device 400 can bypass an ECC circuit configured to: detect and correct errors in first user-accessible data of the first subset; generate a data set by combining the first user-accessible data with second user-accessible data or metadata; and transmit the data set to the host device according to a second burst length (e.g., BL34).

[0061] In some embodiments, when the ECC function is disabled, the host device 408 can be configured to: receive a first data set from the memory device 400 in a first data burst having a second burst length; determine that the first data set includes a first portion of metadata; receive a second data set from the memory device in a second data burst having a second burst length; determine that the second data set includes a second portion of metadata; and combine the first portion of metadata with the second portion of metadata. In this way, the host device 408 can receive metadata from the memory device 400 through multiple data transfer instances, each of which occurs according to the second burst length. In some embodiments, the host device 408 can be configured to transmit an indication to the memory device 400 whether the ECC function is enabled or disabled, so that the memory device 400 can set a register according to the indication transmitted from the host device.

[0062] In some embodiments, when the ECC function is disabled, the memory device 400 may be configured to receive a data set from the host device with a data burst having a second burst length, wherein the data set includes first user accessible data and second user accessible data, and store the first user accessible data in a first subset and store the second user accessible data in a second subset. In some embodiments, the memory device 400 may be configured to set a register to indicate whether the ECC function is enabled or disabled during an initialization cycle of the memory system 401. In such embodiments, the initialization cycle may include a power-on procedure, and the memory device 400 may include a parameter indicating the ECC function state (e.g., whether the ECC function is enabled or disabled) as a default value of the register.

[0063] Figure 5 5 is a flowchart 500 illustrating a method of operating a memory device according to an embodiment of the present technology. Flowchart 500 may be performed by memory device 200 (or peripheral circuit 270 of memory device 200) as shown in FIG. Figure 2 Such a memory device may include a memory array having a set of memory cells, wherein the set of memory cells includes a first subset and a second subset, the first subset being configured to store first user-accessible data, the second subset being configured to: store ECC data when an ECC mode of the memory device is enabled; and store second user-accessible data or metadata or both when the ECC mode of the memory device is disabled.

[0064] The method includes receiving signaling at a mode register of a memory device indicating whether an ECC mode of the memory device is enabled or disabled (block 510). According to one aspect of the present technology, the receiving feature of block 510 can be provided by a peripheral circuit (e.g., Figure 2 Peripheral circuits 270) or control circuit systems (e.g., Figure 4 control circuit system 406) in combination with address / command input circuitry (e.g., Figure 1 The address / command input circuit 105) is executed.

[0065] The method includes selecting a burst length for data transmission from a memory device to a host device based on whether a mode register indicates that an ECC mode is enabled or disabled (block 520). According to one aspect of the present technology, the selection feature of block 520 can be implemented by a peripheral circuit (e.g., Figure 2 Peripheral circuits 270) or control circuit systems (e.g., Figure 4 The control circuit system 406) is executed.

[0066] The method includes transferring data having a selected burst length from the memory device to the host device (block 530). According to one aspect of the present technology, the transfer feature of block 530 can be implemented by a peripheral circuit (e.g., Figure 2 Peripheral circuits 270) or control circuit systems (e.g., Figure 4 The control circuit system 406) combines the input / output circuit (e.g., Figure 1 Input / output circuit 160) is executed.

[0067] The method may further include determining that an ECC mode of the memory device is disabled, wherein the burst length is selected from a first burst length and a second burst length, the second burst length having more bits than the first burst length; and transmitting data having the second burst length from the memory device to the host device (block 540). According to one aspect of the present technology, the determination characteristics and transmission characteristics of block 540 may be determined by a peripheral circuit (e.g., Figure 2 Peripheral circuits 270) or control circuit systems (e.g., Figure 4 The control circuit system 406) combines the input / output circuit (e.g., Figure 1 Input / output circuit 160) is executed.

[0068] In some embodiments, one or more bits of the transmission having the second burst length include metadata about information about the transmitted data or the memory device, or both. In some embodiments, each bit of the transmission having the second burst length includes data. In some embodiments, the first burst length includes thirty-two (32) bits and the second burst length includes thirty-four (34) bits.

[0069] The method may further include: determining that an ECC mode of the memory device is enabled; detecting at least one error in first user-accessible data in the first subset using ECC data in the second subset; and correcting the at least one error in the first user-accessible data before outputting the first user-accessible data to the host device. The method may further include simultaneously accessing the first subset and the second subset of the set of memory cells when the ECC function is disabled.

[0070] In some embodiments, the method may further include bypassing an ECC circuit configured to perform an ECC function on the first user accessible data using the ECC data stored in the second subset, wherein transmitting the data having the selected burst length to the host device corresponds to transmitting the first user accessible data and the second user accessible data or metadata to the host device. In some embodiments, the method may further include determining a second burst length based on an amount of the second user accessible data or an amount of metadata, wherein the second burst length is greater than the first burst length, and transmitting the data having the selected burst length to the host device corresponds to transmitting the first user accessible data and the second user accessible data or metadata to the host device. In some embodiments, determining the second burst length further includes incrementing the first burst length by an even number of bursts.

[0071] In some embodiments, the method may further include combining the first user accessible data with the second user accessible data or metadata for transmission to a host device, wherein transmitting the data having the selected burst length to the host device corresponds to transmitting the first user accessible data and the second user accessible data or metadata to the host device. In some embodiments, the method may further include: receiving third user accessible data having the selected burst length from the host device, the third user accessible data including the first user accessible data and the second user accessible data; storing the first user accessible data in the first subset; and storing the second user accessible data in the second subset.

[0072] Figure 6 600 is a flowchart illustrating a method of operating a system according to an embodiment of the present technology. Flowchart 600 may be a host device (e.g., reference Figure 2 Host device described, reference Figure 4 The host device 408 described in the reference Figure 2 and 4 The described method or aspects comprising the described method.

[0073] The method includes transmitting signaling to a mode register of a memory device indicating whether an ECC mode of the memory device is enabled or disabled (block 610). According to one aspect of the present technology, the transmission feature of block 610 can be transmitted by a host device (e.g., Figure 4 Executed by host device 408).

[0074] The method includes transmitting a read command to the memory device (block 620). According to one aspect of the present technology, the transmission feature of block 620 can be transmitted by a host device (e.g., Figure 4 Executed by host device 408).

[0075] The method includes receiving data in response to a read command, wherein a burst length of the data is based on whether the ECC mode is enabled or disabled, as indicated by a mode register (block 630). According to one aspect of the present technology, the receiving feature of block 630 can be provided by a host device (e.g., Figure 4 Executed by host device 408).

[0076] It should be noted that the methods described above describe possible implementations, and operations and steps may be rearranged or otherwise modified, and other implementations are possible. In addition, embodiments of two or more of the methods described may be combined.

[0077] The information and signals described herein may be represented using any of a variety of different processes and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some of the figures may show a signal as a single signal; however, one of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have various bit widths.

[0078] The devices including memory devices discussed herein may be formed on a semiconductor substrate or die such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of a substrate or a sub-region of a substrate may be controlled by doping with various chemicals, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0079] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features implementing the functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations.

[0080] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, so that, for example, at least one of a list A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0081] In light of the above, it should be understood that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. On the contrary, in the foregoing description, many specific details are discussed to provide a thorough and enabling description of embodiments of the present invention. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the present invention. Generally, it should be understood that in addition to those specific embodiments disclosed herein, various other devices, systems, and methods may also be within the scope of the present invention.

Claims

1. A method for memory operation, comprising: receiving signaling at a mode register of a memory device indicating whether an error correction code (ECC) mode of the memory device is enabled or disabled; selecting a burst length for data transfer from the memory device to a host device based at least in part on whether the mode register indicates that the ECC mode is enabled or disabled; as well as Data having a selected burst length is transferred from the memory device to the host device.

2. The method according to claim 1, further comprising: determining that the ECC mode of the memory device is disabled, wherein the burst length is selected from a first burst length and a second burst length, the second burst length having more bits than the first burst length; and Data having the second burst length is transferred from the memory device to the host device.

3. The method of claim 2, wherein one or more bits of a transmission having the second burst length include metadata of information about the transmitted data or the memory device or both. The method of claim 2 , wherein each bit of a transmission having the second burst length comprises data.

5. The method of claim 2, wherein the first burst length comprises thirty-two bits and the second burst length comprises thirty-four bits.

6. The method of claim 1 , wherein the memory device comprises a memory array including a plurality of memory cells, the plurality of memory cells having a first subset and a second subset, the first subset being configured to store first user-accessible data, the second subset being configured to: (1) store ECC data when the ECC mode of the memory device is enabled; and (2) storing second user-accessible data or metadata or both while the ECC mode of the memory device is disabled, and wherein the method further comprises: determining that the ECC mode of the memory device is enabled; detecting at least one error in the first user accessible data in the first subset using the ECC data in the second subset; and The at least one error in the first user-accessible data is corrected prior to outputting the first user-accessible data to the host device.

7. The method according to claim 6, further comprising: The first subset and the second subset of the plurality of memory cells are accessed concurrently while the ECC mode is disabled.

8. The method of claim 6, wherein transmitting the data having the selected burst length to the host device corresponds to transmitting the first user-accessible data and the second user-accessible data or metadata to the host device, and wherein the method further comprises: An ECC circuit is bypassed, the ECC circuit being configured to perform an ECC function on the first user-accessible data using the ECC data stored in the second subset.

9. The method of claim 6, wherein transmitting the data having the selected burst length to the host device corresponds to transmitting the first user-accessible data and the second user-accessible data or metadata to the host device, and wherein the method further comprises: A second burst length is determined based on an amount of the second user-accessible data or an amount of the metadata, wherein the second burst length is greater than the first burst length.

10. The method of claim 9, wherein determining the second burst length further comprises incrementing the first burst length by an even number of bursts.

11. The method of claim 6, wherein transmitting the data having the selected burst length to the host device corresponds to transmitting the first user-accessible data and the second user-accessible data or metadata to the host device, and wherein the method further comprises: The first user-accessible data is combined with the second user-accessible data or metadata for transmission to the host device.

12. The method according to claim 6, further comprising: receiving third user-accessible data having the selected burst length from the host device, the third user-accessible data comprising the first user-accessible data and the second user-accessible data; storing the first user-accessible data in the first subset; as well as The second user-accessible data is stored in the second subset.

13. A memory system comprising: a register configured to indicate whether an error checking and correction (ECC) function is enabled or disabled; a memory array comprising a plurality of memory cells, the plurality of memory cells comprising a first subset and a second subset, the first subset being configured to store first user-accessible data, the second subset being configured to: store second user-accessible data, metadata associated with the memory system, or both when the register indicates that the ECC function is disabled; and store ECC data when the register indicates that the ECC function is enabled; as well as A circuit system, the circuit system being configured to: communicating with a host device for a first burst length when the register indicates that the ECC function is enabled, the first burst length being used to transmit the first user-accessible data in the first subset, and Communicating with the host device for a second burst length for transmitting the first user-accessible data in the first subset and the second user-accessible data in the second subset or the metadata when the register indicates that the ECC function is disabled.

14. The memory system of claim 13, further comprising: An ECC circuit is coupled to the second subset and configured to perform the ECC function on the first user accessible data in the first subset using the ECC data in the second subset when the register indicates that the ECC function is enabled.

15. The memory system of claim 14, wherein the ECC circuit is configured to detect two or more errors in the first user accessible data and / or to correct one or more errors in the first user accessible data.

16. The memory system of claim 13, further comprising: A first logic circuit is coupled to the plurality of memory cells, the first logic circuit being configured to combine the first user accessible data with the second user accessible data or metadata when the register indicates that the ECC function is disabled.

17. The memory system of claim 13, wherein the first burst length is smaller than the second burst length.

18. The memory system of claim 13, wherein the metadata comprises information related to an operating mode of the memory system, the information including operating temperature, latency settings associated with access commands, parameters for data transfers, test patterns, or a combination thereof.

19. The memory system of claim 13, further comprising: A second register configured to indicate whether an access command is directed to the first subset or both the first subset and the second subset.

20. A method for memory operation, comprising: transmitting signaling to a mode register of a memory device indicating whether an error correction code (ECC) mode of the memory device is enabled or disabled; transmitting a read command to the memory device; as well as Data is received in response to the read command, wherein a burst length of the data is based at least in part on whether the ECC mode is enabled or disabled, as indicated by the mode register.

Images