Method of guiding a semiconductor manufacturing process and electronic device

Abstract

A method of guiding a semiconductor manufacturing process includes receiving semiconductor manufacturing process data corresponding to a target semiconductor product; generating first semiconductor property data corresponding to the semiconductor manufacturing process data by using a technology computer-aided design (TCAD) model trained by machine learning based on training data including TCAD simulation data; generating second semiconductor property data corresponding to the semiconductor manufacturing process data by using a compact model generated based on measurement information of at least one semiconductor property of a first semiconductor product; generating a plurality of process strategies respectively corresponding to a plurality of countermeasure references by using a plurality of countermeasure models based on the first semiconductor property data and the second semiconductor property data; and providing a final process strategy corresponding to the target semiconductor product based on the plurality of process strategies.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0105286, filed on August 27, 2019, and Korean Patent Application No. 10-2020-0051830, filed on April 28, 2020, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entireties by reference. TECHNICAL FIELD

[0003] Example embodiments of the present inventive concept relate to a method and an electronic device for guiding a semiconductor manufacturing process, and more particularly, to a method and an electronic device for providing a process recipe for a semiconductor product according to a user input and based on a technology computer aided design (TCAD) model and a compact model. BACKGROUND

[0004] As the electronic industry develops, a semiconductor foundry industry in which manufacturers produce semiconductor products designed by other companies is becoming more important. In the foundry industry, the manufacturers can check the performance of the semiconductor products through simulation before actually manufacturing the semiconductor products according to the design. In this case, when the design of the semiconductor product needs to be changed (for example, by a request from a customer of the manufacturer) during the simulation, it can take a lot of time to re-perform the simulation based on the changed design, and thus, additional costs and time loss can be incurred. Also, the customer of the manufacturer can request data about the simulation from the manufacturer. In this case, the manufacturing proprietary knowledge of the manufacturer can be released without a mask. SUMMARY

[0005] One or more example embodiments of the present inventive concept provide a method and an electronic device for providing a process recipe (for example, an optimal process recipe) based on technology computer aided design (TCAD) based simulation data reflecting semiconductor characteristics of an existing semiconductor product and compact model based data, and for enhancing security of manufacturing proprietary knowledge by assigning different permission levels for each user information item.

[0006] According to an aspect of the inventive concept, there is provided a method of guiding a semiconductor manufacturing process, the method including: receiving semiconductor manufacturing process data corresponding to a target semiconductor product; generating first semiconductor property data corresponding to the semiconductor manufacturing process data by using a technology computer aided design (TCAD) model trained based on training data including TCAD simulation data through machine learning; generating second semiconductor property data corresponding to the semiconductor manufacturing process data by using a compact model generated based on measured information of at least one semiconductor property of a first semiconductor product; generating a plurality of process strategies respectively corresponding to a plurality of countermeasure references by using a plurality of countermeasure models based on the first semiconductor property data and the second semiconductor property data; and providing a final process strategy corresponding to the target semiconductor product based on the plurality of process strategies.

[0007] According to another aspect of the inventive concept, there is provided an electronic device for guiding a semiconductor manufacturing process. The electronic device includes a display; at least one non-transitory computer readable medium; and at least one processor configured to execute instructions stored in the at least one non-transitory computer readable medium, wherein the at least one processor is further configured to: receive semiconductor manufacturing process data corresponding to a target semiconductor device; generate first semiconductor property data corresponding to the semiconductor manufacturing process data by using a technology computer aided design (TCAD) model trained based on training data including information of a plurality of semiconductor properties through machine learning; generate second semiconductor property data corresponding to the semiconductor manufacturing process data by using a compact model generated based on measured information of at least one semiconductor property of a first semiconductor device; and generate a plurality of process strategies corresponding to a plurality of countermeasure references by using a plurality of countermeasure models based on the first semiconductor property data and the second semiconductor property data, and control the display to display at least one of the plurality of process strategies as a process strategy corresponding to the target semiconductor device.

[0008] According to another aspect of the inventive concept, there is provided an electronic system for guiding a semiconductor manufacturing process. The electronic system includes a communication unit, a display, a processor configured to: receive semiconductor manufacturing process data corresponding to a target semiconductor device; output first semiconductor property data corresponding to the semiconductor manufacturing process data by using a technology computer aided design (TCAD) model trained based on training data including TCAD simulation data through machine learning; output second semiconductor property data corresponding to the semiconductor manufacturing process data by using a compact model generated based on measured information of at least one semiconductor property of a first semiconductor device; generate a plurality of process recipes based on the first semiconductor property data and the second semiconductor property data; and a management device configured to receive user information from the processor and transmit information on a level of authority corresponding to the user information to the processor, wherein the processor is further configured to control the display to display at least a portion of the plurality of process recipes based on the information on the level of authority. BRIEF DESCRIPTION OF DRAWINGS

[0009] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of an electronic device according to an example embodiment;

[0011] Figure 2 is a flowchart of a method of guiding a semiconductor manufacturing process according to an example embodiment;

[0012] Figure 3 is a block diagram of an electronic device according to an example embodiment;

[0013] Figure 4 is a block diagram for describing a technology computer aided design (TCAD) model according to an example embodiment;

[0014] Figure 5 is a table for describing semiconductor manufacturing process data according to an example embodiment;

[0015] Figure 6 is a table for describing output settings according to an example embodiment;

[0016] Figure 7 is a block diagram of an electronic device according to an example embodiment;

[0017] Figure 8 is a block diagram for describing a compact model according to an example embodiment;

[0018] Figure 9 is a block diagram for describing a compact sub-model according to an example embodiment;

[0019] Figure 10 is a block diagram for describing an operation of comparing first semiconductor characteristic data with second semiconductor characteristic data according to an example embodiment;

[0020] Figure 11 is a flowchart of a comparison operation according to an example embodiment;

[0021] Figure 12 is a block diagram for describing a method of generating a plurality of process strategies and a final process strategy according to an example embodiment;

[0022] Figure 13 is a diagram of a graphical user interface according to an example embodiment; and

[0023] Figure 14 is a block diagram of an electronic system according to an example embodiment. DETAILED DESCRIPTION

[0024] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 is a block diagram of an electronic device according to an example embodiment.

[0026] Referring to Figure 1 , the electronic device 1 can include an input unit 11, a storage 12, a processor 13, a display 14, and a communication unit 15. The electronic device 1 can provide a process strategy of a target semiconductor product to be manufactured based on various information related to the target semiconductor product. For example, the electronic device 1 can acquire information on desired semiconductor characteristics (e.g., electrical characteristics and / or structural characteristics) by performing simulation based on information related to the target semiconductor product, and provide a process strategy of the target semiconductor product based on the acquired information on the characteristics. The process strategy can include various information related to a manufacturing process of a semiconductor product, such as a design structure, an applied voltage, and a type of ion implantation.

[0027] The input unit 11 can receive semiconductor manufacturing process data used in simulation of a target semiconductor product from a user. The user can input semiconductor manufacturing process data corresponding to the target semiconductor product to the electronic device 1 through the input unit 11.

[0028] The semiconductor manufacturing process data can include information on at least one selected from a kind of a semiconductor product, a semiconductor manufacturing process, a semiconductor device, and a version of a semiconductor product. The semiconductor manufacturing process data can further include information on at least one semiconductor layout (or structure) and ion implantation corresponding to the semiconductor product, process, device, and / or version of a semiconductor product. The information on ion implantation can include a kind of dopant and a concentration of dopant. The semiconductor manufacturing process data is not limited to those described above, and can additionally include various information.

[0029] In an embodiment, the input unit 11 can receive information on at least one selected from a kind, a process, a device, and a version of a semiconductor product corresponding to a target semiconductor product and information on at least one selected from a semiconductor layout and ion implantation from a user. For example, the input unit 11 can receive a first semiconductor product corresponding to the target semiconductor product and a first semiconductor layout corresponding to the first semiconductor product from a user.

[0030] In an embodiment, the input unit 11 can receive information on at least one selected from a semiconductor layout and ion implantation corresponding to a target semiconductor product from a user as semiconductor manufacturing process data. For example, the input unit 11 can receive only second semiconductor ion implantation information corresponding to a second semiconductor device from a user, the second semiconductor device corresponding to the target semiconductor product. The semiconductor manufacturing process data received by the input unit 11 can be provided to the processor 13. The semiconductor manufacturing process data received by the input unit 11 is not limited to the above-described example.

[0031] The input unit 11 can further receive electrical and / or structural characteristics of a target semiconductor product from a user as output settings. The output settings can be setting information indicating that the user selects at least one of the electrical and / or structural characteristics of the target semiconductor product desired by the user as a simulation result of the target semiconductor product. For example, information that the user can select through the output settings can include at least one selected from a threshold voltage, a gain, a linearity, a breakdown voltage, an oxide degradation, a junction and / or tunneling leakage current, a capacitance-voltage (C-V) curve, a current-voltage (I-V) curve, a drain current-gate voltage (Id-Vg) curve, a drain voltage-drain current (Vd-Id) curve, a distribution image of a semiconductor product (e.g., a potential distribution, a doping distribution, or an electrostatic field distribution), and a field image of a semiconductor product.

[0032] For example, the input unit 11 can include one or more hardware interfaces such as a keyboard, a mouse, and a touch panel, and one or more software interfaces such as a graphical user interface and a text-based interface. In another example, the input unit 11 can include a general-purpose interface configured to receive semiconductor manufacturing process data and output settings from an internal or external device of the electronic device 1. Examples of the general-purpose interface can include a Peripheral Component Interconnect Express (PCIe) interface, a Remote Direct Memory Access (RDMA) interface over Ethernet, a Serial Advanced Technology Attachment (SATA) interface, a Fibre Channel interface, a Non-Volatile Memory Express (NVMe) interface, an Ethernet interface, and a Universal Serial Bus (USB) interface.

[0033] The storage 12 can include at least one non-transitory computer readable medium. In an embodiment, the storage 12 can additionally include at least one transitory computer readable medium.

[0034] The processor 13 can execute computer program commands and interact with other system elements to perform various functions described herein. The electronic device 1 can include at least one processor 13. Hereinafter, according to some embodiments, the operation of the electronic device 1 can be implemented as instructions stored in a non-transitory computer readable medium, and the instructions can be executed by the processor 13.

[0035] The storage 12 can store a technology computer aided design (TCAD) model trained based on training data through machine learning. The TCAD model can perform simulation using semiconductor manufacturing process data as input data and output information on electrical and / or structural characteristics of a target semiconductor product as a simulation result. The TCAD model can be implemented in a mathematical expression according to mathematical and physical theories. The TCAD model can be trained through machine learning using TCAD simulation results as training data. The TCAD model can be pre-trained and stored in the storage 12, but the processor 13 can train the TCAD model through machine learning.

[0036] The processor 13 can acquire information on electrical and / or structural characteristics of a target semiconductor product corresponding to semiconductor manufacturing process data based on the TCAD model stored in the storage 12. In an embodiment, the processor 13 can input semiconductor manufacturing process data received from the input unit 11 into the TCAD model, and acquire electrical and / or structural characteristics of a target semiconductor product from the TCAD model. Hereinafter, for convenience of description, information on electrical and / or structural characteristics of a target semiconductor product acquired through the TCAD model is referred to as first semiconductor characteristic data.

[0037] In an embodiment, the TCAD model can generate first semiconductor characteristic data including electrical and / or structural characteristics corresponding to the output setting input through the input unit 11. For example, when a user inputs a breakdown voltage as the output setting to the input unit 11, the TCAD model can generate first semiconductor characteristic data including information on the breakdown voltage as a simulation result.

[0038] The storage 12 can store a compact model. Like the TCAD model, the compact model can perform a simulation using semiconductor manufacturing process data as input data and output information on electrical and / or structural characteristics of a target semiconductor product as a simulation result. Unlike the TCAD model, the compact model can reflect real measurement information of electrical and / or structural characteristics of a semiconductor product. In detail, the compact model can reflect measurement information obtained by measuring electrical and / or structural characteristics of an actual semiconductor product manufactured by semiconductor manufacturing equipment using semiconductor measurement equipment. The processor 13 can generate or update the compact model based on measurement information obtained by measuring electrical and / or structural characteristics of an actual semiconductor product.

[0039] The processor 13 can acquire information on electrical and / or structural characteristics of a target semiconductor product corresponding to semiconductor manufacturing process data based on the compact model stored in the storage 12. In an embodiment, the processor 13 can input semiconductor manufacturing process data received from the input unit 11 into the compact model and acquire electrical and / or structural characteristics of a target semiconductor product from the compact model. Hereinafter, for convenience of description, information on electrical and / or structural characteristics of a target semiconductor product acquired through the compact model will be referred to as second semiconductor characteristic data.

[0040] In an embodiment, the compact model can generate second semiconductor characteristic data including electrical and / or structural characteristics corresponding to the output setting input through the input unit 11. For example, when a user inputs a breakdown voltage as the output setting to the input unit 11, the compact model can generate second semiconductor characteristic data including information on the breakdown voltage as a simulation result.

[0041] Because the compact model reflects electrical and / or structural characteristics of an actual semiconductor product that has been manufactured, a conservative simulation result can be generated. In another example, the compact model can be an empirical data model including a small amount of data. On the other hand, the TCAD model does not include a result of measuring electrical and / or structural characteristics of a semiconductor product, and thus can be considered a basic data model. Because the TCAD model is trained using a large amount of training data, the TCAD model can be a basic data model including a large amount of data.

[0042] The processor 13 can generate at least one process strategy using the first semiconductor characteristic data and the second semiconductor characteristic data. In detail, the processor 13 can generate at least one process strategy from the first semiconductor characteristic data and the second semiconductor characteristic data using a decision model configured to generate a process strategy based on information about electrical and / or structural characteristics of a semiconductor product. The decision model can generate a process strategy according to a counter-reference for generating a process strategy using information (e.g., the first semiconductor characteristic data and / or the second semiconductor characteristic data) about electrical and / or structural characteristics of a target semiconductor product.

[0043] In an embodiment, when the decision model has a plurality of counter-references, the decision model can generate a plurality of process strategies corresponding to the plurality of counter-references. The counter-reference can include at least one selected from a risk-taking degree, a priority order of electrical and / or structural characteristics, a target range of electrical and / or structural characteristics, and any combination thereof. The counter-reference is not limited to the above description, and can include various items. Hereinafter, a detailed description will be made with reference to Figure 12 A detailed description is made of an operation of generating a plurality of process strategies by using a decision model.

[0044] The processor 13 can determine at least one of the plurality of process strategies as a final process strategy (e.g., as an optimal process strategy) by using the decision model. In an embodiment, the input unit 11 can receive a decision weight for determining a final process strategy from among a plurality of process strategies of a semiconductor product from a user. The decision model can determine at least one of the process strategies as the final process strategy based on the decision weight.

[0045] Here, the decision weight can include a priority order with respect to at least one of a plurality of semiconductor characteristics. The semiconductor characteristic can include an electrical and / or structural characteristic of a semiconductor product. For example, the semiconductor characteristic can include an electrical and / or structural characteristic of the semiconductor product itself. Alternatively, the semiconductor characteristic can include an electrical and / or structural characteristic of at least one element included in the semiconductor product. Hereinafter, a detailed description will be made with reference to Figure 12 A detailed description is made of an operation of determining at least one of a plurality of process strategies as a final process strategy by using a decision model.

[0046] The processor 13 can display the final process strategy through the display 14. Embodiments are not limited thereto. For example, the processor 13 can display all process strategies or a predetermined number of process strategies among all process strategies on the display 14, or can sequentially display all process strategies on the display 14.

[0047] The processor 13 can include a central processing unit (CPU) and / or a graphic processing unit (GPU). At least one selected from the storage 12, the processor 13, and the communication unit 15 can include an application processor (AP).

[0048] The at least one non-transitory computer readable medium of the storage 12 can include a volatile computer readable medium including, for example, but not limited to, a register, a cache, a static random access memory (SRAM), a dynamic RAM (DRAM), etc., which temporarily stores data and is readable by the device. Unlike the non-transitory computer readable medium, the volatile computer readable medium can be included in the processor 13. For example, the arithmetic result of the processor 13 can be stored in the transitory computer readable medium included in the processor 13. However, the embodiments are not limited thereto. Figure 1

[0049] The at least one non-transitory computer readable medium of the storage 12 can include a medium such as a compact disc (CD), a digital versatile disc (DVD), a hard disk, a solid state drive (SSD), a Blu-ray disc, a USB memory, or a read only memory (ROM), which semi-permanently stores data and is readable by the device. The non-volatile computer readable medium can include one or more various non-volatile memory devices. For example, the non-volatile memory device can include at least one selected from a flash memory, a phase change RAM (PRAM), a resistance RAM (ReRAM), and a magnetoresistive RAM (MRAM), but is not limited thereto.

[0050] The computer program commands, the TCAD model, the compact model, and the decision model can be stored in the transitory or non-transitory computer readable medium. In at least some embodiments, values generated by simulation performed by the processor 13 or values obtained from arithmetic processing performed by the processor 13 can be stored in the transitory or non-transitory computer readable medium. In at least some embodiments, intermediate values generated during machine learning can be stored in the transitory or non-transitory computer readable medium. In at least some embodiments, the first semiconductor characteristic data, the second semiconductor characteristic data, and the process recipe, which will be described below, can be stored in the transitory or non-transitory computer readable medium. However, the embodiments are not limited thereto.

[0051] The display 14 can visually output various data to be used for the operation of the electronic device 1. For example, the display 14 can display a setting screen via which one or more inputs of the semiconductor manufacturing process data, the output setting, and the decision weight are received. In another example, the display 14 can display at least one process recipe. The display 14 can include at least one selected from a liquid crystal display (LCD), a light emitting diode (LED) display, an organic LED (OLED) display, and a quantum dot (QD) display, and can include a three-dimensional (3D) display.

[0052] ​The communication unit 15 can transmit data, data models, and process policies generated and / or output by the electronic device 1 to the inside or outside of the electronic device 1, or can receive data and data models to be used for arithmetic processing of the electronic device 1 from an external device. The communication unit 15 can perform communication via various wired and / or wireless communication interfaces.

[0053] Figure 2 is a flowchart of a method of guiding a semiconductor manufacturing process according to an example embodiment. Figure 1 The same reference numerals will be used to refer to the same or similar elements throughout the drawings.

[0054] In operation S210, the electronic device 1 can receive semiconductor manufacturing process data corresponding to a target semiconductor product and output settings for setting electrical and / or structural characteristics of the target semiconductor product.

[0055] In operation S220, the electronic device 1 can output first semiconductor characteristic data corresponding to the semiconductor manufacturing process data using a TCAD model trained through machine learning based on training data including TCAD simulation data. For example, the TCAD model trained through machine learning can be stored in the storage 12, and the processor 13 can input the semiconductor manufacturing process data to the TCAD model and output first semiconductor characteristic data received from the TCAD model, the first semiconductor characteristic data corresponding to electrical and / or structural characteristics of the target semiconductor product.

[0056] The electronic device 1 can generate or update the compact model based on values obtained by actually measuring electrical and / or structural characteristics of a semiconductor product in operation S230, and can output second semiconductor characteristic data corresponding to the semiconductor manufacturing process data using the compact model in operation S240. For example, the compact model can be newly generated or updated in real time based on measurement information obtained by measuring electrical and / or structural characteristics of an actual semiconductor product that has been manufactured by a semiconductor manufacturing equipment using a semiconductor measurement equipment. The processor 13 can input the semiconductor manufacturing process data to the compact model and can output second semiconductor characteristic data received from the compact model, the second semiconductor characteristic data corresponding to electrical and / or structural characteristics of the target semiconductor product.

[0057] In operation S250, the electronic device 1 can output a plurality of process strategies based on the first semiconductor characteristic data and the second semiconductor characteristic data by using a decision model that generates a process strategy based on information about electrical and / or structural characteristics of a semiconductor product. The first semiconductor characteristic data can reflect a result (e.g., a simulation result) of a TCAD model, and the second semiconductor characteristic data can reflect a result of actually measuring a semiconductor product. Thus, the electronic device 1 can output a process strategy by considering both the first semiconductor characteristic data and the second semiconductor characteristic data.

[0058] In operation S260, the electronic device 1 can provide a final process strategy based on the process strategies. For example, the electronic device 1 can provide at least one of the process strategies as the final process strategy, or can determine a priority order of at least some of the process strategies and provide the final process strategy by displaying the process strategies according to the priority order.

[0059] Figure 3 is a block diagram of an electronic device according to an example embodiment; Figure 4 is a block diagram for describing a TCAD model according to an example embodiment; Figure 5 is a table for describing semiconductor manufacturing process data according to an example embodiment; Figure 6 is a table for describing output settings according to an example embodiment. Figure 1 The same reference numerals will be used to refer to the same or similar elements throughout the drawings.

[0060] Referring to Figure 3 , the electronic device 1a can include an input unit 11, a storage 12, and a processor 13. The storage 12 can include a TCAD model 121.

[0061] According to an example embodiment, the input unit 11 can transmit semiconductor manufacturing process data MD to the processor 13, and the processor 13 can generate first semiconductor characteristic data from the semiconductor manufacturing process data MD by using the TCAD model 121. In this case, the TCAD model 121 can include a data model that is stored in the storage 12 through a series of learning processes. Alternatively, the processor 13 can receive training data and train the TCAD model 121 stored in the storage 12 by machine learning.

[0062] Referring to Figure 4The TCAD model 121 can include a plurality of TCAD sub-models, e.g., first to N-th TCAD sub-models 121_1 to 121_N, and a combination module 131. Here, N is a natural number equal to or greater than 2. The processor 13 can perform arithmetic processing by inputting the semiconductor manufacturing process data MD to the TCAD model 121. For example, the first to N-th TCAD sub-models 121_1 to 121_N can be implemented by an artificial neural network model, which can include at least one selected from a convolutional neural network (CNN), a region with CNN (R-CNN), a region proposal network (RPN), a recurrent neural network (RNN), a stack-based deep neural network (S-DNN), a state-space dynamic neural network (S-SDNN), a deconvolutional network, a deep belief network (DBN), a restricted Boltzmann machine (RBM), a fully convolutional network, a long short-term memory (LSTM) network, and a classification network.

[0063] Each of the first to N-th TCAD sub-models 121_1 to 121_N can perform machine learning to simulate different electrical and / or structural characteristics of the semiconductor product. The electrical and / or structural characteristics of the semiconductor product can include at least one selected from a threshold voltage, a gain, a linearity, a breakdown voltage, an oxide degradation, a junction and / or a tunneling leakage current, a C-V curve, an I-V curve, an Id-Vg curve, a Vd-Id curve, a distribution image of the semiconductor product (e.g., a potential distribution, a doping distribution, or an electrostatic field distribution), and a field image of the semiconductor product. The items of the electrical and / or structural characteristics of the semiconductor product simulated by the first to N-th TCAD sub-models 121_1 to 121_N, respectively, can be the same as the items set by the output.

[0064] For example, the first TCAD sub-model 121_1 can be trained based on first training data ED1, which can include data on C-V curves of semiconductor products. The first TCAD sub-model 121_1 can perform simulation based on semiconductor manufacturing process data MD and generate first prediction data TO1 on C-V curves. In another example, the second TCAD sub-model 121_2 can be trained based on second training data ED2, which can include image data of cross sections of semiconductor products to show doping concentrations. The second TCAD sub-model 121_2 can perform simulation based on semiconductor manufacturing process data MD and generate second prediction data TO2 including image data of cross sections of semiconductor products to show doping concentrations. In yet another example, the N-th TCAD sub-model 121_N can be trained based on N-th training data EDN, which can include data on electrostatic field characteristics of semiconductor products. The N-th TCAD sub-model 121_N can perform simulation based on semiconductor manufacturing process data MD and generate N-th prediction data TON on electrostatic field characteristics of semiconductor products.

[0065] The processor 13 can perform simulation by using at least one selected from the first to N-th TCAD sub-models 121_1 to 121_N. For example, the processor 13 can select a TCAD sub-model to be used for simulation from the first to N-th TCAD sub-models 121_1 to 121_N based on semiconductor manufacturing process data MD and / or output settings. For example, when the output settings include a C-V curve item, the processor 13 can select a TCAD sub-model that generates prediction data on C-V curves (e.g., the first TCAD sub-model 121_1).

[0066] According to an example embodiment, the processor 13 can set environment variables. For example, the processor 13 can set environment variables involved in simulation equipment, designers, manufacturing equipment, etc. The environment variables can include calibration parameters and information on data scaling. The processor 13 can set the environment variables in response to user input, and can also set the environment variables using data that has been stored in the storage 12. The first to N-th TCAD sub-models 121_1 to 121_N can perform simulation in consideration of the environment variables.

[0067] The TCAD model 121 can generate first to Nth prediction data TO1 to TON. The first to Nth prediction data TO1 to TON can be output from the first to Nth TCAD sub-models 121_1 to 121_N, respectively. In other words, the first to Nth prediction data TO1 to TON can correspond to electrical and / or structural characteristics of the semiconductor product, which are predicted by the first to Nth TCAD sub-models 121_1 to 121_N, respectively, from the semiconductor manufacturing process data MD.

[0068] The TCAD model 121 can output first semiconductor characteristic data SD1 by combining the first to Nth prediction data TO1 to TON using a combination module 131. For example, the combination module 131 can include a hardware and / or software module implemented to represent data indicating general characteristics of the semiconductor product by combining the first to Nth prediction data TO1 to TON including electrical characteristics different from each other and structural characteristics different from each other. The processor 13 can generate the first semiconductor characteristic data SD1 using the TCAD model 121, and can store the first semiconductor characteristic data SD1 in the storage 12 or use the first semiconductor characteristic data SD1 in subsequent arithmetic processing.

[0069] Referring to FIG. 1, Figure 5 The semiconductor manufacturing process data MD can include data values according to element types to be used for a semiconductor manufacturing process. The semiconductor manufacturing process data MD can include information A about a product (e.g., a product name), information B about a process (e.g., a process name), information C about a semiconductor product (e.g., a name of a semiconductor device), information D about a version, information E about a semiconductor layout, and information F about ion implantation. Embodiments are not limited thereto, and the semiconductor manufacturing process data MD can omit or replace any of the above information, or can further include various other items.

[0070] Referring to FIG. 1, Figure 6 The output setting can include a data type related to an output of the semiconductor product and a field indicating selection or non-selection of the corresponding data type.

[0071] When the user selects at least one of the data types related to the output in the output setting, the processor 13 can output values, texts, and / or images regarding the type of data selected through simulation. The output setting can include at least one selected from a threshold voltage, a gain, a linearity, a breakdown voltage, an oxide degradation, a junction and / or a tunneling leakage current, a C-V curve, an I-V curve, an Id-Vg curve, a Vd-Id curve, a distribution image of a semiconductor product (e.g., a potential distribution, a doping distribution, or an electrostatic field distribution), and a field image of a semiconductor product. Embodiments are not limited thereto, and the output setting can include, for example, information regarding a layout of a semiconductor circuit and / or an image of the layout, and can further include various data indicating structures and characteristics of a semiconductor product.

[0072] For example, referring to Figure 6 , the user selects a threshold voltage Vt, a breakdown voltage, and a distribution image of a semiconductor product for an output setting, the processor 13 can perform simulation using a TCAD model and / or a compact model, and can output the threshold voltage Vt, the breakdown voltage, and the distribution image as predicted electrical and / or structural characteristics of a target semiconductor product.

[0073] Figure 7 is a block diagram of an electronic device according to an example embodiment, Figure 8 is a block diagram for describing a compact model according to an example embodiment, and Figure 9 is a block diagram example embodiment for describing a compact sub-model according to an example embodiment.

[0074] Referring to Figure 7 , the electronic device 1b can include an input unit 11, a storage 12, and a processor 13, and the storage 12 can include a compact model 122. The electronic device 1b, the semiconductor manufacturing equipment 31, and the semiconductor measurement equipment 32 can form a semiconductor system. Embodiments are not limited thereto, and the electronic device 1b can be implemented as a semiconductor system separate from the semiconductor manufacturing equipment 31 and the semiconductor measurement equipment 32.

[0075] According to an example embodiment, the input unit 11 can transmit semiconductor manufacturing process data MD to the processor 13, and the processor 13 can generate second semiconductor characteristic data from the semiconductor manufacturing process data MD by using the compact model 122. The processor 13 can generate or update the compact model 122 based on the measurement data SM, and store the compact model 122 in the storage 12.

[0076] The compact model 122 can be generated or updated based on the measurement data SM. The measurement data SM can include electrical and / or structural characteristics of the semiconductor product actually measured by the semiconductor measurement equipment 32. The semiconductor product measured by the semiconductor measurement equipment 32 can have been manufactured by the semiconductor manufacturing equipment 31 based on the semiconductor manufacturing data OD. The semiconductor manufacturing data OD can be related to the manufacturing of the target semiconductor device or the manufacturing of a semiconductor device similar to the target semiconductor device.

[0077] The compact model 122 can be updated in response to the measurement of the electrical and / or structural characteristics of the semiconductor product by the semiconductor measurement equipment 32. For example, in response to receiving the measurement data SM from the semiconductor measurement equipment 32, the processor 13 can update the compact model 122 to reflect the latest measurement data SM. The processor 13 can receive the measurement data SM from the semiconductor measurement equipment 32 through the input unit 11 or the communication unit 15.

[0078] The storage 12 can include equipment information selected from at least one of the semiconductor manufacturing equipment 31 and the semiconductor measurement equipment 32. For example, depending on the type of the semiconductor manufacturing equipment 31, the semiconductor product can have different electrical and / or structural characteristics. Also, the electrical and / or structural characteristics of the semiconductor product can be measured differently depending on the type of the semiconductor measurement equipment 32. To reduce errors related to the types of the semiconductor manufacturing equipment 31 and the semiconductor measurement equipment 32, the storage 12 can include various equipment information such as information on the manufacturers of the semiconductor manufacturing equipment 31 and the semiconductor measurement equipment 32, model information of the semiconductor manufacturing equipment 31 and the semiconductor measurement equipment 32, and performance information thereof. The processor 13 can update the compact model 122 with reference to the equipment information stored in the storage 12.

[0079] Referring to Figure 8 The compact model 122 can be a kind of data model, and can perform simulation based on the semiconductor manufacturing process data MD. To obtain accurate simulation results, the processor 13 can update the compact model 122 based on the measurement data SM. In other words, the processor 13 can output the second semiconductor characteristic data SD2 based on the semiconductor manufacturing process data MD by using the compact model 122 that has been updated based on the measurement data SM.

[0080] Referring to Figure 9The compact model 122 can include a plurality of compact sub-models, for example, first to Nth compact sub-models 122_1 to 122_N, and a combination module 132. For example, N can be a natural number equal to or greater than 2. In another example, N can be equal to the number of the first to Nth TCAD sub-models 121_1 to 121_N described above. In other words, the processor 13 can generate the first to Nth compact sub-models 122_1 to 122_N in the same number as the first to Nth TCAD sub-models 121_1 to 121_N. Each of the first to Nth compact sub-models 122_1 to 122_N can include information on the same electrical and / or structural characteristics as the corresponding one of the first to Nth TCAD sub-models 121_1 to 121_N. For example, when the first prediction data TO1 of the first TCAD sub-model 121_1 is on a C-V curve in Figure 4 , the first compact sub-model 122_1 can generate first output data CO1 on the C-V curve. When the second TCAD sub-model 121_2 includes image data of a cross section of the semiconductor product to show a doping concentration in Figure 4 , the second compact sub-model 122_2 can generate second output data CO2 including the image data of the cross section of the semiconductor product to show the doping concentration.

[0081] The processor 13 can perform simulation using at least one selected from the first to Nth compact sub-models 122_1 to 122_N. For example, the processor 13 can select a compact sub-model to be used for simulation from the first to Nth compact sub-models 122_1 to 122_N based on the semiconductor manufacturing process data MD and / or the output setting. For example, when the output setting includes a C-V curve item, the processor 13 can select a compact sub-model that generates output data on a C-V curve.

[0082] According to an example embodiment, the processor 13 can set environment variables. For example, the processor 13 can set environment variables involved in simulation equipment, designers, manufacturing equipment, etc. The environment variables can include calibration parameters and information on data scaling. The processor 13 can set the environment variables in response to user input, and can also set the environment variables using data already stored in the storage 12. The first to Nth compact sub-models 122_1 to 122_N can perform simulation in consideration of the environment variables.

[0083] The compact model 122 can generate first to Nth output data CO1 to CON, each of which includes information on different electrical and / or structural characteristics. The compact model 122 can output second semiconductor characteristic data SD2 by combining the first to Nth output data CO1 to CON using a combination module 132. For example, the combination module 132 can include a hardware and / or software module implemented to represent data indicating general characteristics of a semiconductor product by combining the first to Nth output data CO1 to CON including electrical characteristics different from each other and / or structural characteristics different from each other. The processor 13 can generate the second semiconductor characteristic data SD2 using the compact model 122, and can store the second semiconductor characteristic data SD2 in the storage 12 or can use the second semiconductor characteristic data SD2 in subsequent arithmetic processing.

[0084] Figure 10 is a block diagram for describing an operation of comparing first semiconductor characteristic data with second semiconductor characteristic data according to an example embodiment; and Figure 11 is a flowchart of a comparison operation according to an example embodiment.

[0085] Referring to Figure 10 and 11 , the processor 13 can generate the first semiconductor characteristic data SD1 by using the TCAD model 121 and the second semiconductor characteristic data SD2 by using the compact model 122, and can generate combination data CM based on the first semiconductor characteristic data SD1 and the second semiconductor characteristic data SD2.

[0086] In detail, in operation S310, the processor 13 can receive an output setting including a first characteristic (for example, a breakdown voltage selected as the output setting in Figure 6 ) and a second characteristic (for example, a distribution image of a semiconductor product selected as the output setting in Figure 6 ) among electrical and / or structural characteristics of a semiconductor product.

[0087] In operation S320, the processor 13 can classify information on the first characteristic included in each of the first semiconductor characteristic data SD1 and the second semiconductor characteristic data SD2 as first classification data CA1 or CB1. In detail, referring to Figure 10 , the processor 13 can classify information on the first characteristic in the first semiconductor characteristic data SD1 as the first classification data CA1 by using a first classification module 141. In addition, the processor 13 can classify information on the first characteristic in the second semiconductor characteristic data SD2 as the first classification data CB1 by using a second classification module 142. The first classification data CA1 and CB1 can include the same kind of electrical characteristics or the same kind of structural characteristics.

[0088] Similarly, in operation S350, the processor 13 can classify information on the second characteristics included in each of the first semiconductor characteristics data SD1 and the second semiconductor characteristics data SD2 as second classification data CA2 or CB2. In detail, with reference to Figure 10 , the processor 13 can classify information on the second characteristics in the first semiconductor characteristics data SD1 as the second classification data CA2 by using the first classification module 141. Also, the processor 13 can classify information on the second characteristics in the second semiconductor characteristics data SD2 as the second classification data CB2 by using the second classification module 142. The second classification data CA2 and CB2 can include the same kind of electrical characteristics or the same kind of structural characteristics.

[0089] In operation S330, the processor 13 can compare the first classification data CA1 of the first semiconductor characteristics data SD1 with the first classification data CB1 of the second semiconductor characteristics data SD2 based on the first comparison reference RF1, and can output first comparison result data CA in operation S340. In detail, the processor 13 can compare the first classification data CA1 with the first classification data CB1 by using the first comparison module 151, and can output data more in accordance with the first comparison reference RF1 between the first classification data CA1 and the first classification data CB1 as the first comparison result data CA.

[0090] The first comparison reference RF1 can correspond to the first characteristics and can be set according to the properties of the first characteristics. For example, when the first characteristics are the breakdown voltage, the first comparison reference RF1 can be set to have a smaller breakdown voltage. In this case, the processor 13 can output data corresponding to a smaller breakdown voltage between the first classification data CA1 and the first classification data CB1 as the first comparison result data CA. The method of setting the first comparison reference RF1 is not limited to the above. For example, the first comparison reference RF1 can be set in consideration of at least one selected from a priority order, a risk tolerance, and a target range set for the first characteristics and any combination thereof. For example, the first comparison reference RF1 can be set to a target range set for the first characteristics, and the processor 13 can output data more in accordance with the target range set for the first characteristics indicated by the first comparison reference RF1 between the first classification data CA1 and the first classification data CB1 as the first comparison result data CA.

[0091] In operation S360, the processor 13 can compare the second classification data CA2 of the first semiconductor characteristic data SD1 with the second classification data CB2 of the second semiconductor characteristic data SD2 based on the second comparison reference RF2, and can output second comparison result data CB in operation S370. In detail, the processor 13 can compare the second classification data CA2 with the second classification data CB2 by using the second comparison module 152, and can output data more in accordance with the second comparison reference RF2 between the second classification data CA2 and the second classification data CB2 as the second comparison result data CB.

[0092] The second comparison reference RF2 can correspond to the second characteristic and can be set according to a property of the second characteristic. A method of setting the second comparison reference RF2 is not limited to the above. For example, the second comparison reference RF2 can be set in consideration of at least one selected from a priority order set for the second characteristic, a risk tolerance, and a target range.

[0093] In operation S380, the processor 13 can generate combined data by combining the first comparison result data CA and the second comparison result data CB. In detail, referring to Figure 10 , the processor 13 can generate combined data CM by combining the first comparison result data CA and the second comparison result data CB by using the combination module 161. For example, the first comparison result data CA can be about the first characteristic, and the second comparison result data CB can be about the second characteristic. Thus, the processor 13 can combine the first comparison result data CA and the second comparison result data CB by using the combination module 161 to generate combined data CM including a plurality of semiconductor characteristics of the semiconductor product. The combined data CM can include a plurality of comparison result data, for example, the first comparison result data CA and the second comparison result data CB.

[0094] Although Figure 10 and 11 the classification and comparison of information about only the first and second characteristics are illustrated, embodiments are not limited thereto, and characteristics of at least two semiconductor products can be classified and compared. In this case, at least two classification models and at least two comparison models can be used.

[0095] Figure 12 is a block diagram for describing a method of generating a plurality of process strategies and a final process strategy according to an example embodiment.

[0096] Referring to Figure 12 , the decision model 170 can include a plurality of countermeasure models, for example, first to Mth countermeasure models 170_1 to 170_M (where M is a natural number equal to or greater than 2), and a process strategy decision module 180. The decision model 170 can receiveFigure 10 the combined data CM and outputs a final process policy (e.g., an optimal process policy) FP.

[0097] In detail, the first through Mth countermeasure models 170_1 through 170_M of the decision model 170 can respectively generate first through Mth process policies PP1 through PPM based on the combined data CM. The first through Mth countermeasure models 170_1 through 170_M can respectively generate different process policies according to respective different countermeasure references. The countermeasure reference can include at least one selected from a risk tolerance, a priority order of electrical and / or structural characteristics, a target range of electrical and / or structural characteristics, and a combination thereof. Each of the first through Mth countermeasure models 170_1 through 170_M can be trained to generate a process policy according to a countermeasure reference.

[0098] Here, the risk tolerance can refer to a degree of priority given to a performance (e.g., a bandwidth) of a semiconductor product compared to a reliability (e.g., a durability or a yield) of the semiconductor product. For example, when the risk tolerance of the semiconductor product increases, the performance of the semiconductor product can increase, but the reliability of the semiconductor product can decrease. In an embodiment, the risk tolerance can be calculated based on various information related to the semiconductor product. For example, the risk tolerance can be determined using a performance score calculated based on electrical and / or structural characteristics of the semiconductor product and a reliability score calculated based on a change in a second characteristic with respect to a change in a first characteristic, wherein the first and second characteristics are included in the electrical and / or structural characteristics of the semiconductor product.

[0099] Here, the first characteristic can include at least one selected from a characteristic related to ion implantation (e.g., an ion implantation energy, an ion implantation angle, an ion implantation projection range, and an ion implantation mask), a characteristic related to a design structure (e.g., a gate oxide, a gate length, a gate width, a shallow trench isolation (STI) depth and / or slope, and a contact position), and an internal physical characteristic (e.g., a random dopant fluctuation, a trap distribution, and a mobility). The second characteristic can include at least one selected from a threshold voltage, a gain, a linearity, a breakdown voltage, an oxide degradation, a junction and / or tunneling leakage current, a C-V curve, an I-V curve, an Id-Vg curve, a Vd-Id curve, a distribution image (e.g., a potential distribution, a doping distribution, and / or an electrostatic field distribution) of the semiconductor product, and a field image of the semiconductor product. The above-described kinds of the first and second characteristics are merely examples, and embodiments are not limited thereto. The first and second characteristics can include various other characteristics.

[0100] For example, a first countermeasure reference of the first countermeasure model 170_1 can be set to generate a process policy having a high risk tolerance. In this case, the first countermeasure model 170_1 can output a first process policy PP1 of a semiconductor product having a high performance while providing a lower yield.

[0101] The priority order of the electrical and / or structural characteristics can refer to a priority order value assigned to each of the electrical and / or structural characteristics of the semiconductor product. The countermeasure reference can be set to generate a process policy allowing the semiconductor characteristics having a high priority to have an appropriate value. For example, a second countermeasure reference of the second countermeasure model 170_2 can be set to give the highest priority to the leakage current among the electrical and / or structural characteristics of the semiconductor product. In this case, the second countermeasure model 170_2 can output a second process policy PP2 designed for a low leakage current. The countermeasure reference based on the setting of the priority order value is not limited to the above. For example, the countermeasure reference can be set to generate a process policy allowing a plurality of semiconductor characteristics having at least a certain priority order value to have an appropriate value.

[0102] The target range of the electrical and / or structural characteristics can refer to a target range of a measured value (or a simulated value) of each of the electrical and / or structural characteristics of the semiconductor product. For example, an Mth countermeasure reference of an Mth countermeasure model 170_M can be set to allow at least one electrical and / or structural characteristic to be within the target range. In this case, the Mth countermeasure model 170_M can output an Mth process policy PPM to allow at least one electrical and / or structural characteristic to be within the target range. In other words, with respect to the same input (i.e., the combined data CM), the first to Mth countermeasure models 170_1 to 170_M can output different process policies, i.e., the first to Mth process policies PP1 to PPM, respectively.

[0103] The processor 13 can receive the decision weight from the user through the input unit 11 and / or the communication unit 15. For example, the decision weight can include a priority order of at least one or some of the plurality of semiconductor characteristics. The semiconductor characteristics can include electrical and / or structural characteristics of the semiconductor product itself and / or electrical and / or structural characteristics of at least one element included in the semiconductor product. In an embodiment, the processor 13 can receive the decision weight with respect to a target semiconductor product from the user.

[0104] The process strategy decision module 180 of decision model 170 can determine a final (e.g., optimal) process strategy FP based on the first to Mth process strategies PP1 to PPM. In an embodiment, the process strategy decision module 180 can calculate a priority score for each of the first to Mth process strategies PP1 to PPM using decision weights, and can determine the final process strategy FP based on the calculated priority scores. For example, the process strategy decision module 180 can determine the first process strategy PP1, which has the highest priority score among the first to Mth process strategies PP1 to PPM, as the final process strategy FP. The method of determining the final process strategy FP using the process strategy decision module 180 is not limited to the examples described above, and there can be at least one final process strategy FP. For example, the final process strategy FP can include all or some of the first to Mth process strategies PP1 to PPM that are prioritized based on decision weights.

[0105] The processor 13 can provide the user of the electronic device 1 with the final process strategy FP output from the decision model 170 as a process strategy, which optimally conforms to the semiconductor manufacturing processing data MD and the user-selected values. For example, the processor 13 can provide the final process strategy FP to the user via the display 14.

[0106] Figure 13 This is a diagram of a graphical user interface according to an example embodiment.

[0107] refer to Figure 13 The processor 13 can display a graphical user interface (GUI) via a display 14. The GUI may include menus "Semiconductor Manufacturing Process Data Selection 1" and "Semiconductor Manufacturing Process Data Selection 2" for selecting information to be included in the semiconductor manufacturing process data MD. Through menu "Semiconductor Manufacturing Process Data Selection 1," the processor 13 can receive one or more inputs related to the semiconductor product, semiconductor manufacturing process, semiconductor equipment, and semiconductor product version included in the semiconductor manufacturing process data MD. Through menu "Semiconductor Manufacturing Process Data Selection 2," the processor 13 can receive at least one selected from information about semiconductor layout (or structure) and information about ion implantation, corresponding to the product, process, equipment, and / or version selected in menu "Semiconductor Manufacturing Process Data Selection 1."

[0108] The GUI can include a menu "output setting" for selecting at least one property among electrical and / or structural properties of the target semiconductor product which the user desires to be provided as a simulation result of the target semiconductor product. For example, through the menu "output setting", the processor 13 can receive at least one item of information included in each of one-dimensional (ID) value information (e.g., a voltage or current value), two-dimensional (2D) value information (e.g., a voltage-current (VI) curve), and distribution information (e.g., 3D electrical properties, a doping concentration, or electrostatic field information).

[0109] Figure 14 is a block diagram of an electronic system according to an example embodiment.

[0110] Reference Figure 14 The electronic system 2 can include the electronic device 1 and a management device 16. The electronic device 1 can have substantially the same structure as the electronic device 1 of Figure 1

[0111] The electronic device 1 can receive user information ID1 from a user. For example, the user can input personalized user information ID1 to the electronic device 1 through an input device such as a keyboard. The processor 13 can identify a permission level of the user information ID1.

[0112] For example, the management device 16 can be a server external to the electronic device 1, and can include a plurality of items of user information and data about a usage history of the electronic device 1. The processor 13 can transmit the user information ID1 to the management device 16 through the communication unit 15, and the management device 16 can transmit information about the permission level to the processor 13 through the communication unit 15 in response to the user information ID1. The processor 13 can identify the permission level of the user information ID1 based on the information about the user information ID1 received through the management device 16.

[0113] Alternatively, the storage 12 can store information about the permission level. The processor 13 can identify the permission level of the user information ID1 based on the information about the user information ID1 stored in the storage 12. For example, the processor 13 can identify a first level corresponding to a permission level assigned to a foundry company based on the user information ID1 of the foundry company, and can identify a second level corresponding to a permission level assigned to a non-processor company based on the user information ID1 of the non-processor company.

[0114] The processor 13 can provide at least a portion of the semiconductor manufacturing process data MD to the user according to the identified permission level. In an embodiment, when the identified permission level is the first level, the processor 13 can provide all items of the semiconductor manufacturing process data MD (e.g., Figure 13 ​The processor 13 may not provide all items of the semiconductor manufacturing process data (MD) to the user (e.g., ion implantation items) when the identified permission level is Level 2. The processor 13 may provide at least a portion of the final process strategy (FP) to the user based on the identified permission level. In an embodiment, when the identified permission level is Level 1, the processor 13 may provide all items of the final process strategy (FP) to the user (e.g., design structure, applied voltage, and type of ion implantation). When the identified permission level is Level 2, the processor 13 may not provide some items of the final process strategy (FP) to the user.

[0115] According to an embodiment, when multiple final process policies (FPs) exist, the processor 13 may provide at least one of the final process policies (FPs) to the user. In an embodiment, when the identified permission level is Level 1, the processor 13 may provide all final process policies (FPs) to the user. When the identified permission level is Level 2, the processor 13 may provide only one of the final process policies (FPs) to the user.

[0116] The scope of information provided to the user by the processor 13 according to the permission level is not limited to the examples described above and can vary with different embodiments. For example, there may be at least three permission levels, and the processor 13 may be configured such that the at least three permission levels have different scopes of information to be provided to the user.

[0117] Processor 13 can block, cover up, erase and / or hide at least a portion of semiconductor manufacturing process data MD and at least a portion of final process strategy FP according to the permission level, and can display data DP_ID1 on display 14, which includes remaining information (i.e., accessible information according to the permission level).

[0118] The term "module" can refer to software components and / or hardware components, such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs), and a "module" can perform certain functions. However, a "module" is not limited to software or hardware. A "module" can be configured to be included in addressable storage media or to reproduce one or more processors. Thus, for example, a "module" can include components such as software components, object-oriented software components, class components, and task components, processes, functions, attributes, procedures, subroutines, program code segments, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functionality provided in components and "modules" can be integrated with a smaller number of components and "modules," or it can be divided into additional components and "modules."

[0119] While the concept of the present application has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of guiding a semiconductor manufacturing process, the method comprising: receiving semiconductor manufacturing process data corresponding to a target semiconductor product; generating first semiconductor property data corresponding to the semiconductor manufacturing process data by using a technology computer aided design (TCAD) model trained by machine learning based on training data including TCAD simulation data; generating second semiconductor property data corresponding to the semiconductor manufacturing process data by using a compact model generated based on measured information of at least one semiconductor property of a first semiconductor product; generating a plurality of process strategies respectively corresponding to a plurality of countermeasure references by using a plurality of countermeasure models based on the first semiconductor property data and the second semiconductor property data; and providing a final process strategy corresponding to the target semiconductor product based on the plurality of process strategies, wherein the generating of the plurality of process strategies comprises: comparing the first semiconductor property data and the second semiconductor property data based on each of a plurality of reference properties, and outputting a plurality of comparison result data by determining data between the first semiconductor property data and the second semiconductor property data that conforms to each of the plurality of reference properties; and generating the plurality of process strategies based on the plurality of comparison result data according to the plurality of countermeasure references of the plurality of countermeasure models. 2.The method of claim 1, further comprising receiving a decision weight from a user; wherein the providing of the final process strategy comprises determining a final process strategy from the plurality of process strategies based on the decision weight. 3.The method of claim 2, wherein the decision weight comprises a priority order of at least one semiconductor property. 4.The method of claim 3, wherein the at least one semiconductor property comprises at least one selected from an electrical property of a semiconductor product, a structural property of the semiconductor product, an electrical property of at least one element of the semiconductor product, and a structural property of the at least one element. 5.The method of claim 3, wherein the providing of the final process strategy comprises determining a process strategy having a high priority with respect to the at least one semiconductor property corresponding to the decision weight among the plurality of process strategies as the final process strategy. 6.The method of claim 1, further comprising receiving an output setting for setting at least one semiconductor property corresponding to the target semiconductor product, wherein the generating of the first semiconductor property data comprises generating the first semiconductor property data including the at least one semiconductor property corresponding to the output setting from an output of the TCAD model, and the generating of the second semiconductor property data comprises generating the second semiconductor property data including the at least one semiconductor property corresponding to the output setting from an output of the compact model. 7.The method of claim 1, wherein the plurality of countermeasure models comprises a first countermeasure model and a second countermeasure model, ​ ​ wherein the first countermeasure model comprises a decision model trained based on a first countermeasure reference of the plurality of countermeasure references, and wherein the second countermeasure model comprises a decision model trained based on a second countermeasure reference of the plurality of countermeasure references.

8. The method of claim 7, wherein the plurality of process strategies comprises a first process strategy and a second process strategy, wherein the first process strategy is generated based on the first countermeasure reference by using the first countermeasure model, and wherein the second process strategy is generated based on the second countermeasure reference by using the second countermeasure model.

9. The method of claim 7, wherein the plurality of countermeasure references comprises at least one selected from a risk tolerance, a priority order value of each of a plurality of semiconductor characteristics, and a target range of each of the plurality of semiconductor characteristics.

10. The method of claim 1, wherein the compact model is updated based on measurement information of a plurality of semiconductor characteristics of the first semiconductor product using external measurement equipment.

11. The method of claim 1, wherein each of the first semiconductor characteristic data and the second semiconductor characteristic data comprises data corresponding to a first characteristic and data corresponding to a second characteristic, and wherein outputting the plurality of comparison result data comprises: classifying, in each of the first semiconductor characteristic data and the second semiconductor characteristic data, the data corresponding to the first characteristic as first classification data; classifying, in each of the first semiconductor characteristic data and the second semiconductor characteristic data, the data corresponding to the second characteristic as second classification data; generating first comparison result data by comparing the first classification data of the first semiconductor characteristic data with the first classification data of the second semiconductor characteristic data based on a first comparison reference; and generating second comparison result data by comparing the second classification data of the first semiconductor characteristic data with the second classification data of the second semiconductor characteristic data based on a second comparison reference.

12. The method of claim 1, wherein the TCAD model comprises a plurality of TCAD sub-models, wherein each of the plurality of TCAD sub-models is trained based on a different piece of the training data, and wherein the training data comprises at least one selected from a threshold voltage, a gain, a linearity, a breakdown voltage, an oxide degradation, a junction and / or a tunneling leakage current, a capacitance-voltage curve, a current-voltage curve, a drain current-gate voltage curve, a drain voltage-drain current curve, a distribution image of a semiconductor product, and a field image of the semiconductor product.

13. The method of claim 12, wherein the first semiconductor characteristic data is obtained by inputting the semiconductor manufacturing process data to the TCAD model and combining pieces of data respectively output from the plurality of TCAD sub-models.

14. The method of claim 12, wherein the compact model comprises a plurality of compact sub-models, and ​ wherein the plurality of compact sub-models are updated based on measurement information of different semiconductor characteristics of the first semiconductor product respectively, the plurality of compact sub-models being trained correspondingly with the plurality of TCAD sub-models respectively.

15. The method of claim 1, further comprising: receiving user information; and identifying a level of authority of the user information, wherein providing the final process policy comprises providing at least a portion of the final process policy according to the identified level of authority.

16. An electronic device for guiding a semiconductor manufacturing process, the electronic device comprising: a display; at least one non-transitory computer-readable medium; and at least one processor configured to execute instructions stored in the at least one non-transitory computer-readable medium, wherein the at least one processor is further configured to: receive semiconductor manufacturing process data corresponding to a target semiconductor device; generate first semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a technical computer-aided design (TCAD) model, the TCAD model being trained by machine learning based on training data including information on a plurality of semiconductor characteristics; generate second semiconductor characteristic data corresponding to the semiconductor manufacturing process data by using a compact model, the compact model being generated based on measurement information of at least one semiconductor characteristic of a first semiconductor device; generate a plurality of process policies respectively corresponding to a plurality of countermeasure references by using a plurality of countermeasure models based on the first semiconductor characteristic data and the second semiconductor characteristic data; and control the display to display at least one of the plurality of process policies as a process policy corresponding to the target semiconductor device, wherein the at least one processor is further configured to generate the plurality of process policies by performing: comparing the first semiconductor characteristic data and the second semiconductor characteristic data based on each of a plurality of reference characteristics, and outputting a plurality of comparison result data by determining data between the first semiconductor characteristic data and the second semiconductor characteristic data that conforms to each of the plurality of reference characteristics; and generating the plurality of process policies based on the plurality of comparison result data according to the plurality of countermeasure references of the plurality of countermeasure models.

17. The electronic device of claim 16, wherein the plurality of countermeasure models comprises a first countermeasure model and a second countermeasure model, wherein the at least one processor is further configured to generate a first process policy by using the first countermeasure model based on a first countermeasure reference among the plurality of countermeasure references, and wherein the at least one processor is further configured to generate a second process policy by using the second countermeasure model based on a second countermeasure reference among the plurality of countermeasure references.

18. The electronic device of claim 16, wherein the plurality of countermeasure references comprises at least one selected from a risk tolerance, a priority order value of each of a plurality of semiconductor characteristics, and a target range of each of the plurality of semiconductor characteristics.

19. An electronic system for guiding a semiconductor manufacturing process, the electronic system comprising: a communication unit; a display; a processor configured to: receive semiconductor manufacturing process data corresponding to a target semiconductor device; output first semiconductor property data corresponding to the semiconductor manufacturing process data by using a technology computer aided design (TCAD) model, the TCAD model being trained based on training data including TCAD simulation data; output second semiconductor property data corresponding to the semiconductor manufacturing process data by using a compact model, the compact model being generated based on measured information of at least one semiconductor property of a first semiconductor device; generate a plurality of process strategies based on the first semiconductor property data and the second semiconductor property data; and a management device configured to receive user information from the processor and transmit information on a level of authority corresponding to the user information to the processor, wherein the processor is further configured to control the display to display at least a portion of the plurality of process strategies based on the information on the level of authority, wherein the processor is further configured to generate the plurality of process strategies by performing the following operations: compare the first semiconductor property data and the second semiconductor property data based on each of a plurality of reference properties, and output a plurality of comparison result data by determining data between the first semiconductor property data and the second semiconductor property data that conforms to each of the plurality of reference properties; and generate the plurality of process strategies based on the plurality of comparison result data according to the plurality of reference properties. ​ ​

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