Memory circuit and method

Abstract

The present disclosure relates to memory circuits and methods. A circuit includes: a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when a selection signal has a first logic state, and pass the second address to the output when the selection signal has a second logic state different from the first logic state. The circuit also includes a decoder configured to decode the passed first address or the second address.

Description

Technical Field

[0001] The present disclosure relates to memory circuits and methods. Background Art

[0002] Memory arrays are often used to store and access data for various types of calculations, such as logical or mathematical operations. To perform these operations, data is moved through data ports between the memory array and the circuits used to perform these calculations. In some cases, the number of data lines in the memory array through which stored data is accessed is less than the number of data ports, and some or all of the data lines are shared for data movement operations. Summary of the invention

[0003] According to one embodiment of the present disclosure, a memory circuit is provided, comprising: a selection circuit configured to: receive a first address at a first input and a second address at a second input, pass the first address to an output when a selection signal has a first logic state, and pass the second address to the output when the selection signal has a second logic state different from the first logic state; and a decoder configured to decode the passed first address or second address.

[0004] According to another embodiment of the present disclosure, a method for operating a memory circuit is provided, the method comprising: receiving a first address and a second address at a selection circuit; passing one of the first address or the second address to an address decoder using the selection circuit; and decoding the one of the first address or the second address using the address decoder.

[0005] According to another embodiment of the present disclosure, a memory circuit is provided, comprising: a memory array; a selection circuit configured to: receive a write address at a first input and a read address at a second input, pass the write address to an output when a selection signal has a first logic state, and pass the read address to the output when the selection signal has a second logic state different from the first logic state; and a decoder configured to: decode the passed write address or read address and activate a word line signal path in the memory array corresponding to the decoded write address or read address. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1is a diagram of a memory circuit according to some embodiments.

[0008] Figure 2A and Figure 2B is a graph of memory circuit operating parameters according to some embodiments.

[0009] Figure 3A and Figure 3B is a diagram of a control circuit according to some embodiments.

[0010] Figure 4A and Figure 4B is a graph of memory circuit operating parameters according to some embodiments.

[0011] Figure 5 is a diagram of a signal generating circuit according to some embodiments.

[0012] Figure 6 is a diagram of a signal generating circuit according to some embodiments.

[0013] Fig. 7A and Figure 7B is a graph of memory circuit operating parameters according to some embodiments.

[0014] Figure 8 is a flow chart of a method of operating a memory circuit according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. The specific examples of parts, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. Other parts, values, operations, materials, arrangements, etc. are expected. In addition, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in a directly contacting manner, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another (or additional) elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] In various embodiments, the circuit includes a single decoder and selection circuit and is configured to select and decode one of two addresses corresponding to a data movement (e.g., read and write) operation in a memory array. By using a single decoder to activate a control line during a data movement operation, area requirements are reduced compared to an approach that uses a separate decoder for each of the two addresses in a memory array data movement operation.

[0018] Figure 1 1 is a diagram of a memory circuit 100 according to some embodiments. The memory circuit 100 (also referred to as circuit 100) includes a latch circuit 110, a selection circuit 120, a latch circuit 130, a pre-decoder 140, a decoder 150, a memory array 160, and a control circuit 170. As described below, the control circuit 170 includes a signal generating portion and a clock buffer portion, which in some embodiments is also referred to as a double pump generator and is configured to generate various timing signals, and the clock buffer portion is configured to output various control signals based on the timing signals.

[0019] As described below, the memory circuit 100 is configured to receive an address RX from a port P1, an address WX from a port P2, a clock signal CLK, and enable signals REB and WEB, and select and decode one of the addresses RX or WX in response to the clock signal CLK and the enable signals REB and WEB, thereby generating one or more of N word line signals WL[1]-WL[N] on corresponding one or more word line signal paths WP[1]-WP[N].

[0020] In some embodiments, memory array 160 is a static random access memory (SRAM) array including single-port memory cells, and memory circuit 100 is configured to facilitate data movement into and out of the single-port memory cells identified by addresses RX and WX. In some embodiments, memory circuit 100 is configured to facilitate data movement into and out of the single-port memory cells at column positions (also referred to as X positions) identified by addresses RX and WX. In some embodiments, addresses RX and WX are derived from corresponding addresses (not shown) that include additional information (e.g., a column identifier), and addresses RX and WX do not include the additional information.

[0021] In some embodiments, the memory array 160 includes a register file of a processor register including a single-port memory cell, and the memory circuit 100 is configured to control data movement in a pseudo dual-port register file (2PRF) operation. In a pseudo 2PRF operation, in some embodiments, a single-port memory cell is used to perform the function of a dual-port memory cell by using a single clock signal instead of two separate clock signals. The first half of the clock cycle of the single clock signal is used to control a read operation based on a read address received on a read port, and the second half of the clock cycle is used to control a write operation based on a write address received on a write port. In some embodiments, the memory circuit 100 is included in an ultra-high density (UHD) pseudo 2PRF circuit. In some embodiments, the memory circuit 100 is an integrated circuit (IC).

[0022] exist Figure 1 In the embodiment depicted in FIG, memory circuit 100 includes memory array 160 coupled to decoder 150 via word line signal paths WP[1]-WP[N]. In various embodiments, memory circuit 100 includes word line signal paths WP[1]-WP[N] but not memory array 160, or includes neither memory array 160 nor word line signal paths WP[1]-WP[N].

[0023] The latch circuit 110 is coupled to the port P2, the selection circuit 120, and the control circuit 170; the selection circuit 120 is coupled to the port P1, each latch circuit 110 and 130, and the control circuit 170; the latch circuit 130 is coupled to the selection circuit 120, the pre-decoder 140, and the control circuit 170; the pre-decoder 140 is coupled to the latch circuit 130, the decoder 150, and the control circuit 170; the decoder 150 is coupled to the pre-decoder 140 and the memory array 160.

[0024] Two or more circuit elements are considered coupled based on one or more direct signal connections and / or one or more indirect signal connections (including one or more logic devices, such as inverters or logic gates, between the two or more circuit elements. In some embodiments, the signal communication between the two or more coupled circuit elements can be modified by one or more logic devices, such as being inverted or limited to conditions.

[0025] Each of the addresses RX and WX includes a combination of logic states that are configured to identify one or more physical locations in a memory array (e.g., memory array 160) that correspond to a given word. In some embodiments, each word corresponds to a row of memory array 160, and the address RX is configured to identify the corresponding row in memory array 160 in a read operation, and the address WX is configured to identify the corresponding row in memory array 160 in a write operation.

[0026] The address RX or WX includes a corresponding address in some or all of the memory (eg, memory array 160) corresponding to 2 L In some embodiments, L is the number of logic states ranging from two logic states corresponding to four words to 12 logic states corresponding to 4096 words. In some embodiments, address RX or WX includes L equal to four logic states corresponding to 16 words. In some embodiments, 2 corresponding to the L logic states in addresses RX and WX are L A word is equal to the number N of word line signal paths WP[1]-WP[N].

[0027] exist Figure 1 In the embodiment depicted in , each of ports P1 and P2, latch circuits 110 and 130, selection circuit 120, and pre-decoder 140 includes one or more electrical paths that are configured to conduct one or more signals corresponding to the L logic states included in addresses RX and WX. In some embodiments, each of ports P1 and P2, latch circuits 110 and 130, selection circuit 120, and pre-decoder 140 includes a number of electrical paths equal to L.

[0028] In various embodiments, at least one of latch circuits 110 or 130 is one of a plurality of latch circuits (not shown) and / or selection circuit 120 is one of a plurality of selection circuits (not shown), and the at least one latch circuit and / or selection circuit is configured to conduct one or more signals corresponding to the L logic states included in addresses RX and WX in common. In some embodiments, each of latch circuits 110 and 130 includes a single electrical path and is one of the L latch circuits, selection circuit 120 includes a single electrical path and is one of the L selection circuits, and therefore, circuit 100 is configured to conduct one or more signals corresponding to the L logic states included in addresses RX and WX in common.

[0029] The latch circuit 110 is an electronic circuit including an input 111 configured to receive an address WX from a port P2, an input 113 configured to receive a clock pulse signal CKTW from a control circuit 170, and an output 112 configured to output the address WX, which is selectively latched in response to the clock pulse signal CKTW.

[0030] The selection circuit 120 is an electronic circuit that includes an input 121 configured to receive an address RX from the port P1, an input 123 configured to receive an address WX from the output 112 of the latch circuit 110, an input 125 configured to receive a selection signal PSEL from the control circuit 170, and an output 122 configured to output one of the addresses RX or WX in response to the selection signal PSEL. Thus, the selection circuit 120 is configured to pass the selected address RX or WX to the output 122. In some embodiments, the selection circuit 120 includes a multiplexer.

[0031] The latch circuit 130 is an electronic circuit including an input 131 configured to receive one of the addresses RX or WX from the output 122 of the selection circuit 120; an input 133 configured to receive the clock pulse signal CKTR from the control circuit 170; and an output 132 configured to output the received address RX or WX, which is selectively latched in response to the clock pulse signal CKTR.

[0032] The predecoder 140 is a combinational logic circuit including an input 141 configured to receive an address RX or WX from an output 132 of the latch circuit 130; an input 143 configured to receive a clock pulse signal CKP from the control circuit 170; and an output 142 configured to output a partially decoded address PD based on the received address RX or WX, and to be selectively enabled in response to the clock pulse signal CKP.

[0033] The decoder 150 is a combinational logic circuit that includes: an input 151 that is configured to receive a partially decoded address PD from an output 142 of the pre-decoder 140; and an output 152 that is configured to output corresponding one or more word line signals WL[1]-WL[N] on one or more word line signal paths WP[1]-WP[N] based on the partially decoded address PD.

[0034] exist Figure 1 In the embodiment depicted in FIG, pre-decoder 140 and decoder 150 are separate circuits. In some embodiments, pre-decoder 140 and decoder 150 are a single combinatorial logic circuit that is configured to output corresponding one or more word line signals WL[1]-WL[N] on one or more word line signal paths WP[1]-WP[N] based on the address RX or WX received on input 141 from output 132 of latch circuit 130, selectively enabled in response to clock pulse signal CKP.

[0035] In some embodiments, the memory circuit 100 does not include the decoder 150 , the output 142 of the pre-decoder 140 is the output of the memory circuit 100 , and the pre-decoder 140 is configured to output the partially decoded address PD as one or more output signals of the memory circuit 100 .

[0036] Memory array 160 is an array of memory cells (not shown) arranged in rows and columns. The memory cells of memory array 160 include electrical devices, electromechanical devices, electromagnetic devices, or other devices configured to store bit data represented by logical states. In some embodiments, the logical state corresponds to the voltage level of the charge stored in a given memory cell. In some embodiments, the logical state corresponds to the physical properties of the components of a given memory cell, such as resistance or magnetic orientation.

[0037] In some embodiments, the memory cells of the memory array 160 include SRAM cells. In various embodiments, the SRAM cells include five-transistor (5T) SRAM cells, six-transistor (6T) SRAM cells, eight-transistor (8T) SRAM cells, nine-transistor (9T) SRAM cells, or SRAM cells having other numbers of transistors. In some embodiments, the memory cells of the memory array 160 include dynamic random access memory (DRAM) cells or other memory cell types capable of storing bits of data.

[0038] Some or all of the memory cells in a given row or column of the memory array 160 are configured to be activated simultaneously as a word in read and write operations in response to corresponding one or more word line signals WL[1]-WL[N] received from one or more word line signal paths WP[1]-WP[N]. In some embodiments, each word corresponds to a row of memory cells in the memory array 160, and each of the word line signal paths WP[1]-WP[N] is coupled to the memory cells in the row corresponding to the given word.

[0039] The addresses RX and WX, the clock pulse signals CKTW, CKTR, and CKP, the select signal PSEL, the word line signals WL[1]-WL[N], and other signals used by the memory circuit 100 discussed below are configured to have one or more voltage levels corresponding to logic states. A high logic state corresponds to a voltage level equal to or higher than a first predetermined threshold, and a low logic state corresponds to a voltage level equal to or lower than a second predetermined threshold. In various embodiments, the first predetermined threshold corresponds to a voltage level at or near an operating voltage level (e.g., voltage level VDD or VDDM) of the memory circuit 100, and / or the second predetermined threshold corresponds to a voltage level at or near a reference voltage level (e.g., voltage level VSS or ground potential) of the memory circuit 100.

[0040] In various embodiments, the latch circuit 110 is configured to latch the address WX in response to the clock pulse signal CKTW having a predetermined one of a high or low logic state, the selection circuit 120 is configured to pass a given one of the addresses RX or WX to the output 122 in response to the selection signal PSEL having a corresponding one of a high or low logic state, and the latch circuit 130 is configured to latch the address RX or WX in response to the clock pulse signal CKTR having a predetermined one of a high or low logic state. The predecoder 140 is configured to output the partially decoded address PD in response to the clock pulse signal having a predetermined one of a high logic state or a low logic state.

[0041] In various embodiments, decoder 150 is configured to activate given one or more word line signal paths WP[1]-WP[N] by outputting one or more word line signals WL[1]-WL[N] having a predetermined one of a high or low logic state, thereby activating the corresponding word. In some embodiments, outputting a given one of word line signals WL[1]-WL[N] having a predetermined one of a high or low logic state is also referred to as activating a given one of word line signals WL[1]-WL[N], and outputting a given one of word line signals WL[1]-WL[N] having another one of a high or low logic state is referred to as deactivating a given one of word line signals WL[1]-WL[N].

[0042] The control circuit 170 is an electronic circuit configured to receive the clock signal CLK and the enable signals REB and WEB, and generate the clock pulse signals CKTW, CKTR, and CKP, and select the signal PSEL based on the clock signal CLK and the enable signals REB and WEB. The control circuit 170 is configured to control the operating parameters of the memory circuit 100, thereby generating the clock pulse signals CKTW, CKTR, and CKP and the following about Figure 2A and 2B The selection signal PSEL discussed has a timing relationship. In some embodiments, the control circuit 170 includes the control circuit 300 discussed below with respect to FIG.

[0043] Figure 2A is a graph of operating parameters of the memory circuit 100 according to some embodiments. Figure 2A In the non-limiting example depicted in , signals CLK, CKTW, CKTR, PSEL, and CKP include transitions between high logic states and low logic states at times t1 - t5 corresponding to operation of memory circuit 100 , as described below. Figure 2A A case is depicted in which each of the enable signals REB and WEB has a logic state corresponding to an enable state, and the enable signal is not shown for clarity.

[0044] exist Figure 2A In the embodiment depicted in , each of the latch circuits 110 and 130 is configured to latch the received address and pass the latched address to the corresponding output in response to the corresponding clock pulse signal transitioning to a high logic state until the corresponding clock pulse signal transitions to a low logic state, and pass the received address to the corresponding output without performing a latching operation in response to the corresponding clock pulse signal having a low logic state. The selection circuit 120 is configured to pass each of the addresses RX and WX to the output 122 in response to the selection signal PSEL having a corresponding low logic state and a high logic state, and the predecoder 140 is configured to selectively output the partially decoded address PD in response to the clock pulse signal CKP having a high logic state.

[0045] In various embodiments, the memory circuit 100 is configured based on Figure 2A 1 and 2. The CLK and CKP signals may be operated with one or more of the signals CLK, CKTW, CKTR, PSEL, or CKP having one or more logic states and / or transitions that are different from those depicted in FIG.

[0046] The clock signal CLK is generated by a circuit external to the memory circuit 100 and includes a series of pulses having a predetermined period T. A rising edge of a pulse corresponds to a transition from a low logic state to a high logic state, and a falling edge of a pulse corresponds to a transition from a high logic state to a low logic state.

[0047] At time t1 , the control circuit 170 is configured to respond to a rising edge of the clock signal CLK by generating a rising edge in each of the clock pulse signals CKTW, CKTR, and CKP when the select signal PSEL has a low logic state.

[0048] Based on the rising edge of the clock pulse signal CKTW, the latch circuit 110 latches the address WX and transmits the latched address WX to the output 112. Based on the low logic state of the selection signal PSEL, the selection circuit 120 transmits the address RX to the output 122. Based on the rising edge of the clock pulse signal CKTR, the latch circuit 130 latches the address RX and transmits the latched address RX to the output 122. Based on the rising edge of the clock pulse signal CKP, the pre-decoder 140 becomes enabled, thereby generating a partially decoded address PD at the output 142 based on the latched address RX, and the decoder 150 activates the word line signal corresponding to the address RX among the word line signals WL[1]-WL[N], as described below with respect to Figure 2B As discussed.

[0049] After time t1 , at time t2 , the control circuit 170 is configured to generate a rising edge in the selection signal PSEL while each of the clock pulse signals CKTW, CKTR, and CKP remains in a high logic state.

[0050] Since the clock pulse signal CKTW remains in a high logic state, the latch circuit 110 continues to pass the latch address WX to the output 112. Based on the rising edge of the selection signal PSEL, the selection circuit 120 passes the latch address WX to the output 122. Since the clock pulse signal CKTR remains in a high logic state, the latch circuit 130 continues to pass the latch address RX to the output 132. Since the clock pulse signal CKP remains in a high logic state, the pre-decoder 140 remains enabled, thereby continuing to generate the partially decoded address PD at the output 142 based on the latch address RX, so that the decoder 150 continues to activate the word line signal corresponding to the address RX among the word line signals WL[1]-WL[N].

[0051] After time t2 , at time t3 , the control circuit 170 is configured to generate a falling edge in each of the clock pulse signals CKTR and CKP while maintaining each of the clock pulse signal CKTW and the selection signal PSEL in a high logic state.

[0052] Since the clock pulse signal CKTW remains in a high logic state, the latch circuit 110 continues to pass the latch address WX to the output 112. Since the selection signal PSEL remains in a high logic state, the selection circuit 120 continues to pass the latch address WX to the output 122. Based on the falling edge of the clock pulse signal CKTR, the latch circuit 130 stops latching the address RX and passes the latch address WX to the output 122. Based on the falling edge of the clock pulse signal CKP, the pre-decoder 140 becomes disabled, thereby stopping generating the partially decoded address PD at the output 142 based on the latch address RX, and the decoder 150 deactivates the word line signal corresponding to the address RX among the word line signals WL[1]-WL[N].

[0053] After time t3 , at time t4 , the control circuit 170 is configured to generate a rising edge in the clock pulse signal CKP while maintaining each of the clock pulse signal CKTW and the selection signal PSEL at a high logic state and maintaining the clock pulse signal CKTR at a low logic state.

[0054] Since the clock pulse signal CKTW remains in a high logic state, the latch circuit 110 continues to pass the latch address WX to the output 112. Since the selection signal PSEL remains in a high logic state, the selection circuit 120 continues to pass the latch address WX to the output 122. Since the clock pulse signal CKTR remains in a low logic state, the latch circuit 130 continues to pass the latch address WX to the output 122. Based on the rising edge of the clock pulse signal CKP, the pre-decoder 140 becomes enabled to generate a partially decoded address PD at the output 142 based on the latch address WX, and the decoder 150 activates the word line signal corresponding to the address WX among the word line signals WL[1]-WL[N], as described below with respect to Figure 2B As discussed.

[0055] After time t4 , at time t5 , the control circuit 170 is configured to generate a falling edge in each of the clock pulse signals CKTW and CKP and the selection signal PSEL while maintaining the clock pulse signal CKTR in a low logic state.

[0056] Based on the falling edge of the clock pulse signal CKTW, the latch circuit 110 stops passing the latched address WX to the output 112. Based on the falling edge of the selection signal PSEL, the selection circuit 120 passes the address RX to the output 122. Since the clock pulse signal CKTR continues to have a low logic state, the latch circuit 130 passes the address RX to the output 122. Based on the falling edge of the clock pulse signal CKP, the pre-decoder 140 becomes disabled, thereby stopping generating the partially decoded address PD at the output 142 based on the latched address WX, and the decoder 150 deactivates the word line signal corresponding to the address WX among the word line signals WL[1]-WL[N].

[0057] The interval from time t1 to t3 corresponds to a pulse PL1 of the clock pulse signal CPK, during which the decoder 150 activates one of the word line signals WL[1]-WL[N] based on the latch address RX passed to the pre-decoder 140. In some embodiments, the pulse PL1 corresponds to a read operation in the memory array 160.

[0058] exist Figure 2A In the embodiment depicted in FIG. 1 , the memory circuit 100 is configured to pass the latch address RX to the predecoder 140 during the pulse PL1 by generating a rising edge of each of the clock pulse signals CKTW, CKTR, and CKP at time t1 prior to generating a rising edge of the select signal PSEL at time t2. In various embodiments, the memory circuit 100 is configured to transmit the latch address RX to the predecoder 140 during the pulse PL1 by generating a rising edge of each of the clock pulse signals CKTW, CKTR, and CKP at time t1 prior to generating a rising edge of the select signal PSEL at time t2. Figure 2A The latch address RX is transferred to the predecoder 140 at the rising edges of the clock pulse signals CKTW, CKTR, and CKP of a timing different from the timing depicted in the figure. Such timing includes transferring the latch address RX to the predecoder 140 before the rising edge of the selection signal PSEL is generated at time t2.

[0059] The interval from time t4 to t5 corresponds to a pulse PL2 of the clock pulse signal CKP, during which the decoder 150 activates one of the word line signals WL[1]-WL[N] based on the latch address WX passed to the pre-decoder 140. In some embodiments, the pulse PL2 corresponds to a write operation in the memory array 160.

[0060] exist Figure 2A In the embodiment depicted in FIG. 1 , the memory circuit 100 is configured to pass the latch address WX to the predecoder 140 during the pulse PL2 by generating a rising edge of the clock pulse signal CKTW at time t1 prior to generating a rising edge of the pulse PL2 at time t4 and generating a rising edge of the selection signal PSEL at time t2. In various embodiments, the memory circuit 100 is configured to have a latch address WX during the pulse PL2. Figure 2AThe latch address WX is passed to the predecoder 140 at the rising edge of the clock pulse signal CKTW and the selection signal PSEL of a timing different from the timing depicted in the figure. Such timing includes passing the latch address WX to the predecoder 140 before or at the same time as the rising edge of the clock pulse signal CKP is generated at time t4.

[0061] As mentioned above, Figure 2A A case where each of the enable signals REB and WEB has a logic state corresponding to an enable state is depicted. In some embodiments, the memory circuit 100 is configured to respond to a case where the enable signal REB has a logic state corresponding to a disable state by generating the clock pulse signal CKP without the pulse PL1 and / or to respond to a case where the enable signal WEB has a logic state corresponding to a disable state by generating the clock pulse signal CKP without the pulse PL2.

[0062] As in Figure 2A As depicted in the non-limiting example of , the memory circuit 100 is configured to generate pulses PL1 and PL2 within an interval from time t1 to t5 that is less than a period T of the clock signal CLK. Therefore, the memory circuit 100 is able to enable read operations and write operations in the memory array 160 during a single period T of the clock signal CLK.

[0063] Figure 2B is a graph of operating parameters of the memory circuit 100 according to some embodiments. Figure 2B Depicted are non-limiting examples of word line signals WL[1]-WL[N] generated in response to received addresses RX and WX, clock signal CLK, and enable signals REB and WEB. Figure 2B The non-limiting example diagram shows four clock signal cycles TA, TB, TC, and TD, and includes each of the enable signals REB and WEB having a low logic state corresponding to an enabled state, and the word line signals WL[1]-WL[N] having a high logic state corresponding to an activated state. The address nR is a non-limiting example of the received address RX, and the address nW is a non-limiting example of the received address WX.

[0064] At the beginning of the clock signal cycle TA, the enable signal REB has a low logic state corresponding to enabling the read operation, and the enable signal WEB has a low logic state corresponding to enabling the write operation. At the beginning of the clock signal cycle TB, the enable signal REB has a low logic state corresponding to enabling the read operation, and the enable signal WEB has a high logic state corresponding to disabling the write operation. At the beginning of the clock signal cycle TC, the enable signal REB has a high logic state corresponding to disabling the read operation, and the enable signal WEB has a low logic state corresponding to enabling the write operation. At the beginning of the clock signal cycle TD, the enable signal REB has a high logic state corresponding to disabling the read operation, and the enable signal WEB has a high logic state corresponding to disabling the write operation.

[0065] Therefore, the clock pulse signal CKP generated by the circuit 100 during the clock signal period TA includes each of the pulses PL1 and PL2, during the clock signal period TB includes the pulse PL1 but not the pulse PL2, during the clock signal period TC includes the pulse PL2 but not the pulse PL1, and during the clock signal period TD includes neither the pulse PL1 nor the pulse PL2.

[0066] Figure 2B Non-limiting examples of word line signals WL[1]-WL[N] are depicted for two cases: a first case where a single word line signal WL[nR=nW] corresponds to an address nR that is the same as address nW; and a second case where word line signal WL[nR] corresponds to address nR and word line signal WL[nW] corresponds to an address nW that is different from address nR. In various embodiments, each of addresses nR and nW has a number L equal to 4, and one or both of addresses nR or nW are equal to 0000 and / or 1111.

[0067] In the first case, during the clock signal cycle TA, the decoder 150 generates a word line signal WL[nR=nW] including an activated read state in response to the address nR and the pulse PL1 and an activated write state in response to the address nW and the pulse PL2. During the clock signal cycle TB, the decoder 150 generates a word line signal WL[nR=nW] including an activated read state in response to the address nR and the pulse PL1 but not including an activated write state. During the clock signal cycle TC, the decoder 150 generates a word line signal WL[nR=nW] not including an activated read state but including an activated write state in response to the address nW and the pulse PL2. During the clock signal cycle TD, the decoder 150 generates a word line signal WL[nR=nW] including neither an activated read state nor an activated write state.

[0068] In the second case, during the clock signal cycle TA, the decoder 150 generates a word line signal WL[nR] including an activated read state in response to the address nR and the pulse PL1 but not including an activated write state, and generates a word line signal WL[nW] not including an activated read state but including an activated write state in response to the address nW and the pulse PL2. During the clock signal cycle TB, the decoder 150 generates a word line signal WL[nR] including an activated read state in response to the address nR and the pulse PL1 but not including an activated write state, and generates a word line signal WL[nW] not including an activated read state and not including an activated write state. During the clock signal cycle TC, the decoder 150 generates a word line signal WL[nR] not including an activated read state and not including an activated write state, and generates a word line signal WL[nW] not including an activated read state but including an activated write state in response to the address nW and the pulse PL2. During the clock signal period TD, the decoder 150 generates a word line signal WL[nR] that does not include an active read state and does not include an active write state, and generates a word line signal WL[nW] that does not include an active read state and does not include an active write state.

[0069] Through the configuration discussed above, the memory circuit 100 is able to select and decode one of the two addresses corresponding to the data movement operation in the memory array 160 using the decoder 150 and the selection circuit 120 during a single clock cycle. Therefore, compared with the method of using a separate decoder for each of the two addresses in the memory array data movement operation during a single clock cycle, the area requirement of the memory circuit 100 is reduced.

[0070] A significant reduction in area is achieved by reducing the number of data lines used to activate a given word in the memory array.By reducing the number of decoders from two to one, the number of data lines carrying enable signals used to activate a given word is similarly reduced from two to one.

[0071] Figure 3A and Figure 3B is a diagram of a control circuit 300 according to some embodiments. The control circuit 300 may be used as described above with respect to the memory circuit 100 and Figure 1-2B Control circuit 170 discussed.

[0072] Figure 3A A signal generating portion of the control circuit 300 is depicted, which is configured to generate various signals including a select signal PSEL based on a clock signal CLK and enable signals REB and WEB. Figure 3B A clock buffer portion of the control circuit 300 is depicted, which is configured to generate clock pulse signals CKTW, CKTR, and CKP based on various signals, as described below.

[0073] The signal generating section of the control circuit 300 includes latch circuits 310 and 320, signal generating circuits 330, 340, and 350, port tracking circuits 360 and 370, an OR gate OR1 and a NAND gate NAND1. The clock buffer section of the control circuit 300 includes an inverter INV1 and NAND gates NAND2 and NAND3.

[0074] The output of latch circuit 310 is coupled to the input of signal generating circuit 330 and the input of OR gate OR1. The output of latch circuit 320 is coupled to the input of signal generating circuit 350 and the input of OR gate OR1. The output of OR gate OR1 is coupled to the input of signal generating circuit 340.

[0075] The output of signal generating circuit 330 is coupled to the input of NAND gate NAND1, the output of signal generating circuit 340 is coupled to the other input of NAND gate NAND1, and the output of signal generating circuit 350 is coupled to the input of port tracking circuit 370. The output of NAND gate NAND1 is coupled to the input of port tracking circuit 360.

[0076] The output of port tracking circuit 360 is coupled to the input of signal generating circuit 330 and the input of signal generating circuit 340. The output of port tracking circuit 370 is coupled to the input of signal generating circuit 350.

[0077] The latch circuit 310 is an electronic circuit configured to receive the enable signal REB and the clock signal CLK, and latch and output the enable signal REB to the signal generating circuit 330 and the OR gate OR1 in response to the clock signal CLK.

[0078] The latch circuit 320 is an electronic circuit configured to receive the enable signal WEB and the clock signal CLK, and latch and output the enable signal WEB to the signal generating circuit 350 and the OR gate OR1 in response to the clock signal CLK.

[0079] The OR gate OR1 is a logic gate configured to receive the latched enable signals REB and WEB and output the enable signal RWEB to the signal generating circuit 340 in response to the latched enable signals REB and WEB.

[0080] The signal generating circuit 330 is an electronic circuit configured to receive the clock signal CLK, the latched enable signal REB, and the reset signal RSC1, and output the clock pulse signal CKPB1 to the NAND gates NAND1 and NAND3 and the inverter INV1 in response to the clock signal CLK, the latched enable signal REB, and the reset signal RSC1. The signal generating circuit 330 is configured to generate the following Figure 4A and Figure 4B In some embodiments, the signal generating circuit 330 is as follows: Figure 5 The signal generating circuit 500 is discussed.

[0081] The signal generating circuit 340 is an electronic circuit configured to receive the clock signal CLK, the enable signal RWEB, and the reset signal RSC1, and output the clock pulse signal CKPB1_TRK to the NAND gates NAND1 and NAND2 in response to the clock signal CLK, the enable signal RWEB, and the reset signal RSC1. The signal generating circuit 340 is configured to generate the following Figure 4A and Figure 4B In some embodiments, the signal generating circuit 340 is as follows: Figure 5 The signal generating circuit 500 is discussed.

[0082] The signal generating circuit 350 is an electronic circuit configured to receive the clock pulse signal CKP1_TRK, the latch enable signal WEB, and the reset signal RSC2, and in response to the clock pulse signal CKP1_TRK, the latch enable signal WEB, and the reset signal RSC2, output the clock pulse signal CKPB2 to the port tracking circuit 370 and the NAND gates NAND2 and NAND3, output the reset signal RSTCKB to the NAND gate NAND2, and Figure 1 and Figure 2A The signal generation circuit 330 is configured to generate the following signal: Figure 4A The clock pulse signal CKPB2, reset signal RSTCKB, and selection signal PSEL of the logic state transition discussed. In some embodiments, the signal generation circuit 350 is as follows Figure 6 The signal generating circuit 600 is discussed.

[0083] The NAND gate NAND1 is a logic gate configured to receive the clock pulse signals CKPB1 and CKPB1_TRK and output the clock pulse signal CKP1_TRK to the port tracking circuit 360 in response to the clock pulse signals CKPB1 and CKPB1_TRK.

[0084] The port tracking circuit 360 is an electronic circuit configured to receive the clock pulse signal CKP1_TRK and generate a reset signal RSC1 in response to the timing of a tracking circuit (not shown), the tracking circuit being configured to replicate a read operation using port P1 and being initiated by the clock pulse signal CKP1_TRK, thereby generating the reset signal RSC1 including a logic state transition after a sufficiently long tracking interval to ensure that the read operation is completed on port P1.

[0085] The port tracking circuit 370 is an electronic circuit configured to receive the clock pulse signal CKPB2 and generate a reset signal RSC2 in response to the timing of a tracking circuit (not shown), the tracking circuit being configured to replicate a write operation using port P2 and initiated by the clock pulse signal CKPB2, thereby generating the reset signal RSC2 including a logic state transition after a sufficiently long tracking interval to ensure that the write operation is completed on port P2.

[0086] The inverter INV1 is a logic gate configured to receive the clock pulse signal CKPB1 and output the inverted clock pulse signal CKPB1 as described above. Figure 1 and Figure 2A Discuss and below about Figure 4B The clock pulse signal CKTR discussed.

[0087] The NAND gate NAND2 is a logic gate configured to receive the clock pulse signals CKPB1_TRK and CKPB2 and the reset signal RSTCKB, and output the above-mentioned Figure 1 and Figure 2A Discuss and below about Figure 4B The clock pulse signal CKTW is discussed.

[0088] The NAND gate NAND3 is a logic gate configured to receive the clock pulse signals CKPB1 and CKPB2 and output the above related Figure 1-2B Discuss and below about Figure 4B The clock pulse signal CKP discussed.

[0089] Figure 4A and Figure 4B is a graph of operating parameters of the memory circuit 100 and the control circuit 300 according to some embodiments. Figure 4A and Figure 4BIn the non-limiting example depicted in , signals CLK, CKPB1, CKPB1_TRK, CKP1_TRK, RSC1, RSTCKB, CKPB2, RSC2, PSEL, CKP, CKTR, and CKTW include transitions T1-T24 between high logic states and low logic states corresponding to operation of control circuit 300, as described below. Figure 4A and Figure 4B The case where the enable signals REB, WEB, and thus RWEB have logic states corresponding to the enable state is depicted and are not shown for clarity.

[0090] like Figure 4A As depicted in , transition T1 is the rising edge of the clock signal CLK. In response to transition T1, the signal generating circuit 330 generates transition T2, which is the falling edge of the clock pulse signal CKPB1, and the signal generating circuit 340 generates transition T3, which is the falling edge of the clock pulse signal CKPB1_TRK. Figure 4A and Figure 4B In the case depicted in FIG. 1 , where both signal generating circuits 330 and 340 are enabled, transitions T2 and T3 are generated simultaneously. In response to either transition T2 or T3, NAND gate NAND1 generates transition T4, ie, the rising edge of clock pulse signal CKP1_TRK.

[0091] In response to transition T4, the signal generating circuit 350 generates transition T5, i.e., a falling edge of the reset signal RSTCKB, and in response to transition T5, generates transition T6, i.e., a rising edge of the selection signal PSEL. In response to transition T4, and after the tracking interval discussed above, the port tracking circuit 360 generates transition T7, i.e., a falling edge of the reset signal RSC1.

[0092] In response to transition T7, signal generating circuit 330 generates transition T8, i.e., a rising edge of clock pulse signal CKPB1, and signal generating circuit 340 generates transition T9, i.e., a rising edge of clock pulse signal CKPB1_TRK. In response to transitions T8 and T9, NAND gate NAND1 generates transition T10, i.e., a falling edge of clock pulse signal CKP1_TRK.

[0093] In response to transition T10, signal generation circuit 350 generates transition T11, ie, a falling edge of clock pulse signal CPKB2. In response to transition T11, and after the tracking interval discussed above, port tracking circuit 370 generates transition T12, ie, a falling edge of reset signal RSC2.

[0094] In response to transition T12 , the signal generating circuit 350 generates transition T13 , ie, a rising edge of the reset signal RSTCKB, and transition T14 , ie, a rising edge of the clock pulse signal CKPB2 .

[0095] In response to the transition T14 , the port tracking circuit 370 generates a transition T15 , ie, a rising edge of the reset signal RSC2 , and the signal generating circuit 350 generates a transition T16 , ie, a falling edge of the selection signal PSEL.

[0096] like Figure 4B As shown, in response to transitions T2 and T8, i.e., the corresponding falling and rising edges of the clock signal CKPB1, the NAND gate NAND3 generates transitions T17 and T18. Transitions T17 and T18, i.e., the corresponding rising and falling edges of the pulse PL1 of the clock signal CKPB1, correspond to the pulse width of the pulse PL1 based on the clock signal CKPB1.

[0097] In response to transitions T11 and T14, ie, the corresponding falling and rising edges of the clock signal CKPB2, the NAND gate NAND3 generates transitions T19 and T20. Transitions T19 and T20, ie, the corresponding rising and falling edges of the pulse PL2 of the clock signal CKPB2, thus correspond to the pulse width of the pulse PL2 based on the clock signal CKPB2.

[0098] In response to transitions T2 and T8 , ie, the respective falling and rising edges of the clock pulse signal CKPB1 , the inverter INV1 generates transitions T21 and T22 , ie, the respective rising and falling edges of the clock pulse signal CKTR.

[0099] In response to transitions T3 and T14 , ie, the respective falling edge of the clock pulse signal CKPB1_TRK and the rising edge of the clock pulse signal CKPB2 , the NAND gate NAND2 generates transitions T23 and T24 , ie, the respective rising and falling edges of the clock pulse signal CKTW.

[0100] Transition T17 is generated by the NAND gate NAND3 in response to transition T2, whereby a single gate delay is generated after transition T2, which single gate delay is a time interval corresponding to a logic state transition in a logic gate. Transition T21 is generated by the inverter INV1 in response to transition T2, whereby a single gate delay is generated after transition T2. ​​Transition T23 is generated by the NAND gate NAND2 in response to transition T3 and simultaneously in response to transition T2, whereby a single gate delay is generated after transition T2.

[0101] By delaying each of transitions T17, T21, and T23 (the rising edge of the respective clock pulse signals CKP, CKTR, and CKTW) by a single gate after transition T2, the control circuit 300 is configured to generate the rising edge of the respective clock pulse signals CKP, CKTR, and CKTW at or near time t1, as described above with respect to Figure 2A As discussed.

[0102] Transition T4 is generated by NAND gate NAND1 in response to either of simultaneous transitions T2 or T3, and is thus delayed by a single gate after transition T2. ​​Transition T6 is generated by signal generation circuit 350 in response to transition T4, and is thus delayed by at least one gate after transition T4, and by at least two gates after transition T2.

[0103] By delaying transition T6 (ie, the rising edge of the select signal PSEL) by at least two gates after transition T2, the control circuit 300 is configured to generate the rising edge of the select signal PSEL at time t2 after time t1, as described above with respect to Figure 2A As discussed, it is thereby ensured that the latch circuit 130 has latched the address RX based on the transition T21 of the clock pulse signal CKTR before the selection circuit 120 stops passing the address RX to the latch circuit 130 based on the rising edge of the selection signal PSEL.

[0104] Since transition T18 (i.e., the falling edge of pulse PL1 of clock pulse signal CKP) and transition T22 (i.e., the falling edge of clock pulse signal CKTR) are respectively followed by a tracking interval after transition T7 (i.e., the falling edge of reset signal RSC1), control circuit 300 is configured to cause partially decoded address PD to be outputted from predecoder 140 based on latched address RX until time t3, as described above with respect to Figure 2A As discussed, it is ensured that the corresponding read operation is completed before the signal transitions T18 and T22.

[0105] By making transition T16 (ie, the falling edge of the selection signal PSEL) after transitions T18 and T22, the control circuit 300 is configured to make the selection circuit 120 and the latch circuit 130 pass the latch address WX to the predecoder 140 after the corresponding read operation is completed.

[0106] The control circuit 300 is configured to provide an interval from time t3 to time t4 by causing transition T9 (the rising edge of pulse PL2 of clock pulse signal CKP) to follow transition T18 (i.e., the falling edge of pulse PL1 of clock pulse signal CKP), as discussed above with respect to FIG. 4 , thereby ensuring that the latch address WX is passed to the pre-decoder 140 before a subsequent write operation begins.

[0107] By including the OR gate OR1, the signal generating circuits 330 and 340, and the NAND gate NAND1, the control circuit 300 is configured to generate a transition T10 in the clock pulse signal CKP1_TRK in response to either of the enable signals REB or WEB having a logic state corresponding to the enable state, so that the pulse PL2 of the clock pulse signal CKP starts at time t4, so that the write operation has a timing relative to the clock signal CLK regardless of performing a read operation.

[0108] As described above, transition T12 (i.e., the falling edge of the reset signal RSC2) occurs after the tracking interval corresponding to the write operation has elapsed. Transition T14 (i.e., the rising edge of the clock pulse signal CKPB2) is after transition T12. Since transition T20 (i.e., the falling edge of the pulse PL2 of the clock pulse signal CKP) and transition T24 (i.e., the falling edge of the clock pulse signal CKTW) are after transition T14, the control circuit 300 is configured so that the partially decoded address PD is output from the predecoder 140 based on the latched address WX until time t5, as described above with respect to Figure 2A As discussed above, it is ensured that the corresponding write operation is completed before the signal transitions T20 and T24.

[0109] As mentioned above, Figure 4A and Figure 4B The case where each of the enable signals REB and WEB has a logic state corresponding to the enable state is depicted. In the case where the enable signal REB has a logic state corresponding to the disable state, the signal generation circuit 330 is configured so that transitions T2 and T8 in the clock pulse signal CKPB1 are not generated, and the control circuit 300 is thereby configured to respond to the disable state by generating the clock pulse signal CKP without the pulse PL1, as described above with respect to Figure 2B As discussed, the predecoder 140 does not output the partially decoded address PD during the interval from time t1 to time t3.

[0110] In the case where the enable signal WEB has a logic state corresponding to the disabled state, the signal generation circuit 350 is configured so that transitions T11 and T14 in the clock pulse signal CKPB2 are not generated, and the control circuit 300 is thereby configured to respond to the disabled state by generating the clock pulse signal CKP without the pulse PL2, as described above with respect to Figure 2B As discussed, the predecoder 140 does not output the partially decoded address PD during the interval from time t4 to time t5.

[0111] In addition to the above Figure 3A and Figure 3BIn addition to the timing characteristics discussed in the configuration depicted in FIG. 1 , the control circuit 300 can be based on the above-described memory circuit 100 and Figure 1-2B The clock signal CLK and the enable signals REB and WEB of the discussed timing control and benefit generate the clock pulse signals CKTW, CKTR, and CKP, and the selection signal PSEL.

[0112] Figure 5 is a diagram of a signal generating circuit 500 according to some embodiments. The signal generating circuit 500 may be used as described above with respect to the control circuit 300 and Figure 3A-Figure 4B One or both of the signal generating circuits 330 or 340 in question.

[0113] The signal generating circuit 500 includes p-type metal oxide semiconductor (PMOS) transistors P1 - P7 , n-type metal oxide semiconductor (NMOS) transistors N1 - N7 , and logic gates inverters INV2 - INV4 and a NOR gate NOR1 .

[0114] Transistors P1, N1, and N2 are coupled in series between a power supply node VDD and a reference node VSS. A source terminal of transistor P1 is coupled to the power supply node VDD, a drain terminal of transistor P1 is coupled to a drain terminal of transistor N1, a source terminal of transistor N1 is coupled to a drain terminal of transistor N2, and a source terminal of transistor N2 is coupled to the reference node VSS.

[0115] Transistors P2 and P3 are coupled in series with each other and in parallel with transistor P1. A source terminal of transistor P2 is coupled to power supply node VDD, a drain terminal of transistor P2 is coupled to a source terminal of transistor P3, and a drain terminal of transistor P3 is coupled to drain terminals of transistors P1 and N1.

[0116] The transistor N3 is coupled in parallel with the transistor N2. A drain terminal of the transistor N3 is coupled to a drain terminal of the transistor N2, and a source terminal of the transistor N3 is coupled to a reference node VSS.

[0117] Transistors P4, P5, N4, and N5 are coupled in series between a power supply node VDD and a reference node VSS. A source terminal of transistor P4 is coupled to the power supply node VDD, a drain terminal of transistor P4 is coupled to a source terminal of transistor P5, a drain terminal of transistor P5 is coupled to a drain terminal of transistor N4, a source terminal of transistor N4 is coupled to a drain terminal of transistor N5, and a source terminal of transistor N5 is coupled to the reference node VSS.

[0118] Transistors P6, P7, N6, and N7 are coupled in series between a power supply node VDD and a reference node VSS. A source terminal of transistor P6 is coupled to the power supply node VDD, a drain terminal of transistor P6 is coupled to a source terminal of transistor P7, a drain terminal of transistor P7 is coupled to a drain terminal of transistor N6, a source terminal of transistor N6 is coupled to a drain terminal of transistor N7, and a source terminal of transistor N7 is coupled to the reference node VSS.

[0119] The drain terminals of transistors P4 and P6 are coupled to the source terminals of transistors P5 and P7, and the gates of transistors P5 and P7 are configured to receive the reset signal RSC1, as described above with respect to control circuit 300 and Figure 3A-Figure 4B As discussed, the gates of transistors P6 and N4 are configured to receive the clock signal CLK.

[0120] The drain terminals of transistors P5, P7, N4, and N6 are coupled to each other and to the output OUT1, and are thereby configured to output the above-described control circuit 300 and Figure 3A-Figure 4B One of the clock pulse signals CKPB1 or CKPB1_TRK is discussed.

[0121] The inverter INV2 is coupled to the gates of the transistors P2 and N2 and is thus configured to receive the clock signal CLK and output the inverted clock signal CLK as the clock signal CLKB to the gates of the transistors P2 and N2.

[0122] The inverter INV3 is coupled between the inverter INV4 and the gates of the transistors P1 and N1 , and is thereby configured to output a signal CKP1B to the gates of the transistors P1 and N1 .

[0123] The inverter INV4 is coupled between the output OUT1 and the inverter INV3 and the gates of the transistors P7 and N6 , and is thus configured to output the inverted clock pulse signal CKPB1 or CKPB1_TRK to the inverter INV3 and the gates of the transistors P7 and N6 .

[0124] The NOR gate NOR1 is coupled to the drains of the transistors P1, P3, and N1 and the gates of the transistors P3, P4, N3, and N5, and is thereby configured to receive the signal CEB, which is the signal CEB described above with respect to the memory circuit 100, the control circuit 300, and Figure 1-4B The latch enable signal CLK_EN is discussed as complementing one of the latch enable signals REB or RWEB, and outputs the signal CLK_EN to the gates of transistors P3, P4, N3, and N5.

[0125] In operation, the initial state of the signal generating circuit 500 includes the clock signal CLK having a low logic state, the signal CEB having a low logic state corresponding to the activation of the signal generating circuit 500, the reset signal RSC1 having a high logic state, and the clock pulse signal CKPB1 or CKPB1_TRK having a high logic state.

[0126] In response to the clock signal CLK having a low logic state, the inverter INV2 outputs the signal CLKB having a high logic state, thereby turning off the transistor P2 and turning on the transistor N2 and configuring the transistors P1 and N1 as inverters.

[0127] The reset signal RSC1 having a high logic state turns off the transistor P5 , and the clock signal CLK having a low logic state turns off the transistor N4 , thereby decoupling the output OUT1 from the transistors P4 and N5 .

[0128] The clock signal CLK having a low logic state turns on the transistor P6 , and the reset signal RSC1 having a high logic state turns on the transistor N7 , thereby configuring the transistors P7 and N6 as an inverter cross-coupled with the inverter INV4 .

[0129] In response to the signal CEB having a low logic state, the NOR gate NOR1 outputs the signal CLK_EN in response to the logic states of the drains of the transistors P1 , P3 , and N1 .

[0130] In response to the clock pulse signal CKPB1 or CKPB1_TRK having a high logic state, the inverter INV4 outputs a low logic state, and the inverter INV3 outputs a signal CKP1B having a high logic state, thereby turning off the transistor P1 and turning on the transistor N1. The drains of the transistors P1, P3, and N1 have a low logic state, and the NOR gate NOR1 outputs a signal CLK_EN having a high logic state, thereby turning off the transistors P3 and P4 and turning on the transistors N3 and N5.

[0131] In response to the above description of the control circuit 300 and Figures 3A-4B In the transition T1 of the clock signal CLK in question, the clock signal CLK having a high logic state turns off the transistor P6 and turns on the transistor N4, thereby decoupling the output OUT1 from the power supply node VDD, coupling the output OUT1 to the reference node VSS through the transistors N4 and N5, and causing the generated clock pulse signal CKPB1 or CKPB1_TRK to have a low logic state. The change of the clock pulse signal CKPB1 or CKPB1_TRK from the high logic state to the low logic state corresponds to the above description of the control circuit 300 and Figure 3A-Figure 4B The corresponding transition in question is T2 or T3.

[0132] In response to the clock signal CLK having a high logic state, the inverter INV2 outputs the signal CLKB having a low logic state, thereby turning on the transistor P2 and turning off the transistor N2.

[0133] In response to the clock pulse signal CKPB1 or CKPB1_TRK having a low logic state, the inverter INV4 outputs a high logic state, and the inverter INV3 outputs a signal CKP1B having a low logic state, thereby turning on the transistor P1 and turning off the transistor N1. The drains of the transistors P1, P3, and N1 have a high logic state, and the NOR gate NOR1 outputs a signal CLK_EN having a low logic state, thereby turning on the transistors P3 and P4 and turning off the transistors N3 and N5.

[0134] Due to gate delays introduced by inverter INV3, transistors P1 and N1, and NOR gate NOR1, transistor N5 is turned off after transistor N7 is turned on, and output OUT1 is coupled to reference node VSS through transistors N6 and N7.

[0135] In response to the above description of the control circuit 300 and Figure 3A-Figure 4B The transition T7 of the reset signal RSC1 discussed, the reset signal RSC1 having a low logic state turns on the transistor P5 and turns off the transistor N7, thereby decoupling the output OUT1 from the reference node VSS, coupling the output OUT1 to the power supply node VDD through the transistors P4 and P5, and causing the generated clock pulse signal CKPB1 or CKPB1_TRK to have a high logic state. The clock pulse signal CKPB1 or CKPB1_TRK that changes from a low logic state to a high logic state corresponds to the above description of the control circuit 300 and Figure 3A-Figure 4B The corresponding transition in question is T8 or T9.

[0136] pass Figure 5 In the configuration depicted in and discussed above, the signal generating circuit 500 can respond to the above-described memory circuit 100, the control circuit 300, and Figure 1-4B The clock signal CLK, the corresponding enable signal REB or RWEB, and the reset signal RSC1 of the discussed timing control and benefits generate each of the clock pulse signals CKPB1 or CKPB1_TRK.

[0137] Figure 6 6 is a diagram of a signal generating circuit 600 according to some embodiments. The signal generating circuit 600 may be used as described above with respect to the control circuit 300 and Figure 3A-Figure 4B The signal generating circuit 350 in question.

[0138] The signal generating circuit 600 includes logic gates NAND gates NAND4 - NAND8 , inverters INV5 - INV7 , and NOR gates NOR2 and NOR3 , a delay circuit 610 , and word tracking circuits 620 and 630 .

[0139] The NAND gate NAND4 includes inputs configured to receive the clock pulse signal CKP1_TRK, the enable signal WEB, and the reset signal RSC2 , and an output coupled to the input of the NAND gate NAND5 .

[0140] The NAND gate NAND5 includes an input coupled to the output of the NAND gate NAND6 and an output coupled to the input of the NAND gate NAND6 and the input of the inverter INV5. The NAND gate NAND6 includes an input configured to receive the reset signal RSC2.

[0141] Inverter INV5 includes an output coupled to an input of NOR gate NOR2 and an input of NAND gate NAND8, and is thus configured to output reset signal RSTCKB. NOR gate NOR2 includes an input configured to receive clock pulse signal CKP1_TRK, and an output coupled to input of delay circuit 610 and NAND gate NAND7, and is thus configured to output signal TRK_EN.

[0142] Inverter INV6 includes an input coupled to delay circuit 610 and an output coupled to word tracking circuit 620. Inverter INV7 includes an input coupled to delay circuit 610 and an output coupled to word tracking circuit 630. NOR gate NOR3 includes an output coupled to each of word tracking circuits 620 and 630, and an output coupled to an input of NAND gate NAND7, and is thereby configured to output signal CKP2_PRE to NAND gate NAND7.

[0143] The NAND gate NAND7 includes an input coupled to the NAND gate NAND8 and is configured to output the control circuit 300 and Figure 3A-Figure 4B The NAND gate NAND8 is configured to output the clock pulse signal CKPB2 discussed above. Figure 1-4B The selection signal PSEL in question.

[0144] The delay circuit 610 is a configurable electronic circuit configured to delay the signal TRK_EN output from the NOR gate NOR2 by an interval determined by the signal PTSEL[1:0] and output the delayed signal TRK_EN. Figure 6In the embodiment depicted in , the delay circuit 610 is configured to receive the signal PTSEL[1:0] having one of four logic state combinations, and output the signal TRK_EN having a corresponding delay equal to zero, two, four, or six gate delays. In various embodiments, the delay circuit 610 is configured to receive the signal PTSEL[1:0] having less than or more than four logic state combinations, and output the signal TRK_EN having a corresponding delay equal to a set of gate delays other than zero, two, four, or six gate delays.

[0145] In various embodiments, the signal PTSEL[1:0] includes logic states corresponding to voltage levels or short circuits and open circuits configured by jumpers, pins, or other suitable conductive elements.

[0146] In operation, the configurable delay introduced by the delay circuit 610 in response to the signal PTSEL[1:0] is included in the timing of the clock pulse signal CKPB2 and the select signal PSEL, as described below. Therefore, the timing of the clock pulse signal CKPB2 and the select signal PSEL includes a total delay that includes a predetermined delay component based on the configuration of the delay circuit 610. Since the predetermined delay component is based on the signal PTSEL[1:0], the delay circuit 610 enables the timing control to be adjusted based on the user input of the application in which the signal generation circuit 600 is being used to reflect the timing requirements.

[0147] Each of the word tracking circuits 620 and 630 is an electronic circuit configured to receive the signal TRK_EN delayed by the delay circuit 610 and inverted by the corresponding inverter INV6 or INV7, and generate an output signal in response to the timing of a tracking circuit (not shown) configured to replicate a write operation using the port P2 and enabled by the delayed and inverted signal TRK_EN. Therefore, each of the word tracking circuits 620 and 630 is configured to generate an output signal including a logic state transition after a sufficiently long tracking interval to ensure that the write operation is completed on the port P2.

[0148] The word tracking circuits 620 and 630 include tracking circuits configured to track various aspects of a write operation such that the output signals generated by the tracking circuits 620 and 630 include separate timing information. In some embodiments, the word tracking circuit 620 includes tracking circuits configured to track various aspects of a write operation based on a memory array (e.g., as described above with respect to the memory circuits 100 and Figure 1-2B In some embodiments, the word tracking circuit 630 includes a tracking circuit configured to track the depth of a word line within a column of the memory array (e.g., as discussed above with respect to the memory circuit 100 and Figure 1-2BThe timing is tracked by the width of the columns of the memory array 160 in question.

[0149] In operation, the initial state of the signal generating circuit 600 includes: a clock pulse signal CKP1_TRK having a low logic state, an enable signal WEB having a high logic state corresponding to the activation of the signal generating circuit 600, a reset signal RSC2 having a high logic state, and the NAND gate NAND5 outputting a low logic state is latched to the NAND gate NAND6 outputting a high logic state.

[0150] In response to the clock pulse signal CKP1_TRK having a low logic state, the NAND gate NAND4 outputs a high logic state to the NAND gate NAND5. In response to the NAND gate NAND5 having a low logic state, the inverter INV5 outputs the reset signal RSTCKB having a high logic state.

[0151] In response to the clock pulse signal CKP1_TRK having a low logic state and the reset signal RSTCKB having a high logic state, the NOR gate NOR2 outputs the signal TRK_EN having a low logic state. In response to the signal TRK_EN having a low logic state, the delay circuit 610 outputs a low logic state to each of the inverters INV6 and INV7, each of the inverters INV6 and INV7 outputs a high logic state to the corresponding word tracking circuit 620 or 630, each of the word tracking circuits 620 and 630 outputs a high logic state to the NOR gate NOR3, and the NOR gate NOR3 outputs the signal CKP2_PRE having a low logic state.

[0152] In response to the signal CKP2_PRE having a high logic state and the signal TRK_EN having a low logic state, the NAND gate NAND7 outputs the clock pulse signal CKPB2 having a high logic state.

[0153] In response to the clock pulse signal CKPB2 having a high logic state and the reset signal RSTCKB having a high logic state, the NAND gate NAND8 outputs the selection signal PSEL having a low logic state.

[0154] As the transition T4 of the clock pulse signal CKP1_TRK (as described above with respect to the control circuit 300 and Figure 3A-Figure 4B As a result of the clock pulse signal CKP1_TRK having a high logic state, the NAND gate NAND4 outputs a low logic state, the NAND gate NAND5 outputs a high logic state, and the inverter INV5 outputs the reset signal RSTCKB having a low logic state. The reset signal RSTCKB changes from a high logic state to a low logic state corresponding to the above description of the control circuit 300 and Figure 3A-Figure 4B The transformation in question is T5.

[0155] In response to the clock pulse signal CKP1_TRK having a high logic state and the reset signal RSTCKB having a low logic state, the NOR gate NOR2 continues to output the signal TRK_EN having a low logic state, the NOR gate NOR3 continues to output the signal CKP2_PRE having a high logic state, and the NAND gate NAND7 continues to output the clock pulse signal CKPB2 having a high logic state.

[0156] In response to the clock pulse signal CKPB2 having a high logic state and the reset signal RSTCKB having a low logic state, the NAND gate NAND8 outputs the selection signal PSEL having a high logic state. The change of the selection signal PSEL from the low logic state to the high logic state corresponds to the above description of the control circuit 300 and Figure 3A-Figure 4B The transformation in question is T6.

[0157] As the transition T10 of the clock pulse signal CKP1_TRK (as described above with respect to the control circuit 300 and Figure 3A-Figure 4B As a result of the clock pulse signal CKP1_TRK having a low logic state, the NAND gate NAND4 outputs a high logic state in response to the clock pulse signal CKP1_TRK having a low logic state, and the NAND gate NAND5 continues to output a high logic state in response to the NAND gate NAND6 outputting a low logic state. Therefore, the inverter INV5 continues to output the reset signal RSTCKB having a low logic state.

[0158] In response to each of the clock pulse signal CKP1_TRK and the reset signal RSTCKB having a low logic state, the NOR gate NOR2 outputs the signal TRK_EN having a high logic state. In response to the signal TRK_EN having a high logic state, the delay circuit 610 initially continues to output a low logic state, the NOR gate NOR3 continues to output the signal CKP2_PRE having a low logic state, and the NAND gate NAND7 continues to output the clock pulse signal CKPB2 having a high logic state.

[0159] After the configurable delay discussed above, delay circuit 610 outputs a high logic state to each of inverters INV6 and INV7 , and each of inverters INV6 and INV7 outputs a low logic state to corresponding word tracking circuits 620 and 630 .

[0160] Based on the timing discussed above, each of the word tracking circuits 620 and 630 responds to the received low logic state by outputting a low logic state after a corresponding tracking delay. Before both the word tracking circuits 620 and 630 output the low logic state, the NOR gate NOR3 continues to output the signal CKP2_PRE having a low logic state. In response to both the word tracking circuits 620 and 630 outputting the low logic state, the NOR gate NOR3 outputs the signal CKP2_PRE having a high logic state.

[0161] In response to the output signal CKP2_PRE and the signal TRK_EN having a high logic state, the NAND gate NAND7 outputs the clock pulse signal CKPB2 having a low logic state. The clock pulse signal CKPB2 changes from a high logic state to a low logic state corresponding to the above description of the control circuit 300 and Figure 3A-Figure 4B The transformation in question is T11.

[0162] In response to each of the clock pulse signal CKPB2 and the reset signal RSTCKB having a low logic state, the NAND gate NAND8 continues to output the selection signal PSEL having a high logic state.

[0163] In response to the transition T12 of the reset signal RSC2 (as described above with respect to the control circuit 300 and Figure 3A-Figure 4B As discussed above), the reset signal RSC2 has a low logic state. In response to the reset signal RSC2 having a low logic state, the NAND gate NAND6 outputs a high logic state, the NAND gate NAND5 outputs a low logic state, and the inverter INV5 outputs the reset signal RSTCKB having a high logic state. The reset signal RSTCKB changes from a low logic state to a high logic state corresponding to the above description of the control circuit 300 and Figure 3A-Figure 4B The transformation in question is T13.

[0164] In response to the clock pulse signal CKP1_TRK having a low logic state and the reset signal RSTCKB having a high logic state, the NOR gate NOR2 outputs the signal TRK_EN having a low logic state. In response to the signal TRK_EN having a low logic state and the signal CKP2_PRE having a low logic state or a high logic state, the NAND gate NAND7 outputs the clock pulse signal CKPB2 having a high logic state. The clock pulse signal CKPB2 changes from a low logic state to a high logic state corresponding to the above description of the control circuit 300 and Figure 3A-Figure 4B The transformation in question is T14.

[0165] In response to each of the clock pulse signal CKPB2 and the reset signal RSTCKB having a high logic state, the NAND gate NAND8 outputs the selection signal PSEL having a low logic state. The change of the selection signal PSEL from the high logic state to the low logic state corresponds to the above description of the control circuit 300 and Figure 3A-Figure 4B The conversion in question is T16.

[0166] pass Figure 6 The configuration depicted in FIG. 1 and as described above, the signal generating circuit 600 can respond to the memory circuit 100, the control circuit 300, and Figure 1-4B The clock pulse signal CKP1_TRK, the enable signal WEB, and the reset signal RSC2 of the discussed timing control and benefits generate the clock pulse signal CKPB2, the reset signal RSTCKB, and the selection signal PSEL.

[0167] In addition, through Figure 6 With the configuration depicted in FIG. 6 and as described above, the signal generating circuit 600 is able to generate the select signal PSEL including self-timing that ensures that the read and write addresses are latched without requiring additional timing circuits.

[0168] Fig. 7A and Figure 7B is a graph of operating parameters of the memory circuit 100 and the control circuit 300 according to some embodiments. Fig. 7A and 7B In the embodiment depicted in FIG. 1 , the memory circuit 100 is configured to generate a clock pulse signal CKTR having a high logic state during a write operation, thereby causing the latch circuit 130 to latch the address WX during the write operation. The memory circuit 100 is configured to generate a clock pulse signal CKTW having a high logic state, thereby causing the latch circuit 110 to latch the address WX during the write operation. Fig. 7A In each write operation in the embodiment shown, Figure 7B In the illustrated embodiment, address WX is latched as part of each write operation.

[0169] Fig. 7A and Figure 7B Each of the non-limiting examples depicted in FIG. 1 includes transitions T2, T3, T6, T8, T11, T14, and T16-T24 (each of which is described above with respect to Figure 1-4B , and PSEL, and the clock pulse signal CKTR including transitions T25 and T26 discussed below. Fig. 7A and Figure 7B1 depicts a case in which each of the enable signals REB and WEB has a logic state corresponding to an enable state and is not shown for clarity.

[0170] exist Fig. 7A and Figure 7B In the embodiment depicted in , the control circuit 300 is configured to generate a transition T25 , ie, a rising edge of the clock pulse signal CKTR, in response to the transition T11 , and to generate a transition T26 , ie, a falling edge of the clock pulse signal CKTR, in response to the transition T14 .

[0171] In operation, transition 25 causes latch circuit 130 to latch address WX received from selection circuit 120 and output the latched address WX to predecoder 140 based on the high logic state of selection signal PSEL. Because latch circuit 130 is configured to output latched address WX as long as clock pulse signal CKTR has a high logic state, the logic states of clock pulse signal CKTW and selection signal PSEL between transitions 25 and 26 do not affect latch circuit 130 outputting latched address WX to predecoder 140 during pulse PL2 of clock pulse signal CKP.

[0172] and Figure 3A-Figure 4B In contrast to the embodiment depicted in Fig. 7A and Figure 7B In each of the embodiments depicted in FIG. 1 , the control circuit 300 is configured to generate a transition T16 in the selection signal PSEL in response to a transition T11 in the clock pulse signal CKPB2 and after at least one gate delay. The control circuit 300 is thus configured to generate a transition T16 after the latch circuit 130 has the latch address WX based on the transition T25 and before the latch circuit 130 no longer outputs the latch address WX based on the transition T26.

[0173] and Figure 3A-Figure 4B as well as Fig. 7A In contrast to the embodiment depicted in Figure 7B In the embodiment depicted in FIG. 1 , the control circuit 300 is configured to generate T24 in the clock pulse signal CKTW in response to transition T11 in the clock pulse signal CKPB2 and after at least one gate delay. The control circuit 300 is thus configured to generate transition T24 after the latch circuit 130 has the latch address WX based on transition T25 and before the latch circuit 130 no longer outputs the latch address WX based on transition T26.

[0174] exist Fig. 7A and Figure 7BIn the embodiment depicted in FIG. 1 , the control circuit 300 is thus configured to cause the latch circuit 130 to output the latch address WX to the pre-decoder 140 during the pulse PL2 of the clock pulse signal CKP. In some embodiments, the latch circuit 130 outputs the latch address WX to the pre-decoder 140 during the pulse PL2 of the clock pulse signal CKP corresponding to the memory array (e.g., as described above with respect to the memory circuit 100 and Figure 1-2B The write operation in the memory array 160) is discussed.

[0175] Through the above Fig. 7A and Figure 7B The configuration discussed above can be based on the control circuit 300 having the above-mentioned memory circuit 100 and Figure 1-2B The clock signal CLK and the enable signals REB and WEB of the discussed advantage generate the clock pulse signals CKTW, CKTR, and CKP, and the selection signal PSEL.

[0176] Figure 8 8 is a flow chart of a method 800 of operating a memory circuit according to one or more embodiments. The method 800 may be used in conjunction with a memory circuit (e.g., as described above with respect to Figure 1-2B The memory circuit 100 discussed above is used together with the memory circuit 100).

[0177] Figure 8 The sequence of operating method 800 depicted in FIG. 8 is for illustrative purposes only. The operating method 800 can be performed in different Figure 8 In some embodiments, it is also possible to Figure 8 except that Figure 8 Operations other than those described in .

[0178] In some embodiments, some or all of the operations of method 800 are a subset of register data move operations in a processor (eg, pseudo 2PRF operations as described above).

[0179] At operation 810, in some embodiments, a first address is received at a first latch circuit of a memory circuit. The first address includes information configured to identify one or more locations in a memory array. In some embodiments, the one or more locations correspond to a data word. In some embodiments, the one or more locations correspond to a location within a column of the memory array (e.g., an X location).

[0180] In some embodiments, the memory array includes a register file including a plurality of processor registers, and the first address corresponds to a processor register.In various embodiments, the memory array is included in the memory circuit or is separate from the memory circuit.

[0181] In some embodiments, receiving the first address comprises receiving the first address from a first data port coupled to the memory circuit. In some embodiments, receiving the first address comprises receiving the first address as part of performing a data move operation in the memory array. In some embodiments, receiving the first address comprises receiving a write address as part of performing a write operation in the memory array.

[0182] In some embodiments, receiving the first address at the first latch circuit includes receiving a control signal at the first latch circuit and responding to the control signal by latching the first address. In some embodiments, receiving the control signal includes generating the control signal using the control circuit. In some embodiments, generating the control signal includes generating the control signal in response to a clock signal and one or more enable signals.

[0183] In some embodiments, the first address is address WX, and / or the first latch circuit is latch circuit 110, and / or the memory array is memory array 160, each as described above with respect to memory circuit 100 and Figure 1-2B In some embodiments, generating and / or receiving a control signal includes generating and / or receiving the control signal described above with respect to memory circuit 100, control circuits 170 and 300, and Figure 1-4B and Fig. 7A and Figure 7B The clock pulse signal in question is CKTW.

[0184] At operation 820, a first address and a second address are received at a selection circuit. The second address is the same type of address as the first address discussed above. In some embodiments, receiving the first and second addresses includes receiving one or both of the first or second addresses from a latch circuit (e.g., a first latch circuit).

[0185] In some embodiments, receiving the second address comprises receiving the second address from a second data port coupled to the memory circuit. In some embodiments, receiving the second address comprises receiving the first address as part of performing a data move operation in the memory array. In some embodiments, receiving the second address comprises receiving a read address as part of performing a read operation in the memory array.

[0186] In some embodiments, receiving the first and second addresses includes receiving the first and second addresses at a multiplexer. In some embodiments, receiving the first and second addresses includes receiving the first and second addresses at selection circuit 120 as described above with respect to memory circuit 100 and Figure 1-2B The addresses in question are RX and WX.

[0187] At operation 830, the selection circuit is used to pass one of the first or second address to the address decoder. In some embodiments, using the selection circuit to pass one of the first or second address to the address decoder includes using a multiplexer.

[0188] In some embodiments, passing one of the first or second addresses to the address decoder using the selection circuit includes receiving a control signal at the selection circuit and responding to the control signal by selecting one of the first or second addresses. In some embodiments, receiving the control signal includes generating the control signal using the control circuit. In some embodiments, generating the control signal includes generating the control signal in response to a clock signal and one or more enable signals.

[0189] In some embodiments, the first and second addresses are addresses WX and RX, and / or the selection circuit is selection circuit 120, and / or the address decoder is decoder 150, each as described above with respect to memory circuit 100 and Figure 1-2B In some embodiments, generating and / or receiving a control signal includes generating and / or receiving the control signal described above with respect to memory circuit 100, control circuits 170 and 300, signal generation circuit 600, and Figure 1-4B and Figure 6-7B The selection signal PSEL in question.

[0190] In some embodiments, using the selection circuit to pass one of the first or second addresses to the address decoder includes receiving one of the first or second addresses from the selection circuit at a latch circuit (e.g., a second latch circuit). In some embodiments, using the selection circuit to pass one of the first or second addresses to the address decoder includes the above description with respect to memory circuit 100 and Figure 1-2B The latch circuit 130 in question receives one of the first or second address.

[0191] In some embodiments, receiving one of the first or second addresses at the second latch circuit includes receiving a control signal at the second latch circuit and responding to the control signal by latching one of the first or second addresses. In some embodiments, receiving the control signal includes generating the control signal using the control circuit. In some embodiments, generating the control signal includes generating the control signal in response to a clock signal and one or more enable signals.

[0192] In some embodiments, one of the first or second addresses is one of the addresses WX or RX and / or the second latch circuit is latch circuit 130, each as described above with respect to memory circuits 100 and Figure 1-2B In some embodiments, generating and / or receiving a control signal includes generating and / or receiving the control signal described above with respect to memory circuit 100, control circuits 170 and 300, and Figure 1-4B and Fig. 7A and Figure 7B The clock pulse signal in question is CKTR.

[0193] In some embodiments, using the selection circuit to pass one of the first or second addresses to the address decoder includes receiving one of the first or second addresses from the selection circuit at the pre-decoder. In some embodiments, using the selection circuit to pass one of the first or second addresses to the address decoder includes the above description of the memory circuit 100 and Figure 1-2B The pre-decoder 140 in question receives one of the first or second addresses.

[0194] At operation 840, the address decoder is used to decode one of the first or second addresses passed by the selection circuit. In some embodiments, using the address decoder includes using a pre-decoder, such as described above with respect to memory circuit 100 and Figure 1-2B The pre-decoder 140 is discussed.

[0195] In some embodiments, decoding one of the first or second addresses using the address decoder includes receiving a control signal at a predecoder and / or address decoder and responding to the control signal by predecoding and / or decoding one of the first or second addresses. In some embodiments, receiving the control signal includes generating the control signal using a control circuit. In some embodiments, generating the control signal includes generating the control signal in response to a clock signal and one or more enable signals.

[0196] In some embodiments, one of the first or second addresses is one of the addresses WX or RX, and / or the decoder is decoder 150, each as described above with respect to memory circuits 100 and Figure 1-2B In some embodiments, generating and / or receiving a control signal includes generating and / or receiving the control signal described above with respect to memory circuit 100, control circuits 170 and 300, and Figure 1-4B and Fig. 7A and Figure 7B The clock pulse signal in question is CKP.

[0197] At operation 850, in some embodiments, based on one of the first or second address, a first word line of the memory array is activated in a first data move operation. Activating the first word line includes using a decoder, such as described above with respect to memory circuit 100 and Figure 1-2B The decoder 150 discussed. In some embodiments, activating the first word line includes using one or more circuits, such as logic gates, between the decoder and the first word line. In various embodiments, the first data movement operation is a read operation or a write operation in the memory array.

[0198] In various embodiments, activating the first word line of the memory array includes activating the first word line of the memory array included in the memory circuit or independent of the memory circuit. In some embodiments, activating the first word line includes activating one or more memory cells of the memory array. In some embodiments, activating the first word line includes activating the memory cells described above with respect to memory circuit 100 and Figure 1-2B The word lines of the memory array 160 in question.

[0199] In some embodiments, activating the first word line includes the steps described above with respect to memory circuit 100 and Figure 1-2B A corresponding one of the word line signals WL[1]-WL[N] is generated on one of the word line signal paths WP[1]-WP[N] in question.

[0200] At operation 860, in some embodiments, the selection circuit is used to pass the other of the first or second address to the address decoder. Passing the other of the first or second address to the address decoder using the selection circuit is performed in the same manner as passing one of the first or second address to the address decoder using the selection circuit as discussed above with respect to operation 830.

[0201] At operation 870, in some embodiments, an address decoder is used to decode the other of the first or second address. Decoding the other of the first or second address using the decoder is performed in the same manner as decoding one of the first or second address using the decoder discussed above with respect to operation 840.

[0202] At operation 880, in some embodiments, based on the other of the first or second address, a second word line in the memory array is activated in a write operation. Activating the second word line in the memory array is performed in the same manner as activating the first word line of the memory array discussed above with respect to operation 850.

[0203] In some embodiments, the above descriptions of the memory circuit 100, the control circuits 170 and 300, the signal generating circuits 500 and 600, and Figure 1-7B The self-timing control signals discussed above (e.g., clock pulse signals CKTW, CHTR, and CKP) and the selection signal PSEL are used to perform operations 830 to 880. In some embodiments, operations 830 to 880 are performed on the clock signal (e.g., the clock pulse signals CKTW, CHTR, and CKP described above, the signal generation circuits 500 and 600, and the selection signal PSEL). Figure 1-7B The operation is performed within a single cycle of the clock signal CLK) in question.

[0204] By executing some or all of the operations of method 800 , the memory circuit is used to perform a data move operation based on the selected one of the two received addresses, thereby obtaining the benefits discussed above with respect to memory circuit 100 , control circuit 300 , and signal generation circuit 600 .

[0205] In some embodiments, the circuit includes a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when the selection signal has a first logic state and pass the second address to an output when the selection signal has a second logic state different from the first logic state. The circuit also includes: a decoder configured to decode the passed first address or the second address. In some embodiments, the circuit includes: a first latch circuit configured to output the first address to the first input in response to a first clock pulse signal; and a second latch circuit coupled between the selection circuit and the decoder, the second latch circuit configured to latch the passed first address or the second address in response to a second clock pulse signal. In some embodiments, the circuit includes a control circuit configured to receive a clock signal, a first enable signal, and a second enable signal, and generate a selection signal, a first clock pulse signal, and a second clock pulse signal based on the clock signal, the first enable signal, and the second enable signal. In some embodiments, the second latch circuit is configured to latch the transferred first address or second address in response to a first transition of the second clock pulse signal from the first logic state or the second logic state to the second logic state of the first logic state or the second logic state, and the control circuit is configured to generate the first transition when the select signal has the first logic state. In some embodiments, the second latch circuit is configured to output the transferred first address or second address in response to a second transition of the second clock pulse signal from the second logic state of the first logic state or the second logic state to the first logic state of the first logic state or the second logic state, and the control circuit is configured to generate the second transition when the select signal has the second logic state. In some embodiments, the circuit includes a predecoder coupled between the second latch circuit and the decoder, wherein the control circuit is configured to activate the predecoder for a first interval and a second interval, during the first interval, the second clock pulse signal has the second logic state of the first logic state or the second logic state, and the select signal transitions from the second logic state to the first logic state, and during the second interval, the second clock pulse signal has the second logic state of the first logic state or the second logic state, and the select signal has the first logic state. In some embodiments, the control circuit is configured to cause the select signal to transition from the second logic state to the first logic state based on the clock signal, and to transition from the first logic state to the second logic state based on the tracking signal. In some embodiments, the control circuit is configured to generate the tracking signal in response to the first enable signal and in response to the second enable signal.In some embodiments, the decoder includes an output coupled to a plurality of word line signal paths, and the decoder is configured to activate a word line signal path of the plurality of word line signal paths corresponding to the decoded passed first address or second address.

[0206] In some embodiments, a method of operating a memory circuit includes receiving a first address and a second address at a selection circuit, passing one of the first address or the second address to an address decoder using the selection circuit, and decoding the one of the first address or the second address using the address decoder. In some embodiments, receiving the first address at the selection circuit includes receiving the first address from a latch circuit. In some embodiments, passing the one of the first address or the second address to the address decoder includes receiving the one of the first address or the second address from the selection circuit at the latch circuit. In some embodiments, the method includes passing the other of the first address or the second address to the address decoder using the selection circuit, and decoding the other of the first address or the second address using the address decoder. In some embodiments, the method includes: based on the decoded first address, activating a first word line of the memory array in a write operation, and based on the decoded second address, activating a second word line of the memory array in a read operation.

[0207] In some embodiments, a memory circuit includes a memory array and a selection circuit configured to receive a write address at a first input and a read address at a second input, pass the write address to an output when a selection signal has a first logic state, and pass the read address to the output when the selection signal has a second logic state different from the first logic state. The memory circuit also includes a decoder configured to decode the passed write address or read address and activate a word line signal path corresponding to the decoded write address or read address in the memory array. In some embodiments, the memory circuit includes a control circuit configured to generate a clock pulse signal in response to a clock signal, wherein the clock pulse signal includes at least one of a first pulse or a second pulse during a period of the clock signal, and the memory circuit is configured to activate the word line signal path corresponding to the decoded read address during the first pulse, and activate the word line signal path corresponding to the decoded write address during the second pulse. In some embodiments, the first pulse has a first pulse width based on a first tracking interval, and the second pulse has a second pulse width based on a second tracking interval. In some embodiments, the memory circuit is configured to receive a read address from a first port and a write address from a second port, the first tracking interval is based on a read operation using the first port, and the second tracking interval is based on a write operation using the second port. In some embodiments, the control circuit is configured to generate a first pulse in response to a first enable signal and to generate a second pulse in response to a second enable signal. In some embodiments, the memory array includes a register file of processor registers, and the memory circuit is configured to control data movement in a pseudo dual port register file (2PRF) operation.

[0208] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the present disclosure. Those of ordinary skill in the art should be aware that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0209] Example 1. A memory circuit comprising: a selection circuit configured to: receive a first address at a first input and a second address at a second input, pass the first address to an output when a selection signal has a first logic state, and pass the second address to the output when the selection signal has a second logic state different from the first logic state; and a decoder configured to decode the passed first address or second address.

[0210] Example 2. The circuit according to Example 1 further includes: a first latch circuit, configured to output the first address to the first input in response to a first clock pulse signal; and a second latch circuit, coupled between the selection circuit and the decoder, the second latch circuit being configured to latch the transmitted first address or second address in response to a second clock pulse signal.

[0211] Example 3. The circuit according to Example 2 further includes: a control circuit configured to: receive a clock signal, a first enable signal, and a second enable signal, and generate the selection signal, the first clock pulse signal, and the second clock pulse signal based on the clock signal, the first enable signal, and the second enable signal.

[0212] Example 4. A circuit according to Example 3, wherein the second latch circuit is configured to latch the passed first address or second address in response to a first transition of the second clock pulse signal from a first logic state of the first logic state or the second logic state to a second logic state of the first logic state or the second logic state, and the control circuit is further configured to generate the first transition when the selection signal has the first logic state.

[0213] Example 5. A circuit according to Example 4, wherein the second latch circuit is configured to: output the passed first address or second address in response to a second transition of the second clock pulse signal from the second of the first logic state or the second logic state to the first of the first logic state or the second logic state, and the control circuit is further configured to: generate the second transition when the selection signal has the second logic state.

[0214] Example 6. The circuit according to Example 5 further includes: a predecoder coupled between the second latch circuit and the decoder, wherein the control circuit is further configured to: activate the predecoder for a first interval and a second interval, during the first interval, the second clock pulse signal has the first logic state or the second logic state, and the selection signal is converted from the second logic state to the first logic state, and during the second interval, the second clock pulse signal has the first logic state or the second logic state, and the selection signal has the first logic state.

[0215] Example 7. The circuit of Example 3, wherein the control circuit is further configured to cause the selection signal to: transition from the second logic state to the first logic state based on the clock signal, and transition from the first logic state to the second logic state based on a tracking signal.

[0216] Example 8. The circuit of Example 7, wherein the control circuit is further configured to generate the tracking signal in response to the first enable signal and in response to the second enable signal.

[0217] Example 9. The circuit of Example 1, wherein the decoder includes an output coupled to a plurality of word line signal paths, and the decoder is configured to activate a word line signal path of the plurality of word line signal paths that corresponds to the decoded passed first address or second address.

[0218] Example 10. A method of operating a memory circuit, the method comprising: receiving a first address and a second address at a selection circuit; passing one of the first address or the second address to an address decoder using the selection circuit; and decoding the one of the first address or the second address using the address decoder.

[0219] Example 11. The method of Example 10, wherein receiving the first address at the selection circuit comprises receiving the first address from a latch circuit.

[0220] Example 12. The method of Example 10, wherein passing the one of the first address or the second address to the address decoder comprises: receiving the one of the first address or the second address from the selection circuit at a latch circuit.

[0221] Example 13. The method of Example 10 further includes: passing the other of the first address or the second address to the address decoder using the selection circuit; and decoding the other of the first address or the second address using the address decoder.

[0222] Example 14. The method of Example 13, further comprising: activating a first word line of a memory array in a write operation based on the decoded first address; and activating a second word line of the memory array in a read operation based on the decoded second address.

[0223] Example 15. A memory circuit comprising: a memory array; a selection circuit configured to: receive a write address at a first input and a read address at a second input, pass the write address to an output when a selection signal has a first logic state, and pass the read address to the output when the selection signal has a second logic state different from the first logic state; and a decoder configured to: decode the passed write address or read address and activate a word line signal path in the memory array corresponding to the decoded write address or read address.

[0224] Example 16. The memory circuit according to Example 15 further includes: a control circuit configured to generate a clock pulse signal in response to a clock signal, wherein the clock pulse signal includes at least one of a first pulse or a second pulse during a period of the clock signal, and a memory circuit configured to: activate a word line signal path corresponding to a decoded read address during the first pulse, and activate a word line signal path corresponding to a decoded write address during the second pulse.

[0225] Example 17. The memory circuit of Example 16, wherein the first pulse has a first pulse width based on a first tracking interval, and the second pulse has a second pulse width based on a second tracking interval.

[0226] Example 18. A memory circuit according to Example 17, wherein the memory circuit is configured to: receive the read address from a first port and receive the write address from a second port, the first tracking interval is based on a read operation using the first port, and the second tracking interval is based on a write operation using the second port.

[0227] Example 19. The memory circuit of Example 16, wherein the control circuit is configured to generate the first pulse in response to a first enable signal and to generate the second pulse in response to a second enable signal.

[0228] Example 20. The memory circuit of Example 15, wherein the memory array comprises a register file of processor registers, and the memory circuit is configured to control data movement in a pseudo dual-port register file (2PRF) operation.

Claims

1. A memory circuit, comprising: a first latch circuit configured to output a first address to a first input in response to a first clock pulse signal; The selection circuit is configured as follows: receiving the first address at the first input and receiving the second address at the second input, When the select signal has a first logic state, the first address is passed to the output, and passing the second address to the output when the select signal has a second logic state different from the first logic state; as well as A decoder configured to decode the passed first address or second address; A second latch circuit is coupled between the selection circuit and the decoder, and the second latch circuit is configured to latch the transmitted first address or second address in response to a second clock pulse signal, wherein The second latch circuit is also configured to latch the transmitted first address or second address in response to a first transition of the second clock pulse signal from a first logic state of the first logic state or the second logic state to a second logic state of the first logic state or the second logic state.

2. The circuit according to claim 1, further comprising: The control circuit is configured as follows: receiving a clock signal, a first enable signal, and a second enable signal, and The selection signal, the first clock pulse signal, and the second clock pulse signal are generated based on the clock signal, the first enable signal, and the second enable signal.

3. The circuit according to claim 2, wherein: The control circuit is further configured to generate the first transition when the select signal has the first logic state.

4. The circuit according to claim 3, wherein: The second latch circuit is configured to: output the transferred first address or second address in response to a second transition of the second clock pulse signal from the second of the first logic state or the second logic state to the first of the first logic state or the second logic state, and The control circuit is further configured to generate the second transition when the select signal has the second logic state.

5. The circuit according to claim 4, further comprising: a pre-decoder coupled between the second latch circuit and the decoder, wherein The control circuit is further configured to: activate the predecoder for a first interval and a second interval, During the first interval, the second clock pulse signal has the second of the first logic state or the second logic state, and the selection signal transitions from the second logic state to the first logic state, and During the second interval, the second clock pulse signal has the second logic state of the first logic state or the second logic state, and the selection signal has the first logic state.

6. The circuit according to claim 2, wherein: The control circuit is further configured to cause the selection signal to: transitions from the second logic state to the first logic state based on the clock signal, and A transition is made from the first logic state to the second logic state based on a tracking signal.

7. The circuit according to claim 6, wherein: The control circuit is further configured to generate the tracking signal in response to the first enable signal and in response to the second enable signal.

8. The circuit according to claim 1, wherein: The decoder includes an output coupled to a plurality of word line signal paths, and The decoder is configured to activate a word line signal path among the plurality of word line signal paths corresponding to the decoded transferred first address or second address.

9. A method of operating a memory circuit, the method comprising: receiving a first address and a second address at a selection circuit; passing one of the first address or the second address to a latch circuit using the selection circuit; Using the latch circuit to latch the one of the first address or the second address in response to a clock pulse signal comprises: latching the one of the first address or the second address in response to a first transition of the clock pulse signal from a first of a first logic state or a second logic state to a second of the first logic state or the second logic state; The one of the first address or the second address is decoded using an address decoder.

10. The method according to claim 9, wherein: Receiving the first address at the selection circuit includes receiving the first address from a latch circuit.

11. The method according to claim 9, further comprising: The one of the first address or the second address is passed to the address decoder using the latch circuit.

12. The method according to claim 9, further comprising: passing the other of the first address or the second address to the address decoder using the latch circuit; and The other of the first address or the second address is decoded using the address decoder.

13. The method according to claim 12, further comprising: activating a first word line of the memory array in a write operation based on the decoded first address; and Based on the decoded second address, a second word line of the memory array is activated in a read operation.

14. A memory circuit comprising: Memory array; The selection circuit is configured as follows: receiving a write address at a first input and a read address at a second input, When the select signal has a first logic state, the write address is passed to the output, and passing the read address to the output when the select signal has a second logic state different from the first logic state; The decoder is configured as: Decodes the passed write address or read address, and activating a word line signal path in the memory array corresponding to a decoded write address or a read address; as well as a latch circuit coupled between the selection circuit and the decoder, the latch circuit being configured to latch the delivered write address or the read address in response to a clock pulse signal, wherein The latch circuit is also configured to latch the transmitted write address or the read address in response to a first transition of the clock pulse signal from a first logic state of the first logic state or the second logic state to a second logic state of the first logic state or the second logic state.

15. The memory circuit of claim 14, further comprising: A control circuit is configured to generate a clock pulse signal in response to a clock signal, wherein The clock pulse signal includes at least one of a first pulse or a second pulse during a period of the clock signal, and The memory circuit is configured as follows: activating a word line signal path corresponding to a decoded read address during the first pulse, and A word line signal path corresponding to the decoded write address is activated during the second pulse.

16. The memory circuit according to claim 15, wherein: The first pulse has a first pulse width based on a first tracking interval, and The second pulse has a second pulse width based on a second tracking interval.

17. The memory circuit according to claim 16, wherein: The memory circuit is configured to: receive the read address from the first port and receive the write address from the second port, The first tracking interval is based on a read operation using the first port, and The second tracking interval is based on a write operation using the second port.

18. The memory circuit according to claim 15, wherein: The control circuit is configured to: generating the first pulse in response to a first enable signal, and The second pulse is generated in response to a second enable signal.

19. The memory circuit according to claim 14, wherein: The memory array includes a register file of processor registers, and The memory circuit is configured to control data movement in a pseudo dual-port register file 2PRF operation.

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