Semiconductor device packaging assembly and manufacturing method thereof

Abstract

The present invention is titled "Semiconductor Device Package Assembly and Method of Manufacturing the Same". In one general aspect, a semiconductor device package may include a die attach paddle having a first surface and a second surface opposite the first surface. The package may further include a semiconductor die coupled to the first surface of the die attach paddle. The package may further include a direct bond metal (DBM) substrate. The DBM substrate may include: a ceramic layer having a first surface and a second surface opposite the first surface; a first metal layer disposed on the first surface of the ceramic layer and coupled to the second surface of the die attach paddle; and a second metal layer disposed on the second surface of the ceramic layer. The second metal layer may be exposed to the exterior of the semiconductor device package. The second metal layer may be electrically isolated from the first metal layer by the ceramic layer.

Description

Technical Field

[0001] The present invention generally relates to semiconductor device package assemblies, such as semiconductor device package assemblies having electrically isolated external heat dissipation surfaces, and associated methods of manufacture. Background Art

[0002] Implementations of semiconductor device packages may include external exposed surfaces (e.g., metal surfaces) for dissipating heat generated by operation of associated (one or more) semiconductor devices, wherein the external heat dissipation surfaces are electrically connected (directly or indirectly) to the semiconductor device (die) and / or semiconductor devices included in the package, such as through a surface of the die, a die attach paddle, a metal heat slug, etc. In such implementations, an external heat transfer mechanism (e.g., a heat sink, a heat pipe, etc.) (in conjunction with the heat dissipation surface of the package) may also be used to dissipate heat generated by the semiconductor device during operation, and a thermal interface material (TIM) may be disposed between the external heat dissipation surface of the package and the external heat transfer mechanism.

[0003] In such implementations, the TIM may provide electrical isolation between the external heat transfer mechanism and the externally exposed heat dissipation surface of the package. However, such a TIM may undesirably increase the thermal resistance between one or more semiconductor devices (one or more semiconductor dies) and the external heat transfer mechanism (e.g., heat sink, heat pipe, etc.). Such thermal resistance may be referred to as the junction-sink thermal resistance (R thj-s ). Such increased thermal resistance may result in excessive heating of a semiconductor device (e.g., a power semiconductor device), which may cause damage to the semiconductor device (or other components in a system including the semiconductor device) and / or may shorten the operating life of the device or associated components (e.g., reduce device and / or system reliability). Furthermore, use of such a TIM may increase manufacturing and / or product costs due at least to material costs and processing operations associated with coupling the TIM to an associated semiconductor device package and an external heat transfer mechanism. Summary of the invention

[0004] In one overall aspect, a semiconductor device package may include a die attach paddle having a first surface and a second surface opposite the first surface. The package may also include a semiconductor die coupled to the first surface of the die attach paddle. The package may also include a first direct bond metal (DBM) substrate. The DBM substrate may include: a ceramic layer having a first surface and a second surface opposite the first surface; a first metal layer disposed on the first surface of the ceramic layer and coupled to the second surface of the die attach paddle; and a second metal layer disposed on the second surface of the ceramic layer. The second metal layer may be exposed to the exterior of the semiconductor device package. The second metal layer may be electrically isolated from the first metal layer by the ceramic layer.

[0005] The details of one or more implementations are set forth in the accompanying drawings and the description that follows. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram schematically showing a semiconductor device package assembly.

[0007] Figures 2A to 2D are diagrams showing various isometric views of semiconductor device package assemblies and components of semiconductor device package assemblies.

[0008] Figures 3A to 3D It is shown Figures 2A to 2D Figure 2 is a side view of a semiconductor device package assembly and components of the semiconductor device package assembly.

[0009] Figure 4 is a diagram illustrating a die attach paddle of a semiconductor device package assembly.

[0010] Figure 5 is a diagram showing a side view of a portion of a component that may be included in a semiconductor device package.

[0011] Figure 6 is a diagram schematically showing a semiconductor device package and an external heat sink.

[0012] Figure 7 is a flow chart illustrating a method for manufacturing a semiconductor device package assembly, such as those described herein.

[0013] In the accompanying drawings, reference numerals for identical or similar elements may not be shown for each of those elements. In addition, reference numerals from one view of a given implementation may not be repeated in related views. Furthermore, in some cases, reference numerals from one view of a given implementation may be repeated in other views for the purpose of comparing different views, but may not be specifically discussed with respect to each view. DETAILED DESCRIPTION

[0014] Semiconductor device assemblies (e.g., semiconductor device packages, packaged semiconductor devices, packaged devices, etc.), such as those described herein, may include a die attach paddle, one or more semiconductor dies (e.g., disposed on a die attach paddle), one or more signal leads, one or more wire bonds that electrically couple the one or more semiconductor dies and / or the one or more signal leads to each other, and an isolation substrate. The exemplary implementations described herein may overcome at least some of the disadvantages discussed above. For example, in some implementations, the isolation substrate may include a ceramic substrate that electrically isolates an external heat sink surface (e.g., a metal layer disposed on the ceramic substrate) from the one or more semiconductor dies, the die attach paddle, etc. In addition, such as in the exemplary implementations described herein, the use of an isolation substrate may allow for the elimination of thermal interface materials (TIMs), the elimination of manufacturing operations associated with TIMs, and / or may reduce the overall thermal resistance (e.g., R thj-s ).

[0015] Figure 1 1 is a diagram schematically showing a semiconductor device package assembly (package) 100. Figure 1 As shown, the package 100 includes a die attach paddle (DAP) 110, a semiconductor die (or multiple semiconductor dies) 120, and an isolation substrate 130. The package 100 also includes a signal lead (or multiple signal leads) 140 and a wire bond 150, wherein the wire bond 150 electrically couples the signal lead 140 with the semiconductor die 120 (or can electrically couple different semiconductor dies 120 to each other, or can electrically couple the semiconductor die 120 with the DAP 110). Figure 1 As further shown in FIG. 1 , the package 100 may further include a molding compound 160 that at least partially encapsulates other elements of the package 100 .

[0016] like Figure 1As shown, the DAP 110 has a first surface 112 and a second surface 114 opposite the first surface 112. In the package 100, the semiconductor die 120 is disposed on (coupled to, etc.) the first surface 112 of the DAP 110. In this example, the DAP 110 has a thickness T1 measured along a line L1, wherein the line L1 is orthogonal to the first surface 112 and the second surface 114 of the DAP 110. In some implementations, the thickness T1 of the DAP 110 may be greater than or equal to 0.5 millimeters (mm), which may allow the DAP 110 to effectively absorb (e.g., remove, etc.) thermal energy associated with rapid changes (transients) in heat generated by the semiconductor die 120. In a manner similar to an electrical circuit, the DAP 110 may act as a thermal capacitor (and thermal conductor) that rapidly removes (stores) heat generated by the semiconductor die 120, wherein the absorbed (removed) heat is subsequently transferred to the exterior of the package 100 through the isolation substrate 130.

[0017] like Figure 1 As shown, the DAP 110 may include a protrusion (tab, flange, extension, etc.) 116. The protrusion 116 may extend at least partially around the perimeter of the DAP 110, such as described below. Figure 4 In the example shown. In some implementations, the protrusion 116 can be formed using metal swaging, stamping, etching, etc. The protrusion 116 can be configured, for example, to act as a molding compound lock for the package 100. For example, the protrusion 116 can include multiple surfaces that contact (form an interface with, etc.) the molding compound 160, such that the protrusion 116 helps to fix (securely fix) the molding compound 160 in place in the package 100 to prevent the molding compound 160 from delaminating from the DAP 110, from the semiconductor die 120, and / or from the isolation substrate 130. Such delamination can occur, for example, due to a mismatch between the respective coefficients of thermal expansion (CTE) of the elements of the package 100, such as between the DAP 110 and the molding compound 160.

[0018] Additionally, in some implementations, to further prevent such delamination, the materials included in the DAP 110 may be selected to reduce such CTE mismatch. For example, depending on a particular implementation, the DAP 110 may include copper, copper alloys, aluminum, a clad metal structure including a stack of copper, iron, and copper, a clad metal structure including a stack of copper, nickel, iron, and copper, etc., as compared to other DAP materials, wherein one or more materials included in the DAP 110 are selected to reduce the CTE mismatch between the DAP 110 and, for example, the molding compound 160. In some implementations, the molding compound 160 may be, for example, an epoxy molding compound, although other molding compound substances may be used.

[0019] Although discussed in further detail below, relative to Figure 1Briefly, in some implementations, the isolation substrate 130 can be a direct bond metal (DBM) substrate coupled to (disposed on, etc.) the second surface 114 of the DAP 110. Figure 1 As shown, the isolation substrate 130 may have a thickness T2 measured along line L1, wherein the thickness T2 may be in the range of, for example, 4.5 mm to 6.0 mm. Figure 1 As shown, the encapsulated portion of the package 100 may have a thickness T3 also measured along line L1 , wherein the thickness T3 may be in the range of 4.5 mm to 6.0 mm.

[0020] like Figure 1 As shown, in the package 100, the molding compound 160 encapsulates (e.g., completely encapsulates) the DAP 110, the semiconductor die 120, and the wire bonds 150. In addition, in the exemplary package 100, the molding compound 160 partially encapsulates the isolation substrate 130 and the signal leads 140. For example, as shown in FIG. Figure 1 As shown, the isolation substrate 130 has a surface (eg, metal, heat dissipation surface) exposed through the molding compound 160. In addition, the signal lead 140 includes a first portion 140a disposed within (encapsulated by) the molding compound 160, and a second portion 140b disposed outside (not encapsulated by) the molding compound 160.

[0021] Figures 2A to 2D FIG. 2 is a diagram showing various isometric views of a semiconductor device package assembly (package) 200 and components (eg, subcomponents) of the package 200 , wherein the package 200 may be Figure 1 A specific implementation of the package 100 in FIG. Figure 2A and Figure 2B From the first side ( Figure 2A ) and the second side ( Figure 2B ) shows an isometric view of the package 200. Figure 2A and Figure 2B As shown, package 200 includes an isolation substrate 230, a signal lead 240, and a molding compound 260. As with package 100, molding compound 260 may at least partially encapsulate the components of package 200. For example, Figure 2A and Figure 2B As shown, the signal leads 240 may extend from the molding compound 260 (eg, may be partially encapsulated in the molding compound 260 ).

[0022] like Figure 2BAs shown, the isolation substrate 230 may include a metal layer 234 exposed through the molding compound 260. As discussed herein, the metal layer 234 may be electrically isolated from other elements of the package 200, such as the DAP, the semiconductor die, etc. In addition, the metal layer 234 may provide (serve as, act as, etc.) a heat dissipation surface for the package 200. As described herein, an external heat transfer device (mechanism) such as a heat sink or heat pipe may be directly coupled to the metal layer 234 (e.g., using solder material, sintering material, and / or other thermally conductive materials). Compared to an arrangement including a TIM (which may be referred to as an indirect cooling arrangement), Figure 6 Such a configuration as shown may be referred to as a direct cooling arrangement.

[0023] See also Figure 2C , an assembly 200 a is shown, wherein the assembly 200 a is a subassembly of the package 200 that does not include the isolation substrate 230 or the molding compound 260 . Figure 2D 2 is a diagram showing an isolation substrate 230. Figure 2C As shown, assembly 200 includes DAP 210, first semiconductor die 220a, second semiconductor die 220b, signal leads 240, and wire bonds 250. Figure 2C As shown, semiconductor dies 220a and 220b are disposed on (coupled to) DAP 210 using solder or other suitable die attach material, such as conductive epoxy.

[0024] In addition, Figure 2C As shown, DAP 210 includes a protrusion 216 that can be configured (like protrusion 116 of package 100) to act as a mold compound lock. Figure 2C As shown, assembly 200a also includes wire bonds that electrically couple signal leads 240 to semiconductor dies 220a and 220b, and that electrically couple semiconductor die 220a to semiconductor die 220b.

[0025] Figure 2D An isolation substrate 230 is shown separated from the package 200. Figure 2D As shown, the isolation substrate 230 may include a non-conductive (eg, ceramic) layer 232 and a metal layer 234, such as Figure 2B As shown, the metal layer may be exposed through the molding compound 260 of the package 200 to provide a heat dissipation surface. As described herein, the isolation substrate 230 may be a direct bond metal (DBM) substrate, such as a direct bond copper (DBC) substrate, as described below with respect to, for example Figure 3B In some implementations, the metal layer 234 may be disposed on a surface of the non-conductive (eg, ceramic) layer 232 (eg, Figure 3B At least a portion (eg, greater than 90%) of the surface 232a) shown in FIG.

[0026] Figures 3A to 3D It is shown Figures 2A to 2D 200a and the side view of the components of the package 200 shown in FIG. For example, Figure 3A 2 shows a side view of the assembly 200a, wherein only a portion of the signal lead 240 is shown, as indicated by the cut line. Figure 3A As shown, semiconductor dies 220a and 220b are coupled to DAP 210 (eg, a first surface of DAP 210). In some implementations, DAP 210 can have a thickness, such as thickness T1, as discussed above with respect to DAP 110 of package 100.

[0027] In addition, Figure 3A As shown, wire bonding 250 provides electrical connection between signal lead 240 and semiconductor die 220a and 220b, and electrical connection between semiconductor die 220a and semiconductor die 220b. Figure 3A As shown, the protrusion 216 of the DAP 210 may extend around at least a portion of the DAP 210 .

[0028] See also Figure 3B , shows an example of the isolation substrate 230. As described above, the isolation substrate 230 may be a DBM substrate, such as a DBC substrate. Figure 3B As shown, the isolation substrate 230 may include a non-conductive (eg, ceramic) layer 232 having a first surface 232 a and a second surface 232 b opposite to the first surface 232 a . Figure 3B The metal (eg, copper) layer 234 of the isolation substrate 230 is disposed on the first surface 232a of the layer 232. In some implementations, the non-conductive (eg, ceramic) layer 232 may include aluminum oxide (Al 2 O 3 ), at least one of aluminum nitride (AlN) or silicon nitride (SiN).

[0029] like Figure 3BAs further shown in , the isolation substrate 230 includes another metal (e.g., copper) layer 236 disposed on a second surface 232b of the non-conductive (e.g., ceramic) layer 232. Similar to the metal layer 234 on the surface 232a, the metal layer 236 may be disposed above at least a portion (e.g., greater than 90%) of the surface 232b of the non-conductive (e.g., ceramic) layer 232. In this example, and in other exemplary implementations described herein, the non-conductive layer (e.g., ceramic layer) 232 electrically isolates the two metal layers 234 and 236 from each other, such that the externally exposed metal layer 234 is electrically isolated from the metal layer 236 coupled to the DAP 210. In some implementations, the isolation substrate 230 may have a thickness such as thickness T2, as discussed above with respect to the isolation substrate 130 of the package 100.

[0030] Figure 3C Shows Figure 2A 200 a, wherein an isolation substrate 230 is coupled to a DAP 210, e.g., on a surface of the DAP 210 opposite to a surface of the DAP 210 to which semiconductor dies 220 a and 220 b are coupled, thereby forming the assembly 200 (without the molding compound 260). In some implementations, a solder material can be used to couple the isolation substrate to the DAP 210. In other implementations, other thermally and / or electrically conductive adhesive materials can be used to couple the isolation substrate 230 to the DAP 210.

[0031] Figure 3D The assembly 200 is shown as Figure 3C FIG. 2 is a diagram showing a portion of the assembly 200 after a molding operation for encapsulating the portion of the assembly 200 in a molding compound 260, as shown in FIG. Figure 3D For the purpose of illustration, Figure 3D Only the outline of the molding compound 260 is shown in FIG. Figure 3D Elements of assembly 200 can be seen within molding compound 260 (disposed within, encapsulated by, etc.).

[0032] like Figure 3D As shown, the protrusion 216 of the DAP 210 and the portion 210a of the DAP 210 between the protrusion 216 and the isolation substrate 230 form a step 218 that defines an opening 238 (e.g., a cavity, a recessed area) between the isolation substrate 230 and the protrusion 216 of the DAP 210. That is, the protrusion 216 and the isolation substrate may extend (protrude, etc.) from the portion 210a of the DAP 210 to form the opening 238. In some implementations, such as this example, the opening 238 may extend around the perimeter of the DAP 210. Figure 3DAs shown, the opening 238 formed by the protrusion 216, the step 218, the DAP 210 (e.g., the portion 210a), and the isolation substrate 230 can improve the molding compound lock (e.g., due to the molding compound extending into the opening 238), and thus reduce the risk of the molding compound 260 delaminating from the assembly 200. This further improvement in molding compound lock can further reduce the risk of molding compound delamination.

[0033] In addition, Figure 3D As shown, the metal layer 234 can be exposed through the molding compound. In some implementations, a heat dissipation mechanism (e.g., a heat sink, etc.) can be coupled to the metal layer 234 (e.g., soldered to the metal layer, etc.) to dissipate heat generated during operation of the assembly 200. In this example, the heat dissipation mechanism will be electrically isolated from the internal components of the assembly 200 by the non-conductive layer 232 of the isolation substrate 230.

[0034] Figure 4 is a diagram illustrating a DAP of a semiconductor device package assembly, and in this example, the diagram illustrates a DAP 210 of a package 200 . Figure 4 Also shown are portions of the signal leads 240 of the package 200, for example to show their relative arrangement with respect to the DAP 210. Figure 4 As shown, the projection 216 extends around the entire perimeter of the DAP. Figure 4 , a surface of DAP 210 coupled to isolation substrate 230 in package 200 is shown. Figure 4 The surface of DAP 210 to which semiconductor dies 220a and 220b are coupled is not shown in FIG. 2 because it would be located on the underside of DAP 210 as shown.

[0035] Figure 5 is a diagram showing a side view of a portion of a component 500a that may be included in a semiconductor device package (package) such as package 200. Figure 5 In the illustration of the component 500a in FIG. 5 , signal leads are not specifically shown, but in some implementations, signal leads may be included in a semiconductor device package including the component 500a.

[0036] Similar to Figure 2C , Figure 3A and Figure 3C Component 200a in FIG. 5 includes DAP 520, semiconductor die 520, isolation substrate (eg, DBM substrate or DBC substrate) 530, and wire bonding 550. Figure 5 As shown, which are not shown with respect to package 100 or 200 , one or more of wire bonds 550 may be used to electrically couple semiconductor die 520 to DAP 510 .

[0037] In addition,Figure 5 As shown, DAP 510 includes a protrusion 516, such as protrusion 216 of DAP 210. In assembly 500a, DAP 510 includes a step 518 that forms an opening 538 between isolation substrate 530 and protrusion 516 of DAP 510, similar to the arrangement (e.g., step) of protrusion 216 of DAP 210 and isolation substrate 230 of package 200 discussed above. Figure 5 As shown, the opening formed by step 518, DAP 510 and isolation substrate 530 can be combined with protrusion 516 to further improve the locking of the molding compound (although the molding compound is not in Figure 5 This further improvement in the locking of the molding compound can further reduce the risk of molding compound delamination. Figure 5 As shown, assembly 500 a includes solder (or other adhesive material) for coupling isolation substrate 530 to DAP 510 .

[0038] Figure 6 6 is a diagram schematically illustrating an assembly including a semiconductor device package (package) 600 and an external heat sink 620. By way of example, the package 600 may be a specific implementation of the package 100 or 200 discussed above. Figure 6 As shown, heat sink 620 can be coupled to package 600 (eg, coupled to an exposed metal layer of an isolation substrate) in a direct cooling configuration. Figure 6 In the example of FIG. 6 , the heat sink 620 is directly coupled to the package 600 using a thermally and / or electrically conductive material 610. In some implementations, the material 610 may be a solder material, a sintered material, etc. In some implementations, compared to a similar component with an indirect cooling arrangement (e.g., using a TIM), Figure 6 The components can have a 75% or more reduction in thermal resistance R thj-s .

[0039] Figure 7 is a flow chart showing a method 700 for manufacturing a semiconductor device package assembly such as those described herein. For purposes of illustration, and by way of example, further reference will be made to, for example Figures 2A to 2D The package 200 shown and Figure 6 The method 700 is described with reference to the components shown. However, the method 700 may be used to produce semiconductor device packages and / or components having other configurations or arrangements.

[0040] like Figure 7As shown, method 700 includes (with reference to package 200) attaching (coupling) semiconductor die 220a and 220b to DAP 210 at block 710. At block 720, method 700 includes performing solder printing on isolation substrate (e.g., DBM or DBC) 210 and / or on a surface of DAP 210 opposite to the surface of DAP 210 to which semiconductor die 220a and 220b are coupled at block 710. At block 730, method 700 includes performing a solder reflow operation to couple isolation substrate 230 with a die attach paddle using the solder printing of block 720. At block 740, method 700 includes forming wire bonds, such as the wire bonds described herein (e.g., wire bonds 150, 250, and / or 550). At block 750, method 700 includes performing a molding (encapsulation) operation to encapsulate (e.g., fully or partially) the components of package 200, such as in the exemplary arrangements described herein. At block 760, trimming (e.g., deburring, deburring, plating, cutting, etc.) and electrical testing operations may be performed on packaged semiconductor device 200. At block 770, a heat sink may be attached to package 200 in a direct cooling arrangement, such as Figure 6 As shown in and described with respect to this figure.

[0041] It will be understood that in the foregoing description, when an element is referred to as being on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is referred to as being directly on another element, directly connected to another element, or directly coupled to another element, there is no intermediate element. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, the element shown as being directly on an element, directly connected, or directly coupled can be referred to in this manner. The claims of the present application, if any, may be revised to narrate the exemplary relationships described in the specification or shown in the accompanying drawings.

[0042] As used in this specification, singular forms may include plural forms unless the context clearly indicates a specific case. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some specific implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some specific implementations, the term adjacent can include lateral adjacent or horizontal adjacent.

[0043] Implementations of the various techniques described herein may be implemented (e.g., included) in digital electronic circuitry, in computer hardware, firmware, software, or a combination thereof. Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates, including, but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and the like.

[0044] Although certain features of the described implementations have been described as described herein, those skilled in the art will now appreciate that many modifications, alternatives, variations, and equivalents are contemplated. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The implementations described herein can include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.

Claims

1. A semiconductor device package, include: a die attach paddle having a first surface and a second surface opposite the first surface; a semiconductor die coupled to the first surface of the die attach paddle; and A directly bonded metal substrate, the directly bonded metal substrate comprising: a ceramic layer having a first surface and a second surface opposite to the first surface; a first metal layer disposed on the first surface of the ceramic layer and coupled to the second surface of the die attach paddle; and a second metal layer, the second metal layer being disposed on the second surface of the ceramic layer and exposed to the outside of the semiconductor device package, the second metal layer being electrically isolated from the first metal layer by the ceramic layer, The die attach paddle includes a protrusion extending around at least a portion of a periphery of the die attach paddle such that a step of the die attach paddle is defined between the protrusion and the direct bond metal substrate, the protrusion is proximate to the second surface of the die attach paddle, and a thickness of the protrusion is less than a thickness of the die attach paddle between the first surface of the die attach paddle and the second surface of the die attach paddle.

2. The semiconductor device package according to claim 1, further comprising: include: at least one signal lead; a wire bond electrically coupling a signal lead of the at least one signal lead to the semiconductor die; and Molding material, the molding material: encapsulating the die attach paddle, the semiconductor die, and the wire bonds; as well as partially encapsulating the direct bonding metal substrate and the signal lead, The second metal layer is exposed through the molding compound, A first portion of the signal lead is disposed within the molding compound, and The second portion of the signal lead is disposed outside the molding compound.

3. The semiconductor device package according to claim 1, further comprising a heat sink, The heat sink is directly coupled to the second metal layer using one of a solder material or a sintered material, and The first metal layer is coupled to the second surface of the die attach paddle using a solder material. 4 . The semiconductor device package of claim 1 , wherein the die attach paddle has a thickness greater than or equal to 0.5 millimeters along a line extending orthogonally from the first surface of the die attach paddle to the second surface of the die attach paddle. 5 . The semiconductor device package according to claim 1 , wherein the first metal layer and the second metal layer are disposed on at least 90% of the first surface of the ceramic layer and at least 90% of the second surface of the ceramic layer, respectively. 6 . The semiconductor device package of claim 1 , further comprising a molding compound encapsulating the die attach paddle and the semiconductor die, the protrusion having at least one surface in contact with the molding compound.

7. A semiconductor device package, include: a die attach paddle having a first surface and a second surface opposite the first surface; a semiconductor die coupled to the first surface of the die attach paddle; Multiple signal leads; at least one wire bond electrically coupling a signal lead of the plurality of signal leads to the semiconductor die; A directly bonded copper substrate, the directly bonded copper substrate comprising: a ceramic layer having a first surface and a second surface opposite to the first surface; a first copper layer disposed on the first surface of the ceramic layer and coupled to the second surface of the die attach paddle; and a second copper layer disposed on the second surface of the ceramic layer and exposed to the outside of the semiconductor device package, the second copper layer being electrically isolated from the first copper layer by the ceramic layer; and Molding material, the molding material: encapsulating the die attach paddle, the semiconductor die, and the at least one wire bond; and partially encapsulating the direct bond copper substrate and the plurality of signal leads, The second copper layer is exposed through the molding compound, A respective first portion of each of the plurality of signal leads is disposed within the molding compound, and A respective second portion of each of the plurality of signal leads is disposed outside the molding compound, The die attach paddle includes a protrusion extending around at least a portion of a periphery of the die attach paddle such that a step of the die attach paddle is defined between the protrusion and the direct bond copper substrate, the protrusion is proximate the second surface of the die attach paddle, a thickness of the protrusion is less than a thickness of the die attach paddle between the first surface of the die attach paddle and the second surface of the die attach paddle, and The protrusion has at least one surface in contact with the molding compound.

8. A method for producing a semiconductor device package, the method include: coupling a semiconductor die to a first surface of a die attach paddle; as well as coupling a direct bonding metal substrate to a second surface of the die attach paddle, the second surface being opposite the first surface, the die attach paddle including a protrusion extending around at least a portion of a periphery of the die attach paddle such that a step of the die attach paddle is defined between the protrusion and the direct bonding metal substrate, the protrusion being proximate to the second surface of the die attach paddle, the protrusion having a thickness that is less than a thickness of the die attach paddle between the first surface of the die attach paddle and the second surface of the die attach paddle, The direct bonding metal substrate comprises: a ceramic layer having a first surface and a second surface opposite to the first surface; a first metal layer disposed on the first surface of the ceramic layer, the first metal layer coupled to the second surface of the die attach paddle; and A second metal layer is disposed on the second surface of the ceramic layer, and the second metal layer is electrically isolated from the first metal layer by the ceramic layer.

9. The method of claim 8, wherein the direct bonding metal substrate is coupled to the second surface of the die attach paddle. include: The first metal layer of the direct bond metal substrate is soldered to the second surface of the die attach paddle.

10. The method according to claim 8, further comprising: include: Wire bonds are formed to electrically connect signal leads of the semiconductor device package to the semiconductor die.

11. The method according to claim 10, further comprising: include: Molding operations are performed to: encapsulating the die attach paddle, the semiconductor die, and the wire bonds in a molding compound such that the protrusion has at least one surface in contact with the molding compound; as well as partially encapsulating the direct bonding metal substrate and the signal lead in the molding compound, The second metal layer is exposed through the molding compound, A first portion of the signal lead is disposed within the molding compound, and The second portion of the signal lead is disposed outside the molding compound.

Images