Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes a package and a cooling cover. The package includes a first tube core, the first tube core has an active surface and a rear surface opposite to the active surface. The rear surface has a cooling zone and a peripheral area that closes the cooling zone. The first tube core includes a micro groove located in the cooling zone of the rear surface. The cooling cover is stacked on the first tube core. The cooling cover includes a fluid inlet port and a fluid outlet port located above the cooling zone and connected to the micro groove.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] As electronic products continue to miniaturize, heat dissipation of packaged die has become an important issue in packaging technology. In addition, for multi-die packaging, the arrangement of the die has affected the data transmission speed between the die and the reliability of the packaged product. Summary of the invention

[0003] According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes a package and a cooling cover. The package includes a first tube core, the first tube core has an active surface and a rear surface opposite to the active surface. The rear surface has a cooling zone and a peripheral area that closes the cooling zone. The first tube core includes a plurality of micro grooves located in the cooling zone of the rear surface. The cooling cover is stacked on the first tube core. The cooling cover includes a fluid inlet port and a fluid outlet port located above the cooling zone and connected to the plurality of micro grooves.

[0004] According to some embodiments of the present invention, a semiconductor device is provided. The semiconductor device includes a package and a cooling cover. The package includes a substrate, an interposer and a tube core. The interposer is arranged on the substrate and electrically connected to the substrate. The tube core is arranged on the interposer and electrically connected to the interposer. The tube core includes a continuous ring pattern and a plurality of discontinuous patterns enclosed by the continuous ring pattern on the upper surface of the tube core opposite to the interposer. The cooling cover is stacked on the tube core. The cooling cover includes a fluid inlet port and a fluid outlet port located on the plurality of discontinuous patterns.

[0005] According to some embodiments of the present invention, a method for manufacturing a semiconductor device is provided. The method includes at least the following steps. A tube core is provided. The tube core has an active surface and a rear surface opposite to the active surface. The rear surface has a cooling zone and a peripheral zone that closes the cooling zone. A plurality of micro grooves are formed in the cooling zone of the rear surface. The tube core is placed on an interposer so that the active surface of the tube core faces the interposer. The interposer is placed on a substrate. A cooling cover is attached to the rear surface of the tube core. The cooling cover includes a fluid inlet port and a fluid outlet port located above the cooling zone and connected to the plurality of micro grooves. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0007] Figures 1A to 1FSchematic cross-sectional views showing structures formed at various stages of a method for manufacturing a package according to some embodiments of the present disclosure.

[0008] Figure 2A and Figure 2B They are respectively schematic top views of a tube die according to some embodiments of the present disclosure.

[0009] FIG. 3A to FIG. 3C They are respectively schematic top views of microcolumns according to some embodiments of the present disclosure.

[0010] Figure 4A and Figure 4B are schematic cross-sectional views of tube dies according to some embodiments of the present disclosure.

[0011] Figure 5A and Figure 5B are schematic cross-sectional views of tube dies according to some embodiments of the present disclosure.

[0012] Fig. 6A and Figure 6B are schematic cross-sectional views of tube dies according to some embodiments of the present disclosure.

[0013] Fig. 7A is a schematic top view of a die according to some embodiments of the present disclosure.

[0014] FIG. 7B to FIG. 7D are schematic cross-sectional views of tube dies according to some embodiments of the present disclosure.

[0015] Fig. 8A is a schematic cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure.

[0016] Figure 8B is a schematic cross-sectional view of a semiconductor device in use according to some embodiments of the present disclosure.

[0017] Figure 8C is a schematic top view of a semiconductor device in use according to some embodiments of the present disclosure.

[0018] Fig.9A is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0019] Fig. 9B is a schematic side view of a semiconductor device according to some embodiments of the present disclosure.

[0020] Fig. 9C is a schematic side view of a semiconductor device according to some embodiments of the present disclosure.

[0021] FIG. 10A to FIG. 10D They are respectively schematic stereoscopic views of a cooling cover according to some embodiments of the present disclosure.

[0022] Description of Figure Numbers

[0023] 10, 12: Package

[0024] 15, 25, 35, 45: Semiconductor devices

[0025] 100: Semiconductor wafer

[0026] 101, 111, 131, 210: Semiconductor substrate

[0027] 101a: Front surface

[0028] 110, 110A, 110B, 130, 1101, 1102, 1103, 1104, 1105: die

[0029] 110s: Edge

[0030] 111a: Active surface

[0031] 111r, 131r: rear surface

[0032] 113, 133: Contact pad

[0033] 115, 135: Passivation layer

[0034] 117, 1171, 1172, 1173, 1175: discontinuous pattern

[0035] 117A: Stripe pattern

[0036] 117B, 117B1, 117B2, 117B3: Microcolumns

[0037] 119: Continuous Ring Pattern

[0038] 120, 121, 122, 1201, 1202, 1203, 1204, 1205: micro grooves

[0039] 120A: Stripe-shaped micro grooves

[0040] 120B: Reticulated micro grooves

[0041] 200: Intermediary layer

[0042] 220: Semiconductor drilling

[0043] 230: Inner Link Structure

[0044] 231: Dielectric layer

[0045] 233: Conductive traces

[0046] 300, 310: Conductive terminals

[0047] 400: Substrate

[0048] 400b, 1201b, 1202b, 1203b, 1204b: bottom surface

[0049] 400t: Top surface

[0050] 500: Connecting terminal

[0051] 600A, 600B, 600C, 600D, 600E: Cooling cover

[0052] 610: Shell

[0053] 612: Baseboard / Panel

[0054] 614: Side Panel / Panel

[0055] 616: Top Panel / Panel

[0056] 620, 6201, 6202, 6203, 6204: Fluid ports

[0057] 620in: Fluid inlet port

[0058] 620out: Fluid outlet port

[0059] 622in, 622out: interface pipeline

[0060] 624in, 624out: connecting pipes

[0061] 630, 6301, 6302, 6303: Fluid channels

[0062] 630in: Fluid inlet channel

[0063] 630out: Fluid outlet channel

[0064] 640: Sealing groove

[0065] 650, 660: vertical pipe

[0066] 661: Narrow fluid ports

[0067] 662: Wider fluid ports

[0068] 700: Sealing ring

[0069] 810: Screw

[0070] 820: Fixture

[0071] 822: Upper arm

[0072] 824: Lower arm

[0073] 826: Fixture body

[0074] 830: Heat dissipation layer

[0075] 1174: Discontinuous pattern / striped pattern

[0076] 1191, 1192, 1193, 1194: Segment

[0077] 1201s, 1202s, 1203s, 1204s: Sidewall

[0078] CC: Cutting Line

[0079] CL: Cooling fluid

[0080] CS: Cycle Space

[0081] CR: Cooling zone

[0082] D: Depth

[0083] D1: First flow direction

[0084] D2: Second direction

[0085] L: Length

[0086] P: Pitch

[0087] PR: Peripheral Area

[0088] R: Tip

[0089] T111: Maximum thickness

[0090] W: Width

[0091] II, II-II, III-III, IV-IV: lines

[0092] α: Angle DETAILED DESCRIPTION

[0093] The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to make the disclosure concise. Of course, these are only examples and are not intended to be limiting. For example, in the following description, a first feature formed on or formed on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature cannot be directly contacted. In addition, the disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not inherently dictate the relationship between the various embodiments and / or configurations discussed.

[0094] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0095] Other features and processes may also be included. For example, a test structure may be included to assist in verification testing of three-dimensional (3D) packages or three-dimensional integrated circuits (3DIC) devices. The test structure may include, for example, a test pad formed in a redistribution layer or formed on a substrate, the test pad allowing the three-dimensional package or three-dimensional integrated circuit to be tested, allowing the use of probes and / or probe cards, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that includes verifying a known good die at an intermediate stage to improve yield and reduce costs.

[0096] Figures 1A to 1F 1 is a schematic cross-sectional view showing structures formed at various stages of a method for manufacturing a package 10 according to some embodiments of the present disclosure. Figure 1A, a semiconductor wafer 100 is provided. In some embodiments, the semiconductor wafer 100 may be divided into a plurality of tube cores 110. In some embodiments, the semiconductor wafer 100 may be a wafer made of a semiconductor material (e.g., a semiconductor material of Group III-V in the periodic table). In some embodiments, the semiconductor wafer 100 may include: an elemental semiconductor material, such as silicon or germanium; a compound semiconductor material, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide; or an alloy semiconductor material, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. For example, the semiconductor wafer 100 may be a silicon bulk wafer. In some embodiments, the tube core 110 is part of the semiconductor wafer 100 and the sidewall of each tube core 110 extends along the cutting line CC. Each tube core 110 may include a semiconductor substrate 111, which is a part of the semiconductor substrate 101 of the semiconductor wafer 100. A plurality of contact pads 113 and a passivation layer 115 may be formed on the front side surface 101a of the semiconductor wafer 100. In Figure 1A , two dies 110 are shown to represent a plurality of dies 110 formed in the semiconductor wafer 100, but more than two dies 110 may be formed in the semiconductor wafer 100. Each of the dies 110 may include active components (e.g., transistors, etc.) formed in a semiconductor substrate 111 and may optionally include passive components (e.g., resistors, capacitors, inductors, etc.) formed in the semiconductor substrate 111. Each of the dies 110 may be a logic die, such as a central processing unit (CPU) die, a graphic processing unit (GPU) die, a micro control unit (MCU) die, an input / output (I / O) die, a baseband (BB) die, or an application processor (AP) die. In some alternative embodiments, the die 110 may be a memory die, such as a high bandwidth memory (HBM) die.

[0097] In some embodiments, the contact pads 113 are formed on the active surface 111a of the semiconductor substrate 111 of each die 110. That is, each active surface 111a may correspond to a portion of the front side surface 101a of the semiconductor substrate 101 of the semiconductor wafer 100. In some embodiments, the contact pads 113 include aluminum pads, copper pads, or other suitable metal pads. Figure 1AAs shown in , the passivation layer 115 extends over the front side surface 101a of the semiconductor wafer 100. In some embodiments, the passivation layer 115 is formed with an opening that exposes the contact pad 113. In some embodiments, the passivation layer 115 can be a single-layer structure or a multi-layer structure, which includes a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a dielectric layer formed of other suitable dielectric materials, or a combination thereof. The opening of the passivation layer 115 can at least partially expose the contact pad 113.

[0098] refer to Figure 1B In some embodiments, the microgrooves 120 are formed on a rear surface 111r of the semiconductor substrate 111 opposite to the active surface 111a. In some embodiments, the microgrooves 120 are formed by removing a portion of the semiconductor substrate 111. In some embodiments, the microgrooves 120 may be formed via an etching process. In some embodiments, the etching process includes a dry etching process or a wet etching process. In some alternative embodiments, the microgrooves 120 may be formed via a cutting process. In some embodiments, laser sawing or mechanical die sawing may be used as a cutting process. In some embodiments, the microgrooves 120 are formed via an etching process or a cutting process so that the microgrooves 120 may be formed in a cost-saving manner. In some embodiments, when the microgrooves 120 are formed, a plurality of discontinuous patterns 117 may be simultaneously formed on the rear surface 111r of the die 110. For example, the discontinuous pattern 117 is located between two adjacent microgrooves 120. In some embodiments, the discontinuous pattern 117 is a semiconductor microstructure remaining on the rear surface 111r of the die 110 after a portion of the semiconductor substrate 111 is removed to form the microgroove 120. In some embodiments, the microgroove 120 partially penetrates the semiconductor substrate 111, and a portion of the semiconductor substrate 111 may be exposed at the side and bottom of the microgroove 120. That is, the depth D of the microgroove 120 (the distance from the horizontal height of the rear surface 111r to the bottom of the microgroove 120) may be less than the maximum thickness T111 of the semiconductor substrate 111. In some embodiments, the discontinuous pattern 117 is closed by the continuous ring pattern 119. In some embodiments, the discontinuous pattern 117 is located in the cooling region CR of the die 110, and the continuous ring pattern 119 is located in the peripheral region PR surrounding the cooling region CR. In some embodiments, the maximum thickness T111 may correspond to the thickness of the peripheral region PR (corresponding to the continuous ring pattern 119).

[0099] refer to Figure 1B and Figure 1C, a singulation process is performed on the semiconductor wafer 100 to separate the individual dies 110. For example, the semiconductor wafer 100 is cut along the cutting lines CC arranged between the individual dies 110 through the entire thickness of the semiconductor wafer 100. In some embodiments, the singulation process generally involves performing a wafer sawing process using mechanical die sawing and / or laser sawing.

[0100] refer to Figure 1D , the die 110 is bonded to the interposer 200. In some embodiments, the interposer 200 includes a semiconductor substrate 210, a through semiconductor via (TSV) 220 formed in the semiconductor substrate 210, and an interconnect structure 230 formed on one side of the semiconductor substrate 210. The semiconductor substrate 210 may be made of the same material as the semiconductor substrate 111 of the die 110, and thus will not be described in detail herein. In some embodiments, the interposer 200 includes a silicon wafer.

[0101] In some embodiments, an interconnect structure 230 is disposed on a semiconductor substrate 210, and the interconnect structure 230 includes a dielectric layer 231 and a conductive trace 233 extending through the dielectric layer 231. For simplicity, the dielectric layer 231 is shown as a single dielectric layer and the conductive trace 233 is shown as being embedded in the dielectric layer 231. However, from a manufacturing process perspective, the dielectric layer 231 is composed of at least two dielectric layers. The conductive trace 233 may be sandwiched between two adjacent dielectric layers. Some of the conductive traces 233 may extend vertically through the dielectric layer 231 to establish electrical connections between different metallization levels of the interconnect structure 230. In some embodiments, the outermost dielectric layer 231 (when there are multiple dielectric layers in the dielectric layer 231) may be patterned to expose the underlying conductive trace 233. In some embodiments, the material of the dielectric layer 231 includes polyimide, epoxy resin, acrylic resin, phenolic resin, benzocyclobutene (BCB), polybenzoxazole (PBO) or any other suitable polymer dielectric material. The dielectric layer 231 can be formed, for example, by a suitable manufacturing technique, such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), etc. In some embodiments, the material of the conductive trace 233 includes aluminum, titanium, copper, nickel, tungsten or an alloy thereof. The conductive trace 233 can be formed, for example, by electroplating, deposition and / or photolithography and etching. It should be noted that Figure 1DThe number of dielectric layers 231 and the number of conductive traces 233 shown in FIG. 2 are for illustration purposes only, and the present disclosure is not limited thereto. In some alternative embodiments, fewer or more layers of dielectric layers 231 or conductive traces 233 may be formed according to the circuit design.

[0102] like Figure 1D As described in the figure, a semiconductor through-via 220 is formed in a semiconductor substrate 210 to provide a double-sided electrical connection. In some embodiments, one end of the semiconductor through-via 220 is connected to a conductive trace 233 of an interconnect structure 230 and the other end is connected to the die 110 via a conductive terminal 300. In some embodiments, the material of the semiconductor through-via 220 includes one or more metals. For example, the metal material of the semiconductor through-via 220 includes copper, titanium, tungsten, aluminum, combinations thereof, and the like.

[0103] In some embodiments, the die 110 is bonded to the interposer 200 via the conductive terminals 300. In some embodiments, the conductive terminals 300 are micro bumps disposed on the semiconductor through vias 220 and / or the contact pads 113. In some embodiments, the die 110 is provided with an active surface 111a (a surface on which the contact pads 113 are formed) facing the interposer 200. That is, the rear surface 111r on which the micro grooves 120 are formed faces away from the interposer 200. In some embodiments, the rear surface 111r is referred to as the upper surface of the die 110.

[0104] although Figures 1A to 1D The die 110 is shown bonded to the interposer 200 after the back surface 111r has been patterned to form the microgrooves 120, but the present disclosure is not limited thereto. In some alternative embodiments, the die 110 may be placed on the interposer 200 before removing portions of the semiconductor substrate 111 to form the microgrooves 120, such as Figure 1E Subsequently, micro grooves 120 may be formed on the rear surface 111r to obtain Figure 1D That is, in some embodiments, the micro grooves 120 may be formed after the die 110 is bonded to the interposer 200 .

[0105] refer to Figure 1F ,Will Figure 1D The structure shown in FIG. 1 is placed on a substrate 400 to obtain a package 10. For example, the interposer 200 with the die 110 bonded on top can be connected to the substrate 400, such as a printed circuit board, a motherboard, etc. In some embodiments, the interposer 200 is disposed between the die 110 and the substrate 400. Figure 1FAs shown in , a plurality of connection terminals 500 are formed between the interposer 200 and the substrate 400 to establish electrical connections between the interposer 200 and the substrate 400. In some embodiments, the connection terminals 500 may be controlled collapse chip connections (controlled collapse chip connections, C4) bumps. In some embodiments, the interposer 200 may be fastened to the substrate 400 via a reflow process, etc. In some embodiments, the package 10 may be referred to as a chip on wafer on substrate (CoWoS) package.

[0106] Figure 2A and Figure 2B 110A and 110B, respectively. In some embodiments, the die 110A or the die 110B may be replaced. Figure 1F The die 110 of the package 10 is shown in FIG. Figure 2A , the tube core 110A has a cooling region CR surrounded by a peripheral region PR. In some embodiments, a strip-shaped micro groove 120A is formed in the cooling region CR. In some embodiments, the strip-shaped micro grooves 120A are parallel to each other. In some embodiments, the strip-shaped micro grooves 120A are also parallel to one of the edges 110s of the tube core 110A. In some embodiments, the tube core 110A has a strip-shaped pattern 117A located between two adjacent strip-shaped micro grooves 120A and a continuous ring pattern 119 surrounding the strip-shaped micro grooves 120A and the strip-shaped pattern 117A. In some embodiments, the strip-shaped pattern 117A corresponds to Figure 1F In some embodiments, the stripe-shaped pattern 117A is located in the cooling region CR and the continuous ring pattern 119 is located in the peripheral region PR. In some embodiments, the stripe-shaped pattern 117A is connected to the continuous ring pattern 119. For example, in Figure 2A In the top view of FIG. 1 , the continuous ring pattern 119 can be divided into four segments 1191 , 1192 , 1193 and 1194 , which are joined together to form a square ring pattern. In some embodiments, the stripe pattern 117A is connected to the segment 1192 and the segment 1194 .

[0107] refer to Figure 2B , the tube core 110B has a cooling region CR surrounded by a peripheral region PR. In some embodiments, the network of micro grooves 120B is formed in the cooling region CR. In some embodiments, the tube core 110B has micro pillars 117B surrounded by the network of micro grooves 120B and a continuous ring pattern 119 surrounding the network of micro grooves 120B and the micro pillars 117B. In some embodiments, the micro pillars 117B correspond to Figure 1F. In some embodiments, the micropillars 117B are located in the cooling region CR, and the continuous ring pattern 119 is located in the peripheral region PR. In some embodiments, the micropillars 117B are arranged in an array and are spaced apart from the continuous ring pattern 119. In some embodiments, the micropillars 117B are spaced apart from each other by a mesh of microgrooves 120B. In some embodiments, the mesh of microgrooves 120B may be formed by microgrooves 121 extending along a first direction and microgrooves 122 extending along a second direction intersecting the first direction. In some embodiments, the first direction and the second direction may be perpendicular to each other, but the present invention is not limited thereto. In some embodiments, additional microgrooves (not shown) extending along additional directions intersecting the first direction and the second direction may also be included.

[0108] In some embodiments, micropillars 117B may be formed in various shapes. Figures 3A to 3C 117B1, 117B2 and 117B3 are schematic top views of microcolumns according to some embodiments of the present disclosure. Figure 3A , the micro-pillars 117B1 may be a square pattern from a top view and may be referred to as square micro-pillars. Figure 3B , the micro-pillars 117B2 may be a diamond pattern when viewed from a top view, and may be referred to as diamond-shaped micro-pillars. Figure 3C , micropillars 117B3 may be triangular in shape from a top view and may be referred to as triangular micropillars. It should be noted that the present invention is not limited thereto. In some alternative embodiments, Figure 2B The microcolumn 117B may be Figures 3A to 3C In addition, although the shape of the Figure 2B The die 110B is shown to include micropillars 117B having the same shape, but the present invention is not limited thereto. In some alternative embodiments, the die 110B may include micropillars 117B having different shapes. For example, a combination of square micropillars 117B1 and triangular micropillars 117B3 may be seen in the die 110B at the same time.

[0109] Figure 4A and Figure 4B , Figure 5A and Figure 5B as well as Fig. 6A and Figure 6B 1101, 1102, and 1103 according to some embodiments of the present disclosure. In some embodiments, the die 1101, the die 1102, or the die 1103 may be replaced. Figure 1F The die 110 of the package 10 is shown in FIG. Figure 4A , Figure 5A and Fig. 6A A schematic cross-sectional view of Figure 2Aline II (extending across a plurality of strip-shaped patterns 117A) or along Figure 2B Similarly, Figure 4B , Figure 5B and Figure 6B A schematic cross-sectional view of Figure 2A Line II-II or along Figure 2B The image is taken along one of the lines II-II and IV-IV (along the bottom of the strip-shaped micro groove 120A or the bottom of the mesh-shaped micro groove 120B to avoid the discontinuous pattern 117).

[0110] refer to Figure 4A and Figure 4B , a micro groove 1201 of the tube core 1101 is formed by dry etching. In some embodiments, the micro groove 1201 may be Figure 2A The stripe-shaped micro grooves 120A or Figure 2BThe mesh micro grooves 120B shown in . In some embodiments, a patterned mask (not shown) is applied on the rear surface 111r of the tube core 1101 and then deep reactive-ion etching (DRIE) is performed to form the micro grooves 1201. In some embodiments, the patterned mask covers the peripheral region PR of the tube core 1101 and covers a portion of the semiconductor substrate 111, and the portion of the semiconductor substrate 111 later forms the discontinuous pattern 1171. At the same time, the patterned mask exposes some portions of the cooling region CR, and the semiconductor substrate 111 is removed from the exposed portion of the cooling region CR to form the micro grooves 1201. After the etching step, the patterned mask can be removed. In some embodiments, forming the micro grooves 1201 by dry etching can form the micro grooves 1201 with a substantially rectangular outline. That is, the bottom surface 1201b of the micro groove 1201 (the surface of the semiconductor substrate 111 exposed at the bottom of the micro groove 1201) and the sidewall 1201s of the micro groove 1201 may be substantially straight. In some embodiments, the sidewall 1201s may be joined to the bottom surface 1201b at a substantially right angle. In some embodiments, the sidewall 1201s of the micro groove 1201 may be regarded as the side edge of the discontinuous pattern 1171. That is, in some embodiments, the discontinuous pattern 1171 may have a substantially straight side edge. In some embodiments, the depth D of the micro groove 1201 (the distance between the level of the rear surface 111r and the level of the bottom surface 1201b) may be in the range of from 5 μm to 700 μm. In some embodiments, the width W of the microgroove 1201 (the distance between the sidewalls 1201s of one microgroove 1201 facing each other along a direction perpendicular to the extension direction of the microgroove 1201) may be in the range of 5 μm to 500 μm. In some embodiments, the pitch P of the discontinuous pattern 1171 (the distance between the corresponding side edges (i.e., the sidewalls 1201s) of the adjacent discontinuous patterns 1171) may be in the range of 6 μm to 1000 μm. In some embodiments, the length L of the microgroove 1201 may be measured according to the distance between the sidewalls 1201s of the microgroove 1201 facing each other along the extension direction of the microgroove 1201 (e.g., perpendicular to the measurement direction of the width W). In some embodiments, along the same direction, the length L of the microgroove 1201 may be about 85% of the length of the tube core 1101. For example, the length L of the microgroove 1201 may be in the range of 5 mm to 29 mm.

[0111] refer to Figure 5A and Figure 5B , the micro grooves 1202 of the tube core 1102 are formed by a cutting process using a mechanical tube core saw. In some embodiments, the micro grooves 1202 may be Figure 2A The stripe-shaped micro grooves 120A or Figure 2B In some embodiments, a portion of the semiconductor substrate 111 may be removed by mechanical die sawing to obtain strip-shaped micro grooves. In some embodiments, micro grooves (e.g., Figure 2B The micro grooves 121) and then form micro grooves along one or more directions intersecting the first direction (for example, Figure 2B In some embodiments, when the microgrooves 1202 are formed using a mechanical die saw, the sidewalls 1202s of the microgrooves 1202 may be substantially straight, while the bottom surface 1202b may have a curved profile. In some embodiments, the angle at the junction between the sidewalls 1202s and the bottom surface 1202b of the microgrooves 1202 may be greater than 90 degrees. That is, in the die 1102, the discontinuous pattern 1172 may be larger at the base (where the discontinuous pattern 1172 emerges from the semiconductor substrate 111) and narrows toward the top (e.g., at the level of the rear surface 111r) to reach a substantially constant width. In some embodiments, the range of the depth D, pitch P, width W, and length L of the microgrooves 1202 may be similar to Figure 4A and Figure 4B The depth D, pitch P, width W and length L of the micro groove 1201 are shown in FIG. Figure 5A and Figure 5B As shown in FIG. 1 , the depth D of the microgroove 1202 can be considered as the distance from the level of the rear surface 111r to the bottommost point of the microgroove 1202. In other words, the depth D of the microgroove 120 is the maximum depth of the microgroove 1202. The pitch P, width W, and length L can be considered similar to those previously described with reference to FIG. Figure 4A and Figure 4B Discussed pitch P, width W, and length L. In some embodiments, the surface roughness (arithmetic average roughness) of the sidewalls 1202s of the micro-grooves 1202 is in a range from 5 μm to 1000 μm.

[0112] refer to Fig. 6A and Figure 6B , the micro groove 1203 of the tube core 1103 is formed by a cutting process using a laser saw. In some embodiments, the micro groove 1203 may be Figure 2A The stripe-shaped micro grooves 120A or Figure 2B In some embodiments, a portion of the semiconductor substrate 111 may be removed by laser sawing to obtain a strip-shaped micro-groove. In some embodiments, micro-grooves (e.g., Figure 2BThe micro grooves 121) and then form micro grooves along one or more directions intersecting the first direction (for example, Figure 2B In some embodiments, when the microgrooves 1203 are formed using laser sawing, the sidewalls 1203s of the microgrooves 1203 may be inclined and the bottom surface 1203b may have a curved profile. In some embodiments, the angle of the junction between the sidewalls 1203s of the microgrooves 1203 and the bottom surface 1203b may be greater than 90 degrees. In addition, the angle α between the horizontal height of the rear surface 111r and the sidewalls 1203s of the microgrooves 1203 may be in the range of from 45 degrees to 90 degrees. That is, in the tube core 1103, the discontinuous pattern 1173 may have a truncated solid (frusta) shape, that is, larger at the base and narrower toward the top (for example, at the horizontal height of the rear surface 111r). In some embodiments, the range of the depth D, pitch P, width W and length L of the microgrooves 1203 may be similar to Figure 4A and Figure 4B The depth D, pitch P, width W, and length L of the micro groove 1201 are shown in FIG. In some embodiments, the surface roughness (arithmetic mean roughness) of the sidewall 1203s of the micro groove 1203 is in the range of 5 μm to 1000 μm.

[0113] Fig. 7A is a schematic top view of die 1104 according to some embodiments of the present disclosure. Figure 7B and Figure 7C are respectively along the tube core 1104 according to some embodiments of the present disclosure Fig. 7ASchematic cross-sectional views taken along line II and line II-II of FIG. In some embodiments, microgrooves 1204 are formed in the tube core 1104 via a wet etching process. In some embodiments, a patterned auxiliary mask (not shown) may be provided on the semiconductor substrate 111 before applying the etchant. The patterned auxiliary mask may include openings that expose some areas, and portions of the semiconductor substrate 111 are removed from the exposed areas to form the microgrooves 1204. In some embodiments, the shape of the microgrooves may be determined according to the material of the semiconductor substrate 111 and the composition of the etchant used. For example, when the semiconductor substrate 111 is made of crystalline silicon, the etchant may include KOH, and the microgrooves 1204 may be formed by exposing the (111) surface (Miller index) of silicon. That is, the sidewalls 1204s of the microgrooves 1204 may be obliquely joined to each other at the bottom of the microgrooves 1204, and the bottom surface 1204b of the microgrooves 1204 may correspond to the junction of the two sidewalls 1204s. In some embodiments, the bottom surface 1204b has a substantially straight profile. In addition, the sidewalls 1204s of the adjacent microgrooves 1204 may be directly joined to each other, so that the discontinuous pattern 1174 has a prism shape including a triangular base. That is, the discontinuous pattern 1174 may include a stripe-shaped pattern having a triangular prismatic shape and extending parallel to each other. In some embodiments, the facing sidewalls 1204s of two adjacent discontinuous patterns (also referred to as stripe-shaped patterns) 1174 may constitute the sidewalls 1204s of the microgrooves 1204 that separate the adjacent stripe-shaped patterns 1174. In these embodiments, the width W of the microgrooves 1204 may be consistent with the pitch P of the microgrooves 1204, and measured according to the distance between the tips R of the adjacent stripe-shaped patterns 1174. However, the present invention is not limited thereto. Fig.7D is a schematic cross-sectional view of a die 1105 according to some alternative embodiments. Fig.7D The cross-sectional view can be taken along Fig. 7A In the tube core 1105 , the micro groove 1205 is also formed by wet etching, and the discontinuous pattern 1175 can be a trapezoidal prism, and the pitch P can be greater than the width W of the micro groove 1205 .

[0114] Fig. 8A1 is a schematic cross-sectional view of a semiconductor device 15 according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 15 includes a package 10 and a cooling cover 600A stacked on the package 10. In some embodiments, the interposer 200, the die 110, and the cooling cover 600A are sequentially stacked on the substrate 400 of the package 10. In some embodiments, the cooling cover 600A faces the rear surface 111r of the die 110. In some embodiments, the cooling cover 600A extends over the cooling region CR and over a portion of the peripheral region PR or over the entirety of the peripheral region PR. In some embodiments, the cooling cover 600A includes a casing 610 and a fluid port 620. In some embodiments, the casing 610 includes a bottom panel (also referred to as a panel) 612, a side panel (also referred to as a panel) 614, and optionally includes a top panel (also referred to as a panel) 616. In some embodiments, the bottom panel 612, the side panel 614, and the top panel 616 may be assembled together to form the casing 610. For example, the side panel 614 can join the bottom panel 612 with the top panel 616. In some embodiments, the fluid port 620 includes a fluid inlet port 620in and a fluid outlet port 620out. In some embodiments, the cooling cover 600A is configured so that the bottom panel 612 faces the rear surface 111r of the tube core 110. A circulation space CS can be formed between the bottom panel 612 and the rear surface 111r of the tube core 110, and the micro grooves 120 and the discontinuous pattern 117 are located in the circulation space CS. In some embodiments, the fluid port 620 is connected to the fluid channel 630. In some embodiments, the fluid port 620 includes a fluid inlet port 620in and a fluid outlet port 620out. Similarly, the fluid channel 630 includes a fluid inlet channel 630in and a fluid outlet channel 630out. In some embodiments, the fluid channel 630 extends at least partially above the cooling zone CR. In this way, the fluid port 620 and the fluid channel 630 are in fluid communication with the circulation space CS and the micro groove 120. In some embodiments, the fluid port 620 has an opening located on the side panel 614. For example, the fluid port 620 opens in the opposite side panels 614 (non-adjacent side panels 614 facing each other) and is connected to the bottom panel 612 through the fluid channel 630. That is, the fluid inlet port 620in can be connected to the bottom panel 612 through the fluid inlet channel 630in, and the fluid outlet port 620out can be connected to the bottom panel 612 through the fluid outlet channel 630out. In some embodiments, the fluid inlet port 620in may include: an interface conduit 622in, which opens in one of the side panels 614; and a connecting conduit 624in, which connects the interface conduit 622in with the fluid inlet channel 630in. In some embodiments, the cross-sectional area of ​​the interface conduit 622in may be larger than the cross-sectional area of ​​the connecting conduit 624in.In some embodiments, the interface conduit 622in and the connecting conduit 624in can be circular conduits. In some alternative embodiments, the interface conduit 622in and the connecting conduit 624in can be rectangular conduits. In some embodiments, the fluid outlet port 620out has a structure similar to the fluid inlet port 620in. That is, the fluid outlet port 620out has an interface conduit 622out and a connecting conduit 624out. In some embodiments, the interface conduits 622in, 622out and the connecting conduits 624in, 624out extend along a first direction. In some embodiments, the first direction is orthogonal to the side panel 614 in which the fluid port 620 is open. In some embodiments, the fluid channel 630 extends along a second direction different from the first direction. In some embodiments, the second direction is parallel to the plane of the side panel 614. In some embodiments, the second direction is orthogonal to the bottom panel 612. For example, the second direction is perpendicular to the first direction.

[0115] In some embodiments, the base plate panel 612 includes a sealing groove 640 that accommodates the sealing ring 700. In some embodiments, the sealing ring 700 is disposed between the cooling cover 600A and the tube core 110 to seal the circulation space CS. In some embodiments, the sealing ring 700 is disposed on the continuous ring pattern 119 in the peripheral region PR. In some embodiments, the fluid port 620 and / or the fluid channel 630 are open in the area of ​​the base plate panel 612 closed by the sealing groove 640. In some embodiments, the sealing ring 700 may include an adhesive material and may fasten the cooling cover 600A to the tube core 110. In some embodiments, sealing the circulation space CS via the sealing ring 700 facilitates the placement and replacement of the cooling cover 600A.

[0116] It should be noted that although Fig. 8A The CoWoS package 10 is illustrated as being attached to the cooling cover 600A, but the present invention is not limited thereto. In some alternative embodiments, other types of packages 10 may be assembled with the cooling cover 600A. For example, in some alternative embodiments, an integrated fan-out (InFO) package may also be assembled with the cooling cover 600.

[0117] Figure 8B is a schematic cross-sectional view of a semiconductor device 15 in use according to some embodiments of the present disclosure. Figure 8C is a schematic top view of a semiconductor device 15 in use according to some embodiments of the present disclosure. In some embodiments, Figure 8B and Figure 8C A semiconductor device 15 is shown with a cooling fluid CL (schematically indicated by arrows) flowing through it. Figure 8C The micro grooves 120 are mesh-like micro grooves (similar to Figure 2B In some alternative embodiments, the semiconductor device 15 may include a die 110 having a microgroove 120 and a discontinuous pattern 117 according to any of the above-disclosed embodiments, for example, the microgroove 120 is a stripe-shaped microgroove (similar to Figure 2A Die 110A is shown).

[0118] In some embodiments, the cooling fluid CL is a coolant. In some embodiments, the cooling fluid CL is a water-based coolant. In some embodiments, additives are added to water to produce the cooling fluid CL. Examples of additives include surfactants, corrosion inhibitors, biocides, antifreeze, etc. In some embodiments, the cooling fluid CL may enter the cooling cover 600A from the fluid inlet port 620in. In some embodiments, the fluid inlet port 620in and the fluid outlet port 620out are connected to a cooling system (not shown), which may include a pump and a radiator connected by a piping system. Interface pipes 622in and 622out may be connected to the piping system of the cooling system. The pump may drive the cooling fluid CL to reach the cooling cover 600A via the fluid inlet port 620in. For example, the cooling fluid CL may enter the semiconductor device 15 via the interface pipe 622in. Thereafter, the cooling fluid CL travels through the connecting pipe 624in to reach the fluid inlet channel 630in. Then, the cooling fluid CL passes through the fluid inlet channel 630in to reach the circulation space CS. In the circulation space CS, the cooling fluid CL may directly contact the cooling region CR of the tube core 110. For example, the cooling fluid CL may pass over the rear surface 111r of the tube core 110. In some embodiments, the cooling fluid CL may enter one end of the micro groove 120, pass through the micro groove 120, and leave the micro groove 120 from the other end of the micro groove 120. For example, Figure 8C As shown in FIG. 1 , when the microgrooves 120 are a mesh of microgrooves formed by intersecting strip-shaped microgrooves extending in two directions (such as with respect to FIG. 1 ), Figure 2BIn some embodiments, the first flow direction D1 of the cooling fluid CL may be parallel to one of the extension directions of the strip-shaped microgrooves. However, the cooling fluid may also flow in the strip-shaped microgrooves extending in the intersecting direction along the second direction D2. In some embodiments, the fluid inlet channel 630in and the fluid outlet channel 630out may have an elongated shape, and the elongation direction thereof is inclined relative to the extension direction of the microgrooves 120. In some embodiments, the elongation direction of the fluid inlet channel 630in and the elongation direction of the fluid outlet channel 630out may be perpendicular to the extension direction of at least some of the microgrooves 120. In some embodiments, the fluid inlet channel 630in and the fluid outlet channel 630out may be open across a plurality of discontinuous patterns 117 and a plurality of microgrooves 120. In some embodiments, the cooling fluid CL may overfill the microgrooves 120 and also cover the discontinuous patterns 117. After exiting the micro trench 120 , the cooling fluid CL may travel through the fluid outlet channel 630 out and exit the semiconductor device 15 from the fluid outlet port 620 out.

[0119] In some embodiments, the temperature of the die 110 may increase during use. In some embodiments, the temperature of the die 110 during use may be higher than the temperature of the cooling cover 600A and the temperature of the cooling fluid CL. In some embodiments, heat exchange may occur between the cooling fluid CL and the die 110 as the cooling fluid CL travels over the die 110. For example, the cooling fluid CL may warm up due to contact with the die 110, so that the temperature of the cooling fluid CL at the fluid outlet port 620out may be higher than the temperature of the cooling fluid CL at the fluid inlet port 620in. In some embodiments, the cooling fluid CL may reenter the piping system of the cooling system via the fluid outlet port 620out. In some embodiments, the cooling fluid CL may be cooled by a heat sink before being pumped back into the semiconductor device 15. In some embodiments, the cooling fluid CL is in direct contact with the semiconductor substrate 111. That is, heat exchange may be achieved between the cooling fluid CL and the semiconductor substrate 111 without the need for an intermediate thermal interface material (TIM). In some embodiments, removing the heat path through the thermal interface material may increase the thermal resistance of the semiconductor device 15.

[0120] Fig. 9A 600B is a schematic cross-sectional view of a semiconductor device 25 according to some embodiments of the present disclosure. The semiconductor device 25 includes a package 10 and a cooling cover 600B. Fig. 9A The semiconductor device 25 shown in FIG. Fig. 8A15 is shown in the figure, so it will not be described in detail herein. In some embodiments, the semiconductor device 25 further includes a screw 810 and the cooling cover 600B further includes a vertical pipe 650 that penetrates through the top panel 616 and the bottom panel 612. In some embodiments, the vertical pipe 650 can be a screw hole, and the cooling cover 600B can be fastened to the package 10 via the screw 810. In some embodiments, the vertical pipe 650 is a closed channel that runs through the housing 610 from the top panel 616 to the bottom panel 612. In some embodiments, the head of the screw 810 can be placed on the top panel 616, and the thread of the screw 810 can be fastened to the substrate 400 after being fitted into the vertical pipe 650. In some embodiments, a threaded hole (not shown) can be formed in the substrate 400 to accommodate the threaded end of the screw 810. In some embodiments, the cooling cover 600B has a greater width than the interposer 200, and the vertical pipe 650 is disposed in the cooling cover 600B so as not to overlap with the interposer 200. That is, the screws 810 may be disposed along the peripheral edge of the interposer 200 .

[0121] Fig. 9B is a schematic cross-sectional view of a semiconductor device 35 according to some embodiments of the present disclosure. Fig. 9B The semiconductor device 35 shown in FIG. Fig. 8A 10 is not shown in the semiconductor device 15, so it will not be described in detail herein. In some embodiments, the semiconductor device 35 further includes a clamp 820. In the semiconductor device 35, the cooling cover 600A can be fastened to the package 10 by applying an inward pressure. For example, the cooling cover 600A and the package 10 can be pressed together by the clamp 820. In some embodiments, the upper arm 822 of the clamp 820 can be placed on the top plate panel 616 of the cooling cover 600A, and the lower arm 824 of the clamp 820 can contact the bottom surface 400b of the substrate 400. The bottom surface 400b of the substrate 400 can be opposite to the top surface 400t on which the package 10 and the cooling cover 600A are stacked. In some embodiments, the upper arm 822 and the lower arm 824 of the clamp 820 can be connected by a clamp body 826. The combined action of the upper arm 822 and the lower arm 824 can firmly fasten the cooling cover 600A and the package 10 together. In some embodiments, a plurality of clamps 820 may be applied to secure the cooling cover 600A to the package 10 .

[0122] Fig. 9C is a schematic cross-sectional view of a semiconductor device 45 according to some embodiments of the present disclosure. Fig. 9C The semiconductor device 45 shown in FIG. Fig. 8AThe semiconductor device 15 is shown in FIG. 1 , and thus will not be described in detail herein. In some embodiments, the semiconductor device 45 includes a package 12 and a cooling cover 600A stacked on the package 12 . Fig. 9C The package 12 shown in FIG. 1 is similar to Fig. 8A The package 10 is shown in the figure, so it will not be described in detail herein. However, the package 12 also includes a die 130 disposed on the interposer 200 next to the die 110. In some embodiments, the die 130 includes a semiconductor substrate 131, and the semiconductor substrate 131 has: a contact pad 133 formed on an active surface of the semiconductor substrate 131; and a passivation layer 135 covering the active surface and exposing a portion of the contact pad 133. In some embodiments, the die 130 is arranged so that the contact pad 133 faces the interposer 200. In some embodiments, the die 130 is connected to the interposer 200 via a conductive terminal 310. The conductive terminal 310 can establish an electrical connection between the contact pad 133 and the interposer 200. In some embodiments, the conductive terminal 310 is a microbump. As Fig. 9C As shown in , the rear surface 131r of the semiconductor substrate 131 faces the cooling cover 600A. In some embodiments, the rear surface 131r of the semiconductor substrate 131 may be substantially flat. In some embodiments, the semiconductor device 45 further includes a heat dissipation layer 830 formed on the rear surface 131r of the tube core 130. In some embodiments, the heat dissipation layer 830 may include a thermal interface material (TIM). In some embodiments, the thermal interface material is an adhesive material. In some embodiments, the thermal interface material includes a grease-based material, a phase change material, a gel, an adhesive, a polymer, a metal material, or a combination thereof. In some embodiments, the thermal interface material includes a lead-tin solder (PbSn), silver paste (Ag), gold, tin, gallium, indium or other suitable thermally conductive materials. Depending on the type of material used, the thermal interface material can be formed by deposition, lamination, printing, plating or any other suitable technology. In some embodiments, the thermal interface material is a gel-type material. In some embodiments, the thermal interface material is a film-type material (e.g., carbon nanotubes or graphite). In some embodiments, the cooling cover 600A is bonded to the die 130 of the package 12 via the heat dissipation layer 830. In some embodiments, the die 130 may be disposed below an area of ​​the cooling cover 600A outside of an area surrounded by the sealing groove 640. In some embodiments, heat generated by the die 130 during operation of the semiconductor device 45 may be dissipated by the heat dissipation layer 830.

[0123] FIG. 10A to FIG. 10DSchematic perspective views of cooling covers 600B, 600C, 600D and 600E according to some embodiments of the present disclosure. In some embodiments, the cooling cover 600C, the cooling cover 600D or the cooling cover 600E may be replaced. Fig. 8A , Fig. 9A , Fig. 9B and Fig. 9C The cooling cover 600A or the cooling cover 600B shown in FIG. FIG. 10A to FIG. 10D In the perspective view of FIG. 610 , the corresponding cooling cover components are shown, although the panels 612 , 614 , 616 of the housing 610 may not necessarily be transparent. Fig. 10A , showing Fig. 9A Cooling cover 600B. Fig. 10A As described in the drawings, the fluid inlet port 620in and the fluid outlet port 620out may be open on opposite side panels 614 of the housing 610. In some embodiments, the fluid inlet port 620in and the fluid outlet port 620out are connected to the fluid inlet channel 630in and the fluid outlet channel 630out, respectively. The sealing groove 640 formed in the bottom panel 612 may surround the fluid inlet channel 630in and the fluid outlet channel 630out, and may pass under the fluid inlet port 620in and the fluid outlet port 620out. The vertical pipe 650 may form a channel that penetrates the cooling cover 600B from the bottom panel 612 to the top panel 616, and may be designed to accommodate screws (e.g., Fig. 9A 8) to secure the cooling cover 600B to an underlying package (e.g. Fig. 9A As shown in FIG. 1 , package 10 ).

[0124] Fig. 10B is a schematic perspective view of a cooling cover 600C according to some embodiments of the present disclosure. Fig. 10B The cooling cover 600C shown in FIG. is similar to Fig. 10A614, and therefore will not be described in detail herein. However, the cooling cover 600C may include: a plurality of fluid ports 620 having openings in the side panels 614; and a plurality of fluid channels 630 having openings in the bottom panel 612. For example, the cooling cover 600C includes: four fluid ports 6201, 6202 having openings in one of the side panels 614; and four fluid ports 6203, 6204 having openings in the side panel 614 opposite to the side panel in which the fluid ports 6201 and 6202 open. In some embodiments, the plurality of fluid ports 620 may be located at different levels. For example, two fluid ports 6201 and two fluid ports 6203 may be open at a first level closer to the bottom panel 612 than the fluid ports 6202 and 6204, and the fluid ports 6202 and 6204 may be located at a second level closer to the top panel 616. In some embodiments, the plurality of fluid ports 620 may be connected to different fluid channels 630 depending on the level at which the fluid ports 620 are located and / or the side panels 614 having the open fluid ports 620. For example, the cooling cover 600C may include three fluid channels 630, two fluid channels (6301 and 6303) of the three fluid channels 630 reach above the first level but do not reach the second level, and one fluid channel (6302) of the three fluid channels 630 reaches above the second level. The three fluid channels 630 may all have openings in the base panel 612, the openings being located within the region closed by the sealing groove 640. In some embodiments, the fluid channel 6302 reaching the second level is located between the two fluid channels 6301, 6303 that do not reach the second level, and is connected to the fluid ports 6202, 6204 located at the second level. In some embodiments, the fluid channels 6301, 6303 that do not reach the second level are connected to the fluid ports 6201, 6203 located at the first level. That is, the fluid port 6201 and the fluid channel 6301 are located on one side of the fluid channel 6302 and are directly connected to each other, while the fluid port 6203 and the fluid channel 6303 are located on the opposite side of the fluid channel 6302 and are directly connected to each other. In some embodiments, the fluid ports 6201, 6203 located at the first level can be used as fluid inlet ports. On the other hand, the fluid ports 6202, 6204 located at the second level can be used as fluid outlet ports. However, the present invention is not limited to this. In some alternative embodiments, the fluid inlet port can be the fluid ports 6202, 6204 located at the second level, and the fluid outlet port can be the fluid ports 6201, 6203 located at the first level.

[0125] Fig. 10C600D according to some embodiments of the present disclosure. The cooling cover 600D may include a plurality of vertical pipes 650, 660, the openings of one end of the plurality of vertical pipes 650, 660 are located in the bottom panel 612 and the openings of the other end are located in the top panel 616. In some embodiments, the vertical pipe 650 is used as a screw hole. In some embodiments, the vertical pipe 650 is located in a zone outside the enclosure of the sealing groove 640. In some embodiments, the vertical pipe 660 is a fluid port and is located in a zone enclosed by the sealing groove 640. In some embodiments, the vertical pipe 660 includes pipes with different diameters. For example, the vertical pipe 660 may include a narrower fluid port 661 and a wider fluid port 662. In some embodiments, the narrower fluid port 661 is arranged toward the corner of the zone enclosed by the sealing groove 640, and the wider fluid port 662 is arranged at the center of the zone enclosed by the sealing groove 640. However, the present invention is not limited thereto. In some embodiments, the diameter of the narrower fluid port 661 is smaller than the diameter of the wider fluid port 662. In some embodiments, the wider fluid port 662 can be used as a fluid inlet port, and the narrower fluid port 661 can be used as a fluid outlet port. However, the present invention is not limited to this. In some embodiments, the fluid inlet port and the fluid outlet port can have openings in the top panel 616 instead of in the side panel 614. In some embodiments, the fluid inlet port and the fluid outlet port can be directly connected to the bottom panel 612 without an intervening fluid channel.

[0126] Fig. 10D is a schematic perspective view of a cooling cover 600E according to some embodiments of the present disclosure. Fig. 10D The cooling cover 600E shown in the Fig. 10A 616 of the housing 610. In some embodiments, the vertical conduit 660 is located in a region enclosed by the sealing groove 640. In some embodiments, the fluid port 620 may be connected to the fluid channel 630, and the vertical conduit 660 may be directly open in the bottom panel 612 without an intervening fluid channel. In some embodiments, the fluid port 620 may be used as a fluid inlet port and the vertical conduit 660 may be used as a fluid outlet port. In some alternative embodiments, the fluid port 620 may be used as a fluid outlet port and the vertical conduit 660 may be used as a fluid inlet port.

[0127] Based on the above, a semiconductor device includes a package and a cooling cover disposed on the package. In some embodiments, the cooling cover allows the coolant flow to directly contact the package, thereby eliminating the need for a thermal interface material. In some embodiments, the direct contact of the coolant with the package can ensure efficient heat exchange, thereby providing a cooling effect for the package. In some embodiments, the cooling cover and the package form a circulation space through which the coolant flows. In addition, in the case where microgrooves are formed on the rear surface of the tube core of the package, the coolant can flow through the microgrooves, thereby improving the heat dissipation efficiency of the semiconductor device.

[0128] In some embodiments of the present invention, a semiconductor device includes a package and a cooling cover. The package includes a first tube core, the first tube core has an active surface and a rear surface opposite to the active surface. The rear surface has a cooling zone and a peripheral zone enclosing the cooling zone. The first tube core includes a plurality of micro grooves located in the cooling zone of the rear surface. The cooling cover is stacked on the first tube core. The cooling cover includes a fluid inlet port and a fluid outlet port located above the cooling zone and connected to the plurality of micro grooves. In some embodiments, the semiconductor device further includes a sealing ring located above the peripheral zone, wherein the sealing ring seals the space between the cooling cover and the plurality of micro grooves. In some embodiments, the sealing ring includes an adhesive material, and the cooling cover is bonded to the first tube core through the sealing ring. In some embodiments, the cooling cover further includes a fluid inlet channel and a fluid outlet channel, the fluid inlet channel is connected to the fluid inlet port and the fluid outlet channel is connected to the fluid outlet port, the fluid inlet port and the fluid outlet port extend along a first direction respectively, and the fluid inlet channel and the fluid outlet channel extend along a second direction perpendicular to the first direction respectively. In some embodiments, the package further comprises: an interposer, wherein the first die is stacked on the interposer, and the active surface is electrically connected to the interposer; and a substrate, wherein the interposer, the first die, and the cooling cover are stacked on the substrate in sequence. In some embodiments, the semiconductor device further comprises a screw, wherein the cooling cover is fixed to the package by the screw. In some embodiments, the semiconductor device further comprises a clamp, wherein the cooling cover is fixed to the package by the clamp. In some embodiments, the package further comprises a second die located next to the first die, the semiconductor device further comprises a heat dissipation layer located between the second die and the cooling cover, and the heat dissipation layer comprises a thermal interface material (TIM). In some embodiments, the bottom surface of the plurality of microgrooves is curved. In some embodiments, the sidewall of each microgroove is inclined.

[0129] In some embodiments of the present invention, a semiconductor device includes a package and a cooling cover. The package includes a substrate, an interposer and a die. The interposer is disposed on the substrate and electrically connected to the substrate. The die is disposed on the interposer and electrically connected to the interposer. The die includes a continuous ring pattern and a plurality of discontinuous patterns enclosed by the continuous ring pattern on the upper surface of the die opposite to the interposer. The cooling cover is stacked on the die. The cooling cover includes a fluid inlet port and a fluid outlet port located above the plurality of discontinuous patterns. In some embodiments, the semiconductor device further includes a sealing ring located between the cooling cover and the continuous ring pattern of the die. In some embodiments, the plurality of discontinuous patterns include a plurality of strip-shaped patterns parallel to each other, and the plurality of strip-shaped patterns are connected to the continuous ring pattern. In some embodiments, the plurality of discontinuous patterns are arranged in an array and spaced apart from the continuous ring pattern. In some embodiments, the plurality of discontinuous patterns are square patterns, triangular patterns, or diamond patterns.

[0130] In some embodiments of the present invention, a method for manufacturing a semiconductor device includes at least the following steps. A tube core is provided. The tube core has an active surface and a rear surface opposite to the active surface. The rear surface has a cooling zone and a peripheral zone enclosing the cooling zone. A plurality of micro grooves are formed in the cooling zone of the rear surface. The tube core is placed on an interposer so that the active surface of the tube core faces the interposer. The interposer is placed on a substrate. A cooling cover is attached to the rear surface of the tube core. The cooling cover includes a fluid inlet port and a fluid outlet port located above the cooling zone and connected to the plurality of micro grooves. In some embodiments, the plurality of micro grooves are formed before the tube core is placed on the interposer. In some embodiments, the plurality of micro grooves are formed after the tube core is placed on the interposer. In some embodiments, the plurality of micro grooves are formed by an etching process. In some embodiments, the plurality of micro grooves are formed by a cutting process.

[0131] Those skilled in the art will appreciate that various modifications and variations may be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover numerous modifications and variations as long as they are within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device, include: A package comprising a first die, the first die having an active surface and a rear surface opposite to the active surface, wherein the rear surface has a cooling zone and a peripheral zone enclosing the cooling zone, and the first die comprises a plurality of micro grooves in the cooling zone of the rear surface; a cooling cover stacked on the first tube core, wherein the cooling cover includes a fluid inlet port and a fluid outlet port located above the cooling zone and communicating with the plurality of micro grooves, wherein the cooling cover includes a base plate panel facing the first tube core, and the base plate panel includes a sealing groove; and A sealing ring is received in the sealing groove and contacts the peripheral region of the first die, wherein the sealing ring seals a space between the cooling cover and the plurality of micro grooves. 2 . The semiconductor device of claim 1 , wherein the sealing ring comprises an adhesive material, and the cooling cover is bonded to the first die through the sealing ring.

3. The semiconductor device according to claim 1, wherein the cooling cover further comprises a fluid inlet channel and a fluid outlet channel, the fluid inlet channel is connected to the fluid inlet port and the fluid outlet channel is connected to the fluid outlet port, the fluid inlet port and the fluid outlet port extend along a first direction respectively, and the fluid inlet channel and the fluid outlet channel extend along a second direction perpendicular to the first direction respectively.

4. The semiconductor device according to claim 1, wherein the package further comprises: include: an interposer, wherein the first die is stacked on the interposer and the active surface is electrically connected to the interposer; as well as A substrate, wherein the interposer, the first die, and the cooling cover are sequentially stacked on the substrate. 5 . The semiconductor device according to claim 1 , further comprising a screw, wherein the cooling cover is fixed to the package by the screw. 6 . The semiconductor device according to claim 1 , further comprising a clamp, wherein the cooling cover is fixed to the package by the clamp.

7. The semiconductor device of claim 1, wherein the package further comprises a second die located beside the first die, the semiconductor device further comprises a heat dissipation layer located between the second die and the cooling cover, and the heat dissipation layer comprises a thermal interface material (TIM).

8. The semiconductor device according to claim 1, wherein bottom surfaces of the plurality of micro trenches are curved.

9. The semiconductor device according to claim 1, wherein a sidewall of each micro trench is inclined.

10. A semiconductor device, include: Package, including: substrate; an interposer disposed on the substrate and electrically connected to the substrate; and a die disposed over the interposer and electrically connected to the interposer, wherein the die includes a continuous ring pattern and a plurality of discontinuous patterns enclosed by the continuous ring pattern on an upper surface of the die opposite to the interposer; a cooling cover stacked on the tube core, wherein the cooling cover includes a fluid inlet port and a fluid outlet port located above the plurality of discontinuous patterns, wherein the cooling cover includes a base plate panel facing the tube core, and the base plate panel includes a sealing groove; and A sealing ring is received in the sealing groove and contacts the continuous ring pattern of the die, wherein the sealing ring seals a space between the cooling cover and the plurality of discontinuous patterns. 11 . The semiconductor device of claim 10 , wherein the plurality of discontinuous patterns include a plurality of stripe-shaped patterns parallel to each other, and the plurality of stripe-shaped patterns are connected to the continuous ring pattern. 12 . The semiconductor device according to claim 10 , wherein the plurality of discontinuous patterns are arranged in an array and are spaced apart from the continuous ring pattern. 13 . The semiconductor device according to claim 12 , wherein the plurality of discontinuous patterns are square patterns, triangle patterns, or diamond patterns.

14. A method for manufacturing a semiconductor device, include: Providing a tube core, the tube core having an active surface and a back surface opposite to the active surface, wherein the back surface has a cooling area and a peripheral area enclosing the cooling area; forming a plurality of micro grooves in the cooling zone of the rear surface; placing the die on an interposer such that the active surface of the die faces the interposer; placing the interposer on a substrate; as well as attaching a cooling cover to the rear surface of the tube core, wherein the cooling cover comprises a fluid inlet port and a fluid outlet port located above the cooling zone and communicating with the plurality of micro grooves, wherein the cooling cover comprises a base plate panel facing the tube core, and the base plate panel comprises a sealing groove; as well as A sealing ring is provided to seal a space between the cooling cover and the plurality of micro grooves, wherein the sealing ring is received in the sealing grooves and contacts the peripheral region of the die. 15 . The method for manufacturing a semiconductor device according to claim 14 , wherein the plurality of micro trenches are formed before placing the die on the interposer. 16 . The method for manufacturing a semiconductor device according to claim 14 , wherein the plurality of micro trenches are formed after placing the die on the interposer.

17. The method for manufacturing a semiconductor device according to claim 14, wherein the plurality of micro grooves are formed by an etching process.

18. The method for manufacturing a semiconductor device according to claim 14, wherein the plurality of micro grooves are formed by a cutting process.

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