Semiconductor device and method of manufacturing semiconductor device

Abstract

Semiconductor devices and methods of manufacturing semiconductor devices. A packaged semiconductor device includes a substrate having a first major surface and an opposing second major surface. A stacked semiconductor device structure is connected to the first major surface and includes a plurality of semiconductor dies having terminals. A conductive interconnect structure electrically connects the terminals of the semiconductor dies together. The semiconductor dies are stacked together such that the terminals are exposed and the stacked semiconductor device structure comprises a stepped profile. The conductive interconnect structure comprises a conformal layer that substantially follows the stepped profile.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to electronic devices, and more particularly, to semiconductor devices and methods for manufacturing semiconductor devices. BACKGROUND

[0002] Existing semiconductor packages and methods for forming semiconductor packages are deficient, for example, resulting in excessive cost, reduced reliability, relatively low performance, or too large package size. Additional limitations and disadvantages of such methods will become apparent to one of ordinary skill in the art through comparison of such methods with the present disclosure, and in view of the following detailed description, taken in conjunction with the accompanying drawings. SUMMARY

[0003] Among other features, the present specification includes a packaged electronic device including a stacked semiconductor device structure having semiconductor dies connected in an offset stack configuration that exposes terminals of the semiconductor dies. Conductive interconnect structures in a conformal configuration electrically connect the terminals of the semiconductor dies together. In some examples, the conformal configuration follows a stepped shape provided by the offset stack configuration of the stacked semiconductor device structure.

[0004] In some examples, the conductive interconnect structures electrically connect one or more of the semiconductor dies to a substrate that can be attached with the stacked semiconductor device structure. In some examples, the conductive interconnect structures are isolated from the semiconductor dies by a dielectric layer. In some examples, the conductive interconnect structures or the dielectric layer are formed using a 3D printing technique. In other examples, the conductive interconnect structures can be formed using a mask plating technique.

[0005] In some examples, a package covers the stacked semiconductor device structure to provide an encapsulated stacked semiconductor device structure. In further examples, multiple encapsulated stacked semiconductor device structures can be attached together to support a package-in-package (PIP) configuration in various packages. In some examples, the conductive interconnect structures including a conformal layer can electrically connect the encapsulated stacked semiconductor devices together in a PIP configuration. The conductive interconnect structures facilitate packaged semiconductor devices having a thinner profile compared to related devices. Additionally, the conductive interconnect structures provide a flexible interconnect configuration between the semiconductor dies and / or the substrate.

[0006] In further examples, a first semiconductor die can be attached to a substrate, and a dielectric layer can be disposed to cover one or more side surfaces of the first semiconductor die immediately adjacent to electrically conductive terminals provided as part of the first semiconductor die. In some examples, the dielectric layer is positioned substantially only along the side surfaces immediately adjacent to the electrically conductive structures, without extending substantially over a major surface of the first semiconductor die (i.e., a majority of the major surface of the first semiconductor die is not covered by the dielectric layer). One or more electrically conductive interconnect layers, including a conformal layer, electrically connect the electrically conductive terminals of the first semiconductor die to the substrate. In other examples, a further semiconductor die can be attached to the first semiconductor die in an offset stack configuration, and can also be electrically connected to the first semiconductor die and / or the substrate through the electrically conductive interconnect layers. In some examples, a further dielectric layer can be substantially only disposed on side surfaces of the further semiconductor die. In some examples, the dielectric layer along the side surfaces of the first semiconductor die includes an outer surface having an arcuate shape. This shape advantageously provides a non-abrupt transition of the electrically conductive interconnect layers from the first semiconductor die to the next semiconductor or substrate.

[0007] In one example, a packaged semiconductor device includes a substrate having a first major surface and a second major surface opposite the first major surface, the substrate including one or more organic dielectric layers. A stacked semiconductor device structure is coupled to the first major surface and includes semiconductor dies having respective die terminals, where the semiconductor dies are coupled together such that the respective die terminals are exposed, and the stacked semiconductor device structure includes a stepped profile. Electrically conductive interconnect structures are located over portions of the stacked semiconductor device structure and couple the die terminals of the semiconductor dies together, where the electrically conductive interconnect structures include a conformal layer that substantially conforms to the stepped profile.

[0008] In some examples, the electrically conductive interconnect structures include a 3D printed conformal layer. In other examples, the electrically conductive interconnect structures include a plated layer. In some examples, at least one of the electrically conductive interconnect structures is located over the substrate and electrically couples at least one of the semiconductor dies to the substrate.

[0009] In one example, a method of forming a packaged semiconductor device includes providing a substrate having a first major surface and a second major surface opposite the first major surface, the substrate including one or more organic dielectric layers. The method includes providing a stacked semiconductor device structure including semiconductor dies each having a respective die terminal. The method includes providing a conductive interconnect structure over portions of the stacked semiconductor device structure, the conductive interconnect structure coupling the die terminals of the semiconductor dies together, wherein the semiconductor dies are coupled together such that the respective die terminals are exposed, and the stacked semiconductor device structure includes a stepped profile, the stacked semiconductor device structure coupled to the substrate; and the conductive interconnect structure includes a conformal layer substantially following the stepped profile.

[0010] In one example, a packaged semiconductor device includes a first substrate having a first major surface and a second major surface opposite the first major surface and first substrate terminals disposed proximate to the second surface of the first substrate, the substrate including one or more organic dielectric layers. A first stacked semiconductor device structure is coupled to the first major surface of the first substrate and includes first semiconductor dies each having a first die terminal, wherein the first semiconductor dies are coupled together such that the first die terminals are exposed, and the first stacked semiconductor device structure includes a first stepped profile. A first conductive interconnect structure electrically couples the first die terminals of the first semiconductor dies together, wherein the first conductive interconnect structure substantially conforms to the first stepped profile. A first encapsulation covers the first stacked semiconductor device structure.

[0011] In one example, a packaged semiconductor device includes a substrate having a first major surface and a second major surface opposite the first major surface, the substrate having a substrate terminal proximate the first major surface. A first semiconductor die is coupled to the first major surface and has a first die terminal, and a first dielectric layer is disposed proximate an edge surface of the first semiconductor die proximate the first die terminal. A conductive interconnect structure is conformal with the first semiconductor die, the first dielectric layer, and a portion of the first major surface of the substrate, the conductive interconnect structure coupling the first die terminal to the substrate terminal. In another example, the packaged semiconductor device can further include a second semiconductor die coupled to the first semiconductor die to provide a stacked semiconductor device structure. The second semiconductor die can include a second die terminal, and the second semiconductor die can be attached to the first semiconductor die laterally offset to expose the first die terminal. A second dielectric layer can be disposed proximate an edge surface of the second semiconductor die proximate the second die terminal. The conductive interconnect structure can be conformal with a portion of the second semiconductor die and the second dielectric layer to couple the second die terminal to at least the first die terminal.

[0012] Other examples are included in the disclosure. Such examples can be found in the drawings, claims, and / or specification of the disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A perspective view of a packaged electronic device of the present specification is shown;

[0014] Figure 2A A cross-sectional view of a packaged electronic device of the present specification is shown;

[0015] Figure 2B A partial enlarged cross-sectional view of a stacked semiconductor device structure of the present specification is shown;

[0016] Figure 2C A partial enlarged cross-sectional view of a stacked semiconductor device structure of the present specification is shown;

[0017] Figure 3 is a flowchart showing an example method for manufacturing a packaged electronic device of the present specification;

[0018] Figure 4A 、 4B , 4C, 4D, 4E, and 4F show cross-sectional views of a packaged electronic device at various stages of manufacture according to the method of Figure 3 ;

[0019] Figure 5a perspective view of a packaged electronic device of the present specification is shown;

[0020] Figure 6 a cross-sectional view of a packaged electronic device of the present specification is shown;

[0021] Figure 7 a cross-sectional view of a packaged electronic device of the present specification is shown;

[0022] Figure 8 a cross-sectional view of a packaged electronic device of the present specification is shown;

[0023] Figure 9A , 9B and 9C show partial cross-sectional views of packaged electronic devices of the present specification at various steps in manufacture;

[0024] Figure 10A , 10B , 10C and 10D show partial cross-sectional views of packaged electronic devices of the present specification at various steps in manufacture;

[0025] Figure 11A , 11B , 11C and 11D show partial cross-sectional views of packaged electronic devices of the present specification at various steps in manufacture;

[0026] Figure 12A , 12B , 12C and 12D show partial cross-sectional views of packaged electronic devices of the present specification at various steps in manufacture;

[0027] Figure 13 a packaged electronic device of the present specification is shown;

[0028] Figure 14 a packaged electronic device of the present specification is shown;

[0029] Figure 15 a packaged electronic device of the present specification is shown;

[0030] Figure 16 a packaged electronic device of the present specification is shown; and

[0031] Figure 17 a packaged electronic device of the present specification is shown. DETAILED DESCRIPTION

[0032] For the sake of simplicity and clarity, the elements of the drawings are not necessarily drawn to scale, and the same reference numbers in different drawings can designate the same elements. Further, for the sake of simplifying the description, the description and details of well-known steps and elements are omitted. As used herein, the term and / or includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of the present disclosure. The recitation "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one example of the present invention. Thus, the appearances of the phrase "in one example" or "in an example" in various places throughout this specification are not necessarily all referring to the same example, albeit they can. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more example embodiments. Additionally, the term while is intended to mean for at least a portion of the time during which an action is initiated. The use of the words approximately, about, or substantially means that the value of an element is intended to be close to a stated value or position. However, as is well known in the art, there are always slight differences from the exact value or position due to manufacturing tolerances. Unless otherwise specified, the words above or including, as used herein, designate an orientation, placement, or relationship in which an element can be in direct or indirect physical contact. The term "or" means any one or more of the items in a list of alternatives. As an example, "x or y" means any element of the three-element set {(x), (y), (x, y)}.As another example, "x, y, or z" means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0033] It should be further understood that the examples shown and described below as appropriate can have examples and / or can be practiced in the absence of any element not specifically disclosed herein. The term "coupled" can be used to describe either a physical or electrical coupling between elements, or an indirect coupling between elements in which one or more other elements are disposed between the coupled elements. For example, if element A is coupled to element B, then element A can be directly contacted with element B, or element A can be indirectly connected to element B through intervening element C.

[0034] Figure 1 A perspective view of an example packaged electronic device 10, such as a packaged semiconductor device 10, is shown in accordance with the present specification. In Figure 1 In the example presented, the packaged electronic device 10 includes a substrate 11; electronic components 16A, 16B, 16C, and 16D, such as electronic devices 16A-16D, semiconductor devices 16A-16D, semiconductor components 16A-16D, packaged semiconductor devices 16A-D, or semiconductor dies 16A-16D; electrically conductive interconnect structures 21, such as electrically conductive interconnect structures 21A, 21B, 21C, 21D, and 21E; and an enclosure structure 36, such as an encapsulant 36 or a package 36. The package 36 is presented as transparent in Figure 1 to disclose the internal contents of the packaged electronic device 10. It should be understood that the package 36 can not be transparent and can be opaque. Additionally, it should be understood that the term "semiconductor die" as used herein can be in the singular as well as in the plural, such as a plurality of semiconductor dies (i.e., more than one).

[0035] According to the present description, the semiconductor dies 16A-16D are attached to one another in an offset stacked shape, profile, or outline 161 or stepped configuration, profile, or outline 161 to allow or facilitate electrical connections or electrical communication between the semiconductor dies 16A-16D and / or between the semiconductor dies 16A-16D and the substrate 11. In the present description, the configuration of the semiconductor dies 16A-16D can also be referred to as a stacked semiconductor device structure 160. Additionally, the conductive interconnect structures 21A-21E are provided as substantially conformal conductive layers or traces that conform to or mimic the offset stacked shape 161 of the semiconductor dies 16A-16D or the stacked semiconductor device structure 160. That is, the conductive interconnect structures 21A-21E follow the stepped outline 161 of the semiconductor dies 16A-16D so as to also include the stepped outline. In this manner, the packaged electronic device 10 is provided with a lower profile electrical interconnect structure that, among other things, facilitates a thinner size or profile as compared to existing devices.

[0036] The substrate 11, the conductive interconnect structures 21A-21E, and the encapsulation 36 can be referred to as a semiconductor package 190, and the semiconductor package 190 can provide protection for the semiconductor dies 16A-16D from external elements and / or environmental exposure. Additionally, the semiconductor package 190 can provide electrical coupling from external electrical components (not shown) to the conductive interconnect structures 21A-21E and the semiconductor dies 16A-16D.

[0037] The substrate 11 can be selected from among common circuit boards (e.g., rigid circuit boards and flexible circuit boards), multilayer substrates, laminated substrates, coreless substrates with built-up layers, core substrates, ceramic substrates, lead frame substrates, molded lead frame substrates, or similar substrates known to those of ordinary skill in the art. In this regard, the present description is not intended to be limited to any particular type of substrate 11. The semiconductor dies 16A-16D can be the same type of semiconductor device or different types of semiconductor devices within the stacked semiconductor device structure 160. The semiconductor dies 16A-16D can include integrated circuit devices such as memory devices, application specific integrated circuit devices (“ASICs”), controller devices, power supply devices, signal processing devices, microcontroller devices, microprocessor devices, sensor devices, optical devices, or other devices known to those of ordinary skill in the art. As will be explained in greater detail later, the conductive interconnect structures 21A-21E include a conductive material such as one or more metals and can be provided through plating, printing, or other deposition techniques.

[0038] Figure 2AA cross-sectional view of a packaged electronic device, such as packaged semiconductor device 10 (or other packaged electronic device as described herein) in accordance with the present specification is shown. In the present example, semiconductor die 16A is attached or connected to substrate top surface 110A of substrate 11 by attachment material 18. Semiconductor die 16A is provided with one or more die terminals 165A, such as conductive pads 165A, disposed above, on, as part of, or within semiconductor die 16A. Conductive pads 165A can comprise a conductive material, such as one or more metallic materials, and can be provided using evaporation, sputtering, plating, or other deposition techniques. Masking and etching techniques can be used to pattern the conductive pads. In some examples, conductive pads 165A are configured to facilitate input and output of electrical signals to and from semiconductor die 16A. Such signals can include data signals, bias signals, ground signals, or other signals known to those of ordinary skill in the art.

[0039] Substrate 11 can be provided with substrate terminals 111 or conductive pads 111 proximate to substrate top surface 110A, which can be further connected to conductive pads 112 or conductive pads 112 proximate to substrate bottom surface 110B of substrate 11 by conductive layers / vias 114 within substrate 11. Substrate 11 further includes a dielectric or passivation structure 115 comprising one or more dielectric layers. Dielectric structure 115 can comprise one or more organic dielectric layers. In some examples, substrate 11 can be further provided with solder mask structures 22 between conductive pads 112 proximate to substrate bottom surface 110B.

[0040] In some examples, the substrate 11 can be a pre-formed substrate. The pre-formed substrate can be manufactured prior to attachment to an electronic device and can include dielectric layers between respective conductive layers. The conductive layers can include copper and can be formed using a plating process. The dielectric layers can be formed primarily of organic materials. The dielectric layers can be relatively thick non-photodefinable layers that can be attached in pre-formed films rather than as liquids, and can contain resins with fillers such as strands, weaves, and / or other particles for rigidity and / or structural support. Because the dielectric layers are non-photodefinable, features such as vias or openings can be formed by using a drill or a laser. In some examples, the dielectric layers can include prepreg materials or anisotropic build-up film (ABF). The pre-formed substrate can contain a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layers and conductive layers can be formed on the permanent core structure. In other examples, the pre-formed substrate can be a coreless substrate that omits a permanent core structure, and the dielectric layers and conductive layers can be formed on a sacrificial carrier that is removed after forming the dielectric layers and conductive layers and prior to attachment to an electronic device. The pre-formed substrate can be referred to as a printed circuit board (PCB) or laminate substrate. Such pre-formed substrates can be formed by a semi-additive or modified semi-additive process. Other substrates in the present disclosure can also include pre-formed substrates.

[0041] In some examples, the external interconnects 211 can be attached to the conductive pads 112 and can include conductive materials such as solder balls, solder bumps, copper bumps, nickel gold bumps, or similar materials known to those of ordinary skill in the art. In other examples, the external interconnects 211 are omitted and the conductive pads 112 can be configured to directly connect or attach to a next level assembly such as a printed circuit board.

[0042] The attachment material 18 can include a thermally and electrically conductive material, or a thermally and non-conductive material. In some examples, the attachment material 18 includes an epoxy type die attach material. In other examples, the attachment material 18 can be a solder material such as a solder paste, or other materials known to those of ordinary skill in the art. The attachment material 18 is generally used to provide mechanical fixation of the semiconductor die 16A to the substrate 11. In other examples, the attachment material 18 can enable heat transfer from the semiconductor die 16A to the substrate 11.

[0043] Semiconductor die 16B is attached to the top surface of semiconductor die 16A by an attachment material 19, which can be similar or different from attachment material 18. In some examples, attachment material 19 includes an epoxy-type die attach material. In some examples, and similar to semiconductor die 16A, semiconductor die 16B further includes die terminals 165B, such as conductive pads 165B, disposed above, on, as part of, or within semiconductor die 16B. Attachment material 19 is generally used to provide mechanical fixation of semiconductor die 16B to semiconductor die 16A. Semiconductor die 16C is attached to the top surface of semiconductor die 16C by an attachment material 19, and includes die terminals 165C, such as conductive pads 165C, disposed above, on, as part of, or within semiconductor die 16C. Semiconductor die 16D is attached to the top surface of semiconductor die 16C by an attachment material 19, and includes die terminals 165D, such as conductive pads 165D, disposed above, on, as part of, or within semiconductor die 16D. Attachment material 19 is generally used to provide mechanical fixation of semiconductor die 16B to semiconductor die 16A, semiconductor die 16C to semiconductor die 16B, and semiconductor die 16D to semiconductor die 16C. In other examples, attachment material 19 can be configured to enable heat transfer from semiconductor dies 16 to substrate 11 or one or more other heat spreader structures (not shown).

[0044] According to the present description, semiconductor dies 16A-16D are provided with an offset stack shape 161. This provides a stacked semiconductor device structure 160 in which conductive pads 165A-165D of semiconductor dies 16A-16D are exposed to the exterior to facilitate electrical interconnection between semiconductor dies 16A-16D. In some examples, conductive pads 165A-165D can include aluminum, an aluminum alloy, copper, a solderable metal, or other conductive materials known to those of ordinary skill in the art.

[0045] It should be appreciated that although stacked semiconductor device structure 160 is shown with four semiconductor dies 16A-16D, according to the present description, more or fewer semiconductor dies can be used, including a single semiconductor die 16. Additionally, those of ordinary skill in the art will appreciate that semiconductor dies 16A-16D are shown in a simplified form to not interfere with the present description, and can further include multiple diffusion regions, multiple conductive layers, and multiple dielectric layers.

[0046] According to the present specification, the insulating film 27, dielectric layer 27, passivation film 27, passivation layer 27, or passivation structure 27 is disposed on some or all of the exposed surfaces of the stacked semiconductor device structure 160 and the substrate top surface 110A of the substrate 11. In some examples, the dielectric layer 27 can cover all of the side surfaces of at least one of the semiconductor dies 16. In some examples, the dielectric layer 27 includes an inorganic dielectric, such as an oxide material, such as silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or hafnium oxide, combinations thereof, or similar materials known to those of ordinary skill in the art. In one example, the dielectric layer 27 can be zirconium oxide in a polymer suspension (e.g., PVP) and can have a thickness in a range of about 2 microns to about 50 microns. In some examples, the dielectric layer 27 can include an organic material, such as polyimide, a polymer, polyimide silicone, other silicones, elastomers, UV-curable materials, thermoset liquid crystal polymers such as polybenzoxazole (PBO), combinations thereof, or similar materials known to those of ordinary skill in the art. In some examples, the dielectric layer 27 can be formed using deposition, dispensing, coating, or screen printing techniques. In some examples, the dielectric layer 27 can be cured after deposition. In further examples, the dielectric layer 27 can include one or more different layers of material.

[0047] The openings 270A, 270B, 270C, and 270D are disposed in the dielectric layer 27 over or adjacent to the conductive pads 165A, 165B, 165C, and 165D to respectively expose at least portions of the conductive pads 165A-165D. Additionally, the opening 270E is disposed over or adjacent to the conductive pad 111 on the substrate 11. The openings 270A-270E can be provided using masking and removal processes such as photolithographic masking and etching processes. In some examples, a masking layer is provided prior to forming the dielectric layer 27. In other examples, a masking layer is provided after forming the dielectric layer 27. In some examples, the dielectric layer 27 has a thickness in a range of about 2 microns to about 50 microns or more. In some examples, the dielectric layer 27 has a thickness in a range of about 2 microns to about 10 microns. In other examples, the dielectric layer 27 has a thickness in a range of about 25 microns to about 50 microns or more.

[0048] Conductive interconnect structures 21 are disposed on or superimposed on the stacked semiconductor device structure 160 to electrically connect semiconductor dies 16A-16D together, and in some instances, electrically connect one or more semiconductor dies 16A-16D to the substrate 11. According to this specification, the conductive interconnect structure 21 has a shape that substantially conforms to or substantially mimics the stacked semiconductor device structure 160. The conductive interconnect structure 21 is disposed on or overlaps with the top surfaces 167A, 167B, 167C, and 167D and the side surfaces 168A, 168B, 168C, and 168D of the semiconductor dies 16A-16D.

[0049] Figure 2A A conductive interconnect structure 21A is shown, which is one of the conductive interconnect structures 21. In some instances, the conductive interconnect structure 21 comprises one or more metals, such as copper, copper alloys, gold, silver, or other conductive materials known to those skilled in the art. In some instances, the conductive interconnect structure 21 can be provided using 3D printing technology, which generally refers to a method of forming a three-dimensional object using additive processing based on a digitally created file. More specifically, the object can be created by continuously laying down many thin layers of material using a 3D printing device. Examples of 3D printing types include metal printing, such as selective laser melting (SLM) and electron beam melting (EBM); selective laser sintering (SLS); jetting processes, stereolithography (SLA); and fusion deposition modeling (FDM). In other instances, plating, deposition, coating, dispensing, or screen printing techniques can be used to form the conductive interconnect structure 21. In still other instances, the conductive interconnect structure 21 may comprise one or more layers comprising different materials. In some instances, 3D printing technology can also be used to form a dielectric layer 27 or a portion thereof.

[0050] In some instances, the conductive interconnect structure 21 may include, for example: Figure 1 The end portions 216A, 216B, 216C, 216D, and 216E shown have a gradually decreasing thickness, and at these end portions, conductive interconnect structures 21A-21E terminate on the substrate 11. In some embodiments, end portions 216A-216E may each include, for example... Figure 1 The wedge shape is shown. One advantage of this shape is that it reduces sharp edges and / or corners at the termination locations of the end portions 216A-216E, thereby reducing the likelihood of damage to the conductive interconnect structures 21A-21E during subsequent processing. In some instances, 3D printing technology can be used to provide the end portions 216A-216E in the desired shape (such as the tapered shape described herein).

[0051] In some examples, the encapsulant 36 can be a polymer-based composite material, such as an epoxy with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The encapsulant 36 includes a non-conductive and environmentally friendly material that protects the stacked semiconductor device structure 160 from external elements and contaminants. The encapsulant 36 can be formed using paste printing, compression molding, transfer molding, overmolding, liquid encapsulant molding, vacuum lamination, other suitable applicators, or other processes known to those skilled in the art. In some embodiments, the encapsulant 36 is an epoxy molding compound (“EMC”) and can be formed using transfer or injection molding techniques.

[0052] Figure 2B A partial enlarged cross-sectional view of an example stacked semiconductor device structure 160A in accordance with the present specification is shown. It should be understood that the stacked semiconductor device structure 160A can be used with any of the example packaged electronic devices described herein (e.g., packaged electronic devices 10, 10A, 10AA, 10BB, 10CC, 20, 30, 30AA, 30BB, 30CC, and / or 40) and any variations thereof. The stacked semiconductor device 160A only shows details of semiconductor dies 16D and 16C, but it should be understood that similar features can be included for semiconductor dies 16B and / or 16A included in the stacked semiconductor device 160A, as well as additional semiconductor dies.

[0053] As Figure 2B shown, the semiconductor die 16D includes a passivation layer 164D over the top surface 167D, and the semiconductor die 16C includes a passivation layer 164C over the top surface 167C. The passivation layers 164C and 164D can be one or more dielectric layers, such as silicon oxide, silicon nitride, or combinations thereof, or the passivation layers 164C and 164D can be a polymeric material, such as a polyimide material. The passivation layers 164C and 164D function to protect and electrically insulate active devices and conductive interconnects within or on the semiconductor dies 16C and 16D. As Figure 2B shown, the passivation layer 164D is provided with openings to expose the die terminals 165D, and the passivation layer 164C is provided with openings to expose the die terminals 165C. The passivation layers 164C and 164D can be formed while the semiconductor dies 16C and 16D are in wafer form. Processing techniques such as chemical vapor deposition (including low pressure, low temperature, or plasma enhanced), spin-on deposition, thermal oxidation, or similar processes can be used to form the passivation layers 164C and 164D. Photolithography and etching techniques can be used to provide the openings in the passivation layers 164C and 164D.

[0054] In some examples, the dielectric layer 27 is located over portions of the passivation layer 164D over the top surface 167D of the semiconductor die 16D and includes openings to expose portions of the passivation layer 164D and the die terminal 165D. That is, in the present example, the dielectric layer 27 covers or is located over a majority of the top surface 167D. The dielectric layer 27 is further disposed over the side surface 168D of the semiconductor die 16D. In accordance with the present specification, the portion of the dielectric layer 27 over the side surface 168D and a portion of the top surface 167C of the semiconductor die 16C does not have a uniform thickness. In some examples, this portion of the dielectric layer 27 has a thickness 275B at which the side surface 168D intersects or abuts the attachment material 19 and the passivation layer 164C of the semiconductor die 16C. In some examples, the thickness 275B is thicker than the thickness 275A of the dielectric layer 27 toward the top surface 167D of the semiconductor die 16D and thicker than the thickness 275C of the dielectric layer 27 along the top surface 167C of the semiconductor die 16C proximate the die terminal 165C. Additionally, as shown, the outer surface of the dielectric layer 27 over the side surface 168D of the semiconductor die 16D and the top surface 167C of the semiconductor die 16C has an arcuate or curved shape 276 that advantageously provides a smoother or non-abrupt transition area for the conductive connection structure 21 between the semiconductor dies. This avoids sharp corners, notches, or transitions that can result in thinner areas or missing portions of the conductive connection structure 21. Such defects can result in reliability issues due to issues such as increased electrical resistance that can cause hot spots. As shown, the conductive connection structure 21 advantageously follows the contour of the dielectric layer 27 such that the conductive connection structure 21 has a more uniform thickness as it transitions from the semiconductor die 16D to the semiconductor die 16C. Figure 2B As shown, the outer surface of the dielectric layer 27 over the side surface 168D of the semiconductor die 16D and the top surface 167C of the semiconductor die 16C has an arcuate or curved shape 276 that advantageously provides a smoother or non-abrupt transition area for the conductive connection structure 21 between the semiconductor dies. This avoids sharp corners, notches, or transitions that can result in thinner areas or missing portions of the conductive connection structure 21. Such defects can result in reliability issues due to issues such as increased electrical resistance that can cause hot spots. As shown, the conductive connection structure 21 advantageously follows the contour of the dielectric layer 27 such that the conductive connection structure 21 has a more uniform thickness as it transitions from the semiconductor die 16D to the semiconductor die 16C. Figure 2B As shown, the conductive connection structure 21 advantageously follows the contour of the dielectric layer 27 such that the conductive connection structure 21 has a more uniform thickness as it transitions from the semiconductor die 16D to the semiconductor die 16C.

[0055] Figure 2C A partial enlarged cross-sectional view of an example stacked semiconductor device structure 160B in accordance with the present specification is shown. It should be understood that the stacked semiconductor device structure 160B can be used with any of the example packaged electronic devices described herein (e.g., packaged electronic devices 10, 10A, 10AA, 10BB, 10CC, 20, 30, 30AA, 30BB, 30CC, and / or 40) and any variations thereof. The stacked semiconductor device 160B only shows details of the semiconductor dies 16D and 16C, but it should be understood that similar features can be included for the semiconductor dies 16B and / or 16A included in the stacked semiconductor device 160B as well as additional semiconductor dies.

[0056] The stacked semiconductor device structure 160B is similar to the stacked semiconductor device structure 160A, and only the differences will be described. In the stacked semiconductor device structure 160B, the dielectric layer 27 is primarily disposed on the side surfaces of the semiconductor die (such as side surfaces 168D, 168C, etc.), and only on a portion of the top surface of the semiconductor die adjacent to the side surfaces. That is, in this example, most of the top surface 167D of the semiconductor die 16D is not covered by the dielectric layer 27. In some examples, a portion of the dielectric layer 27 is located only on the top surface 167D between the die terminal 165D and the side surface 168D. The dielectric layer 27 in the stacked semiconductor device structure 160B has the same characteristics as the stacked semiconductor device structure 160A, which includes an arcuate shape 276, which provides a smoother transition for the conductive connection structure 21, thereby improving the reliability of the stacked semiconductor device structure 160B.

[0057] Figure 3 This is a flowchart illustrating an example method 300 for providing a packaged electronic device with conductive interconnect structures, such as a packaged semiconductor device 10 having a stacked semiconductor device structure 160 and conductive interconnect structures 21A-21E. Figure 4A , 4B 4C, 4D, 4E and Figure 4F This is a cross-sectional view of the packaged semiconductor device 10 at various manufacturing stages according to method 300.

[0058] Block S310 of method 300 includes providing a stacked semiconductor device subassembly, the stacked semiconductor device subassembly including a substrate and a stacked semiconductor device structure attached to a surface of the substrate. For example, the substrate may be similar to substrate 11, and the stacked semiconductor device structure may be similar to... Figure 4A The presented stacked semiconductor device structure 160, Figure 4A This is a cross-sectional view of a stacked semiconductor device subassembly 10A at a certain manufacturing step. It should be understood that although only one stacked semiconductor device is shown, multiple stacked semiconductor devices may be provided, as will be described later. In other instances, a single semiconductor die, such as semiconductor die 16A, may be the only semiconductor die attached to substrate 11.

[0059] In some examples, the substrate, such as substrate 11, can be selected from a common circuit board (e.g., rigid circuit board and flexible circuit board), a multi-layer substrate, a laminated substrate, a coreless substrate with a build-up layer, a coreless substrate, a ceramic substrate, a leadframe substrate, a molded leadframe substrate, or similar substrates known to those of ordinary skill in the art. In other examples, the substrate is a copper-based leadframe (e.g., a leadframe including copper / iron / phosphorus; 99.8 / 0.01 / 0.025), a copper alloy-based leadframe (e.g., a leadframe including copper / chromium / tin / zinc; 99.0 / 0.25 / 0.22), or an alloy 42-based leadframe (e.g., a leadframe including iron / nickel; 58.0 / 42.0). In further examples, the substrate can include other conductive or non-conductive materials, which can be further plated (in whole or in part) with one or more conductive layers.

[0060] In some examples, the stacked semiconductor device structure 160 is connected to the substrate top surface 110A of the substrate 11 by the attachment material 18 described previously. In some examples, first semiconductor die 16A is connected to the substrate 11 by the attachment material 18, then semiconductor die 16B is connected to semiconductor die 16A by the attachment material 19 described previously, then semiconductor die 16C is connected to semiconductor die 16B by the attachment material 19, and then semiconductor die 16D is connected to semiconductor die 16C by the attachment material 19 to provide the stacked semiconductor device structure 160 having an offset stack shape 161, as Figure 4A illustrated.

[0061] Block 320 of the method 300 includes providing a dielectric layer over the stacked semiconductor device and the substrate, the dielectric layer having an opening exposing a conductive pad that is part of the stacked semiconductor device structure. For example, the dielectric layer can be similar to the dielectric layer 27 having openings 270A, 270B, 270C, 270D, and 270E, as Figure 4B illustrated. In other examples, the dielectric layer 27 can be as depicted in Figure 2B and 2C illustrated. The dielectric layer 27 and the openings 270A-270E can be provided as described previously. As will be described later, in some examples, the dielectric layer 27 can be disposed only on the side surface portions of the stacked semiconductor device structure 160 at which the conductive interconnect structure 21 is to be formed or provided.

[0062] Block S330 of the method 300 includes providing a seed layer over the stacked semiconductor device. For example, the seed layer can be similar to the seed layer 29, as Figure 4CAs shown, seed layer 28 can be disposed to overlie at least portions of dielectric layer 27 proximate to locations where electrically conductive interconnect structures 21 are to be formed. In some examples, seed layer 28 provides a starting layer for a subsequent electroplated layer, and can be used to establish the texture and grain size of the electroplated layer. In some examples, seed layer 28 includes an electrically conductive material such as copper, and can be formed using physical vapor deposition, chemical vapor deposition, and / or atomic layer deposition techniques. In some examples, a thin barrier layer (not shown) such as tantalum or tantalum nitride can be formed prior to forming seed layer 28. In some examples, seed layer 28 can be about 100 nanometers thick and can be patterned after it is formed, such as by a lift-off process. Figure 4C As generally shown. In other examples, seed layer 28 covers all exposed surfaces of dielectric layer 27 and is not patterned. As Figure 4C As further shown, seed layer 28 physically contacts electrically conductive pads 165A-165D and 111 through openings 270A-270E, respectively.

[0063] Block S340 of method 300 includes providing a patterned mask layer over the seed layer. In some examples, as Figure 4D As shown, patterned mask layer 46 is disposed over seed layer 28. In some examples, patterned mask layer 46 includes a photoresist mask that adheres well to dielectric layer 27 and is chemically stable to an electroplating process. In some examples, patterned mask layer 46 can include a cross-linked negative photoresist having a thickness of up to about 30 microns. As Figure 4D As shown, patterned mask layer 46 includes one or more openings 460, which in some examples correspond to locations where electrically conductive interconnect structures such as electrically conductive interconnect structures 21 are to be formed.

[0064] Block S350 of method 300 includes forming electrically conductive interconnect structures that are electrically connected to electrically conductive pads on the stacked semiconductor device and the substrate. For example, as Figure 4E As shown, electrically conductive interconnect structures 21 can be formed in openings 460. In some examples, subassembly 10A can be placed in an electroplating bath, and an electroplating process can be used to form electrically conductive interconnect structures 21 with current passing through seed layer 28. In some examples, electrically conductive interconnect structures 21 include one or more metals such as copper or a combination of metals including copper. In some examples, electrically conductive interconnect structures 21 have a thickness in a range of about 5 microns to about 25 microns. In other examples, electrically conductive interconnect structures 21 can have a thickness in a range of about 20 microns to about 70 microns or more.

[0065] Block S360 of the method 300 includes removing the patterned mask layer and portions of the seed layer 28 that are covered by the patterned mask layer. In some examples, the patterned mask layer 46 can be removed using a photoresist stripping process, and portions of the seed layer 28 that are exposed after removal of the patterned mask layer 46 can be removed using an appropriate chemical etchant. In some examples in which the seed layer 28 includes copper, a dilute sulfuric acid (H2SO4) or alkaline dip cleaner can be used to remove the exposed seed layer 28. This provides the sub-assembly 10A with electrically conductive interconnect structures 21 that are electrically connected to the electrically conductive pads 165A-165D and 111, as Figure 4F shown. In some examples, only some of the electrically conductive interconnect structures 21 are directly connected to the substrate 11.

[0066] In a subsequent step, a package 36 can be provided to cover portions of the stacked semiconductor device structure 160 and the substrate 11, and then external interconnects 211 can be attached to the electrically conductive pads 112 to provide a packaged semiconductor device 10 as Figure 2A shown. In other examples, the external interconnects 211 are not used, and the packaged semiconductor device 10 can be attached to a next level assembly using the electrically conductive pads 112.

[0067] Figure 5 A perspective view of an example packaged electronic device 20, such as a packaged semiconductor device 20, in accordance with the present specification is shown. Figure 6 A cross-sectional view of the packaged semiconductor device 20 is shown. The packaged semiconductor device 20 is similar to the packaged semiconductor device 10, and only the differences will be described below.

[0068] As Figure 5As shown, conductive interconnect structures 210, such as conductive interconnect structures 210A, 210B, 210C, and 210D, include at least one interconnect structure with a different shape compared to other conductive interconnect structures. In this example, conductive interconnect structure 210B includes a non-linear shape and laterally crosses one or more top device surfaces of semiconductor dies 16A-16D. In this example, conductive interconnect structure 210B includes a portion 210BA laterally crossing the top device surfaces of semiconductor dies 16C and 16D, and a portion 210BB laterally crossing the top device surface of semiconductor die 16B. In this way, conductive interconnect structure 210B contacts more than one die terminal on the semiconductor die, said more than one die terminal being laterally offset and misaligned with each other. Conductive interconnect structure 210B is an example of a conductive interconnect structure that electrically interconnects at least two die terminals or conductive pads 165 within a semiconductor die 16 (such as semiconductor die 16B). Additionally, conductive interconnect structure 210C includes a conductive interconnect structure that connects a smaller number of die terminals together compared to, for example, conductive interconnect structures 210A, 210B, and 210D. In some instances, 3D printing technology can be used to provide conductive interconnect structures 210A-210D. Although conductive interconnect structures 210A-210D are shown to have a more stepped shape, wherein they terminate on substrate 11, it should be understood that conductive interconnect structures 210A-210D can have, for example, a stepped shape. Figure 1 The end portions depicted are 216A-216E.

[0069] The conductive interconnect structure 210B is an example of a conductive interconnect structure that would be expensive to replicate using conventional interconnect structures (such as wire bonding). More specifically, the conductive interconnect structure 210B is configured to electrically connect multiple conductive pads at different locations within a semiconductor die to facilitate flexible and reliable interconnect schemes that support more complex configurations.

[0070] One of conductive pads 165D and one of conductive pads 165C are in Figure 5 The conductive pads are shown as being exposed from one of the conductive interconnect structures 210A-210D. These conductive pads can remain electrically floating or be interconnected to other conductive structures via through-silicon vias (TSVs) or via wires. In other instances, a second dielectric layer 27 can be disposed on top of the conductive interconnect structure 210B, and conductive pads 165D can be connected to conductive pads 165C using conductive interconnect structures. Another difference from the packaged semiconductor device 20 is that the dielectric structure 271 can be configured as a plurality of dielectric portions 271A, 271B, 271C, and 271D. In some instances, such as Figures 5-6As shown, the dielectric portions 271A-271D can be disposed to only abut or be adjacent to the side surfaces of the semiconductor dies 16A-16D to help apply the interconnect structures 271A-271D conformally on such side surfaces. This is similar to the examples shown in Figure 2C In some examples, the dielectric portions 271A-271D are similar to the dielectric layer 27 and can be formed by 3D printing or by deposition and patterning techniques. In other examples, the dielectric portions 271A-271D can overlap the top surfaces of the semiconductor dies 16A-16D to a lesser extent, but the dielectric portions 271A-271D do not substantially overlap the major surfaces of the semiconductor dies 16A-16D. This can be similar to the examples shown in Figure 2C

[0071] Figure 7 A cross-sectional view of a packaged electronic device 30, such as a packaged semiconductor device 30, in accordance with the present specification is shown. The packaged semiconductor device 30 is similar to the packaged semiconductor device 10, and only the differences will be described hereafter. In the packaged semiconductor device 30, the uppermost semiconductor die 16D of the stacked semiconductor device structure 160 is electrically connected to the substrate 11.

[0072] ​In the packaged semiconductor device 30, the substrate 11 is provided in the form of a redistribution layer (RDL) substrate. The RDL substrate can include one or more electrically conductive redistribution layers and one or more dielectric layers that can be formed layer-by-layer (a) over an electronic device that is electrically coupled to the RDL substrate or (b) over a carrier that is completely removed or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate can be fabricated layer-by-layer as a wafer-level substrate on a circular wafer in a wafer-level process and / or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate can be formed in an additive build-up process that can include one or more dielectric layers stacked alternately with one or more electrically conductive layers that define respective electrically conductive redistribution patterns or traces configured to collectively (a) fan out electrical traces beyond a footprint of the electronic device and / or (b) fan in electrical traces within the footprint of the electronic device. The electrically conductive redistribution patterns can be formed using a plating process (e.g., an electroplating process or an electroless plating process). The electrically conductive redistribution patterns can include an electrically conductive material such as copper or other platable metal. The electrically conductive redistribution patterns can be positioned using a photopatterning process (e.g., a photolithography process) and a photoresist material to form a photoresist mask. The dielectric layers of the RDL substrate can be patterned by a photopatterning process that can include a photoresist mask through which light is exposed to features of the photo pattern desired in the dielectric layer, such as vias in the dielectric layer. The dielectric layers can be made of a photo-definable organic dielectric material (e.g., polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO)). Such photo-definable dielectric materials can be spin-coated or otherwise coated in a liquid form rather than attached in the form of a pre-formed film. To allow the desired photo-defined features to be properly formed, such photo-definable dielectric materials can omit structural enhancers or can be filler-free, free of strands, weaves, or other particles that can interfere with light from the photopatterning process. In some examples, this filler-free characteristic of the filler-free dielectric material can allow a thickness of the resulting dielectric layer to be reduced. In some examples, the RDL substrate can omit a permanent core structure or carrier such as a dielectric material including a bismaleimide triazine (BT) or FR4, and these types of RDL substrates can be referred to as coreless substrates. Other substrates in this specification can also include RDL substrates.

[0073] In some embodiments, substrate 11 may include dielectric layers 115A and 115B, conductive layers 114A and 114B, and conductive pads 112. Dielectric layers 115A and 115B may include organic materials. In some embodiments, substrate 11 further includes external interconnects 211. It should be understood that in other embodiments, substrate 11 may include more passivation layers and conductive layers than shown in this embodiment.

[0074] In this example, the opening in the package 36 along the first surface 360 ​​of the package is provided as follows: Figure 7 The conductive interconnect layer 21A, as shown, is electrically connected to the conductive layer 114A of the substrate 11. Other portions of the conductive layer 114A may be electrically connected to other conductive interconnect layers 21 within the packaged semiconductor device 30. In some instances, openings in the package 36 can be provided by removing portions of the package 36 after its formation to expose conductive interconnect structures 21 adjacent to the semiconductor die 16D. This may include masking and etching techniques, grinding techniques, polishing techniques, or other removal techniques known to those skilled in the art. In other instances, film-assisted molding can be used to expose the conductive interconnect structures 21 through the first surface 360 ​​of the package 36. In yet another embodiment, a heat-removing structure, such as a heat sink (not shown), can be attached to the semiconductor die 16A exposed through the second surface 361 of the package. In other instances, the substrate 11 in the packaged semiconductor device 30 may be a laminated substrate.

[0075] Figure 8 A cross-sectional view of a packaged electronic device 40, such as a packaged semiconductor device 40, according to this specification is shown. The packaged semiconductor device 40 is similar to packaged semiconductor devices 10 and 30 and uses a substrate 11 configured as an RLD-type substrate, wherein a semiconductor die 16A is attached to the top substrate surface 110A of the substrate 11.

[0076] Figure 9A , 9B Figures 9 and 9C show partial cross-sectional views of various packaged electronic devices (such as packaged semiconductor devices 10AA, 10BB, and 10CC) at various stages of manufacturing according to this specification. In some instances, packaged semiconductor devices 10AA, 10BB, and 10CC are similar to... Figure 1 The packaged semiconductor device 10 shown in 2 and 4A to 4F is provided to demonstrate a method of forming a package 36 and other subsequent processing steps after attaching the stacked semiconductor device 160 to the substrate 11 and after the conductive connection structure 21 has been formed to electrically connect the semiconductor die and / or substrate together. For ease of understanding, in Figure 9A , 9Band fewer elements are labeled in FIGS. 9C to not make the depiction overly complex. Details of the individual elements are shown, for example, in Figure 1 , 2, and 4A-4F.

[0077] Figure 9A Packaged semiconductor devices 10AA, 10BB, and 10CC attached to substrates 11 are shown, which can be provided in an NxM matrix of multiple substrates 11 (where N and / or M can be > 2). In the present example, encapsulants 36 are provided in the form of overmolded encapsulants that cover each of stacked semiconductor device structures 160A, 160B, and 160C as well as the top substrate surface 110A of substrate 11. In other examples, multiple or single encapsulants 36 can be provided using cavity molding techniques. Dotted lines 92 represent singulation lines 92 or separation lines 92 at which packaged semiconductor devices 10AA, 10BB, and 10CC will later be separated into individual packaged semiconductor devices.

[0078] Figure 9B Packaged semiconductor devices 10AA-10CC are shown after further processing. In some examples, external interconnects 211 such as solder balls or solder bumps 211 are attached to conductive pads (e.g., conductive pads 112 shown in FIG. 9C) on substrate 11. In some examples, solder paste is provided on the conductive pads, external interconnects 211 are attached to the solder paste, external interconnects 211 are heated to reflow external interconnects 211, and the subassembly can then be cleaned to remove the solder paste. In other examples, external interconnects 211 can be provided using screen printing, plating, or paste processes. In further examples, no external interconnects 211 are used, and the conductive pads or lands 112 of substrate 11 can be used to attach the packaged semiconductor devices to a next level assembly. Figure 2A

[0079] Figure 9C Packaged semiconductor devices 10AA-10CC are shown after further processing. In some examples, singulation or separation processes are used to singulate or separate encapsulants 36 and substrates 11 immediately adjacent to singulation lines 92 to provide packaged semiconductor devices 10AA-10CC as individual devices. In some examples, sawing or laser cutting techniques can be used to separate the devices. Packaged semiconductor devices 10AA-10CC are examples of package structures having face-up stacked semiconductor devices 160A-160C (i.e., active surfaces of at least semiconductor dies 16D facing away from substrates 11), substrates 11 configured as laminate substrates, and conductive interconnect structures 21 including conformal layer structures interconnecting the stacked semiconductor dies and respective substrates 11.

[0080] Figure 10A ,​10B FIGS. 10C and 10D illustrate partial cross-sectional views of packaged electronic devices 40 (e.g., packaged semiconductor devices 40A, 40B, and 40C) at various steps in fabrication according to this description. In some examples, the packaged semiconductor devices 40A, 40B, and 40C are similar to the packaged semiconductor devices 40 illustrated, and are provided to illustrate an example method of forming the packaged semiconductor devices 40. For ease of understanding, fewer elements are labeled in FIGS. 10C and 10D than in FIGS. 10A and 10B to not make the depictions overly complex. More details of the various elements are illustrated, for example, in FIGS. 10E and 10F. Figure 8 Figure 10A 10B Figure 8

[0081] Figure 10A Packaged semiconductor devices 40A, 40B, and 40C are illustrated attached to a carrier substrate 511. In some examples, the carrier substrate 511 includes a rigid material configured to support the stacked semiconductor devices 160A, 160B, and 160C during assembly processes. In some examples, the carrier substrate 511 can include a metal plate, a ceramic substrate, a glass substrate, a semiconductor substrate, or other types of substrates known to those of ordinary skill in the art. In some examples, the stacked semiconductor devices 160A, 160B, and 160C are attached to a top surface of the carrier substrate 511 using, for example, the attachment material 18 described previously. In other examples, a different attachment material can be used, such as a UV-releasable adhesive. In some examples, as illustrated, a dielectric layer 27 can be provided over the top substrate surface 512 of the carrier substrate 511. In some examples, the conductive interconnect structures 21 are provided after the stacked semiconductor devices 160A, 160B, and 160C are attached to the carrier substrate 511. Figure 10A

[0082] In this example, the encapsulation 36 is provided in the form of an overmolded encapsulation that covers each of the stacked semiconductor device structures 160A, 160B, and 160C as well as the top substrate surface 512 of the carrier substrate 511. In other examples, multiple or single encapsulations 36 can be provided using cavity molding techniques. The dashed lines 92 represent singulation lines 92 or separation lines 92 at which the packaged semiconductor devices 40A, 40B, and 40C can later be separated into individual packaged semiconductor devices.

[0083] Figure 10B ​​​​​Packaged semiconductor devices 40A-40C are shown after further processing. In some examples, the carrier substrate 511 is removed to expose a portion 246 of the electrically conductive interconnect structure 21 through a bottom surface of the package 36. In some examples, heat and / or solvent can be used to remove the carrier substrate 511. In a subsequent step, as shown in Figure 10C , a substrate 11 configured as an RDL-type substrate is formed adjacent to the bottom surface of the package 36, including, for example, external interconnects 211. In some examples, the substrate 11 includes multiple layers of dielectric and conductor. As shown in Figure 10C , portions of the conductor of the substrate 11 are electrically connected to the electrically conductive interconnect structure 21 at the portion 246.

[0084] Figure 10D Packaged semiconductor devices 40A-40C are shown after further processing. In some examples, a singulation or separation process is used to separate the package 36 and the substrate 11 through the singulation line 92 immediately adjacent to provide packaged semiconductor devices 40A-40C as individual devices. In some examples, sawing or laser cutting techniques can be used to separate the devices. The packaged semiconductor devices 40A-40C are examples of packaged semiconductor devices having face-up stacked semiconductor devices 160A-160C (i.e., the active surfaces of at least the semiconductor dies 16D facing away from the substrate 11), a substrate 11 configured as an RDL-type substrate, and an electrically conductive interconnect structure 21 including conformal layer structures interconnecting the semiconductor dies and the respective substrate 11.

[0085] Figure 11A , 11B , 11C and 11D show partial cross-sectional views of packaged semiconductor devices 40A, 40B and 40C at various manufacturing steps according to the present specification. Figures 11A-11D Similar to Figures 10A-10D , and only the differences will be described in the following.

[0086] In Figure 11A , the substrate 11 is configured as an RDL-type substrate and can be disposed on a top surface 512 of a carrier substrate 511. The stacked semiconductor devices 160A-160C can then be attached to the substrate 11 and the electrically conductive interconnect structure 21 formed to electrically connect the semiconductor dies together and to the substrate 11. The package 36 can then be provided as an overmolded package covering the stacked semiconductor devices 160A-160C and portions of the substrate 11, as shown in Figure 11A .

[0087] Then, as Figure 11BAs shown, the carrier substrate 511 can be removed to expose the substrate 11, which includes, for example, conductive pads 112, for further processing. Next, external interconnects 211 can be attached to the previously described conductive pads, such as... Figure 11C As shown. Finally, a dicing or separation process is used to separate the package 36 and the substrate 11 through the dicing line 92 to provide packaged semiconductor devices 40A-40C as individual devices, such as Figure 11D As shown. In some instances, sawing or laser cutting techniques can be used to separate the devices. Packaged semiconductor devices 40A-40C are examples of packaged semiconductor devices having face-up stacked semiconductor devices 160A-160C (i.e., at least the active surface of the semiconductor die 16D faces away from the substrate 11), a substrate 11 configured as an RDL substrate, and a conductive interconnect structure 21 including a conformal layer structure interconnecting the semiconductor die and the respective substrate 11.

[0088] Figure 12A , 12B Figures 12C and 12D show partial cross-sectional views of various packaged electronic devices (such as packaged semiconductor devices 30AA, 30BB, and 30CC) at various manufacturing stages according to this specification. In some instances, packaged semiconductor devices 30AA, 30BB, and 30CC are similar to... Figure 7 The packaged semiconductor device 10 shown is an example. Figure 12A As shown, stacked semiconductor devices 160A, 160B, and 160C are attached to the top surface 512 of a carrier substrate 511 using, for example, attachment material 18. Conductive interconnect structures 21 are formed to electrically connect semiconductor dies together and to the substrate 11.

[0089] In some instances, such as Figure 12A As generally shown, the package 36 is then provided in the form of an overmolded package that covers each of the stacked semiconductor device structures 160A, 160B, and 160C, as well as the top substrate surface 110 of the substrate 11. In other instances, multiple or single packages 36 may be provided using cavity molding techniques.

[0090] Figure 12BPackaged semiconductor devices 30AA-30CC after further processing are shown. In some examples, the thickness of the encapsulation 36 is reduced such that a portion of the conductive interconnect structure 21 is exposed through the first surface 360 of the encapsulation 36. In some examples, a portion of the encapsulation 36 is removed using etching, grinding, polishing, combinations thereof, or other removal techniques known to those of ordinary skill in the art. In other examples, film assisted molding techniques can be used to expose the conductive interconnect structure 21 through the first surface 360 of the encapsulation 36.

[0091] Next, a substrate 11 is attached or formed over the first surface 360 of the encapsulation 36. In some examples, the substrate 11 is configured as an RDL-type substrate as shown in Figure 12C and includes a plurality of passivation and conductive layers. As shown in FIG. 12, the substrate 11 is electrically connected to the conductive interconnect structure 21 adjacent the first surface 360. In other examples, the substrate 11 can be other types of substrates, including, for example Figure 9A laminated substrates shown. The carrier substrate 511 can be removed before or after the substrate 11 is disposed over the first surface 360. In other examples, the carrier substrate 511 can be removed after the encapsulation 36 is formed and before the substrate 11 is provided.

[0092] Figure 12D Packaged semiconductor devices 30AA-30CC after further processing are shown. In some examples, external interconnects 211 are attached to the substrate 11 and then the encapsulation 36 and substrate 11 are separated through the singulation line 92 using a singulation or separation process to provide packaged semiconductor devices 30AA-30CC as individual devices. In some examples, sawing or laser cutting techniques can be used to separate the devices. The packaged semiconductor devices 30AA-30CC are examples of structures having a face down stacked semiconductor device 160A-160C (i.e., the active surface of at least semiconductor die 16A faces the substrate 11), a substrate 11 configured as an RDL-type substrate, and a conductive interconnect structure 21 including a conformal layer structure interconnecting the semiconductor device and the respective substrate 11.

[0093] Figure 13 、 14 , 15, 16, and 17 show examples of package-in-package (PIP) type devices using a plurality of packaged semiconductor devices of the present description.

[0094] Such packaged semiconductor devices can include packaged semiconductor devices 10, 20, 30, and / or 40 in combination with other packaged semiconductor devices including stacked semiconductor device structure 160 or a single semiconductor die having a conductive interconnect structure 21 provided as a conformal layer substantially following the profile of the stacked semiconductor device structure 160 or the profile of the single semiconductor die. Although the following examples show substrate 611 as a laminate-type substrate, it should be understood that substrate 611 can be selected from a common circuit board (e.g., rigid circuit boards and flexible circuit boards), a multi-layer substrate, a coreless substrate with a build-up layer, a coreless substrate, a ceramic substrate, a lead frame substrate, a molded lead frame substrate, or similar substrates known to those of ordinary skill in the art. In this regard, the present specification is not intended to be limited to any particular type of substrate.

[0095] Figure 13 A cross-sectional view of a packaged electronic device 50, such as a packaged semiconductor device 50, in accordance with the present specification is shown. In the present example, packaged semiconductor device 50 is configured as a PIP-type packaged semiconductor device including a plurality of packaged semiconductor devices each having a single semiconductor die or a stacked semiconductor die (e.g., stacked semiconductor device structure 160) interconnected and / or connected to a substrate through a conductive interconnect structure 21. In the present example, packaged semiconductor device 50 includes a plurality of packaged semiconductor devices 10 (e.g., 10AA, 10BB, and 10CC) previously depicted in, for example, FIGS. 1, 2, and 9A-9C. In some examples, external interconnects 211 are not used with packaged semiconductor devices 10AA-10CC shown. Figure 1 Figure 13

[0096] Packaged semiconductor device 50 includes a substrate 611, which can be similar to substrate 11. In some examples, substrate 611 can be provided with conductive pads 631 proximate to substrate top surface 610A, which can be further connected to conductive pads 612 or conductive lands 612 proximate to substrate bottom surface 610B through conductive layers / structures 614 within substrate 611. Substrate 611 further includes a dielectric or passivation structure 615 comprising one or more dielectric layers. Substrate 611 can be further provided with solder mask structures 622 between conductive lands 612 proximate to substrate bottom surface 610B. In some examples, external interconnects 211 can be attached to conductive lands 612 and can include a conductive material, such as solder balls, solder bumps, copper bumps, nickel gold bumps, or similar materials known to those of ordinary skill in the art. In other examples, conductive lands 612 can be configured to be directly connected or attached to a next level assembly, such as a printed circuit board.

[0097] ​​In some examples, the packaged semiconductor device 10AA is attached to the substrate top surface 610A with an attachment material 18 as previously described. As Figure 13 As shown, the packaged semiconductor device 10AA is attached in a face-down orientation (i.e., the active surface of at least the semiconductor die 16D faces the substrate 611) such that the top surface 360 of the package 36 is proximate to the substrate top surface 610A. In this orientation, the substrate 11 of the packaged semiconductor device 10AA, which can be a laminate substrate, is spaced apart from or distal to the substrate top surface 610A.

[0098] According to this example, the packaged semiconductor device 10AA is electrically connected to the substrate 611. For example, one or more of the conductive pads 632 on the substrate 611 are electrically connected to one or more of the conductive pads 112 on the substrate 11 of the packaged semiconductor device 10AA. In some examples, the conductive interconnect structures 621 are used to electrically connect the packaged semiconductor device 10AA to the substrate 611. By way of example, the conductive interconnect structures 621 can include wires provided using a wire bonding process or similar structures known to those of ordinary skill in the art.

[0099] The packaged semiconductor device 10BB is attached to the substrate 11 of the packaged semiconductor device 10AA with an attachment material 18 as previously described. In some examples, the top surface 360 of the package 36 of the packaged semiconductor device 10BB is attached to the substrate 11 of the packaged semiconductor device 10AA in a face-down orientation. According to this description, the packaged semiconductor device 10BB is attached to the packaged semiconductor device 10AA in a laterally offset configuration so as to expose one or more of the conductive pads 112 on the substrate 11 of the packaged semiconductor device 10AA. In some examples, the substrate 11 of the packaged semiconductor device 10BB is electrically connected to the substrate 611 through one or more of the conductive interconnect structures 621. In some examples, as Figure 13 As generally shown in FIG. 15, one or more of the conductive interconnect structures 621 can electrically connect the packaged semiconductor device 10BB and the packaged semiconductor device 10AA together.

[0100] The packaged semiconductor device 10CC is attached to the substrate 11 of the packaged semiconductor device 10BB using an attachment material 18, such as previously described. In some examples, the top surface 360 of the package 36 of the packaged semiconductor device 10CC is attached to the substrate 11 of the packaged semiconductor device 10BB in a face-down orientation. In accordance with the present description, the packaged semiconductor device 10CC is attached to the packaged semiconductor device in a laterally offset configuration so as to expose one or more conductive lands 112 on the substrate 11 of the packaged semiconductor device 10BB. In some examples, the substrate 11 of the packaged semiconductor device 10CC is electrically connected to the substrate 611 by one or more conductive interconnect structures 621. It should be appreciated that one or more of the packaged semiconductor devices 10AA, 10BB, and / or 10CC can be rotated 180 degrees about a horizontal plane relative to the other packaged semiconductor devices 10AA, 10BB, and / or 10CC. Also, the packaged semiconductor device 10CC can be electrically connected to one or more of the packaged semiconductor devices 10AA and 10BB by conductive interconnect structures, such as the conductive interconnect structures 621. In some examples, the packaged semiconductor devices 10AA, 10BB, and 10CC (or any of the packaged semiconductor devices described herein) are attached to the substrate 611 and to each other prior to providing the conductive interconnect structures 621.

[0101] The packaged semiconductor device 50 further includes a package 636 that covers the packaged semiconductor devices 10AA, 10BB, and 10CC, as well as the substrate top surface 610A and the conductive interconnect structures 621. In some examples, the package 636 can be a polymer-based composite material, such as an epoxy with fillers, an epoxy acrylate with fillers, or a polymer with suitable fillers. The package 636 includes a non-conductive and environmentally friendly material that protects the substrate 611 and the conductive interconnect structures 621 from external elements and contaminants. The package 636 can be formed using paste printing, compression molding, transfer molding, overmolding, liquid encapsulant molding, vacuum lamination, other suitable applicators, or other processes known to those skilled in the art. In some embodiments, the package 636 is an epoxy molding compound (“EMC”) and can be formed using transfer or injection molding techniques. In other examples, the package 636 can be omitted.

[0102] The packaged semiconductor device 50 is an example of a PIP-type semiconductor package with multi-side wire bond interconnects. That is, the conductive interconnect structures 621 are disposed on more than one side of the packaged semiconductor devices 10AA, 10BB, and 10CC, such as Figure 13The package semiconductor devices 10CC can be electrically connected to the substrate 611 on the same side of the substrate 611 as the package semiconductor devices 10AA and 10BB in other examples, to provide a single-sided wire bond interconnect configuration. Similar to the previously described package semiconductor devices 10AA, 10BB, and 10CC, the package semiconductor devices 10CC can be electrically connected to the substrate 611 using conductive interconnect structures 621, such as wire bonds, and / or conductive interconnect structures 621, such as solder connections. Figures 9A to 9C The formation of the package semiconductor devices 10AA, 10BB, and 10CC described can be used to form a package semiconductor device 50 using a matrix of substrates 611 and overmolded packages 636, which can be singulated after formation of the packages 636 to provide a plurality of package semiconductor devices 50.

[0103] Figure 14 A cross-sectional view of a packaged electronic device 60, such as a package semiconductor device 60, in accordance with the present specification is shown. In this example, the package semiconductor device 60 is configured as a PIP-type semiconductor device including a plurality of package semiconductor devices each having a single semiconductor die or having a stacked semiconductor die interconnected and / or connected to a substrate through conductive interconnect structures 21 (e.g., stacked semiconductor device structure 160). The package semiconductor device 60 is similar to the package semiconductor device 50, and only the differences will be described hereinafter.

[0104] In the package semiconductor device 60, the package semiconductor devices 10CC are laterally offset from the package semiconductor devices 10BB so as to be substantially aligned with the package semiconductor devices 10AA. Additionally, the package semiconductor devices 10BB are electrically connected to the substrate 611 using, for example, conductive interconnect structures 621 on the same side as the package semiconductor devices 10CC. The package semiconductor device 60 is an example of a PIP-type semiconductor package having a multi-sided wire bond interconnect. That is, the conductive interconnect structures 621 are disposed on more than one side of the package semiconductor devices 10AA, 10BB, and 10CC, as shown in the cross-sectional view of the package semiconductor device 60. Figure 14 is shown.

[0105] Figure 15 A cross-sectional view of a packaged electronic device 70, such as a package semiconductor device 70, in accordance with the present specification is shown. In this example, the package semiconductor device 70 is configured as a PIP-type semiconductor device including a plurality of package semiconductor devices each having a single semiconductor die or having a stacked semiconductor die interconnected and / or connected to a substrate through conductive interconnect structures 21 (e.g., stacked semiconductor device structure 160). In this example, the package semiconductor device 70 includes a plurality of package semiconductor devices 30 (e.g., 30A, 30B, and 30C) previously described in Figure 7 and 12A -12D. In some examples, the external interconnects 211 are not used with the package semiconductor devices 30A-30C shown. Figure 15 The package semiconductor devices 30A-30C shown are used together.

[0106] The packaged semiconductor device 30AA is attached to the substrate top surface 610A of the substrate 611 using an attachment material such as the attachment material 18 as previously described. As Figure 15 As shown, the packaged semiconductor device 30AA is attached in an upside- down orientation (i.e., with the active surface of at least the semiconductor die 16A facing away from the substrate 611) such that the semiconductor die 16A of the packaged semiconductor device 30AA is proximate to the substrate top surface 610A. In this orientation, the substrate 11 of the packaged semiconductor device 30AA, which can be configured as an RDL-type substrate, is spaced apart from or distal to the substrate top surface 610A. According to the present example, the packaged semiconductor device 30AA is electrically connected to the substrate 611 using, for example, one or more conductive interconnect structures 621, which can include, for example, wires formed using a wire bonding process.

[0107] The packaged semiconductor device 30BB is attached to the substrate 11 of the packaged semiconductor device 30AA using an attachment material such as the attachment material 18 as previously described. In some examples, the packaged semiconductor device 30BB is attached such that at least the semiconductor die 16A of the packaged semiconductor device 30BB is immediately proximate to the substrate 11 of the packaged semiconductor device 30AA in an upside-down orientation (i.e., facing away from the packaged semiconductor device 30AA). According to the present specification, the packaged semiconductor device 30BB is attached to the packaged semiconductor device 30AA in a laterally offset configuration so as to expose one or more conductive pads 112 on the substrate 11 of the packaged semiconductor device 30AA. The substrate 11 of the packaged semiconductor device 30BB is electrically connected to the substrate 611 by one or more conductive interconnect structures 621. In some examples, the one or more conductive interconnect structures 621 can electrically connect the packaged semiconductor device 30BB and the packaged semiconductor device 30AA together.

[0108] The packaged semiconductor device 30CC is attached to the substrate 11 of the packaged semiconductor device 30BB using an attachment material such as attachment material 18 as previously described. In some embodiments, the packaged semiconductor device 30CC is attached such that at least the semiconductor die 16A of the packaged semiconductor device 30CC is adjacent to the substrate 11 of the packaged semiconductor device 30BB in an upward orientation (i.e., away from the packaged semiconductor device 30BB). According to this specification, the packaged semiconductor device 30CC is attached to the packaged semiconductor device 30BB in a laterally offset configuration to expose one or more conductive solder pads 112 on the substrate 11 of the packaged semiconductor device 30BB. In some embodiments, the substrate 11 of the packaged semiconductor device 30CC is electrically connected to a substrate 611 via one or more conductive interconnect structures 621. In some embodiments, the substrate 11 of the packaged semiconductor device 10CC is electrically connected to a substrate 611 via one or more conductive interconnect structures 621. It should be understood that one or more of the packaged semiconductor devices 30AA, 30BB, and / or 30CC can be rotated 180 degrees relative to the other packaged semiconductor devices 30AA, 30BB, and / or 30CC around a horizontal plane. Furthermore, packaged semiconductor device 30CC can be electrically connected to one or more of the packaged semiconductor devices 30AA and 30BB via a conductive interconnect structure such as conductive interconnect structure 621.

[0109] The packaged semiconductor device 70 further includes a package body 636 covering the packaged semiconductor devices 30AA, 30BB, and 30CC, as well as the top substrate surface 110 and the conductive interconnect structure 621. The packaged semiconductor device 70 is an example of a PIP-type semiconductor package with single-sided wire-bonded interconnects. That is, the conductive interconnect structure 621 is disposed on only one side of the packaged semiconductor devices 30AA, 30BB, and 30CC, such as... Figure 15 As shown. Similar to the formation of packaged semiconductor devices 30AA, 30BB and 30CC, packaged semiconductor devices 70 can be formed using a matrix of substrate 611 and an overmolded package 636, which can be diced after the package 636 is formed to provide multiple packaged semiconductor devices 70.

[0110] Figure 16 A cross-sectional view of a packaged electronic device 80, such as a packaged semiconductor device 80, according to this specification is shown. The packaged semiconductor device 80 is similar to the packaged semiconductor device 50, and only the differences will be described below.

[0111] In the packaged semiconductor device 80, the packaged electronic devices 10AA, 10BB, and 10CC are electrically connected to each other and to the substrate 611 by the electrically conductive interconnect structure 721 disposed over portions of the packaged semiconductor devices 10AA, 10BB, and 10CC and over a portion of the substrate top surface 610A of the substrate 611 to electrically connect the packaged semiconductor devices 10AA, 10BB, and 10CC together and to the substrate 11. In some examples, a dielectric layer 727 is disposed under the interconnect structure 721 and includes openings over the electrically conductive lands 112 and the electrically conductive pads 631 to facilitate electrically connecting the electrically conductive interconnect structure 721 to the packaged semiconductor devices 10AA, 10BB, and 10CC and the substrate 611. The dielectric layer 727 can be similar to the previously described dielectric layer 27. In some examples, the dielectric layer 727 is formed using 3D printing techniques or other techniques previously described with respect to the dielectric layer 27.

[0112] According to the present specification, the electrically conductive interconnect structure 721 has a shape that substantially conforms to the shape (e.g., stepped profile) of the stacked packaged semiconductor devices 10AA, 10BB, and 10CC. As Figure 16 As generally shown, the electrically conductive interconnect structure 721 is disposed over the substrates 11 of the packaged semiconductor devices 10AA, 10BB, and 10CC and over the side surfaces 368A, 368B, and 368C of the packaged semiconductor devices 10AA, 10BB, and 10CC.

[0113] In some examples, the electrically conductive interconnect structure 721 includes one or more metals such as copper, copper alloys, gold, silver, or other electrically conductive materials known to those of ordinary skill in the art. In some examples, the electrically conductive interconnect structure 721 can be provided using the previously described 3D printing techniques. In other examples, the electrically conductive interconnect structure 721 can be formed using evaporation, sputtering, chemical vapor deposition, plating, or other techniques known to those of ordinary skill in the art. One advantage of the electrically conductive interconnect structure 721 is that it provides a lower profile that can facilitate the packaged semiconductor device 80 having a thinner profile as compared to, for example, the packaged semiconductor device 50.

[0114] Figure 17A cross-sectional view of a packaged electronic device 90, such as a packaged semiconductor device 90, is shown in accordance with the present specification. The packaged semiconductor device 90 is similar to the packaged semiconductor device 70, and only the differences will be described hereinafter. In the packaged semiconductor device 90, the packaged semiconductor devices 30AA, 30BB, and 30CC are electrically connected to each other and to the substrate 611 by a conductive interconnect structure 721 disposed on portions of the packaged semiconductor devices 30AA, 30BB, and 30CC and a portion of the substrate top surface 610A of the substrate 611 to electrically connect the packaged semiconductor devices 30AA, 30BB, and 30CC together and to the substrate 611. In some examples, a dielectric layer 727 is disposed under the interconnect structure 721 and includes openings to facilitate electrically connecting the conductive interconnect structure 721 to the packaged semiconductor devices 30AA, 30BB, and 30CC and the substrate 611. The dielectric layer 727 can be similar to the previously described dielectric layer 27. In some examples, the dielectric layer 727 is formed using 3D printing techniques or other techniques previously described.

[0115] In accordance with the present specification, the conductive interconnect structure 721 has a shape that substantially conforms to the shape (e.g., stepped profile) of the stacked packaged semiconductor devices 30AA, 30BB, and 30CC. In some examples, as shown in FIG. 8, the conductive interconnect structure 721 is disposed on the substrate 11 of the packaged semiconductor devices 30AA, 30BB, and 30CC and on the side surfaces 368A, 368B, and 368C of the packaged semiconductor devices 30AA, 30BB, and 30CC. Figure 17 As generally shown in FIG. 8, the conductive interconnect structure 721 is disposed on the substrate 11 of the packaged semiconductor devices 30AA, 30BB, and 30CC and on the side surfaces 368A, 368B, and 368C of the packaged semiconductor devices 30AA, 30BB, and 30CC.

[0116] One advantage of the conductive interconnect structure 721 is that it provides a lower profile that can facilitate the packaged semiconductor device 90 having a thinner profile as compared to, for example, the packaged semiconductor device 70.

[0117] In general, a packaged electronic device structure including semiconductor dies attached in an offset stack configuration to provide a stacked semiconductor device structure and associated methods have been described. Terminals of each semiconductor die are exposed in the stacked semiconductor device structure and connected with a conformal conductive interconnect structure that substantially follows the stepped profile of the stacked semiconductor device structure. In some examples, the stacked semiconductor device structure is attached to a substrate and the conductive interconnect structure also electrically connects the stacked semiconductor device structure to the substrate. In some examples, a package covers at least portions of the stacked semiconductor device structure. In some examples, multiple packaged semiconductor devices are attached together in an offset stack configuration and electrically coupled together in a package-in-package configuration. In some examples, a conductive interconnect layer including a conformal layer electrically connects the multiple packaged semiconductor devices together. In some examples, 3D printing techniques can be used to form the conductive interconnect structure. In other examples, plating techniques can be used with a masking seed layer. Among other things, structures and methods according to this specification provide packaged electronic devices with thinner profiles with reliable conductive interconnects that can be formed in a variety of patterns.

[0118] While the subject matter of the present application is described with specific example steps and example embodiments, the foregoing drawings and description thereof are only illustrative of the typical examples of the subject matter and are not intended to be limiting thereof. Other examples and permutations thereof will be read into the specification. For example, semiconductor devices 10, 20 Figure 1 , 2, 4, 5, 6, 9, 13, 14, 16 are presented as including substrate 11 as a preformed substrate, but there can be examples where this substrate 11 can be an RDL substrate. Semiconductor devices 30, 40 Figure 7 , 8 , 10, 11, 12, 15, 17 are shown as including substrate 11 as an RDL substrate, but there can be examples where this substrate 11 can be a preformed substrate. Stacked semiconductor device structure 160 is shown with all of dies 16A, 16B, 16C, and 16D facing the same direction, but there can be examples where at least one of dies 16A, 16B, 16C, 16D faces a different direction than the other dies. For example, semiconductor devices 10, 20, 40 can include die 16A facing substrate 11 and dies 16B, 16C, 16D facing away from substrate 11. Semiconductor devices 50, 60, 70, 80, 90 Figures 13-17) Each is shown as including a stack of semiconductor devices of the same type and same orientation, but there can be instances where the semiconductor devices 50, 60, 70, 80, 90 can include separate stacks with semiconductor devices of different types (e.g., with different combinations of semiconductor devices 10, 20, 30, 40) or separate stacks with semiconductor devices of different orientations (e.g., upward- and downward-facing semiconductor devices 10, 20, 30, 40). Obviously, many alternative solutions and variations, as those described, will be apparent to the skilled person.

[0119] As reflected in the appended claims, aspects of the invention can reside in less than all the features of a single foregoing disclosed example. Accordingly, the following expressed claims are hereby expressly incorporated into this DETAILED DESCRIPTION, wherein each claim stands on its own as a separate example of the invention. Moreover, while some examples described herein include some but not other features of those included in other examples, as will be appreciated by the skilled person, combinations of features of different examples are intended to be within the scope of the invention and form different examples.

Claims

1. A packaged semiconductor device comprising: a substrate having a first major surface and a second major surface opposite the first major surface, the substrate comprising one or more organic dielectric layers; a stacked semiconductor device structure coupled to the first major surface and comprising semiconductor dies, the semiconductor dies comprising a die top side, a die bottom side, a die lateral side, a die terminal adjacent to the die top side, and a passivation layer over the die top side and overlapping the die terminal, wherein: the passivation layer comprises an opening to expose a portion of the die terminal; and the semiconductor dies are coupled together such that the die terminal is exposed and the stacked semiconductor device structure comprises a stepped profile; a conductive interconnect structure over portions of the stacked semiconductor device structure and coupling the die terminals of the semiconductor dies together; and a dielectric structure comprising a dielectric portion interposed between the conductive interconnect structure and the die lateral side and interposed between the conductive interconnect structure and a segment of the die top side covered by the passivation layer, wherein: the conductive interconnect structure comprises a conformal layer conforming to the stepped profile; the dielectric portion extends onto the segment of the die top side without contacting the die terminal; each dielectric portion is a single dielectric; the conductive interconnect structure is in contact with the dielectric portion without an additional intervening dielectric.

2. The packaged semiconductor device of claim 1, wherein: at least one of the conductive interconnect structures is over the substrate and electrically couples at least one of the semiconductor dies to the substrate.

3. The packaged semiconductor device of claim 1, wherein: other segments of the die top side extend between the dielectric portion and the die terminal; the other segments are free of the dielectric portion; and the other segments are laterally adjacent to the die terminal.

4. The packaged semiconductor device of claim 1, wherein: at least one of the conductive interconnect structures is over the substrate and electrically couples at least one of the semiconductor dies to a substrate terminal of the substrate; and wherein one of the dielectric portions overlaps a portion of the substrate adjacent to the substrate terminal but does not overlap the substrate terminal.

5. The packaged semiconductor device of claim 4, wherein: the dielectric structure comprises an organic dielectric; the semiconductor dies comprise a first semiconductor die and a second semiconductor die; the first semiconductor die has a first die top side, a first die bottom side, a first die lateral side extending between the first die top side and the first die bottom side, and a first die terminal adjacent to the first die top side; the second semiconductor die has a second die top side and a second die terminal adjacent to the second die top side; the first semiconductor die is coupled to the second semiconductor die; and the dielectric portion of the second semiconductor die overlaps the first die terminal. ​ The dielectric structure includes a first dielectric portion, the first dielectric portion including: a first thickness proximate where the first semiconductor die is coupled with the second semiconductor die; a second thickness proximate the first die top side; and a third thickness along the second die top side proximate the second die terminal; and the first thickness is greater than the second thickness and the third thickness.

6. The packaged semiconductor device of claim 1, further comprising: a package covering the stacked semiconductor device structure.

7. The packaged semiconductor device of claim 1, wherein: the conductive interconnect structure includes a plated structure.

8. The packaged semiconductor device of claim 1, wherein: the conductive interconnect structure includes a 3D printed structure.

9. The packaged semiconductor device of claim 1, wherein: at least one of the conductive interconnect structures couples at least two die terminals of one of the semiconductor dies together.

10. The packaged semiconductor device of claim 1, wherein: the semiconductor dies include active surfaces; the active surfaces face the first major surface of the substrate; and wherein one of the semiconductor dies has the die terminal connected to the substrate through the conductive interconnect structure.

11. The packaged semiconductor device of claim 1, wherein: the semiconductor dies include active surfaces; and the active surfaces face away from the first major surface of the substrate.

12. A method of forming a packaged semiconductor device, the method comprising: providing a substrate having a first major surface and a second major surface opposite the first major surface, the substrate including one or more organic dielectric layers; providing a stacked semiconductor device structure including semiconductor dies, the semiconductor dies including a die top side, a die bottom side, a die lateral side, and a die terminal adjacent the die top side, and a passivation layer over the die top side and overlapping the die terminal, wherein the passivation layer includes an opening to expose a portion of the die terminal; providing a dielectric structure including a dielectric portion adjacent a segment of the die lateral side and the die top side; providing a conductive interconnect structure over a portion of the stacked semiconductor device structure, the conductive interconnect structure coupling the die terminals of the semiconductor dies together; and coupling the stacked semiconductor device structure to the substrate; wherein: the semiconductor dies are coupled together such that respective the die terminals are exposed, and the stacked semiconductor device structure includes a stepped profile; the conductive interconnect structure conforms to the stepped profile; the dielectric portion extends to the segment of the die top side without contacting the die terminal; the dielectric portion is comprised of a single dielectric; and the conductive interconnect structure directly contacts the dielectric portion without an intervening insulator.

13. The method of claim 12, wherein: providing the stacked semiconductor device structure includes: providing the stacked semiconductor device structure attached to a carrier substrate; the method further includes: forming a package covering the stacked semiconductor device structure; and removing the carrier substrate; and providing the substrate includes attaching the substrate adjacent to one of the semiconductor dies in the stacked semiconductor device structure.

14. The method of claim 12, wherein: providing the stacked semiconductor device structure includes: providing the stacked semiconductor device structure attached to a carrier substrate; the method further includes: forming a package covering the stacked semiconductor device structure; and removing the carrier substrate; and coupling the substrate includes coupling the substrate adjacent to one of the semiconductor dies in the stacked semiconductor device structure after the step of forming the conductive interconnect structure and after the step of forming the package.

15. The method of claim 12, wherein: providing the substrate includes providing the substrate terminal including a top side; coupling the substrate and the stacked semiconductor device structure occurs before the step of providing the dielectric structure; providing the dielectric structure includes: providing a first dielectric portion overlapping the substrate and the substrate terminal; and exposing the top side of the substrate terminal such that the top side of the substrate terminal is free of the first dielectric portion; and providing the conductive interconnect structure includes providing at least one of the conductive interconnect structures over the substrate and coupling a die terminal to the substrate terminal.

16. The method of claim 12, further including: providing the conductive interconnect structure includes providing a first conductive interconnect structure coupling at least two die terminals of one of the semiconductor dies together.

17. The method of claim 12, further including: providing a package covering at least portions of the stacked semiconductor device structure.

18. A packaged semiconductor device, comprising: a first substrate having a first major surface and a second major surface opposite the first major surface and a first substrate terminal disposed proximate the second major surface of the first substrate, the first substrate including one or more organic dielectric layers; a first stacked semiconductor device structure coupled to the first major surface of the first substrate and including first semiconductor dies each having a first die terminal, wherein: the first semiconductor dies are coupled together such that the first die terminals are exposed and the first stacked semiconductor device structure includes a first stepped profile; a first conductive interconnect structure electrically coupling the first die terminals of the first semiconductor dies together, wherein: the first conductive interconnect structure conforms to the first stepped profile; a first encapsulation covering the first stacked semiconductor device structure; a second substrate having a first major surface and a second major surface opposite the first major surface and second substrate terminals disposed proximate the second major surface of the second substrate; a second stacked semiconductor device structure coupled to the first major surface of the second substrate and including second semiconductor dies each having second die terminals, wherein: the second semiconductor dies are coupled together such that the second die terminals are exposed and the second stacked semiconductor device structure includes a second stepped profile; second conductive interconnect structures electrically coupling the second die terminals of the second semiconductor dies together, wherein: the second conductive interconnect structures substantially conform to the second stepped profile; a second encapsulation covering the second stacked semiconductor device structure, wherein: the second encapsulation is attached to the second major surface of the first substrate in an offset configuration to expose the first substrate terminals.

19. The packaged semiconductor device of claim 18, further comprising: a third substrate having a first major surface and a second major surface opposite the first major surface and third substrate terminals disposed proximate the first major surface of the third substrate, wherein the first encapsulation is coupled to the first major surface of the third substrate; third conductive interconnect structures electrically coupling one or more of the first substrate terminals or one or more of the second substrate terminals to the third substrate terminals; and a third encapsulation covering the first substrate, the first encapsulation, the second substrate, the second encapsulation, and the third substrate.

20. The packaged semiconductor device of claim 19, wherein: the third conductive interconnect structures conform to one or more of the first encapsulation, the first substrate, the second encapsulation, or the second substrate. ​

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