Display device

Abstract

A display device can include a pixel, a chip pad spaced apart from the pixel, a film pad spaced apart from the chip pad, a wiring connecting the chip pad and the film pad, and including a first wiring layer and a second wiring layer disposed on the first wiring layer, and an organic insulating layer covering the chip pad and the wiring. A first recess can be defined in the second wiring layer, and a second recess corresponding to the first recess can be defined in the organic insulating layer.

Description

Technical Field

[0001] An exemplary embodiment relates to a display device. More specifically, an exemplary embodiment relates to a display device for preventing damage to the pads and wiring included therein. Background Technology

[0002] A display panel included in a display device typically comprises multiple pixels, and the pixels can be driven by signals received from a driver chip, driver film, etc., and can display images. The display panel typically includes pads connected to the driver chip, driver film, etc., and wiring connecting the pads to each other or to the pixels. Summary of the Invention

[0003] When impurities penetrate into the pads from the outside through the insulating layer, which includes organic materials, the pads may be damaged, or the driver chip connected to the pads may be separated from the display panel. Furthermore, in the process of etching metals used to form electrodes on wiring, the wiring may be damaged due to a chemical reaction between the metal and the wiring when the metal comes into contact with the wiring.

[0004] An exemplary embodiment provides a display device for preventing damage to the pads and wiring included therein.

[0005] An exemplary embodiment of the display device includes: pixels; chip pads spaced apart from the pixels; film pads spaced apart from the chip pads; wiring connecting the chip pads and the film pads, and including a first wiring layer and a second wiring layer disposed on the first wiring layer; and an organic insulating layer covering the chip pads and the wiring. A first recess is defined in the second wiring layer, and a second recess corresponding to the first recess is defined in the organic insulating layer.

[0006] In an exemplary embodiment, the width of the second groove may be smaller than the width of the first groove.

[0007] In an exemplary embodiment, the first wiring layer may include a material having a lower ionization tendency than the material included in the second wiring layer.

[0008] In an exemplary embodiment, the second wiring layer may include a material having a lower resistance than the material included in the first wiring layer.

[0009] In an exemplary embodiment, the chip pads may include: a first chip pad layer, a second chip pad layer disposed on the first chip pad layer, and a third chip pad layer disposed on the second chip pad layer. The first wiring layer may be integral with the first chip pad layer.

[0010] In an exemplary embodiment, the film pad includes a first film pad layer and a second film pad layer disposed on the first film pad layer, and the second wiring layer includes a first portion and a second portion separated by a first groove. The first portion and the second portion may be integral with the third chip pad layer and the second film pad layer, respectively.

[0011] In an exemplary embodiment, the second wiring layer may include the same material as the third chip pad layer and the second film pad layer.

[0012] In an exemplary embodiment, the wiring may further include a third wiring layer disposed between the first wiring layer and the second wiring layer, and the chip pads may further include a fourth chip pad layer disposed between the first chip pad layer and the second chip pad layer. The third wiring layer may be integral with the fourth chip pad layer.

[0013] In an exemplary embodiment, the film pad may include a first film pad layer and a second film pad layer disposed on the first film pad layer. A portion of the second wiring layer may be integral with the second film pad layer.

[0014] In an exemplary embodiment, a pixel may include: a transistor including an active layer, a gate electrode disposed on the active layer, and a source / drain electrode disposed on the gate electrode; a capacitor including a first capacitor electrode integral with the gate electrode and a second capacitor electrode disposed between the first capacitor electrode and the source / drain electrode; a light-emitting element including a pixel electrode disposed on the source / drain electrode, an emitter layer disposed on the pixel electrode, and a counter electrode disposed on the emitter layer; and a connection electrode disposed between the source / drain electrode and the pixel electrode and connecting the source / drain electrode and the pixel electrode.

[0015] In an exemplary embodiment, the first wiring layer may include the same material as the gate electrode.

[0016] In an exemplary embodiment, the first wiring layer may include the same material as the material of the second capacitor electrode.

[0017] In an exemplary embodiment, the second wiring layer may include the same material as the material used to connect the electrodes.

[0018] In an exemplary embodiment, an organic insulating layer may be disposed between the connection electrode and the pixel electrode and cover the connection electrode.

[0019] In an exemplary embodiment, the chip pads may include: a first chip pad layer, a second chip pad layer disposed on the first chip pad layer, and a third chip pad layer disposed on the second chip pad layer. The third chip pad layer may include the same material as the material used for connecting electrodes.

[0020] In an exemplary embodiment, the first chip pad layer may include the same material as the gate electrode.

[0021] In an exemplary embodiment, the first chip pad layer may include the same material as the material of the second capacitor electrode.

[0022] In an exemplary embodiment, the wiring may further include a third wiring layer disposed between the first wiring layer and the second wiring layer, and the chip pad may further include a fourth chip pad layer disposed between the first chip pad layer and the second chip pad layer.

[0023] In an exemplary embodiment, the first wiring layer may include the same material as the gate electrode, and the third wiring layer may include the same material as the second capacitor electrode.

[0024] In an exemplary embodiment, the first chip pad layer may include the same material as the gate electrode, and the fourth chip pad layer may include the same material as the second capacitor electrode.

[0025] In the display device according to the illustrated exemplary embodiment, the second wiring layer of the wiring may have a first groove, and the organic insulating layer covering the chip pads and the wiring may have a second groove corresponding to the first groove. Therefore, damage to the chip pads due to impurities and damage to the wiring due to chemical reactions with metals can be prevented. Attached Figure Description

[0026] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a perspective view illustrating an exemplary embodiment of the display device.

[0028] Figure 2 The illustration includes Figure 1 The circuit diagram of the pixels in the display device.

[0029] Figure 3 The illustration includes Figure 1 A cross-sectional view of pixels in a display device.

[0030] Figure 4 It is a diagram. Figure 1 A plan view of the pad area of ​​the display device.

[0031] Figure 5 It is shown in the diagram along Figure 4 A cross-sectional view of an exemplary embodiment of the display device, taken by line I-I'.

[0032] Figure 6 It is shown in the diagram along Figure 4 A cross-sectional view of an exemplary embodiment of the display device, taken by line I-I'.

[0033] Figure 7 It is shown in the diagram along Figure 4 A cross-sectional view of an exemplary embodiment of the display device, taken by line I-I'. Detailed Implementation

[0034] In the following, the display device according to embodiments will be explained in detail with reference to the accompanying drawings. However, the invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Throughout the text, the same reference numerals refer to the same elements.

[0035] It will be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be an intermediate element between the element and the other element. Conversely, when an element is referred to as being "directly" on another element, there is no intermediate element.

[0036] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another. Therefore, without departing from the teachings of this document, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof.

[0038] Furthermore, as illustrated in the figures, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another. It will be understood that, in addition to the orientations depicted in the figures, the relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when a device in one of the figures is flipped, an element described as being “down” to other elements will subsequently be oriented “up” to other elements. Thus, depending on the specific orientation of the figure, the exemplary term “down” may encompass both “down” and “up” orientations. Similarly, when a device in one of the figures is flipped, an element described as being “below” or “under” other elements will subsequently be oriented “above” other elements. Thus, the exemplary term “below” or “under” may encompass both “up” and “down” orientations.

[0039] Taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), as used herein, “about” or “approximately” includes the stated value and means within an acceptable deviation range of the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0040] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the relevant field and in the context of this invention, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] Exemplary embodiments are described herein with reference to cross-sectional views that are schematic illustrations of preferred embodiments. Therefore, variations in the shapes illustrated are contemplated due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions illustrated herein, but are to include, for example, shape deviations due to manufacturing processes. In exemplary embodiments, regions illustrated as or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the acute angles illustrated may be rounded. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the claims.

[0042] Figure 1 This is a perspective view illustrating an exemplary embodiment of the display device.

[0043] refer to Figure 1The display device may include a display panel (DP), a driver chip (DC), and a driver film (DF). The display panel (DP) can display an image based on signals received from the driver chip (DC) and the driver film (DF).

[0044] The display panel DP may include a display area DA and a non-display area NDA. A plurality of pixels PX may be arranged in the display area DA. In an exemplary embodiment, the pixels PX may be arranged in a substantially matrix form along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the invention is not limited thereto, and the pixels PX may be arranged in various other forms. Light emitted from each of the pixels PX can form an image displayed from the display area DA.

[0045] The non-display area NDA may be adjacent to the display area DA. In an exemplary embodiment, for example, the non-display area NDA may surround the display area DA. The non-display area NDA may include a pad area PA. The pad area PA may include a chip pad area CPA and a film pad area FPA. Multiple chip pads CP may be arranged in the chip pad area CPA. Multiple film pads FP may be arranged in the film pad area FPA.

[0046] Multiple wiring traces (WRs) can be placed between the chip pad area (CPA) and the film pad area (FPA). The wiring traces (WRs) connect the chip pad (CP) to the film pad (FP). Alternatively, wiring traces (WRs) can also be placed between the display area (DA) and the chip pad area (CPA). The wiring traces (WRs) connect the chip pad (CP) to the pixel (PX).

[0047] The driver chip DC can be attached to the chip pad area CPA of the display panel DP. In an exemplary embodiment, the driver chip DC can be an integrated circuit (IC) chip. In an exemplary embodiment, for example, the driver chip DC can be arranged (e.g., mounted) on the display panel DP using a chip-on-plastic (COP) or chip-on-glass (COG) method. However, the invention is not limited thereto, and various other methods can be used. The terminals of the driver chip DC can be connected to chip pads CP arranged in the chip pad area CPA. The driver chip DC can provide signals to pixels PX arranged in the display area DA. In an exemplary embodiment, for example, the driver chip DC can supply data signals, power supply voltage, etc. to the pixels PX via wiring WR.

[0048] The driving film DF can be attached to the film pad area FPA of the display panel DP. In an exemplary embodiment, the driving film DF can be a flexible printed circuit board (FPCB). The driving film DF can be arranged (e.g., mounted) on the display panel DP using a plastic film-on-plate (FOP) method or a glass film-on-plate (FOG) method. However, the invention is not limited thereto, and various other methods can be used. The terminals of the driving film DF can be connected to the film pads FP arranged in the film pad area FPA. The driving film DF can provide signals to the driving chip DC. In an exemplary embodiment, for example, the driving film DF can supply image signals, control signals, power supply voltage, etc. to the driving chip DC through wiring WR. The driving chip DC can convert the image signals into data signals based on the control signals and can supply the data signals to the pixels PX.

[0049] Figure 2 The illustration includes Figure 1 The circuit diagram of the pixel PX in the display device.

[0050] refer to Figure 2 A pixel PX may include multiple transistors, at least one capacitor, and a light-emitting element EE. In an exemplary embodiment, as shown... Figure 2 As illustrated, pixel PX may include two transistors TR1 and TR2 and a capacitor CAP. However, the invention is not limited thereto, and in another exemplary embodiment, pixel PX may include three or more transistors and / or two or more capacitors.

[0051] Transistors TR1 and TR2 may include a first transistor TR1 and a second transistor TR2. The first transistor TR1 may include a gate electrode for receiving a scan signal SC, a source electrode for receiving a data signal DT, and a drain electrode connected to the first node N1. The first transistor TR1 may transmit the data signal DT to the first node N1 in response to the scan signal SC.

[0052] The second transistor TR2 may include a gate electrode connected to the first node N1, a source electrode connected to the second node N2 and receiving a first power supply voltage VDD, and a drain electrode connected to the light-emitting element EE. When the first transistor TR1 is turned on, the second transistor TR2 may provide a drive current to the light-emitting element EE in response to the data signal DT provided to the first node N1.

[0053] The capacitor CAP may include a first electrode connected to a first node N1 and a second electrode connected to a second node N2. When the first transistor TR1 is turned off, the capacitor CAP can maintain a voltage between the first node N1 connected to the gate electrode of the second transistor TR2 and the second node N2 connected to the source electrode of the second transistor TR2.

[0054] The light-emitting element EE may include an anode connected to the drain electrode of the second transistor TR2 and a cathode receiving a second power supply voltage VSS. The light-emitting element EE may emit light based on a drive current supplied from the second transistor TR2. In an exemplary embodiment, the light-emitting element EE may be an organic light-emitting diode (OLED). However, the invention is not limited thereto, and in another exemplary embodiment, the light-emitting element EE may be a quantum dot light-emitting diode (QLED) or the like.

[0055] Figure 3 The illustration includes Figure 1 A cross-sectional view of a pixel PX in a display device.

[0056] refer to Figure 3 The pixel PX may include a first transistor TR1, a second transistor TR2, a capacitor CAP, a connecting electrode 141, and a light-emitting element EE. The substrate 100 may be a transparent insulating substrate. In an exemplary embodiment, the substrate 100 may, for example, include glass, quartz, plastic, etc.

[0057] although Figure 3 Although not shown in the figure, a buffer layer can be disposed on the substrate 100. The buffer layer can be planarized on the substrate 100 and can prevent impurities from penetrating through the substrate 100. The buffer layer may include an inorganic insulating material. In an exemplary embodiment, for example, the buffer layer may include silicon nitride, silicon oxide, etc.

[0058] The first active layer ACT1 and the second active layer ACT2 may be disposed on the substrate 100. In an exemplary embodiment, each of the first active layer ACT1 and the second active layer ACT2 may include amorphous silicon or polycrystalline silicon. In another exemplary embodiment, each of the first active layer ACT1 and the second active layer ACT2 may include an oxide semiconductor. Each of the first active layer ACT1 and the second active layer ACT2 may include a source region, a drain region, and a channel region disposed between the source region and the drain region.

[0059] A first insulating layer 101 may be disposed on a first active layer ACT1 and a second active layer ACT2. The first insulating layer 101 may cover the first active layer ACT1 and the second active layer ACT2, and may be disposed on a substrate 100. The upper surface of the first insulating layer 101 may be provided along a contour beneath the first insulating layer 101. The first insulating layer 101 may include an inorganic insulating material. In an exemplary embodiment, for example, the first insulating layer 101 may include silicon nitride, silicon oxide, etc.

[0060] A first gate electrode 111 and a second gate electrode 112 may be disposed on a first insulating layer 101. The first gate electrode 111 may overlap with the channel region of the first active layer ACT1, and the second gate electrode 112 may overlap with the channel region of the second active layer ACT2. Each of the first gate electrode 111 and the second gate electrode 112 may include a conductive material such as a metal or an alloy of metals. In an exemplary embodiment, for example, each of the first gate electrode 111 and the second gate electrode 112 may include molybdenum (Mo) or the like.

[0061] A second insulating layer 102 may be disposed on the first gate electrode 111 and the second gate electrode 112. The second insulating layer 102 may cover the first gate electrode 111 and the second gate electrode 112, and may be disposed on the first insulating layer 101. The upper surface of the second insulating layer 102 may be provided along a contour beneath the second insulating layer 102. The second insulating layer 102 may include an inorganic insulating material. In an exemplary embodiment, for example, the second insulating layer 102 may include silicon nitride, silicon oxide, etc.

[0062] The second capacitor electrode 121 can be disposed on the second insulating layer 102. The second capacitor electrode 121 can overlap with the second gate electrode 112. The second capacitor electrode 121 can include a conductive material such as a metal or an alloy of metals. In an exemplary embodiment, for example, the second capacitor electrode 121 can include molybdenum (Mo). The second gate electrode 112 can serve as the first capacitor electrode 112 of capacitor CAP and the gate electrode of the second transistor TR2. In other words, the first capacitor electrode 112 and the second gate electrode 112 can be integral with each other. Therefore, the first capacitor electrode 112 and the second capacitor electrode 121 can form capacitor CAP.

[0063] A third insulating layer 103 may be disposed on the second capacitor electrode 121. The third insulating layer 103 may cover the second capacitor electrode 121 and may be disposed on the second insulating layer 102. The upper surface of the third insulating layer 103 may be provided along a contour beneath the third insulating layer 103. The third insulating layer 103 may include an inorganic insulating material. In an exemplary embodiment, for example, the third insulating layer 103 may include silicon nitride, silicon oxide, etc.

[0064] A first source electrode 131, a first drain electrode 132, a second source electrode 133, and a second drain electrode 134 can be disposed on a third insulating layer 103. The first source electrode 131 and the first drain electrode 132 can both be referred to as first source / drain electrode 131 / 132, and the second source electrode 133 and the second drain electrode 134 can both be referred to as second source / drain electrode 133 / 134. The first source / drain electrode 131 / 132 can contact the first active layer ACT1 through contact holes, and the second source / drain electrode 133 / 134 can contact the second active layer ACT2 through contact holes. The first source electrode 131 can be connected to the source region of the first active layer ACT1, and the first drain electrode 132 can be connected to the drain region of the first active layer ACT1. The second source electrode 133 can be connected to the source region of the second active layer ACT2, and the second drain electrode 134 can be connected to the drain region of the second active layer ACT2. Each of the first source electrode 131, the first drain electrode 132, the second source electrode 133, and the second drain electrode 134 may include a conductive material such as a metal or an alloy of metals. In an exemplary embodiment, for example, each of the first source electrode 131, the first drain electrode 132, the second source electrode 133, and the second drain electrode 134 may include aluminum (Al), titanium (Ti), etc. The first active layer ACT1, the first gate electrode 111, the first source electrode 131, and the first drain electrode 132 may form a first transistor TR1, and the second active layer ACT2, the second gate electrode 112, the second source electrode 133, and the second drain electrode 134 may form a second transistor TR2.

[0065] A fourth insulating layer 104 may be disposed on the first source electrode 131, the first drain electrode 132, the second source electrode 133, and the second drain electrode 134. The fourth insulating layer 104 may cover the first source electrode 131, the first drain electrode 132, the second source electrode 133, and the second drain electrode 134, and may be disposed on the third insulating layer 103. The upper surface of the fourth insulating layer 104 may be provided along a contour beneath the fourth insulating layer 104. The fourth insulating layer 104 may include an inorganic insulating material. In an exemplary embodiment, for example, the fourth insulating layer 104 may include silicon nitride, silicon oxide, etc.

[0066] The connection electrode 141 may be disposed on the fourth insulating layer 104. The connection electrode 141 may be connected to the second source / drain electrodes 133 / 134. In an exemplary embodiment, the connection electrode 141 may be connected to the second drain electrode 134. The connection electrode 141 may include a conductive material such as a metal or an alloy of metals. In an exemplary embodiment, for example, the connection electrode 141 may include aluminum (Al), titanium (Ti), etc.

[0067] An organic insulating layer 150 may be disposed on the connection electrode 141. The organic insulating layer 150 may cover the connection electrode 141 and may be disposed on the fourth insulating layer 104. The upper surface of the organic insulating layer 150 may be provided to be substantially planarized. The organic insulating layer 150 may include an organic insulating material. In an exemplary embodiment, for example, the organic insulating layer 150 may include polyimide (PI), etc.

[0068] Pixel electrode 160 can be disposed on organic insulating layer 150. Pixel electrode 160 can be connected to connection electrode 141. Therefore, connection electrode 141 can be disposed between second source / drain electrode 133 / 134 and pixel electrode 160, and the second source / drain electrode 133 / 134 can be connected to pixel electrode 160. Pixel electrode 160 can include a conductive material such as a metal, an alloy of metals, or a transparent conductive oxide. In an exemplary embodiment, for example, pixel electrode 160 can include silver (Ag), indium tin oxide (ITO), etc.

[0069] A pixel defining layer 170 may be disposed on the pixel electrode 160. The pixel defining layer 170 may cover the pixel electrode 160 and may be disposed on the organic insulating layer 150. A pixel opening exposing at least a portion of the pixel electrode 160 may be defined in the pixel defining layer 170. In an exemplary embodiment, the pixel opening may expose a central portion of the pixel electrode 160 and may cover a peripheral portion of the pixel electrode 160. The pixel defining layer 170 may include an organic insulating material. In an exemplary embodiment, for example, the pixel defining layer 170 may include polyimide (PI) or the like.

[0070] The emitting layer 180 can be disposed on the pixel electrode 160. The emitting layer 180 can be disposed on the pixel electrode 160 exposed by the pixel opening. The emitting layer 180 may include at least one of organic light-emitting materials and quantum dots.

[0071] In exemplary embodiments, the organic light-emitting material may include a low molecular weight polymer or a high molecular weight polymer. For example, in exemplary embodiments, the low molecular weight polymer may include at least one of copper phthalocyanine, N,N'-diphenylbenzidine, tris-(8-hydroxyquinoline)aluminum, and the high molecular weight polymer may include at least one of poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, polyfluorene, and the like.

[0072] In an exemplary embodiment, the quantum dot may include a core comprising group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof. In an exemplary embodiment, the quantum dot may have a core-shell structure comprising a core and a shell surrounding the core. The shell may serve as a protective layer to prevent chemical denaturation of the core to maintain its semiconductor properties and as a charging layer to impart electrophoretic properties to the quantum dot.

[0073] Counter electrode 190 can be disposed on emitter layer 180. In an exemplary embodiment, counter electrode 190 can also be disposed on pixel defining layer 170. Counter electrode 190 may include a conductive material such as a metal, an alloy of metals, or a transparent conductive oxide. In an exemplary embodiment, counter electrode 190 may, for example, include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc. Pixel electrode 160, emitter layer 180, and counter electrode 190 can form a light-emitting element EE.

[0074] Figure 4 It is a diagram. Figure 1 A plan view of the pad area PA of the display device. Figure 5 It is shown in the diagram along Figure 4 A cross-sectional view of an exemplary embodiment of the display device, taken by line I-I'.

[0075] refer to Figure 1 , Figure 3 , Figure 4 and Figure 5 The pad area PA can include a chip pad area CPA and a film pad area FPA. Chip pads CP can be arranged in the chip pad area CPA, and film pads FP can be arranged in the film pad area FPA. Wiring WR connecting the chip pads CP to the film pads FP can be arranged between the chip pad area CPA and the film pad area FPA.

[0076] The film pad region FPA can be arranged from the chip pad region CPA in the second direction DR2. Because the wiring WR connects the chip pad CP to the film pad FP, each of the wiring WRs can extend in the second direction DR2.

[0077] Chip pads (CP) can include input chip pads (CPI) and output chip pads (CPO). Input chip pads (CPI) can be connected to film pads (FP) via wiring (WR) and can also be connected to driver chip (DC) via input terminals. Output chip pads (CPO) can be connected to driver chip (DC) via output terminals.

[0078] The chip pad CP may include a first chip pad layer 113, a second chip pad layer 135, and a third chip pad layer 142. The second chip pad layer 135 may be disposed on the first chip pad layer 113, and the third chip pad layer 142 may be disposed on the second chip pad layer 135.

[0079] The first chip pad layer 113 may include the same material as the first gate electrode 111 and the second gate electrode 112, and may be disposed in the same layer as the first gate electrode 111 and the second gate electrode 112. In an exemplary embodiment, for example, the first chip pad layer 113 may include molybdenum (Mo) or the like, and may be disposed on the first insulating layer 101. The second chip pad layer 135 may include the same material as the first source / drain electrodes 131 / 132 and the second source / drain electrodes 133 / 134, and may be disposed in the same layer as the first source / drain electrodes 131 / 132 and the second source / drain electrodes 133 / 134. In an exemplary embodiment, for example, the second chip pad layer 135 may include aluminum (Al), titanium (Ti), or the like, and may be disposed on the third insulating layer 103. The third chip pad layer 142 may include the same material as the connection electrode 141, and may be disposed in the same layer as the connection electrode 141. In an exemplary embodiment, for example, the third chip pad layer 142 may include aluminum (Al), titanium (Ti), etc., and may be disposed on the fourth insulating layer 104.

[0080] The film pad FP may include a first film pad layer 136 and a second film pad layer 143. The second film pad layer 143 may be disposed on the first film pad layer 136.

[0081] The first film pad layer 136 may include the same material as the first source / drain electrodes 131 / 132, the second source / drain electrodes 133 / 134, and the second chip pad layer 135, and may be disposed in the same layer as the first source / drain electrodes 131 / 132, the second source / drain electrodes 133 / 134, and the second chip pad layer 135. In an exemplary embodiment, for example, the first film pad layer 136 may include aluminum (Al), titanium (Ti), etc., and may be disposed on the third insulating layer 103. The second film pad layer 143 may include the same material as the connection electrode 141 and the third chip pad layer 142, and may be disposed in the same layer as the connection electrode 141 and the third chip pad layer 142. In an exemplary embodiment, for example, the second film pad layer 143 may include aluminum (Al), titanium (Ti), etc., and may be disposed on the fourth insulating layer 104.

[0082] The wiring layer WR may include a first wiring layer 114 and a second wiring layer 144. The second wiring layer 144 may be disposed on the first wiring layer 114.

[0083] The first wiring layer 114 may include the same material as the first gate electrode 111, the second gate electrode 112, and the first chip pad layer 113, and may be disposed in the same layer as the first gate electrode 111, the second gate electrode 112, and the first chip pad layer 113. In an exemplary embodiment, for example, the first wiring layer 114 may include molybdenum (Mo) or the like, and may be disposed on the first insulating layer 101. The second wiring layer 144 may include the same material as the connection electrode 141, the third chip pad layer 142, and the second film pad layer 143, and may be disposed in the same layer as the connection electrode 141, the third chip pad layer 142, and the second film pad layer 143. In an exemplary embodiment, for example, the second wiring layer 144 may include aluminum (Al), titanium (Ti), or the like, and may be disposed on the fourth insulating layer 104.

[0084] The first wiring layer 114 can be integrated with the first chip pad layer 113. In other words, the chip pad CP and the wiring WR can share the integrated first chip pad layer 113 and the first wiring layer 114.

[0085] The first recess GR1 can be defined within the second wiring layer 144. A portion of the first wiring layer 114 can be exposed by the first recess GR1. The second wiring layer 144 can include a first portion 144a and a second portion 144b separated by the first recess GR1. The first portion 144a and the second portion 144b can be integral with the third chip pad layer 142 and the second film pad layer 143, respectively. In other words, the chip pad CP and the wiring WR can share the first portion 144a of the third chip pad layer 142 and the second wiring layer 144, which are integral with each other, and the film pad FP and the wiring WR can share the second portion 144b of the second film pad layer 143 and the second wiring layer 144, which are integral with each other. The first recess GR1 can be arranged closer to the chip pad CP than the film pad FP. Therefore, the length of the second portion 144b of the second wiring layer 144 in the second direction DR2 can be greater than the length of the first portion 144a of the second wiring layer 144 in the second direction DR2.

[0086] Although the first recess GR1 separating the second wiring layer 144 is defined in the second wiring layer 144, the signal can be transmitted between the chip pad CP and the film pad FP through the first wiring layer 114 because the wiring WR is provided as a multilayer structure including the first wiring layer 114 and the second wiring layer 144.

[0087] An organic insulating layer 150 covering the chip pads CP and wiring WR can be disposed on the fourth insulating layer 104. The organic insulating layer 150 may not cover the film pads FP. In other words, the organic insulating layer 150 can extend from the display area DA to a portion of the pad area PA between the chip pad area CPA and the film pad area FPA.

[0088] Contact holes CH, which expose portions of the chip pad CP, can be confined within the organic insulating layer 150. The contact holes CH can expose the upper surface of the chip pad CP. Because the contact holes CH are confined within the organic insulating layer 150, the terminals of the driver chip DC can be connected to the chip pad CP through the contact holes CH.

[0089] A portion of the organic insulating layer 150 covering the chip pad CP and a portion of the organic insulating layer 150 surrounding the chip pad region CPA can be separated. Furthermore, within this portion of the organic insulating layer 150 covering the chip pad CP, a portion of the organic insulating layer 150 covering the input chip pad CPI and a portion of the organic insulating layer 150 covering the output chip pad CPO can be separated. Because this portion of the organic insulating layer 150 covering the chip pad CP and this portion of the organic insulating layer 150 surrounding the chip pad region CPA are separated from each other, although impurities flow into this portion of the organic insulating layer 150 surrounding the chip pad region CPA, the path for impurities such as moisture to be transported to this portion of the organic insulating layer 150 covering the chip pad CP can be blocked. Therefore, damage to the chip pad CP due to impurities can be prevented.

[0090] As described above, because the portion of the organic insulating layer 150 covering the chip pad CP and the portion of the organic insulating layer 150 surrounding the chip pad region CPA are separated, the portion of the organic insulating layer 150 covering the chip pad CP and the portion of the organic insulating layer 150 covering the wiring WR can also be separated. Therefore, the organic insulating layer 150 can have a second groove GR2 between the portion of the organic insulating layer 150 covering the chip pad CP and the portion of the organic insulating layer 150 covering the wiring WR.

[0091] The second groove GR2 can correspond to the first groove GR1. The width of the second groove GR2 in the second direction DR2 can be smaller than the width of the first groove GR1 in the second direction DR2. Therefore, the organic insulating layer 150 can cover one end of the first portion 144a and one end of the second portion 144b of the second wiring layer 144, which are separated by the first groove GR1, and the second wiring layer 144 can be kept from being exposed to the outside. Further, a portion of the first wiring layer 114 can be exposed by the first groove GR1 and the second groove GR2. Because this portion of the organic insulating layer 150 covering the chip pad CP and this portion of the organic insulating layer 150 covering the wiring WR are separated by the second groove GR2, although impurities flow into this portion of the organic insulating layer 150 covering the wiring WR, the path for the impurities to be transferred to this portion of the organic insulating layer 150 covering the chip pad CP can be blocked. Therefore, damage to the chip pad CP due to impurities can be prevented.

[0092] In an exemplary embodiment, the first wiring layer 114 may include a material having a lower ionization tendency than the material included in the second wiring layer 144. For example, in an exemplary embodiment, the first wiring layer 114 may include molybdenum (Mo) having a lower ionization tendency than aluminum (Al) included in the second wiring layer 144.

[0093] Because the second groove GR2 is confined within the organic insulating layer 150, the process of forming the pixel electrode 160 on the organic insulating layer 150 includes ions of the material in the pixel electrode 160 (e.g., silver ions (Ag)). + The second wiring layer 144, which includes a material with a relatively high ionization tendency, can come into contact with the wiring layer WR. When ions of the material included in the pixel electrode 160 come into contact with the second wiring layer 144, the material included in the second wiring layer 144 can be ionized, and the ions of the material included in the pixel electrode 160 may be reduced to deposit on the wiring layer WR. In this case, the wiring layer WR can be electrically connected via the deposited material (e.g., silver particles (Ag)) included in the pixel electrode 160, and therefore, defects in the display device may occur.

[0094] However, in the illustrated exemplary embodiment, the first groove GR1 corresponding to the second groove GR2 of the organic insulating layer 150 can be confined in the second wiring layer 144. Therefore, because the organic insulating layer 150 covers the second wiring layer 144, ions of the material included in the pixel electrode 160 may not come into contact with the second wiring layer 144, which includes a material with a relatively high ionization tendency. Furthermore, although ions of the material included in the pixel electrode 160 come into contact with the first wiring layer 114, the material included in the first wiring layer 114 may not be ionized because the first wiring layer 114 has a relatively low ionization tendency. Therefore, defects in the display device can be prevented.

[0095] In an exemplary embodiment, the second wiring layer 144 may include a material having a lower resistance than the material included in the first wiring layer 114. For example, in an exemplary embodiment, the second wiring layer 144 may include aluminum (Al) having a lower resistance than the molybdenum (Mo) included in the first wiring layer 114. The wiring WR may be provided as a multilayer structure including a first wiring layer 114 with a relatively low ionization tendency and a second wiring layer 144 with relatively low resistance, so that the resistance of the wiring WR can be reduced and damage to the wiring WR can be prevented.

[0096] Figure 6 It is shown in the diagram along Figure 4 A cross-sectional view of an exemplary embodiment of the display device, taken by line I-I' in the reference diagram. (The reference diagram may not be repeated.) Figure 6 The description of the components of the described display device is available in reference. Figure 6 The components of the described display device are basically the same as those in the reference. Figure 5 The components of the described display devices are the same or similar.

[0097] refer to Figure 3 and Figure 6 The chip pad CP may include a first chip pad layer 122, a second chip pad layer 135, and a third chip pad layer 142. The second chip pad layer 135 may be disposed on the first chip pad layer 122, and the third chip pad layer 142 may be disposed on the second chip pad layer 135.

[0098] The first chip pad layer 122 may include the same material as the second capacitor electrode 121 and may be disposed in the same layer as the second capacitor electrode 121. In an exemplary embodiment, for example, the first chip pad layer 122 may include molybdenum (Mo) and may be disposed on the second insulating layer 102.

[0099] The wiring layer WR may include a first wiring layer 123 and a second wiring layer 144. The second wiring layer 144 may be disposed on the first wiring layer 123.

[0100] The first wiring layer 123 may include the same material as the second capacitor electrode 121 and the first chip pad layer 122, and may be disposed in the same layer as the second capacitor electrode 121 and the first chip pad layer 122. In an exemplary embodiment, for example, the first wiring layer 123 may include molybdenum (Mo) and may be disposed on the second insulating layer 102.

[0101] The first wiring layer 123 can be integrated with the first chip pad layer 122. In other words, the chip pad CP and the wiring WR can share the integrated first chip pad layer 122 and the first wiring layer 123.

[0102] Figure 7 It is shown in the diagram along Figure 4 A cross-sectional view of an exemplary embodiment of the display device, taken by line I-I' in the reference diagram. (The reference diagram may not be repeated.) Figure 7 The description of the components of the described display device is available in reference. Figure 7 The components of the described display device are basically the same as those in the reference. Figure 5 The components of the described display devices are the same or similar.

[0103] refer to Figure 3 and Figure 7 The chip pad CP may include a first chip pad layer 113, a fourth chip pad layer 122, a second chip pad layer 135, and a third chip pad layer 142. The fourth chip pad layer 122 may be disposed on the first chip pad layer 113, the second chip pad layer 135 may be disposed on the fourth chip pad layer 122, and the third chip pad layer 142 may be disposed on the second chip pad layer 135.

[0104] The fourth chip pad layer 122 may include the same material as the second capacitor electrode 121 and may be disposed in the same layer as the second capacitor electrode 121. In an exemplary embodiment, for example, the fourth chip pad layer 122 may include molybdenum (Mo) and may be disposed on the second insulating layer 102.

[0105] The routing layer WR may include a first routing layer 114, a third routing layer 123, and a second routing layer 144. The third routing layer 123 may be disposed on the first routing layer 114, and the second routing layer 144 may be disposed on the third routing layer 123.

[0106] The third wiring layer 123 may include the same material as the second capacitor electrode 121 and the fourth chip pad layer 122, and may be disposed in the same layer as the second capacitor electrode 121 and the fourth chip pad layer 122. In an exemplary embodiment, for example, the third wiring layer 123 may include molybdenum (Mo) and may be disposed on the second insulating layer 102.

[0107] The third wiring layer 123 can be integrated with the fourth chip pad layer 122. In other words, the chip pad CP and the wiring WR can share the integrated fourth chip pad layer 122 and the third wiring layer 123.

[0108] Although the first recess GR1 separating the second wiring layer 144 is defined in the second wiring layer 144, the signal can be transmitted between the chip pad CP and the film pad FP through the first wiring layer 114 and the third wiring layer 123 because the wiring WR is provided as a multilayer structure including the first wiring layer 114, the third wiring layer 123 and the second wiring layer 144.

[0109] In an exemplary embodiment, the third wiring layer 123 may include a material having a lower ionization tendency than the material included in the second wiring layer 144. For example, in an exemplary embodiment, the third wiring layer 123 may include molybdenum (Mo) having a lower ionization tendency than aluminum (Al) included in the second wiring layer 144.

[0110] In the illustrated exemplary embodiment, the first groove GR1 corresponding to the second groove GR2 of the organic insulating layer 150 can be confined in the second wiring layer 144. Therefore, because the organic insulating layer 150 covers the second wiring layer 144, ions of the material included in the pixel electrode 160 may not come into contact with the second wiring layer 144, which includes a material having a relatively high ionization tendency. Furthermore, although ions of the material included in the pixel electrode 160 come into contact with the third wiring layer 123, the material included in the third wiring layer 123 may not be ionized because the third wiring layer 123 has a relatively low ionization tendency. Therefore, defects in the display device can be prevented.

[0111] In an exemplary embodiment, the second wiring layer 144 may include a material having a lower resistance than the material included in the first wiring layer 114 and the third wiring layer 123. In an exemplary embodiment, for example, the second wiring layer 144 may include aluminum (Al) having a lower resistance than the molybdenum (Mo) included in the first wiring layer 114 and the third wiring layer 123. The wiring WR may be provided as a multilayer structure including a first wiring layer 114 and a third wiring layer 123 having relatively low ionization tendency and a second wiring layer 144 having relatively low resistance, so that the resistance of the wiring WR can be reduced and damage to the wiring WR can be prevented.

[0112] The display device in the exemplary embodiment can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, portable media players (PMPs), personal digital assistants (PDAs), MP3 players, etc.

[0113] Although the display device in the exemplary embodiments has been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and altered by those skilled in the art without departing from the spirit of the technology described in the appended claims.

Claims

1. A display device, comprising: Pixel; Chip pads spaced apart from the pixels; Film pads spaced apart from the chip pads; Wiring, the wiring connecting the chip pads and the film pads, and including a first wiring layer and a second wiring layer disposed on the first wiring layer; as well as An organic insulating layer covering the chip pads and the wiring. The first groove is defined within the second wiring layer, and the second wiring layer includes a first portion and a second portion separated by the first groove. Wherein, the organic insulating layer covers one end of the first portion and one end of the second portion, and The second groove, corresponding to the first groove, is defined within the organic insulating layer.

2. The display device according to claim 1, wherein, The width of the second groove is smaller than the width of the first groove.

3. The display device according to claim 1, wherein, The first wiring layer includes a material having a lower ionization tendency than the material included in the second wiring layer.

4. The display device according to claim 1, wherein, The second wiring layer includes a material with a lower resistance than the material included in the first wiring layer.

5. The display device according to claim 1, wherein, The chip pads include: a first chip pad layer, a second chip pad layer disposed on the first chip pad layer, and a third chip pad layer disposed on the second chip pad layer. The first wiring layer and the first chip pad layer are integrated.

6. The display device according to claim 5, wherein, The film pads include: a first film pad layer and a second film pad layer disposed on the first film pad layer, and The first part and the second part are integral with the third chip pad layer and the second film pad layer, respectively.

7. The display device according to claim 6, wherein, The second wiring layer comprises the same material as the third chip pad layer and the second film pad layer.

8. The display device according to claim 5, wherein, The wiring further includes: a third wiring layer disposed between the first wiring layer and the second wiring layer, and The chip pads further include a fourth chip pad layer disposed between the first chip pad layer and the second chip pad layer; and The third wiring layer and the fourth chip pad layer are integrated.

9. The display device according to claim 1, wherein, The film pads include: a first film pad layer and a second film pad layer disposed on the first film pad layer, and In this embodiment, a portion of the second wiring layer is integral with the second film pad layer.

10. The display device according to claim 1, wherein, The pixels include: A transistor, the transistor including an active layer, a gate electrode disposed on the active layer, and source / drain electrodes disposed on the gate electrode; A capacitor, the capacitor comprising a first capacitor electrode integral with the gate electrode and a second capacitor electrode disposed between the first capacitor electrode and the source / drain electrode; A light-emitting element, comprising a pixel electrode disposed on the source / drain electrode, an emitting layer disposed on the pixel electrode, and a counter electrode disposed on the emitting layer; and A connecting electrode is disposed between the source / drain electrode and the pixel electrode and connects the source / drain electrode and the pixel electrode.

11. The display device according to claim 10, wherein, The first wiring layer comprises the same material as the gate electrode.

12. The display device according to claim 10, wherein, The first wiring layer comprises the same material as the second capacitor electrode.

13. The display device according to claim 10, wherein, The second wiring layer comprises the same material as the connecting electrode.

14. The display device according to claim 10, wherein, The organic insulating layer is disposed between the connection electrode and the pixel electrode and covers the connection electrode.

15. The display device according to claim 10, wherein, The chip pads include: a first chip pad layer, a second chip pad layer disposed on the first chip pad layer, and a third chip pad layer disposed on the second chip pad layer. The third chip pad layer comprises the same material as the connecting electrode.

16. The display device according to claim 15, wherein, The first chip pad layer comprises the same material as the gate electrode.

17. The display device according to claim 15, wherein, The first chip pad layer comprises the same material as the second capacitor electrode.

18. The display device according to claim 15, wherein, The wiring further includes: a third wiring layer disposed between the first wiring layer and the second wiring layer, and The chip pads further include a fourth chip pad layer disposed between the first chip pad layer and the second chip pad layer.

19. The display device according to claim 18, wherein, The first wiring layer comprises the same material as the gate electrode, and The third wiring layer comprises the same material as the second capacitor electrode.

20. The display device according to claim 18, wherein, The first chip pad layer comprises the same material as the gate electrode, and The fourth chip pad layer comprises the same material as the second capacitor electrode.

Images