Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a source / drain pattern disposed on a substrate and a source / drain contact connected to the source / drain pattern. The source / drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure. The upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction. The first sidewall of the upper contact structure includes a plurality of first sub-sidewalls, and each of the first sub-sidewalls includes a concave surface.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0106973, filed with the Korean Intellectual Property Office on August 30, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductors, and more particularly, to a semiconductor device and a method of manufacturing the same. Background Art

[0004] There is a trend to make semiconductors more highly integrated while reducing manufacturing costs. These highly integrated semiconductors assemble a larger number of structures into a smaller size, thereby reducing the pitch of the device. Summary of the Invention

[0005] A semiconductor device includes a source / drain pattern disposed on a substrate and a source / drain contact connected to the source / drain pattern. The source / drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure. The upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction. The first sidewall of the upper contact structure includes a plurality of first sub - sidewalls, and each first sub - sidewall includes a concave surface.

[0006] A semiconductor device includes a substrate having an active region and a field region. At least one active pattern protrudes from the substrate in the active region and extends in a first direction. A gate electrode crosses the active pattern in the active region and extends in a second direction. A source / drain pattern is disposed on the active pattern. A gate contact is connected to the gate electrode and a source / drain contact is connected to the source / drain pattern. A portion of the gate electrode extends into the field region. At least a portion of the gate contact is disposed on the active region. The source / drain contact includes a lower contact structure extending in the first direction and an upper contact structure protruding from the lower contact structure. The upper contact structure includes a first sidewall and a second sidewall facing away from each other in the second direction. The upper contact structure includes at least one vertex portion protruding in the second direction. Each vertex portion is defined where adjacent curved surfaces meet.

[0007] A semiconductor device includes a source / drain pattern disposed on a substrate. A source / drain contact is connected to the source / drain pattern and includes a lower contact structure and an upper contact structure that protrudes from the lower contact structure and includes a first sidewall and a second sidewall facing away from each other. A contact insulating pad extends along the first sidewall of the upper contact structure and the second sidewall of the upper contact structure. Each of the first sidewall of the upper contact structure and the second sidewall of the upper contact structure includes a plurality of sub - sidewalls, and each sub - sidewall has a concave surface.

[0008] A method of manufacturing a semiconductor device includes forming source / drain contacts connected to source / drain patterns in an interlayer insulating film. A mask pattern is formed on the source / drain patterns to expose a part of the source / drain contacts. A first sub-recess is formed by removing a part of the source / drain contacts using the mask pattern. A first sub-insulating liner is formed along sidewalls and a bottom surface of the first sub-recess. A first insulating liner pattern is formed on sidewalls of the first sub-recess defined by the source / drain contacts by anisotropically etching the first sub-insulating liner. A second sub-recess is formed by removing a part of the source / drain contacts using the mask pattern and a second sub-insulating liner is formed along sidewalls and a bottom surface of the second sub-recess. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] When the present disclosure and many attendant aspects thereof are considered in conjunction with the accompanying drawings, a better understanding will be readily obtained by reference to the following detailed description. Accordingly, a more complete understanding of the present disclosure and many attendant aspects thereof will be easily obtained, in which:

[0010] Figure 1 is a layout diagram of a semiconductor device showing an exemplary embodiment according to the present disclosure;

[0011] Figure 2 is a cross-sectional view taken along line A-A of Figure 1 ;

[0012] Figure 3 is Figure 2 an enlarged view of part P of

[0013] Figure 4 , Figure 5 and Figure 6 are cross-sectional views taken along lines B-B, C-C, and D-D of Figure 1 ;

[0014] Figures 7 to 10 respectively show semiconductor devices according to exemplary embodiments of the present disclosure;

[0015] Figures 11 to 13 respectively show semiconductor devices according to exemplary embodiments of the present disclosure;

[0016] Figures 14 to 18 respectively show semiconductor devices according to exemplary embodiments of the present disclosure;

[0017] Figure 19 and Figure 20 respectively show semiconductor devices according to exemplary embodiments of the present disclosure;

[0018] Figures 21A to 22 respectively show semiconductor devices according to exemplary embodiments of the present disclosure;

[0019] Figure 23Shows a semiconductor device according to an exemplary embodiment of the present disclosure;

[0020] Figure 24 and Figure 25 are layout diagrams of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0021] Figures 26 to 35 is a cross-sectional view showing operations in a method of manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure. Detailed Description

[0022] As described and shown herein, as an example, a fin field-effect transistor (FinFET) including a channel region having a fin pattern shape and a transistor including a nanosheet or nanowire are shown. However, the present invention is not limited to these transistors. A semiconductor device according to an exemplary embodiment of the present disclosure may further include a tunneling FET or a three-dimensional (3D) transistor. A semiconductor device according to an exemplary embodiment of the present disclosure may further include a planar transistor. Additionally, a semiconductor device according to an exemplary embodiment of the present disclosure may include a bipolar junction transistor, a laterally double-diffused metal oxide semiconductor (LDMOS), etc.

[0023] Now, reference will be made to Figures 1 to 6 to describe a semiconductor device according to an exemplary embodiment of the present disclosure.

[0024] Figure 1 is a layout diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 2 is along Figure 1 a cross-sectional view taken along line A-A. Figure 3 is Figure 2 an enlarged view of part P of Figure 4 , Figure 5 and Figure 6 are cross-sectional views taken along lines B-B, C-C, and D-D of Figure 1 respectively. For ease of description, Figure 1 the wiring structure 210 is not shown in

[0025] Referring to Figures 1 to 6 , a semiconductor device according to an exemplary embodiment of the present disclosure may include at least one first active pattern AF1, at least one second active pattern AF2, a first gate electrode 120, a second gate electrode 220, a first source / drain contact 170, a second source / drain contact 270, a contact insulating pad 175, a first gate contact 180, and a second gate contact 280.

[0026] The substrate 100 may include a first active region RX1, a second active region RX2, and a field region FX. The field region FX may be directly adjacent to the first active region RX1 and the second active region RX2. The field region FX may share a boundary with each of the first active region RX1 and the second active region RX2.

[0027] The first active region RX1 and the second active region RX2 are spaced apart from each other. The first active region RX1 and the second active region RX2 may be separated by the field region FX.

[0028] For example, the first active region RX1 and the second active region RX2 are spaced apart from each other and may be at least partially surrounded by an element isolation layer. A part of the element isolation layer is disposed between the first active region RX1 and the second active region RX2, and this part may be the field region FX. For example, a part that forms the channel region of a transistor (which may be an example of a semiconductor device) may be an active region, and a part that defines the channel region of the transistor formed in the active region may be a field region. Alternatively, the active region may be a part that forms a fin pattern or a nanosheet serving as the channel region of a transistor, and the field region may be a region where the fin pattern or the nanosheet serving as the channel region is not formed.

[0029] As Figure 2 and Figure 6 shown, the field region FX may be defined by a deep trench DT, but the present invention is not limited to this case. In addition, those skilled in the art to which the present disclosure pertains can distinguish which part is the field region and which part is the active region.

[0030] The substrate 100 may be a silicon substrate or a silicon-on-insulator (SOI) substrate. Otherwise, the substrate 100 may include (but is not limited to including) silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0031] A first active pattern AF1 may be formed in the first active region RX1. The first active pattern AF1 may protrude from the first active region RX1 of the substrate 100. The first active pattern AF1 may be disposed on the substrate 100 and extend along a first direction X1. A second active pattern AF2 may be formed in the second active region RX2. The description of the second active pattern AF2 may be substantially the same as the description of the first active pattern AF1, and thus, insofar as the second active pattern AF2 is not described herein, it may be assumed to be at least similar to the first active pattern AF1.

[0032] In a semiconductor device according to an exemplary embodiment of the present disclosure, each of the first active patterns AF1 may be, for example, a fin pattern. The first active pattern AF1 may be used as a channel pattern of a transistor. Although three first active patterns AF1 and three second active patterns AF2 are shown, this is merely an example for easy description, and the present invention is not limited to this example. The number of the first active patterns AF1 and the number of the second active patterns AF2 may each be at least one.

[0033] Each of the first active pattern AF1 and the second active pattern AF2 may be a part of the substrate 100 or may include an epitaxial layer grown from the substrate 100. Each of the first active pattern AF1 and the second active pattern AF2 may include an elemental semiconductor material such as silicon or germanium. Alternatively, each of the first active pattern AF1 and the second active pattern AF2 may include a compound semiconductor such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0034] The group IV-IV compound semiconductor may be, for example, a binary or ternary compound containing two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn) or a compound obtained by doping a binary or ternary compound with a group IV element. The group III-V compound semiconductor may be, for example, a binary, ternary, or quaternary compound composed of at least one of aluminum (Al), gallium (Ga), and indium (In) (i.e., group III elements) bonded to one of phosphorus (P), arsenic (As), and antimony (Sb) (i.e., group V elements).

[0035] The field insulating layer 105 may be formed on the substrate 100. The field insulating layer 105 may be formed above the first active region RX1, the second active region RX2, and the field region FX. The field insulating layer 105 may fill the deep trench DT.

[0036] The field insulating layer 105 may be formed on a part of the sidewalls of the first active pattern AF1 and a part of the sidewalls of the second active pattern AF2. Each of the first active pattern AF1 and the second active pattern AF2 may protrude above the upper surface of the field insulating layer 105. The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, a nitride oxide layer, or a combination thereof.

[0037] The first gate electrode 120 and the second gate electrode 220 may extend in the second direction Y1. Each of the first gate electrode 120 and the second gate electrode 220 may be disposed on the first active pattern AF1 and the second active pattern AF2. Each of the first gate electrode 120 and the second gate electrode 220 may cross the first active pattern AF1 and the second active pattern AF2.

[0038] Although each of the first gate electrode 120 and the second gate electrode 220 is shown as being disposed over the first active region RX1 and the second active region RX2, this is merely an example for ease of description, and the present invention is not limited to this example. For example, at least one of the first gate electrode 120 and the second gate electrode 220 may be divided into two portions disposed in the first active region RX1 and the second active region RX2.

[0039] The first gate electrode 120 and the second gate electrode 220 may include at least one of, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Each of the first gate electrode 120 and the second gate electrode 220 may include a conductive metal oxide, a conductive metal oxynitride, or an oxidized form of any of the above materials.

[0040] The first gate spacer 140 may be disposed on the sidewalls of the first gate electrode 120. The second gate spacer 240 may be disposed on the sidewalls of the second gate electrode 220. Each of the first gate spacer 140 and the second gate spacer 240 may extend along the second direction Y1.

[0041] Each of the first gate spacer 140 and the second gate spacer 240 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0042] Each of the first gate insulating layer 130 and the second gate insulating layer 230 may be formed over the first active pattern AF1, the second active pattern AF2, and the field insulating layer 105. The first gate insulating layer 130 may be formed between the first gate electrode 120 and the first gate spacer 140. The second gate insulating layer 230 may be formed between the second gate electrode 220 and the second gate spacer 240.

[0043] Each of the first gate insulating layer 130 and the second gate insulating layer 230 may be formed along the contours of the first active pattern AF1 and the second active pattern AF2 protruding above the field insulating layer 105 and along the upper surface of the field insulating layer 105. An interface layer may be further formed along the contours of the first active pattern AF1 and the second active pattern AF2 protruding above the field insulating layer 105. Each of the first gate insulating layer 130 and the second gate insulating layer 230 may be formed on the interface layer.

[0044] Each of the first gate insulating layer 130 and the second gate insulating layer 230 may include silicon oxide, silicon oxynitride, silicon nitride, or a high-k (high dielectric constant) material having a dielectric constant higher than that of silicon oxide. The high-k material may include, for example, one or more of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0045] The shape of the second gate insulating layer 230 and the second gate electrode 220 may be similar to Figure 6 the shape of the first gate insulating layer 130 and the first gate electrode 120 shown.

[0046] The first capping pattern 145 may be disposed on the first gate electrode 120 and the first gate spacer 140. The second capping pattern 245 may be disposed on the second gate electrode 220 and the second gate spacer 240. Similar to the upper surfaces of the first gate electrode 120 and the second gate electrode 220, the upper surfaces of the first gate spacer 140 and the second gate spacer 240 may be recessed toward the upper surface of the first active pattern AF1.

[0047] Different from that shown in the drawings, the upper surfaces of the first gate spacer 140 and the second spacer 240 may not be recessed toward the upper surface of the first active pattern AF1. In this case, the first capping pattern 145 may be disposed between the sidewalls of the first gate spacer 140, and the second capping pattern 245 may be disposed between the sidewalls of the second gate spacer 240.

[0048] Each of the first capping pattern 145 and the second capping pattern 245 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

[0049] Although the lower surfaces of the first capping pattern 145 and the second capping pattern 245 are curved in Figure 4 and Figure 5 , the present invention is not limited to this case.

[0050] The source / drain pattern 150 may be formed on the first active pattern AF1. The source / drain pattern 150 may be located on the substrate 100. The source / drain pattern 150 may be disposed between the first gate electrode 120 and the second gate electrode 220. The source / drain pattern 150 may include an epitaxial pattern. The source / drain pattern 150 may be included in the source / drain regions of the transistors using the first active pattern AF1 as the channel region.

[0051] The source / drain pattern 150 may extend along the second direction Y1. The source / drain pattern 150 may be connected to the channel pattern portion of the first active pattern AF1 serving as the channel.

[0052] Although the source / drain pattern 150 is shown as a pattern formed by merging three epitaxial patterns respectively formed on the first active pattern AF1, this is only an example for easy description, and the present invention is not limited to this example. For example, the epitaxial patterns respectively formed on the first active pattern AF1 may also be separated from each other. Alternatively, two adjacent epitaxial layers may be merged, and another epitaxial layer may not be merged.

[0053] The first source / drain contact 170 and the first gate contact 180 may be disposed on the first active region RX1. The second source / drain contact 270 and the second gate contact 280 may be disposed on the second active region RX2. Different from what is shown in the drawings, the second gate contact 280 may also be disposed on the first active region RX1.

[0054] In the semiconductor device according to an exemplary embodiment of the present disclosure, at least a part of the first gate contact 180 and at least a part of the second gate contact 280 may be respectively disposed on the first active region RX1 and the second active region RX2. For example, at least a part of the first gate contact 180 and at least a part of the second gate contact 280 may be respectively disposed at positions overlapping with the first active region RX1 and the second active region RX2.

[0055] For example, the entire first gate contact 180 may be disposed on the first active region RX1. The entire first gate contact 180 may be disposed at a position overlapping with the first active region RX1. The entire second gate contact 280 may be disposed on the second active region RX2. The entire second gate contact 280 may be disposed at a position overlapping with the second active region RX2.

[0056] The first source / drain contact 170 may be connected to the source / drain pattern 150 formed in the first active region RX1. The second source / drain contact 270 may be connected to the source / drain pattern formed in the second active region RX2. The first gate contact 180 may be connected to the first gate electrode 120, and the second gate contact 280 may be connected to the second gate electrode 220.

[0057] The following description will be given using the first source / drain contact 170 and the first gate contact 180 provided in the first active region RX1.

[0058] The first source / drain contact 170 may be connected to the source / drain pattern 150. The first source / drain contact 170 may be provided on the source / drain pattern 150.

[0059] A silicide layer 155 may be formed between the first source / drain contact 170 and the source / drain pattern 150. Although the silicide layer 155 is shown as being formed along the contour of the boundary surface between the source / drain pattern 150 and the first source / drain contact 170, the present invention is not limited to this case. The silicide layer 155 may include, for example, a metal silicide material.

[0060] The first source / drain contact 170 may include a lower contact structure 171 extending in the second direction Y1 and an upper contact structure 172 provided on the lower contact structure 171. The upper contact structure 172 may protrude from the lower contact structure 171. The upper contact structure 172 protrudes above the upper surface 171us of the lower contact structure 171. The upper contact structure 172 is directly connected to the lower contact structure 171.

[0061] The width of the lower contact structure 171 in the second direction Y1 is greater than the width of the upper contact structure 172. For example, the width of the upper surface 171us of the lower contact structure 171 is greater than the width of the lower surface of the upper contact structure 172. For example, in a cross-sectional view taken in the second direction Y1, the first source / drain contact 170 may have a "T" shape rotated 180 degrees.

[0062] The lower contact structure 171 may include a first sidewall 171sa and a second sidewall 171sb that are spaced apart from each other in the second direction Y1. The upper contact structure 172 may include a first sidewall 172sa and a second sidewall 172sb that are spaced apart from each other in the second direction Y1. The first sidewall 172sa of the upper contact structure 172 and the second sidewall 172sb of the upper contact structure 172 may be directly connected to the upper surface 171us of the lower contact structure 171. The first sidewall 171sa of the lower contact structure 171 is closer to the first sidewall 172sa of the upper contact structure 172 than the second sidewall 172sb of the upper contact structure 172.

[0063] The first source / drain contact 170 may include a first contact barrier layer 170a and a first contact fill layer 170b disposed on the first contact barrier layer 170a. The first contact barrier layer 170a may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). The first contact fill layer 170b may include at least one of, for example, aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo). For example, the first contact fill layer 170b may include cobalt (Co).

[0064] In a semiconductor device according to an exemplary embodiment of the present disclosure, the first contact barrier layer 170a may not be exposed at a first sidewall 172sa of the upper contact structure 172 and a second sidewall 172sb of the upper contact structure 172.

[0065] In a semiconductor device according to an exemplary embodiment of the present disclosure, a first distance W1 from a center line 172CL of the upper contact structure 172 to a first sidewall 171sa of the lower contact structure 171 may be equal to a second distance W2 from the center line 172CL of the upper contact structure 172 to a second sidewall 171sb of the lower contact structure 171.

[0066] Here, the center line 172CL of the upper contact structure 172 may be an imaginary line that bisects an upper surface 172us of the upper contact structure 172 and is orthogonal to the upper surface 172us of the upper contact structure 172. Additionally, points on the first sidewall 171sa of the lower contact structure 171 and on the second sidewall 171sb of the lower contact structure 171 from which the first distance W1 and the second distance W2 are measured may be points at which the first sidewall 171sa of the lower contact structure 171 and the second sidewall 171sb of the lower contact structure 171 meet an imaginary line parallel to the upper surface 172us of the upper contact structure 172 when the imaginary line moves toward the substrate 100.

[0067] In a semiconductor device according to an exemplary embodiment of the present disclosure, the first sidewall 172sa of the upper contact structure 172 and the second sidewall 172sb of the upper contact structure 172 may have an uneven structure. The first sidewall 171sa of the lower contact structure 171 and the second sidewall 171sb of the lower contact structure 171 may not have an uneven structure.

[0068] For example, the first sidewall 172sa of the upper contact structure 172 may include a plurality of first sub-sidewalls 172saa, 172sab, 172sac, and 172sad. The second sidewall 172sb of the upper contact structure 172 may include a plurality of second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd. In a semiconductor device according to an exemplary embodiment of the present disclosure, the number of the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad included in the first sidewall 172sa of the upper contact structure 172 is equal to the number of the second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd included in the second sidewall 172sb of the upper contact structure 172.

[0069] Although each of the first sidewall 172sa of the upper contact structure 172 and the second sidewall 172sb of the upper contact structure 172 includes four sub-sidewalls, the present invention is not limited to this case. The first sidewall 172sa of the upper contact structure 172 and the second sidewall 172sb of the upper contact structure 172 may include the same number (e.g., two or more) of sub-sidewalls.

[0070] Each of the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad may include a surface that is recessed toward the inside of the upper contact structure 172. Each of the second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd may include a surface that is recessed toward the inside of the upper contact structure 172.

[0071] Adjacent first sub-sidewalls 172saa, 172sab, 172sac, and 172sad may be directly connected to each other. Adjacent second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd may be directly connected to each other.

[0072] In a semiconductor device according to an exemplary embodiment of the present disclosure, the respective heights h11, h21, h31, and h41 of the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad may be substantially equal. The respective heights h12, h22, h32, and h42 of the second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd may be substantially equal. Here, "equal height" is intended to cover not only exactly the same height at two compared positions, but may also include two slightly different heights having a slight difference caused by process margins or the like.

[0073] In addition, for example, the height h11 of the (1_1) sub-sidewall 172saa may be equal to the height h12 of the (2_1) sub-sidewall 172sba located at a position corresponding to the (1_1) sub-sidewall 172saa. Accordingly, in the semiconductor device according to an exemplary embodiment of the present disclosure, the height of the first sidewall 172sa of the upper contact structure 172 may be substantially equal to the height of the second sidewall 172sb of the upper contact structure 172.

[0074] The upper contact structure 172 may include one or more vertex portions 172tp. Each vertex portion 172tp may be defined where adjacent curved surfaces (e.g., adjacent concave surfaces) meet. For example, each vertex portion 172tp may be defined where adjacent first sub-sidewalls 172saa and 172sab meet. For example, a portion of the first sub-sidewall included in the first sidewall 172sa of the upper contact structure 172 and a portion of the first sub-sidewall included in the first sidewall 172sa of the upper contact structure 172 may define vertex portions 172tp adjacent to each other in the thickness direction of the substrate 100. In the semiconductor device according to an exemplary embodiment of the present disclosure, the point where the upper surface 172us of the upper contact structure 172 meets the first sidewall 172sa of the upper contact structure 172 and the point where the upper surface 172us of the upper contact structure 172 meets the second sidewall 172sb of the upper contact structure 172 are not vertex portions.

[0075] Each of the first sidewall 172sa and the second sidewall 172sb of the upper contact structure 172 includes a plurality of sub-sidewalls. In the semiconductor device according to an exemplary embodiment of the present disclosure, the upper contact structure 172 may include one or more vertex portions 172tp formed on the first sidewall 172sa of the upper contact structure 172 and one or more vertex portions 172tp formed on the second sidewall 172sb of the upper contact structure 172.

[0076] In the semiconductor device according to an exemplary embodiment of the present disclosure, the upper contact structure 172 may include an even number of vertex portions 172tp.

[0077] The height h11 of the first sub-sidewall 172saa may be equal to the height h12 of the second sub-sidewall 172sba located at a position corresponding to the first sub-sidewall 172saa. Accordingly, the depth (h11 + h21 + h31) from the upper surface 172us of the upper contact structure 172 to the lowermost vertex portion 172tp among the vertex portions 172tp formed on the first sidewall 172sa of the upper contact structure 172 may be equal to the depth (h12 + h22 + h32) from the upper surface 172us of the upper contact structure 172 to the lowermost vertex portion 172tp among the vertex portions 172tp formed on the second sidewall 172sb of the upper contact structure 172.

[0078] The height h52 from the upper surface of the first active pattern AF1 to the upper surface of the first gate electrode 120 may be equal to or greater than the height h51 from the upper surface of the first active pattern AF1 to the upper surface of the lower contact structure 171. Accordingly, even when the first gate contact 180 is disposed in the first active region RX1, a short circuit between the first gate contact 180 and the first source / drain contact 170 can be prevented.

[0079] The contact insulating liner 175 may extend along a first sidewall 172sa of the upper contact structure 172 and a second sidewall 172sb of the upper contact structure 172. The contact insulating liner 175 may extend along first sub-sidewalls 172saa, 172sab, 172sac, and 172sad and second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd.

[0080] In the semiconductor device according to an exemplary embodiment of the present disclosure, the contact insulating liner 175 may not be formed on the upper surface 171us of the lower contact structure 171. The contact insulating liner 175 may not extend along the upper surface 171us of the lower contact structure 171.

[0081] The contact insulating liner 175 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), aluminum oxide (AlO), and aluminum nitride (AIN). The contact insulating liner 175 may have a thickness of (but is not limited to) 1 nm to 6 nm.

[0082] In Figure 3 , portions of the contact insulating liner 175 that extend along the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad are connected to each other, and portions of the contact insulating liner 175 that extend along the second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd are connected to each other. However, the present invention is not limited to this. For example, portions of the contact insulating liner 175 that extend along the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad and the second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd may also be separated at the vertex portion 172tp.

[0083] The thicknesses t11, t21, t31, and t41 of the portions of the contact insulating gasket 175 respectively disposed on the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad may be equal. The thicknesses t12, t22, t32, and t42 of the portions of the contact insulating gasket 175 respectively disposed on the second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd may be equal. For example, the thickness t11 of the contact insulating gasket 175 on the (1_1) sub-sidewall 172saa may be equal to the thickness t21 of the contact insulating gasket 175 on the (1_2) sub-sidewall 172sab. Here, the thickness of the contact insulating gasket 175 may be the thickness at the innermost part of the concave surface of the upper contact structure 172.

[0084] The first gate contact 180 may be disposed on the first gate electrode 120. The first gate contact 180 may penetrate the first capping pattern 145 and may be connected to the first gate electrode 120. The first gate contact 180 may be partially surrounded by the first capping pattern 145.

[0085] The first gate contact 180 may include a first gate contact barrier layer 180a and a first gate contact filling layer 180b disposed on the first gate contact barrier layer 180a. For example, the first gate contact filling layer 180b may include cobalt (Co).

[0086] The first interlayer insulating film 190 may be formed on the field insulating layer 105. The first interlayer insulating film 190 may at least partially surround the first source / drain contact 170 and the first gate contact 180. The first interlayer insulating film 190 does not cover the upper surface 172us of the first source / drain contact 170 and the upper surface of the first gate contact 180. The first interlayer insulating film 190 may expose the upper surface 172us of the first source / drain contact 170 and the upper surface of the first gate contact 180. The first interlayer insulating film 190 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material may include (but is not limited to) at least one of, for example, tetraethyl orthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), tetramethoxysilane (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butylbutoxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), silicone silicate (TOSZ), fluorosilicate glass (FSG), polyimide nanofoam such as polypropylene oxide, carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, and combinations thereof.

[0087] The first etch stop layer 191 may be disposed on the first interlayer insulating film 190. The first etch stop layer 191 may include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxycarbide (SiOC).

[0088] The second interlayer insulating film 192 may be disposed on the first etch stop layer 191. The second interlayer insulating film 192 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0089] The wiring structure 210 may be disposed in the first etch stop layer 191 and the second interlayer insulating film 192. The wiring structure 210 may be electrically connected to, for example, the first source / drain contact 170, the first gate contact 180, the second source / drain contact 270, and the second gate contact 280.

[0090] The wiring structure 210 may include a via 211 and a wiring pattern 212. The wiring structure 210 may include a wiring barrier layer 210a and a wiring filling layer 210b. Each of the via 211 and the wiring pattern 212 may include a wiring barrier layer 210a and a wiring filling layer 210b. The wiring barrier layer 210a may include at least one of, for example, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). The wiring filling layer 210b may include at least one of, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0091] Although the wiring pattern 212 extends in the first direction X1 in Figures 2 to 6 , this is only an example for easy description, and the present invention is not limited to this example.

[0092] Figures 7 to 10 Semiconductor devices according to exemplary embodiments of the present disclosure are respectively shown. For easy description, differences from the semiconductor device described above with reference to Figures 1 to 6 will be mainly described. It will be understood that certain details are not described with respect to Figures 7 to 10 what is shown, and these omitted details may be at least similar to the details of the corresponding elements described above with respect to Figures 1 to 6 .

[0093] Referring to Figure 7 , in a semiconductor device according to an exemplary embodiment of the present disclosure, the contact insulating liner 175 may include a first portion 175a, a second portion 175b, and a third portion 175c.

[0094] The first portion 175a of the contact insulating gasket 175 can extend along the first sidewall 172sa of the upper contact structure 172 and the second sidewall 172sb of the upper contact structure 172. The second portion 175b of the contact insulating gasket 175 can extend along the upper surface 171us of the lower contact structure 171. One end of the second portion 175b of the contact insulating gasket 175 can be connected to the first portion 175a of the contact insulating gasket 175. The third portion 175c of the contact insulating gasket 175 can be connected to the other end of the second portion 175b of the contact insulating gasket 175. The third portion 175c of the contact insulating gasket 175 can extend in a direction away from the lower contact structure 171 from the other end of the second portion 175b of the contact insulating gasket 175. The third portion 175c of the contact insulating gasket 175 can extend to the upper surface of the first interlayer insulating film 190.

[0095] A portion of the first interlayer insulating film 190 can fill the recess defined by the contact insulating gasket 175. The first interlayer insulating film 190 filling the recess defined by the contact insulating gasket 175 can be formed in a manufacturing process different from that of the first interlayer insulating film 190 covering the first sidewall 171sa of the lower contact structure 171 and the second sidewall 171sb of the lower contact structure 171.

[0096] Referring to Figure 3 and Figure 8 In the semiconductor device according to an exemplary embodiment of the present disclosure, the contact insulating gasket 175 can extend along a part of the first sidewall 172sa of the upper contact structure 172 and a part of the second sidewall 172sb of the upper contact structure 172.

[0097] The contact insulating gasket 175 can be disposed on the (1_1) sub-sidewall 172saa, the (1_2) sub-sidewall 172sab, the (1_3) sub-sidewall 172sac, the (2_1) sub-sidewall 172sba, the (2_2) sub-sidewall 172sbb, and the (2_3) sub-sidewall 172sbc. However, the contact insulating gasket 175 is not disposed on the (1_4) sub-sidewall 172sad and the (2_4) sub-sidewall 172sbd connected to the upper surface 171us of the lower contact structure 171.

[0098] Referring to Figure 9 In the semiconductor device according to an exemplary embodiment of the present disclosure, the contact insulating gasket 175 (see Figure 2 ) is not formed on the first sidewall 172sa of the upper contact structure 172 and the second sidewall 172sb of the upper contact structure 172.

[0099] The first sidewall 172sa of the upper contact structure 172 and the second sidewall 172sb of the upper contact structure 172 may contact the first interlayer insulating film 190. Oxides of materials included in the first contact filling layer 170b may be formed along the boundary between the first interlayer insulating film 190 and the upper contact structure 172, but the present invention is not limited to this case.

[0100] Referring Figure 3 and Figure 10 , in a semiconductor device according to an exemplary embodiment of the present disclosure, thicknesses t11, t21, t31, and t41 of portions of the contact insulating liner 175 respectively provided on the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad may be different from each other.

[0101] For example, the thickness t21 of the contact insulating liner 175 provided on the (1_2) sub-sidewall 172sab may be less than the thickness t11 of the contact insulating liner 175 provided on the (1_1) sub-sidewall 172saa and greater than the thickness t31 of the contact insulating liner 175 provided on the (1_3) sub-sidewall 172sac. The thickness t31 of the contact insulating liner 175 provided on the (1_3) sub-sidewall 172sac may be greater than the thickness t41 of the contact insulating liner 175 provided on the (1_4) sub-sidewall 172sad.

[0102] Different from the drawings, for example, the thickness t21 of the contact insulating liner 175 provided on the (1_2) sub-sidewall 172sab may be equal to the thickness t11 of the contact insulating liner 175 provided on the (1_1) sub-sidewall 172saa. For example, the thickness t21 of the contact insulating liner 175 provided on the (1_2) sub-sidewall 172sab and the thickness t31 of the contact insulating liner 175 provided on the (1_3) sub-sidewall 172sac may be equal to the thickness t11 of the contact insulating liner 175 provided on the (1_1) sub-sidewall 172saa.

[0103] The thickness of the contact insulating liner 175 provided on the second sidewall 172sb of the upper contact structure 172 may also be similar to the above thicknesses.

[0104] Figures 11 to 13 Semiconductor devices according to exemplary embodiments of the present disclosure are respectively shown. For ease of description, differences from the semiconductor device described above with reference Figures 1 to 6 will be mainly described. It will be understood that to some extent certain details are not described with respect to Figures 11 to 13 what is shown, and these omitted details may be at least similar to the details of the corresponding elements described above with respect to Figures 1 to 6 what is described.

[0105] Referring Figure 3 andFigure 11 In a semiconductor device according to an exemplary embodiment of the present disclosure, the height h11 of the (1_1) sub-sidewall 172saa, the height h21 of the (1_2) sub-sidewall 172sab, the height h31 of the (1_3) sub-sidewall 172sac, and the height h41 of the (1_4) sub-sidewall 172sad may not be equal.

[0106] The height h11 of the (1_1) sub-sidewall 172saa is equal to the height h31 of the (1_3) sub-sidewall 172sac, the height h21 of the (1_2) sub-sidewall 172sab is equal to the height h41 of the (1_4) sub-sidewall 172sad, and the height h31 of the (1_3) sub-sidewall 172sac is different from the height h41 of the (1_4) sub-sidewall 172sad. However, this is only an example for easy description, and the present invention is not limited to this example.

[0107] The heights of the second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd may also be similar to the above heights. The heights of the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad may be equal to the heights of the second sub-sidewalls 172sba, 172sbb, 172sbc, and 172sbd located at positions corresponding to the first sub-sidewalls 172saa, 172sab, 172sac, and 172sad, respectively.

[0108] Referring to Figure 3 and Figure 12 In a semiconductor device according to an exemplary embodiment of the present disclosure, a first distance W1 from the center line 172CL of the upper contact structure 172 to the first sidewall 171sa of the lower contact structure 171 is greater than a second distance W2 from the center line 172CL of the upper contact structure 172 to the second sidewall 171sb of the lower contact structure 171.

[0109] For example, the height h11 of the (1_1) sub-sidewall 172saa may be greater than the height h12 of the (2_1) sub-sidewall 172sba located at a position corresponding to the (1_1) sub-sidewall 172saa. Accordingly, the height h1 of the first sidewall 172sa of the upper contact structure 172 may be greater than the height h2 of the second sidewall 172sb of the upper contact structure 172.

[0110] When the upper contact structure 172 is concentrated on one side of the second sidewall 171sb of the lower contact structure 171, the number of sub-sidewalls included in the first sidewall 172sa of the upper contact structure 172 may be different from the number of sub-sidewalls included in the second sidewall 172sb of the upper contact structure 172.

[0111] Referring to Figure 3 and Figure 13, in a semiconductor device according to an exemplary embodiment of the present disclosure, the first sidewall 172sa of the upper contact structure 172 has a concavo-convex structure, but the second sidewall 172sb of the upper contact structure 172 does not have a concavo-convex structure.

[0112] The first sidewall 172sa of the upper contact structure 172 may include a plurality of first sub-sidewalls 172saa, 172sab, 172sac, and 172sad. However, the second sidewall 172sb of the upper contact structure 172 does not include a plurality of sub-sidewalls having concave surfaces.

[0113] For example, a vertex portion 172tp may be formed on the first sidewall 172sa of the upper contact structure 172. The vertex portion 172tp is not formed on the second sidewall 172sb of the upper contact structure 172. The upper contact structure 172 may include one or more vertex portions 172tp formed on the first sidewall 172sa of the upper contact structure 172. The upper contact structure 172 does not include a vertex portion 172tp formed on the second sidewall 172sb of the upper contact structure 172.

[0114] The contact insulating liner 175 may extend along the first sidewall 172sa of the upper contact structure 172. The contact insulating liner 175 is not formed on the second sidewall 172sb of the upper contact structure 172.

[0115] The first sidewall 172sa of the upper contact structure 172 may be connected to the first sidewall 171sa of the lower contact structure 171 through the upper surface 171us of the lower contact structure 171. The second sidewall 172sb of the upper contact structure 172 may be directly connected to the second sidewall 171sb of the lower contact structure 171.

[0116] For example, in a cross-sectional view taken in the second direction Y1, the first source / drain contact 170 may be substantially "L"-shaped.

[0117] Figures 14 to 18 Semiconductor devices according to exemplary embodiments of the present disclosure are shown respectively. For ease of description, the differences from the semiconductor devices described above with reference to Figures 1 to 6 will be mainly described. It will be understood that to a certain extent, certain details not described with respect to Figures 14 to 18 the illustration may be at least similar to the details of the corresponding elements described above with respect to Figures 1 to 6 the illustration.

[0118] Referring to Figure 14 , in a semiconductor device according to an exemplary embodiment of the present disclosure, a wiring barrier layer 210a may be disposed between a wiring filling layer 210b included in a via 211 and a wiring filling layer 210b included in a wiring pattern 212.

[0119] The through hole 211 can be formed by a manufacturing process different from that of the wiring pattern 212.

[0120] Referring to Figure 3 , Figure 15 and Figure 16 , in a semiconductor device according to an exemplary embodiment of the present disclosure, the upper surface 171us of the lower contact structure 171 can be bendable.

[0121] In Figure 15 , the highest part of each of the first side wall 171sa and the second side wall 171sb of the lower contact structure 171 can be at the same or lower height as the lowest part of the contact insulating pad 175.

[0122] In Figure 16 , the highest part of each of the first side wall 171sa and the second side wall 171sb of the lower contact structure 171 can be higher than the lowest part of the contact insulating pad 175.

[0123] Referring to Figure 17 , in a semiconductor device according to an exemplary embodiment of the present disclosure, the through hole 211 (see Figure 2 ) may not be formed between the wiring pattern 212 and the first source / drain contact 170.

[0124] For example, in a wiring stack structure formed in a back-end-of-line (BEOL) process, the wiring formed at the lowest level can be the wiring pattern 212 without a through hole.

[0125] Referring to Figure 18 , in a semiconductor device according to an exemplary embodiment of the present disclosure, an insertion contact line 215 can be disposed between the wiring structure 210 and the first source / drain contact 170. The insertion contact line 215 can also be disposed between the first gate contact 180 (see Figure 6 ) and the wiring structure 210.

[0126] The insertion contact line 215 can include a second contact barrier layer 215a and a second contact filling layer 215b disposed on the second contact barrier layer 215a.

[0127] Figure 19 And Figure 20 respectively illustrate semiconductor devices according to exemplary embodiments of the present disclosure. For ease of description, the differences from the semiconductor device described above with reference to Figures 1 to 6 will be mainly described. It will be understood that to a certain extent, certain details not described with respect to Figures 19 to 20 shown can be at least similar to the details of the corresponding elements described above with respect to Figures 1 to 6 .

[0128] Reference Figure 19 , according to an exemplary embodiment of the present disclosure, a semiconductor device may include a dummy protrusion pattern DPF formed in a field region FX. A deep trench DT (see Figure 2 ) is not formed in the field region FX.

[0129] The upper surface of the dummy protrusion pattern DPF is covered by a field insulating layer 105.

[0130] Reference Figure 20 , in a semiconductor device according to an exemplary embodiment of the present disclosure, a substrate 100 may include a base substrate 101 and a buried insulating layer 102 provided on the base substrate 101.

[0131] The base substrate 101 may include (but is not limited to including) a semiconductor material. The buried insulating layer 102 may be formed along the entire upper surface of the base substrate 101. The buried insulating layer 102 may include an insulating material.

[0132] Figures 21A to 22 Semiconductor devices according to exemplary embodiments of the present disclosure are respectively shown. For ease of description, the differences from the semiconductor device described above with reference to Figures 1 to 6 will be mainly described. It will be understood that to a certain extent, certain details not described with respect to Figures 21A to 22 shown may be at least similar to the details of the corresponding elements described above with respect to Figures 1 to 6 .

[0133] Reference Figure 1 and Figures 21A to 22 , in a semiconductor device according to an exemplary embodiment of the present disclosure, a first active pattern AF1 may include a lower pattern BF1 and an upper pattern UF1.

[0134] The lower pattern BF1 may extend in a first direction X1. The lower pattern BF1 may be fin-shaped. The upper pattern UF1 may be provided on the lower pattern BF1 and spaced apart from the lower pattern BF1. The upper patterns UF1 may be spaced apart from each other in the first direction X1. Although three upper patterns UF1 are shown, this is only an example for ease of description, and the present invention is not limited to this example. The upper pattern UF1 may be connected to a source / drain pattern 150. The upper pattern UF1 may be a channel pattern serving as a channel region of a transistor.

[0135] Each of the first gate electrode 120 and the second gate electrode 220 may at least partially surround the upper pattern UF1. The first gate electrode 120 and the second gate electrode 220 may be provided between the upper patterns UF1 spaced apart from each other in the thickness direction of the substrate 100. Each of the first gate insulating layer 130 and the second gate insulating layer 230 may at least partially surround the upper pattern UF1.

[0136] In Figure 21AIn [reference], the first gate spacer 140 may include a first inner spacer 141 and a first outer spacer 142. The second gate spacer 240 may include a second inner spacer 241 and a second outer spacer 242.

[0137] In Figure 21B [reference], different from Figure 21A [reference], the inner spacers are omitted from the first gate spacer 140 and the second gate spacer 240.

[0138] Figure 23 FIG. [reference] shows a semiconductor device according to an exemplary embodiment of the present disclosure. For ease of description, the differences from the semiconductor device described above with reference to Figure 21A and Figure 22 will be mainly described. It will be understood that to a certain extent, certain details not described with respect to Figure 23 shown may be at least similar to the details of the corresponding elements described above with respect to Figures 21A to 22 [reference].

[0139] Referring to Figure 23 [reference], a part of the first source / drain contact 170 may be inserted into the source / drain pattern 150.

[0140] A silicide layer 155 may be formed between the source / drain pattern 150 and the first source / drain contact 170 inserted into the source / drain pattern 150. The bottom surface of the first source / drain contact 170 may be located between the upper surface of the lowermost upper pattern UF1 among the plurality of upper patterns UF1 and the lower surface of the uppermost upper pattern UF1.

[0141] Figure 24 and Figure 25 are layout diagrams of a semiconductor device according to an exemplary embodiment of the present disclosure. For ease of description, the differences from the semiconductor device described above with reference to Figures 1 to 6 [reference] will be mainly described. It will be understood that to a certain extent, certain details not described with respect to Figure 24 and Figure 25 shown may be at least similar to the details of the corresponding elements described above with respect to Figures 1 to 6 [reference].

[0142] Referring to Figure 24 [reference], in a semiconductor device according to an exemplary embodiment of the present disclosure, the first gate contact 180 may be disposed above the first active region RX1 and the field region FX.

[0143] A part of the first gate contact 180 may be disposed at a position overlapping with the first active region RX1.

[0144] Referring to Figure 25, in a semiconductor according to an exemplary embodiment of the present disclosure, the entire first gate contact 180 may be disposed on the field region FX.

[0145] The entire first gate contact 180 may be disposed at a position overlapping with the field region FX.

[0146] Although in Figure 24 and Figure 25 the entire second gate contact 280 is disposed in the second active region RX2, the exemplary embodiment is not limited to this case. A part of the second gate contact 280 may also be disposed in the field region FX, or the entire second gate contact 280 may be disposed on the field region FX.

[0147] In Figure 1 , Figure 24 and Figure 25 , according to the positions of the first gate contact 180 and the second gate contact 280 respectively, the cross-sections (taken in the second direction Y1) of the first source / drain contact 170 and the second source / drain contact 270 may have a "T" shape or an "L" shape rotated 180 degrees. The "T" shape and the "L" shape can be formed by etching a certain part using the manufacturing method described later. Alternatively, the source / drain contact without a gate contact around it may not have an etched part, such as the Figure 27 shown pre-source / drain contact 170p.

[0148] Figures 26 to 35 is a diagram showing operations in a manufacturing method of a semiconductor device according to an exemplary embodiment of the present disclosure.

[0149] Referring to Figure 26 and Figure 27 , a source / drain pattern 150 connected to the first active pattern AF1 is formed on the substrate 100.

[0150] An interlayer insulating film 190 is formed on the field insulating layer 105 to cover the source / drain pattern 150. A pre-contact trench 170t may be formed in the interlayer insulating film 190.

[0151] The pre-contact trench 170t may expose at least a part of the source / drain pattern 150.

[0152] Next, a pre-source / drain contact 170p is formed to fill the pre-contact trench 170t. The pre-source / drain contact 170p may include a pre-contact barrier layer 170ap and a pre-contact filling layer 170bp disposed on the pre-contact barrier layer 170ap.

[0153] The pre-contact barrier layer 170ap may extend along the sidewalls of the pre-contact trench 170t and the source / drain pattern 150. The pre-contact fill layer 170bp may fill the pre-contact trench 170t in which the pre-contact barrier layer 170ap is formed.

[0154] A silicide layer 155 may be formed between the pre-source / drain contact 170p and the source / drain pattern 150. The silicide layer 155 may be formed before forming the pre-source / drain contact 170p, but the present invention is not limited to this case.

[0155] Referring to Figure 28 , a mask pattern 50 is formed on the pre-source / drain contact 170p.

[0156] The mask pattern 50 exposes a part of the pre-source / drain contact 170p.

[0157] Referring to Figure 29 , the pre-source / drain contact 170p is removed using the mask pattern 50 to form a first sub-recess 60r in the pre-source / drain contact 170p.

[0158] The bottom surface and the sidewalls of each first sub-recess 60r may be defined by the pre-source / drain contact 170p. The other sidewalls of each first sub-recess 60r may be defined by the first interlayer insulating film 190.

[0159] The first sub-recess 60r may be formed using, for example, a wet etching process.

[0160] The sidewalls of each first sub-recess 60r defined by the pre-source / drain contact 170p may be curved (e.g., recessed).

[0161] Referring to Figure 30 , a first sub-insulating liner 51 may be formed along the sidewalls and the bottom surface of the first sub-recess 60r.

[0162] The first sub-insulating liner 51 may also be formed on the upper surface of the mask pattern 50 and the upper surface of the first interlayer insulating film 190.

[0163] Referring to Figure 31 , a first insulating liner pattern 51p may be formed on the sidewalls of each first sub-recess 60r by anisotropically etching the first sub-insulating liner 51.

[0164] The bottom surface of the first sub-recess 60r is exposed during the anisotropic etching of the first sub-insulating liner 51.

[0165] The first insulating liner pattern 51p is formed on the sidewalls of each first sub-recess 60r defined by the pre-source / drain contact 170p.

[0166] Referring toFigure 32 Using the mask pattern 50 and the first insulating spacer pattern 51p, the pre-source / drain contact 170p is removed to form a second sub-recess 61r in the pre-source / drain contact 170p.

[0167] The bottom surface and the sidewalls of each second sub-recess 61r may be defined by the pre-source / drain contact 170p. The other sidewalls of each second sub-recess 61r may be defined by the first interlayer insulating film 190.

[0168] The second sub-recess 61r may be formed using, for example, a wet etching process.

[0169] Referring to Figure 33 a second sub-insulating spacer 52 may be formed along the sidewalls and the bottom surface of the second sub-recess 61r.

[0170] The second sub-insulating spacer 51 may also be formed on the upper surface of the mask pattern 50, the upper surface of the first interlayer insulating film 190, and the first insulating spacer pattern 51p.

[0171] Referring to Figure 34 a second insulating spacer pattern 52p may be formed on the sidewalls of each second sub-recess 61r by anisotropically etching the second sub-insulating spacer 52.

[0172] The second insulating spacer pattern 52p is formed on the sidewalls of each second sub-recess 61r defined by the pre-source / drain contact 170p.

[0173] The first insulating spacer pattern 51p may include a part of the second sub-insulating spacer 52.

[0174] The bottom surface of the second sub-recess 61r is exposed during the anisotropic etching of the second sub-insulating spacer 52.

[0175] Referring to Figure 35 a first source / drain contact 170 including an upper contact structure 172 and a lower contact structure 171 may be formed on the source / drain pattern 150 by repeating the process described above with respect to Figures 32 to 34 The first insulating spacer pattern 51p to the third insulating spacer pattern 53p may be formed on the sidewalls of the upper contact structure 172.

[0176] For example, if a first interlayer insulating film 190 covering the first insulating spacer pattern 51p to the third insulating spacer pattern 53p is further formed, the first insulating spacer pattern 51p to the third insulating spacer pattern 53p may become

[0177] the contact insulating spacer 175 of Figure 8

[0178] For example, the first interlayer insulating film 190 may be additionally formed after removing the first to third insulating spacer patterns 51p to 53p. In this case, the resulting structure may be as shown in Figure 9 as follows.

[0179] For example, if the first interlayer insulating film 190 is additionally formed after the manufacturing process described in Figure 33 and Figure 34 , then the contact insulating spacer 175 of Figure 2 can be formed.

[0180] For example, if the first interlayer insulating film 190 is additionally formed after the manufacturing process described in Figure 33 , then the contact insulating spacer 175 of Figure 7 can be formed.

[0181] Next, the mask pattern 50 is removed.

[0182] Upon concluding the detailed description, those skilled in the art will appreciate that numerous variations and modifications can be made to the exemplary embodiments discussed without materially departing from the principles of the present disclosure.

Claims

1. A semiconductor device, comprising: A substrate; A source / drain pattern disposed on the substrate; And A source / drain contact connected to the source / drain pattern, Wherein the source / drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure, Wherein the upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction, Wherein the first sidewall of the upper contact structure includes a plurality of first sub-sidewalls, Wherein each of the plurality of first sub-sidewalls has a concave surface with respect to the interior of the upper contact structure, and Wherein an acute angle is formed between the upper surface of the upper contact structure and the uppermost concave surface of the first sub-sidewall.

2. The semiconductor device according to claim 1, further comprising a contact insulating liner extending along the first sidewall of the upper contact structure.

3. The semiconductor device according to claim 2, wherein, The contact insulating liner does not extend along the upper surface of the lower contact structure.

4. The semiconductor device according to claim 1, wherein, The second sidewall of the upper contact structure includes a plurality of second sub-sidewalls, and each of the plurality of second sub-sidewalls has a concave surface.

5. The semiconductor device according to claim 4, wherein, There are an equal number of first sub-sidewalls and second sub-sidewalls.

6. The semiconductor device according to claim 1 further includes an interlayer insulating film that at least partially surrounds the upper contact structure and exposes an upper surface of the upper contact structure, wherein, The interlayer insulating film contacts the upper contact structure.

7. The semiconductor device according to claim 1, wherein, The upper contact structure includes one or more vertex portions, and each of the one or more vertex portions is defined where adjacent first sub-sidewalls meet.

8. The semiconductor device according to claim 1, wherein, The source / drain contact is L-shaped.

9. The semiconductor device according to claim 1, wherein, At the boundary between the lower contact structure and the upper contact structure, the width of the lower contact structure in the first direction is greater than the width of the upper contact structure in the first direction.

10. The semiconductor device according to claim 1, wherein, The source / drain contact has a T-shape rotated 180 degrees.

11. A semiconductor device, comprising: A substrate; A source / drain pattern disposed on the substrate; And A source / drain contact connected to the source / drain pattern, Wherein the source / drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure, Wherein the upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction, Wherein the first sidewall of the upper contact structure includes a plurality of first sub-sidewalls, Wherein each of the plurality of first sub-sidewalls has a concave surface, Wherein the semiconductor device further includes a contact insulating liner extending along the first sidewall of the upper contact structure, and Wherein the contact insulating liner includes a first portion extending along the upper surface of the lower contact structure, a second portion extending from the first end of the first portion of the contact insulating liner and along the first sidewall of the upper contact structure, and a third portion extending in a direction away from the lower contact structure from the second end of the first portion of the contact insulating liner.

12. A semiconductor device, comprising: A substrate; A source / drain pattern disposed on the substrate; And A source / drain contact connected to the source / drain pattern, Wherein the source / drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure, The upper contact structure includes a first side wall and a second side wall which are away from each other in the first direction. Wherein, the first side wall of the upper contact structure includes a plurality of first sub-side walls, wherein each of the plurality of first sub-side walls has a concave surface, The semiconductor device further comprises a contact insulating pad extending along a first sidewall of the upper contact structure, and The plurality of first sub-side walls include a first sub-lower side wall and a first sub-upper side wall disposed on the first sub-lower side wall, and the contact insulating pad is disposed on the first sub-upper side wall but not on the first sub-lower side wall.

Images