Electrostatic protection circuit

Abstract

An electrostatic protection circuit includes: a power supply terminal, an input pad terminal and a ground terminal, a third PMOS transistor, a third NMOS transistor, an internal circuit, and an electrostatic protection structure; the internal circuit has a first input terminal, a second input terminal, and a third input terminal, the first input terminal is connected to the drain of the third PMOS transistor, the second input terminal is connected to the input pad terminal, and the third input terminal is connected to the drain of the third NMOS transistor; the source of the third PMOS transistor is connected to the power supply terminal, and the gate of the third PMOS transistor is connected to the first control signal terminal; the source of the third NMOS transistor is connected to the ground terminal, and the gate of the third NMOS transistor is connected to the second control signal terminal; the electrostatic protection structure is located between the second input terminal and the power supply terminal of the internal circuit and between the second input terminal and the ground terminal. The electrostatic protection circuit of the present application has a good electrostatic protection function.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an electrostatic protection circuit. Background Art

[0002] When an object with static electricity comes into electrical contact with a component, static electricity will be transferred to the component or discharged through the component; or the component itself is charged and discharged through other objects. Both processes may damage the component, and the degree of damage is related to the mode of electrostatic discharge. In actual processes, there are many sources of static electricity and many forms of discharge. However, through the study of the main sources of static electricity and the actual electrostatic discharge process, it is believed that there are mainly three modes that cause damage to components: the electrostatic discharge mode of charged human body (Human Body Model, HBD), the discharge mode of charged machine (Machine Model, MM) and the discharge mode of charged device (Charged-Device Model, CDM).

[0003] In order to prevent electrostatic discharge from damaging the integrated circuit, corresponding electrostatic protection circuits (ESD protection circuits) need to be set up on the interface circuit of the integrated circuit. The electrostatic protection circuit should not only protect the electronic components from being damaged by electrostatic discharge, but also ensure that the system can continue to operate in the event of an electrostatic discharge event.

[0004] An existing electrostatic protection circuit, please refer to Figure 1 , including: an input pad terminal Input, a power supply terminal VDD, a ground terminal VSS, an internal circuit 100 and an electrostatic protection structure, wherein the internal circuit 100 includes a second NMOS transistor Mn2 and a second PMOS transistor Mp2, the drain of the second NMOS transistor Mn2 is connected to the drain of the second PMOS transistor Mp2, the gate of the second NMOS transistor Mn2 is connected to the gate of the second PMOS transistor Mp2 and is connected to the input pad terminal Input through a resistor Rin, the source of the second NMOS transistor Mn2 is connected to the ground terminal VSS, and the second PMOS transistor The source of the body transistor Mp2 is connected to the power supply terminal VDD, and the electrostatic protection structure includes a first NMOS transistor Mn1 and a first PMOS transistor Mp1. The drain of the first NMOS transistor Mn1 is connected to the drain of the first PMOS transistor Mp1 and is connected to the gate of the second PMOS transistor. The gate of the first NMOS transistor Mn1 is connected to the ground terminal VSS, the gate of the first PMOS transistor Mp1 is connected to the power supply terminal VDD, the source of the first NMOS transistor Mn1 is connected to the ground terminal VSS, and the source of the first PMOS transistor Mp1 is connected to the power supply terminal VDD.

[0005] The premise for the above-mentioned electrostatic protection structure to work normally is that the junction breakdown voltage of the electrostatic protection transistor (the first NMOS transistor Mn1 and the first PMOS transistor Mp1) is less than the gate oxide breakdown voltage of the internal circuit transistor (the second NMOS transistor Mn2 and the second PMOS transistor Mp2). When static electricity occurs, the electrostatic protection transistor is broken down before the internal circuit transistor, thereby releasing static electricity to protect the transistor in the internal circuit.

[0006] However, with the development of advanced processes, the thickness of the gate oxide layer in the internal circuit transistor has become thinner and thinner, and the breakdown voltage of the gate oxide layer in the internal circuit transistor has become smaller than the junction breakdown voltage of the electrostatic protection transistor, making the above-mentioned electrostatic protection circuit ineffective. A new electrostatic protection circuit is urgently needed. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a new electrostatic protection circuit.

[0008] The present invention provides an electrostatic protection circuit, comprising:

[0009] A power supply terminal, an input pad terminal and a ground terminal, a third PMOS transistor, a third NMOS transistor, an internal circuit, and an electrostatic protection structure;

[0010] The internal circuit has a first input terminal, a second input terminal, and a third input terminal, the first input terminal is connected to the drain of the third PMOS transistor, the second input terminal is connected to the input pad terminal, and the third input terminal is connected to the drain of the third NMOS transistor;

[0011] The source of the third PMOS transistor is connected to the power supply terminal, and the gate of the third PMOS transistor is connected to the first control signal terminal;

[0012] The source of the third NMOS transistor is connected to the ground terminal, and the gate of the third NMOS transistor is connected to the second control signal terminal;

[0013] The electrostatic protection structure is located between the second input terminal of the internal circuit and the power terminal and between the second input terminal of the internal circuit and the ground terminal.

[0014] Optionally, the electrostatic protection circuit also includes a control circuit, the control circuit includes a first control signal terminal and a second control signal terminal, the control circuit includes an RC circuit and an inverter circuit connected to the RC circuit, the RC circuit includes a capacitor and a first resistor connected in series, the inverter circuit includes a fourth PMOS transistor and a fourth NMOS transistor connected in series, the source of the fourth PMOS transistor is connected to the power supply terminal, the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are connected together as the second control signal terminal, the second control signal terminal is connected to the gate of the third NMOS transistor, the gate of the fourth PMOS transistor is connected together with the gate of the fourth NMOS transistor and is connected to the electrical connection point between the capacitor and the first resistor in the RC circuit as the first control signal terminal, the first control signal terminal is connected to the gate of the third PMOS transistor, and the drain of the fourth NMOS transistor is connected to the ground terminal.

[0015] Optionally, the electrostatic protection structure includes a first-level electrostatic protection structure, the first electrostatic protection structure includes a first diode and a second diode, the anode of the first diode is connected to the input pad end, the cathode of the first diode is connected to the power supply end, the anode of the second diode is connected to the ground end, and the cathode of the second diode is connected to the input pad end.

[0016] Optionally, the electrostatic protection structure also includes a second-level electrostatic protection structure, which includes a first PMOS transistor and a first NMOS transistor, the source of the first PMOS transistor is connected to the power supply terminal, the drain of the first PMOS transistor is connected together with the drain of the first NMOS transistor and connected to the input pad terminal, and the source of the first NMOS transistor is connected to the ground terminal.

[0017] Optionally, the second-level electrostatic protection structure further includes a second resistor, and the second resistor is located between an electrical connection point where the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected together and the input pad terminal.

[0018] Optionally, the second-level electrostatic protection structure also includes: a fifth PMOS transistor and a fifth NMOS transistor, the source of the fifth PMOS transistor is connected to the power supply terminal, the gate of the fifth PMOS transistor is connected to the ground terminal through a resistor, the drain of the fifth PMOS transistor is connected to the gate of the first PMOS transistor, the source of the fifth NMOS transistor is connected to the ground terminal, the gate of the fifth NMOS transistor is connected to the power supply terminal through a resistor, and the drain of the fifth NMOS transistor is connected to the gate of the first NMOS transistor.

[0019] Optionally, the internal circuit of the chip includes at least a second PMOS transistor and a second NMOS transistor connected in series, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second PMOS transistor is connected together with the gate of the second NMOS transistor as the second input terminal and connected to the drain of the first PMOS transistor Mp1, the source of the second PMOS transistor is connected to the drain of the third PMOS transistor as the first input terminal, and the source of the second NMOS transistor is connected to the drain of the third NMOS transistor as the third input terminal.

[0020] Optionally, the junction breakdown voltage of the first PMOS transistor is less than the sum of the junction breakdown voltage of the third PMOS transistor and the gate oxide breakdown voltage of the second PMOS transistor, and the junction breakdown voltage of the first NMOS transistor is less than the sum of the junction breakdown voltage of the third NMOS transistor and the gate oxide breakdown voltage of the second NMOS transistor.

[0021] Optionally, a junction breakdown voltage of the third PMOS transistor is the same as a junction breakdown voltage of the first PMOS transistor, and a junction breakdown voltage of the third NMOS transistor is the same as a junction breakdown voltage of the first NMOS transistor.

[0022] Optionally, the capacitance value of the capacitor is 5 femtofarads-8 picofarads, and the resistance value of the first resistor is 20 ohms-200 ohms.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] The electrostatic protection circuit of the present invention comprises: a power supply terminal, an input pad terminal and a ground terminal, a third PMOS transistor, a third NMOS transistor, an internal circuit, and an electrostatic protection structure; the internal circuit has a first input terminal, a second input terminal, and a third input terminal, the first input terminal is connected to the drain of the third PMOS transistor, the second input terminal is connected to the input pad terminal, and the third input terminal is connected to the drain of the third NMOS transistor; the source of the third PMOS transistor is connected to the power supply terminal, and the gate of the third PMOS transistor is connected to the first control signal terminal; the source of the third NMOS transistor is connected to the ground terminal, and the gate of the third NMOS transistor is connected to the second control signal terminal; the electrostatic protection structure is located between the second input terminal and the power supply terminal of the internal circuit and between the second input terminal and the ground terminal. The third PMOS transistor and the third NMOS transistor described in the present invention are transistors used to protect the internal circuit of the chip when electrostatic discharge occurs. The third PMOS transistor is connected in series with the second PMOS transistor in the internal circuit of the chip, and the third NMOS transistor is connected in series with the second NMOS transistor in the internal circuit of the chip. When designing, when the oxide layers of the second PMOS transistor and the second NMOS transistor become thinner and the breakdown voltage of their respective gate oxide layers becomes smaller, by adjusting the junction breakdown voltage of the third PMOS transistor and the third NMOS transistor, the junction breakdown voltage of the PMOS transistor in the electrostatic protection structure is less than the junction breakdown voltage of the third PMOS transistor Mp3 and the gate oxide breakdown voltage of the PMOS transistor in the internal circuit of the chip. The junction breakdown voltage of the NMOS transistor in the electrostatic protection structure is less than the sum of the junction breakdown voltage of the third NMOS transistor Mn3 and the gate oxide breakdown voltage of the NMOS transistor in the internal circuit of the chip, so that the electrostatic protection circuit of the present application has a good electrostatic protection function to meet the electrostatic protection needs brought about by the increasingly thin gate oxide layer of the internal circuit of the chip as the process is continuously developed, thereby preventing the breakdown voltage of the gate oxide layer in the internal circuit transistor from becoming less than the junction breakdown voltage of the electrostatic protection transistor, causing the electrostatic protection circuit to fail. Therefore, the electrostatic protection circuit of the present application has a good electrostatic protection function to meet the electrostatic protection needs brought about by the increasingly thin gate oxide layer of the internal circuit of the chip as the process is continuously developed.

[0025] Furthermore, the junction breakdown voltage of the third PMOS transistor is the same as the junction breakdown voltage of the first PMOS transistor, and the junction breakdown voltage of the third NMOS transistor is the same as the first NMOS transistor. Therefore, it is very easy and convenient to make the junction breakdown voltage of the first PMOS transistor smaller than the sum of the junction breakdown voltage of the third PMOS transistor and the gate oxide breakdown voltage of the second PMOS transistor, and the junction breakdown voltage of the first NMOS transistor smaller than the sum of the junction breakdown voltage of the third NMOS transistor and the gate oxide breakdown voltage of the second NMOS transistor, thereby improving the electrostatic protection capability of CDM (Charged Device Model).

[0026] Further, the control circuit includes a first control signal terminal and a second control signal terminal, and the control circuit includes an RC circuit and an inverter circuit connected to the RC circuit, the RC circuit includes a capacitor and a first resistor connected in series, the inverter circuit includes a fourth PMOS transistor and a fourth NMOS transistor connected in series, the source of the fourth PMOS transistor is connected to the power supply terminal, the drain of the fourth PMOS transistor and the source of the fourth NMOS transistor are connected together as the first control signal terminal, the first control signal terminal is connected to the gate of the third NMOS transistor, the gate of the fourth PMOS transistor is connected together with the gate of the fourth NMOS transistor and connected to the electrical connection point between the capacitor and the first resistor in the RC circuit as the second control signal terminal, the second control signal terminal is connected to the gate of the third PMOS transistor, the drain of the fourth NMOS transistor is connected to the ground terminal, and the control circuit can improve the electrostatic protection performance without affecting the normal operation of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural schematic diagram of an electrostatic protection circuit in the prior art;

[0028] Figure 2 Schematic diagram of the structure of the electrostatic protection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As mentioned in the background technology, with the development of advanced processes, the thickness of the gate oxide layer in the internal circuit transistor becomes thinner and thinner, and the breakdown voltage of the gate oxide layer in the internal circuit transistor becomes smaller than the junction breakdown voltage of the electrostatic protection transistor, making the above-mentioned electrostatic protection circuit ineffective.

[0030] Research has found that with the continuous development of advanced processes, the gate oxide layer has become thinner and thinner, and the breakdown voltage of the gate oxide layer of the transistor will decrease faster than the junction breakdown voltage of the transistor. As a result, the breakdown voltage of the gate oxide layer in the internal circuit transistor becomes smaller than the junction breakdown voltage of the electrostatic protection transistor, causing the electrostatic protection circuit to fail.

[0031] To this end, the present invention provides an electrostatic protection circuit, comprising: a power supply terminal, an input pad terminal and a ground terminal, a third PMOS transistor, a third NMOS transistor, an internal circuit, and an electrostatic protection structure; the internal circuit has a first input terminal, a second input terminal, and a third input terminal, the first input terminal is connected to the drain of the third PMOS transistor, the second input terminal is connected to the input pad terminal, and the third input terminal is connected to the drain of the third NMOS transistor; the source of the third PMOS transistor is connected to the power supply terminal, and the gate of the third PMOS transistor is connected to the first control signal terminal; the source of the third NMOS transistor is connected to the ground terminal, and the gate of the third NMOS transistor is connected to the second control signal terminal; the electrostatic protection structure is located between the second input terminal and the power supply terminal of the internal circuit and between the second input terminal and the ground terminal. The third PMOS transistor and the third NMOS transistor described in the present invention are transistors used to protect the internal circuit of the chip when electrostatic discharge occurs. The third PMOS transistor is connected in series with the second PMOS transistor in the internal circuit of the chip, and the third NMOS transistor is connected in series with the second NMOS transistor in the internal circuit of the chip. When designing, when the oxide layers of the second PMOS transistor and the second NMOS transistor become thinner and the breakdown voltage of their respective gate oxide layers becomes smaller, by adjusting the junction breakdown voltage of the third PMOS transistor and the third NMOS transistor, the junction breakdown voltage of the PMOS transistor in the electrostatic protection structure is less than the junction breakdown voltage of the third PMOS transistor Mp3 and the gate oxide breakdown voltage of the PMOS transistor in the internal circuit of the chip. The junction breakdown voltage of the NMOS transistor in the electrostatic protection structure is less than the sum of the junction breakdown voltage of the third NMOS transistor Mn3 and the gate oxide breakdown voltage of the NMOS transistor in the internal circuit of the chip, so that the electrostatic protection circuit of the present application has a good electrostatic protection function to meet the electrostatic protection needs brought about by the increasingly thin gate oxide layer of the internal circuit of the chip as the process is continuously developed, thereby preventing the breakdown voltage of the gate oxide layer in the internal circuit transistor from becoming less than the junction breakdown voltage of the electrostatic protection transistor, causing the electrostatic protection circuit to fail. Therefore, the electrostatic protection circuit of the present application has a good electrostatic protection function to meet the electrostatic protection needs brought about by the increasingly thin gate oxide layer of the internal circuit of the chip as the process is continuously developed.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0033] Figure 2 Schematic diagram of the structure of the electrostatic protection circuit according to an embodiment of the present invention.

[0034] refer to Figure 2 , the electrostatic protection circuit comprises:

[0035] A power supply terminal VDD, an input pad terminal Input and a ground terminal VSS, a third PMOS transistor Mp3, a third NMOS transistor Mn3, an internal circuit 100, and an electrostatic protection structure 103;

[0036] The internal circuit 100 has a first input terminal 1, a second input terminal 2, and a third input terminal 3, wherein the first input terminal 1 is connected to the drain of the third PMOS transistor Mp3, the second input terminal 2 is connected to the input pad terminal Input, and the third input terminal 3 is connected to the drain of the third NMOS transistor Mn3;

[0037] The source of the third PMOS transistor Mp3 is connected to the power supply terminal VDD, and the gate of the third PMOS transistor Mp3 is connected to the first control signal terminal 21;

[0038] The source of the third NMOS transistor Mn3 is connected to the ground terminal VSS, and the gate Mn3 of the third NMOS transistor is connected to the second control signal terminal 22;

[0039] The electrostatic protection structure 103 is located between the second input terminal 2 of the internal circuit 100 and the power terminal VDD and between the second input terminal 2 of the internal circuit and the ground terminal VSS.

[0040] In one embodiment, the electrostatic protection circuit also includes a control circuit 101, the control circuit 101 includes a first control signal terminal 21 and a second control signal terminal 22. Specifically, the control circuit 101 includes an RC circuit and an inverter circuit connected to the RC circuit, the RC circuit includes a capacitor C and a first resistor R connected in series, the inverter circuit includes a fourth PMOS transistor Mp4 and a fourth NMOS transistor Mn4 connected in series, the source of the fourth PMOS transistor Mp4 is connected to the power supply terminal VDD, the drain of the fourth PMOS transistor Mp4 and the drain of the fourth NMOS transistor Mn4 are connected together as the second control signal terminal 22, the first control signal terminal 22 is connected to the gate of the third NMOS transistor Mn3, the gate of the fourth PMOS transistor Mp4 is connected together with the gate of the fourth NMOS transistor Mn4 and is connected to the electrical connection point between the capacitor C and the first resistor R in the RC circuit as the first control signal terminal 21, the first control signal terminal 21 is connected to the gate of the third PMOS transistor Mp3, and the source of the fourth NMOS transistor Mn4 is connected to the ground terminal VSS. In one embodiment, the capacitance value of the capacitor C is 5 femtofarads to 8 picofarads, and the resistance value of the first resistor R is 20 ohms to 200 ohms.

[0041] In one embodiment, the electrostatic protection structure includes a first-level electrostatic protection structure, the first electrostatic protection structure includes a first diode Dp and a second diode Dn, the anode of the first diode Dp is connected to the input pad terminal Input, the cathode of the first diode Dp is connected to the power supply terminal VDD, the anode of the second diode Dn is connected to the ground terminal VSS, and the cathode of the second diode Dn is connected to the input pad terminal Input.

[0042] The electrostatic protection structure also includes a second-level electrostatic protection structure, which includes a first PMOS transistor Mp1 and a first NMOS transistor Mn1, the source of the first PMOS transistor Mp1 is connected to the power supply terminal VDD, the drain of the first PMOS transistor Mp1 is connected together with the drain of the first NMOS transistor Mn1 and is connected to the input pad terminal Input, and the source of the first NMOS transistor Mn1 is connected to the ground terminal VSS.

[0043] The second-level electrostatic protection structure also includes a fifth PMOS transistor Mp5 and a fifth NMOS transistor Mn5, the source of the fifth PMOS transistor Mp5 is connected to the power supply terminal VDD, the gate of the fifth PMOS transistor Mp5 is connected to the ground terminal VSS through a resistor R1, the drain of the fifth PMOS transistor Mp5 is connected to the gate of the first PMOS transistor Mp1, the source of the fifth NMOS transistor Mn5 is connected to the ground terminal VSS, the gate of the fifth NMOS transistor Mn5 is connected to the power supply terminal VDD through a resistor R2, and the drain of the fifth NMOS transistor Mn5 is connected to the gate of the first NMOS transistor Mn1.

[0044] In one embodiment, a second resistor Rin is provided between an electrical connection point where the drain of the first PMOS transistor Mp1 and the drain of the first NMOS transistor Mn1 are connected together and the input pad terminal Input.

[0045] The first-level electrostatic protection structure and the first electrostatic protection structure are designed for the electrostatic discharge mode of the charged human body (Human Body Model, HBD) and the discharge mode of the charged machine (Machine Model, MM). The first-level electrostatic protection structure considers four situations when performing electrostatic discharge: first, a positive electrostatic pulse is generated from the power supply terminal VDD to the input pad terminal Input, and the first diode Dp reversely breaks down to discharge the electrostatic charge; second, a positive electrostatic pulse is generated from the input pad terminal Input to the power supply terminal VDD, and the first diode Dp is forward-conducted to discharge the electrostatic charge; third, a positive electrostatic pulse is generated from the input pad terminal Input to the ground terminal VSS, and the second diode Dn reversely breaks down to discharge the electrostatic charge; fourth, a positive electrostatic pulse is generated from the ground terminal VSS to the input pad terminal Input, and the second diode Dn is forward-conducted to discharge the electrostatic charge. Note that for HBM and MM electrostatic discharge, the first-level electrostatic protection structure plays a major role, and the second-level electrostatic protection structure is further strengthened on the basis of the first-level electrostatic protection structure. The function of the second resistor Rin is to reduce the discharge current, limit the discharge current flowing through the first PMOS transistor Mp1 or the first NMOS transistor Mn1, and protect the first PMOS transistor Mp1 or the first NMOS transistor Mn1 from being burned out (in order to save area and speed up the conduction speed, the first PMOS transistor Mp1 and the first NMOS transistor Mn1 are small in size, so too much discharge current will burn out the first PMOS transistor Mp1 and the first NMOS transistor Mn1); the gate of the fifth PMOS transistor Mp5 is connected to the ground terminal VSS through a resistor R1, and the fifth PMOS transistor Mp5 is always kept in the on state, so that The gate potential of the first PMOS transistor Mp1 is pulled to the power supply terminal VDD voltage, thereby turning off the first PMOS transistor Mp1 (the first PMOS transistor Mp1 is turned off when working normally, and the PN junction from the drain to the source is used to discharge the electrostatic charge when ESD occurs); similarly, the gate of the fifth NMOS transistor Mn5 is connected to the power supply terminal VDD through a resistor R2, so that it always remains in the on state, thereby pulling the gate of the first NMOS transistor Mn1 to the ground terminal VSS potential, turning off the first NMOS transistor Mn1 (the first NMOS transistor Mn1 is turned off when working normally, and this structure is a typical GGNMOS, gate groundNMOS connection); the resistance values ​​of the resistors R1 and R2 are small, which can prevent the gates of the fifth PMOS transistor Mp5 and the fifth NMOS transistor Mn5 from being damaged by ESD.

[0046] The chip internal circuit 100 at least includes a second PMOS transistor Mp2 and a second NMOS transistor Mn2 connected in series, the drain of the second PMOS transistor Mp2 is connected to the drain of the second NMOS transistor Mn2, the gate of the second PMOS transistor Mp2 is connected to the gate of the second NMOS transistor Mn2 as a second input terminal 2 and connected to the drain of the first PMOS transistor Mp1; the source of the second PMOS transistor Mp2 is connected to the drain of the third PMOS transistor Mp3 as a first input terminal 1, and the source of the second NMOS transistor Mn2 is connected to the drain of the third NMOS transistor Mn3 as a third input terminal 3.

[0047] The third PMOS transistor Mp3 and the third NMOS transistor Mn3 are transistors used to protect the chip internal circuit 100 when electrostatic discharge occurs. The third PMOS transistor Mp3 is connected in series with the second PMOS transistor Mp2 in the chip internal circuit 100, and the third NMOS transistor Mn3 is connected in series with the second NMOS transistor Mn2 in the chip internal circuit 100. When designing, when the oxide layers of the second PMOS transistor Mp2 and the second NMOS transistor Mn2 become thinner and the breakdown voltage of their respective gate oxide layers becomes smaller, by adjusting the junction breakdown voltage of the third PMOS transistor Mp3 and the third NMOS transistor Mn3, it is easy to make the junction breakdown voltage of the PMOS transistor (specifically the first PMOS transistor Mp1) in the electrostatic protection structure smaller than that of the third PMOS transistor Mp3. The sum of the junction breakdown voltage of the MOS transistor Mp3 and the gate oxide breakdown voltage of the PMOS transistor (specifically the second PMOS transistor Mp2) in the internal circuit of the chip, and the junction breakdown voltage of the NMOS transistor (specifically the first NMOS transistor Mn1) in the electrostatic protection structure is less than the sum of the junction breakdown voltage of the third NMOS transistor Mn3 and the gate oxide breakdown voltage of the NMOS transistor (specifically the second NMOS transistor Mn2) in the internal circuit of the chip, thereby preventing the breakdown voltage of the gate oxide layer in the internal circuit transistor from becoming less than the junction breakdown voltage of the electrostatic protection transistor, causing the electrostatic protection circuit to fail. Therefore, the electrostatic protection circuit of the present application has a good electrostatic protection function to meet the electrostatic protection needs brought about by the increasingly thin gate oxide layer of the internal circuit of the chip as the process technology is continuously developed.

[0048] Specifically, when the circuit is working normally, the impedance of the capacitor C is much larger than the impedance of the first resistor R. According to the principle of resistor voltage division, the voltage at the first control signal terminal 21 is very small (close to VSS), so that the third PMOS transistor Mp3 is turned on. The voltage at the first control signal terminal 21 passes through the inverter, and the voltage at the second control signal terminal 22 is VDD, so that the third NMOS transistor Mn3 is turned on; during electrostatic discharge, the impedance of the capacitor C is very small (approximately equivalent to zero resistance). According to the principle of voltage division, the voltage at the first control signal terminal 21 is the power supply voltage VDD. After passing through the inverter, the second control signal terminal 22 is the ground voltage VSS. The control circuit 101 controls the third PMOS transistor Mp3 and the third NMOS transistor Mn3 to be turned off, so that the third PMOS transistor Mp3 and the third NMOS transistor Mn3 are both equivalent to a large resistor, which is equivalent to the second PMOS transistor Mp2 and the second NMOS transistor Mn2 in the chip internal circuit 100 are respectively connected in series with a large resistor, and the first PMOS transistor Mp 1 and the trigger voltage of the electrostatic release of the first NMOS transistor Mn1 do not change. Since the large series resistor can divide the voltage, a higher voltage is required for the gate oxide layer of the second PMOS transistor Mp2 and the second NMOS transistor Mn2 to be broken down. Therefore, from the connection point 2 (the connection point 2 is the connection point between the gate of the second PMOS transistor Mp2 and the gate of the second NMOS transistor Mn2) to the power supply terminal VDD, the first PMOS transistor Mp1 will be triggered to release the electrostatic first, and from the terminal 2 to the ground terminal VSS, the first NMOS transistor Mn1 will be triggered to release the electrostatic first. In addition, the electrostatic protection circuit of the present invention, the combination of the third PMOS transistor Mp3 and the third NMOS transistor Mn3 with the control circuit 101 and the aforementioned specific circuit connection method, when the internal circuit of the chip is working normally, the third PMOS transistor Mp3 and the third NMOS transistor Mn3 can be controlled to open in the control circuit 101, so that while achieving electrostatic protection, it will not affect the normal operation of the internal circuit of the chip.

[0049] In one embodiment, the junction breakdown voltage of the third PMOS transistor Mp3 is the same as the junction breakdown voltage of the first PMOS transistor Mp1, and the junction breakdown voltage of the third NMOS transistor Mn3 is the same as the junction breakdown voltage of the first NMOS transistor Mn1. Therefore, it is very easy and convenient to make the junction breakdown voltage of the first PMOS transistor Mp1 smaller than the sum of the junction breakdown voltage of the third PMOS transistor Mp3 and the gate oxide breakdown voltage of the second PMOS transistor Mp2, and the junction breakdown voltage of the first NMOS transistor Mn1 smaller than the sum of the junction breakdown voltage of the third NMOS transistor Mn3 and the gate oxide breakdown voltage of the second NMOS transistor Mn2, thereby improving the electrostatic protection capability of CDM (Charged Device Model).

[0050] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. An electrostatic protection circuit, characterized in that: include: A power supply terminal, an input pad terminal and a ground terminal, a third PMOS transistor, a third NMOS transistor, an internal circuit, and an electrostatic protection structure; The internal circuit has a first input terminal, a second input terminal, and a third input terminal, the first input terminal is connected to the drain of the third PMOS transistor, the second input terminal is connected to the input pad terminal, and the third input terminal is connected to the drain of the third NMOS transistor; The source of the third PMOS transistor is connected to the power supply terminal, and the gate of the third PMOS transistor is connected to the first control signal terminal; The source of the third NMOS transistor is connected to the ground terminal, and the gate of the third NMOS transistor is connected to the second control signal terminal; The electrostatic protection structure is located between the second input terminal of the internal circuit and the power supply terminal and between the second input terminal of the internal circuit and the ground terminal; The electrostatic protection circuit also includes a control circuit, which includes a first control signal terminal and a second control signal terminal. The control circuit includes an RC circuit and an inverter circuit connected to the RC circuit. The RC circuit includes a capacitor and a first resistor connected in series. The inverter circuit includes a fourth PMOS transistor and a fourth NMOS transistor connected in series. The source of the fourth PMOS transistor is connected to the power supply terminal, and the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are connected together as the second control signal terminal. The second control signal terminal is connected to the gate of the third NMOS transistor, and the gate of the fourth PMOS transistor is connected together with the gate of the fourth NMOS transistor and connected to the electrical connection point between the capacitor and the first resistor in the RC circuit as the first control signal terminal. The first control signal terminal is connected to the gate of the third PMOS transistor, and the source of the fourth NMOS transistor is connected to the ground terminal.

2. The electrostatic protection circuit according to claim 1, characterized in that: The electrostatic protection structure includes a first-level electrostatic protection structure, which includes a first diode and a second diode, the anode of the first diode is connected to the input pad end, the cathode of the first diode is connected to the power supply end, the anode of the second diode is connected to the ground end, and the cathode of the second diode is connected to the input pad end.

3. The electrostatic protection circuit according to claim 2, characterized in that: The electrostatic protection structure also includes a second-level electrostatic protection structure, which includes a first PMOS transistor and a first NMOS transistor, the source of the first PMOS transistor is connected to the power supply terminal, the drain of the first PMOS transistor is connected together with the drain of the first NMOS transistor and connected to the input pad terminal, and the source of the first NMOS transistor is connected to the ground terminal.

4. The electrostatic protection circuit according to claim 3, characterized in that: The second-level electrostatic protection structure further includes a second resistor, and the second resistor is located between an electrical connection point where the drain of the first PMOS transistor and the drain of the first NMOS transistor are connected together and the input pad terminal.

5. The electrostatic protection circuit according to claim 4, characterized in that: The second-level electrostatic protection structure also includes: a fifth PMOS transistor and a fifth NMOS transistor, the source of the fifth PMOS transistor is connected to the power supply end, the gate of the fifth PMOS transistor is connected to the ground end through a resistor, the drain of the fifth PMOS transistor is connected to the gate of the first PMOS transistor, the source of the fifth NMOS transistor is connected to the ground end, the gate of the fifth NMOS transistor is connected to the power supply end through a resistor, and the drain of the fifth NMOS transistor is connected to the gate of the first NMOS transistor.

6. The electrostatic protection circuit according to claim 3, characterized in that: The internal circuit at least includes a second PMOS transistor and a second NMOS transistor connected in series, the drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, the gate of the second PMOS transistor is connected together with the gate of the second NMOS transistor as the second input terminal and connected to the drain of the first PMOS transistor, the source of the second PMOS transistor is connected to the drain of the third PMOS transistor as the first input terminal, and the source of the second NMOS transistor is connected to the drain of the third NMOS transistor as the third input terminal.

7. The electrostatic protection circuit according to claim 6, characterized in that: The junction breakdown voltage of the first PMOS transistor is less than the sum of the junction breakdown voltage of the third PMOS transistor and the gate oxide breakdown voltage of the second PMOS transistor, and the junction breakdown voltage of the first NMOS transistor is less than the sum of the junction breakdown voltage of the third NMOS transistor and the gate oxide breakdown voltage of the second NMOS transistor.

8. The electrostatic protection circuit according to claim 7, characterized in that: The junction breakdown voltage of the third PMOS transistor is the same as that of the first PMOS transistor, and the junction breakdown voltage of the third NMOS transistor is the same as that of the first NMOS transistor.

9. The electrostatic protection circuit according to claim 1, characterized in that: The capacitance value of the capacitor is 5 femtofarads to 8 picofarads, and the resistance value of the first resistor is 20 ohms to 200 ohms.

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