Dual-clock architecture for low duty cycle DC-DC converters

Abstract

Embodiments of this disclosure relate to a dual-clock architecture for a small duty cycle DC-DC converter. A DC-DC converter includes: a clock generation circuit that generates a first clock signal and a second clock signal out of phase; and a control signal generator that generates a switching control signal at an edge of the second clock signal based on a comparison of an error voltage and a summed voltage. A boost circuit charges an energy storage component during an on-phase period and discharges the energy storage component during an off-phase period to generate an output voltage. The on-phase and off-phase periods are set according to the switching control signal. The summed voltage generation circuit generates a ramp voltage in response to an edge of the first clock signal and generates a summed voltage at an edge of the second clock signal. This summed voltage represents the ramp voltage plus a voltage representing the current flowing in the energy storage component during the on-phase period.

Description

Technical Field

[0001] This application relates to the field of DC-DC converters, and more particularly to DC-DC converters that utilize a dual-clock architecture to enhance operation at low duty cycles. Background Technology

[0002] DC-DC converters (such as boost converters) are commonly used in various operations to generate the required rail voltage. Known sample DC-DC converters are... Figure 1A The boost converter 10 shown includes an inductor coupled between an input voltage source 11 and the anode of a diode D1, wherein the cathode of diode D1 is coupled to a load 12. A switch S is coupled between the inductor and the anode of diode D1 and selectively (under the control of a control circuit device 13) couples the inductor to ground.

[0003] In operation, the control circuit device 13 generates a pulse width modulation (PWM) control signal PWM_CTRL to drive the actuation / deactivation of switch S, and the resulting pulse width modulation period extends from the falling edge of clock signal CLK to the falling edge (in Figure 1B The timing is shown in the figure. Specifically, on the falling edge of the clock signal CLK, the “on” period of the pulse width modulation cycle during which the switch S is actuated begins and lasts for Ton, and at the end of the “on” period, the “off” period of the pulse width modulation cycle during which the switch S is deactivated begins and lasts for Toff, where time Toff ends at the next falling edge of the clock signal CLK.

[0004] At the beginning of Ton, switch S is closed, and current flows from Vsupply through inductor L to ground, resulting in inductor L storing energy in the form of a magnetic field. When Ton ends and Toff begins, switch S is opened, disconnecting the right terminal of inductor L from ground. As a result, the energy stored in inductor L begins to discharge, with current flowing into diode D1, forming a voltage Vload across load 12 (and charging the load capacitor if load 12 is capacitive). Due to the energy released from inductor L in the form of current, the current flowing into the load is greater than the current flowing into the load solely from input voltage source 11, and therefore Vload is larger than Vload in other cases (and, therefore, "boosted"). Control circuit 13 senses Vload, compares Vload to a reference, and changes the duty cycle of PWM_CTRL (e.g., changes the length of Ton relative to Toff) based on the difference between them to drive Vload to equal the reference.

[0005] In some applications where DC-DC converters are used, such as when powering organic light-emitting diode (OLED) based display panels, a low duty cycle of PWM_CTRL is desired. However, if it is possible to Figure 1B As seen in the diagram, at the beginning of the on-time (Ton) period, the Iramp is ringing and not stable. Therefore, measurements taken during Ton may be incorrect because the outputs of components in control circuitry device 13 (such as the Iramp) have not yet settled. Since Ton decreases as the PWM duty cycle decreases, there is a minimum length requirement for applying Ton so that measurements can be taken once the outputs of components in control circuitry device 13 (such as the Iramp) have settled. Otherwise, the measurements may be inaccurate, leading to incorrect generation of the PWM_CTRL and an incorrect PWM duty cycle, and the performance of the DC-DC converter 10 may not be as expected.

[0006] One known way to address this drawback is to use a DC-DC converter that utilizes pulse frequency modulation (PFM) instead of PWM, where the desired duty cycle is achieved through frequency modulation (i.e., by modulating the frequency of a clock signal). However, PFM-based DC-DC converters are clearly unsuitable for applications where a low duty cycle is desired and a fixed-frequency DC-DC converter is required.

[0007] Another way to address this drawback is to use a DC-DC converter that utilizes pulse skipping mode. In this operation, one or more pulses in PWM_CTRL are suppressed (i.e., skipped). However, this is not particularly useful for some applications, such as OLED displays, because pulse skipping introduces noise, which manifests as visible flicker in some displays.

[0008] Therefore, further development of PWM-based DC-DC converters is needed. Summary of the Invention

[0009] One claimed aspect disclosed herein is a DC-DC converter that boosts an input voltage to an output voltage. The DC-DC converter includes: a clock generation circuit that generates a first clock signal and a second clock signal that are out of phase with each other; a control signal generator that generates a switching control signal at an edge of the second clock signal based on a comparison of an error voltage and a summed voltage; and a boost circuit. It is configured to charge an energy storage component during an on-phase period and discharge the energy storage component during an off-phase period to generate the output voltage. The on-phase and off-phase periods are set according to the switching control signal. The summed voltage circuit is configured to: generate a ramp voltage; and generate a summed voltage at an edge of the second clock signal, the summed voltage representing the ramp voltage and a voltage representing a current signal carrying information about the storage component current flowing in the energy storage component during the on-phase period.

[0010] Another claimed aspect disclosed herein is a DC-DC converter that boosts an input voltage at the input to an output voltage at the output. This DC-DC converter includes: an energy storage component coupled between the input voltage and an intermediate node; and a control signal generator that provides a switching control signal based on a comparison of an error voltage and a summed voltage. The summed voltage varies according to a ramp voltage and a voltage representing a current signal carrying information about the storage component current flowing in the energy storage component during the on-phase. The error voltage represents the difference between the desired operating point and the output voltage. A boost circuit is configured to charge the energy storage component during the on-phase and discharge it during the off-phase to generate the output voltage. The on-phase and off-phase are set according to the switching control signal. A summed voltage circuit is configured to generate the summed voltage.

[0011] The summation voltage circuit device includes a ramp voltage generator configured to increase the ramp voltage in response to a falling edge of a first clock signal and decrease the ramp voltage in response to a rising edge of the first clock signal. The summation voltage circuit device also includes a first voltage-to-current converter circuit configured to convert the ramp voltage into a ramp current. The summation voltage circuit device further includes a second voltage-to-current converter circuit configured to convert the voltage at an intermediate node into a current signal carrying information about the storage component current in response to a falling edge of a second clock signal, the second clock signal being out of phase with the first clock signal. The summation voltage circuit device also includes a branch or element configured to generate a summation voltage based on the ramp current and the sum of the current signal carrying information about the storage component current. The ramp voltage increase caused by the ramp voltage generator in response to a falling edge of the first clock signal causes the ramp current to stabilize before the falling edge of the second clock signal. Attached Figure Description

[0012] Figure 1A This is a schematic diagram of a known boost converter.

[0013] Figure 1B It is shown Figure 1A The switching cycle of the boost converter is shown, and a graph of the resulting ramp current values ​​generated in the control circuit is also shown.

[0014] Figure 2 This is a graph showing the clock voltage and the resulting ramp current values ​​for the DC-DC converter disclosed herein.

[0015] Figure 3 This is a schematic block diagram of the DC-DC converter disclosed in this article, which utilizes... Figure 2 Dual clocks are used to enhance low duty cycle operation.

[0016] Figure 4 yes Figure 3 A schematic diagram of the ramp generator and peak current sensing circuit. Detailed Implementation

[0017] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those described in detail above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but should be given the widest scope consistent with the principles and features disclosed or suggested herein.

[0018] As will be described in detail in this article, refer to Figure 2This disclosure teaches the generation and utilization of a dedicated setup time frame Tset, during which components in the control circuitry of a PWM-controlled DC-DC converter stabilize, allowing correct measurements to be taken during the short on-time (Ton) period included in low duty cycle PWM operation. As will be described below, this is achieved using two clock signals CLK1 and CLK2, which have the same frequency and duty cycle but are out of phase by the time period Tact (illustratively, where the rising edge of CLK2 coincides with the falling edge of CLK1). However, in some cases, CLK1 and CLK2 may have the same frequency but different duty cycles.

[0019] Specifically, CLK1 is used to turn on and / or reset the components in the control circuitry, so that during CLK2, the components in the control circuitry can be set up and ready to operate during the on-time Ton of the next PWM cycle. Therefore, at the falling edge of CLK2 when Ton begins, the components in the control circuitry will not exhibit nonlinearity or other undesirable behavior. Thus, measurements can be performed accurately regardless of the duration of Ton, and the DC-DC converter can be correctly controlled.

[0020] First, refer to Figure 3 To describe the structure of the DC-DC converter 100 that implements the control scheme, and then refer to Figure 4 The structure of the ramp generator and peak current sensing circuit 105 of the DC-DC converter 100 is described, and then the operation of the DC-DC converter 100 and the ramp generator and peak current sensing circuit 105 is described.

[0021] Now go to Figure 3 The DC-DC converter 100 includes a clock generator 101, which generates a first clock signal and second clock signals CLK1 and CLK2. The first clock signal CLK1 and the second clock signal CLK2... Figure 2The signals are shown and described above, and are identical in frequency and duty cycle, but out of phase via Tact. Digital controller 102 receives a first clock signal and second clock signals CLK1 and CLK2, and generates a high-side turn-on signal HS_ON and a low-side turn-on signal LS_ON based on these clock signals and the COMP_PWM signal (described below), for transmission to driver 103. The ratio of the pulse width of LS_ON to the sum of the pulse widths of HS_ON and LS_ON sets the PWM duty cycle for DC-DC converter 100, where LS_ON sets the on-time Ton and HS_ON sets the off-time Toff.

[0022] Inductor L1 is coupled between input voltage generator 104 and node N1. n-channel transistor T1 has a drain coupled to node N1, a source coupled to ground, and a gate controlled by driver 103 (in response to the LS_ON signal). p-channel transistor T2 has a source coupled to load capacitor Cload, a drain coupled to node N1, and a gate controlled by driver 103 (in response to the HS_ON signal). Load capacitor Cload is coupled between the source of p-channel transistor T2 and ground. The output voltage Vout is generated based on the current supplied by p-channel transistor T2 to load capacitor Cload.

[0023] The ramp generator and peak current sensing circuit 105 operates based on a first clock signal and a second clock signal CLK1, CLK2. The ramp generator and peak current sensing circuit 105 has an input coupled to the drain of the n-channel transistor T1 to sense the drain-to-source voltage of the n-channel transistor T1. The ramp generator and peak current sensing circuit 105 sums the drain-to-source voltage of the n-channel transistor T1 with the ramp voltage Vramp to generate the output Vsum.

[0024] Error amplifier 107 has a non-inverting input coupled to a reference voltage Vref and an inverting input, and generates an error voltage Verr at its output. The inverting input is coupled to a feedback divider 106 to receive a scaled feedback voltage Vfb, which represents the output voltage Vout. The error voltage Verr represents the difference between the feedback voltage Vfb and the error voltage Verr. Comparator 108 has a non-inverting input coupled to receive the error voltage Verr and an inverting input coupled to receive a voltage Vsum from the ramp generator and peak current sensing circuit 105. Comparator 108 generates a COMP_PWM signal based on the comparison between Verr and Vsum, where COMP_PWM controls the PWM duty cycle of DC-DC converter 100.

[0025] Now go to Figure 4 The ramp generator and peak current sensing circuit 105 includes a ramp generator 200, which operates based on a first clock signal CLK1 to generate a voltage ramp Vramp. Specifically, the ramp generator 200 includes a capacitor C1, which is coupled to a current source 199 via a switch SW2 to receive a current I, and is also coupled to a bias voltage Voffset via the switch SW2. The bias voltage Voffset is lower than the supply voltage Vcc but higher than ground. The switch SW2 is controlled by the first clock signal CLK1.

[0026] Capacitor C1 is coupled between the non-inverting terminal of operational amplifier 201 and ground. The n-channel transistor T3 has a drain coupled to the input of current mirror 202, a source coupled to node N2, and a gate coupled to the output of operational amplifier 201. Resistor R1 is coupled between node N2 and ground. Therefore, operational amplifier 201, n-channel transistor T3, and resistor R1 form a voltage-to-current converter.

[0027] The current mirror 202 has an input coupled to the drain of the n-channel transistor T3 and an output coupled to node N3. The current mirror 202 includes a p-channel transistor T4, which has a source coupled to the supply voltage Vcc, a drain coupled to the drain of the n-channel transistor T3, and a gate coupled to both the drain of the p-channel transistor T4 and the gate of the p-channel transistor T5. The p-channel transistor T5 has a source coupled to the supply voltage Vcc, a drain coupled to node N3, and a gate coupled to the gate of the p-channel transistor T4.

[0028] Operational amplifier 204 has a non-inverting terminal selectively coupled to node N1 via switch SW1, which is actuated by the falling edge of the CLK2 signal and released at the end of Ton. n-channel transistor T8 has a drain coupled to the input of current mirror 203, a source coupled to node N4, and a gate coupled to the output of operational amplifier 204. Resistor R3 is coupled between node N4 and ground. Therefore, operational amplifier 204, n-channel transistor T8, and resistor R3 form a voltage-to-current converter.

[0029] The current mirror 203 has an input coupled to the drain of the n-channel transistor T8 and an output coupled to node N3. The current mirror 203 includes a p-channel transistor T7, which has a source coupled to the supply voltage Vcc, a drain coupled to the drain of the n-channel transistor T8, and a gate coupled to the drain of the p-channel transistor T7 and the gate of the p-channel transistor T6. The p-channel transistor T6 has a source coupled to the supply voltage Vcc, a drain coupled to node N3, and a gate coupled to the gate of the p-channel transistor T7. A resistor R2 is coupled between node N3 and ground, and the voltage Vsum at node N3 is generated by the sum of Iramp and Icoil.

[0030] The operation of the DC-DC converter 100 will now be described. At the beginning of Ton (see...) Figure 2 At the beginning of Ton and the end of Toff, HS_ON is asserted by digital controller 102, and LS_ON is deasserted by digital controller 102, causing driver 103 to turn on n-channel transistor T1, allowing current I1 to flow from Vin through n-channel transistor T1 to ground, through inductor L1, thereby storing energy in inductor L1. At the end of Ton and the beginning of Toff, HS_ON is asserted by digital controller 102, and LS_ON is deasserted by digital controller 102, causing driver 103 to turn off n-channel transistor T1 and turn on p-channel transistor T2. Since inductor L1 is now disconnected from ground, inductor L1 begins to channel energy into load capacitor Cload in the form of current through p-channel transistor T2, thereby increasing the magnitude of Vout compared to the case where current is supplied solely from input voltage source 104.

[0031] The generation of HS_ON and LS_ON by the digital controller 102 is now described. A ramp generator and peak current sensing circuit 105 generate a voltage Vsum, which represents the sum of the ramp voltage Vramp and the voltage at N1. As will be explained in detail below, unlike a single clock signal, Vsum is accurate and stable at the beginning of Ton due to the use of clock signals CLK1 and CLK2, thus eliminating the problems faced by the prior art at low duty cycles.

[0032] As a result of comparing the feedback voltage Vfb (representing Vout) with the reference voltage Vref, the error amplifier 107 generates an error voltage Verr. The comparator 108 compares the error voltage Verr with Vsum and generates a PWM control voltage COMP_PWM as a result of this comparison. The digital controller 102 generates HS_ON and LS_ON signals based on the PWM control voltage COMP_PWM, and based on these HS_ON and LS_ON signals, the driver 103 controls the operation of transistors T1 and T2 (and thus sets the voltage Vout).

[0033] Now, let's describe how Vsum is generated. Now, refer to... Figure 4 The operation of the ramp generator and peak current sensing circuit 105 shown is illustrated. The ramp generator 200 uses a first clock signal CLK1 to generate a voltage ramp Vramp. Specifically, when the first clock signal CLK1 is low, switch SW2 is coupled to current source 199, causing capacitor C1 to charge, thereby generating the ramp voltage Vramp. The minimum voltage of Vramp is Voffset, and the maximum voltage of Vramp depends on the length of time the first clock signal CLK1 is low.

[0034] Since operational amplifier 201, n-channel transistor T3, and resistor R1 are in a closed loop, operational amplifier 201 modulates its output to the gate of n-channel transistor T3 to force the voltage across R1 to equal Vramp, thereby drawing a ramp current Iramp from the input of current mirror 202. The ramp current Iramp is proportional to the voltage ramp Vramp. The ramp current Iramp is then mirrored to node N3 through current mirror 202.

[0035] As in Figure 2 As can be seen, at the first falling edge of the first clock signal CLK1, Iramp begins to rise (because Vramp begins to rise when capacitor C1 is charged by current I). Note that the operational amplifier 201 in a voltage-to-current configuration has a limited bandwidth, and therefore Iramp has a settling time, and under some conditions, it can stabilize until the falling edge of CLK2, which indicates the end of Tset. Therefore, at this falling edge of CLK2, the operational amplifier 201 has properly stabilized and correctly tracked Vramp.

[0036] It can also be seen that at the next rising edge of CLK1, switch SW2 couples capacitor C1 to the bias voltage Voffset, which causes capacitor C1 to discharge to the bias voltage Voffset, whereby Vramp discharges to the bias voltage Voffset, and the ramp current Iramp decreases accordingly.

[0037] As stated, the Iramp has stabilized at the first falling edge of CLK2. Therefore, the Iramp is ready for accurate processing. Thus, at the first falling edge of CLK2, switch SW1 closes, coupling the voltage at node N1 (representing the drain current I1 of the n-channel transistor T1) to the non-inverting terminal of operational amplifier 204. Operational amplifier 204 is in a closed loop with n-channel transistor T8 and resistor R3, and thus, by modulating the gate voltage of n-channel transistor T8, forces the voltage across R3 to equal the voltage at N1, thereby converting the voltage at N1 (which is the drain-to-source voltage of n-channel transistor T1) into a current Icoil. The current Icoil is mirrored to node N3 through current mirror 203, where it is summed with the Iramp, and the resulting voltage Vsum is read across resistor R2. Vsum can be accurately and appropriately generated at the beginning of the on-time Ton because switch SW2 is controlled by the first clock signal CLK1, but switch SW1 is actuated by the falling edge of the second clock signal CLK2 and released at the end of Ton.

[0038] If switches SW1 and SW2 are powered by the same clock signal (e.g., ... Figure 1B As shown in the CLK control, Vsum will be inaccurate at the beginning of Ton because the Iramp will not be stable. However, since switch SW2 is controlled by the first clock signal CLK1, but switch SW1 is actuated by the falling edge of the second clock signal CLK2 and released at the end of Ton, Ton can have any duration, and therefore, the low duty cycle operation of the DC-DC converter 100 can be improved compared to the prior art PWM design in which Vsum (and therefore COMP_PWM) will be inaccurate if Ton is less than a certain duration.

[0039] Although this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments may be contemplated without departing from the scope of this disclosure as disclosed herein. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. A DC-DC converter that boosts an input voltage to an output voltage, the DC-DC converter comprising: The clock generation circuit is configured to generate a first clock signal and a second clock signal that are out of phase with each other. A control signal generator is configured to generate a switch control signal at the edge of the second clock signal based on a comparison between the error voltage and the summed voltage. A boost circuit is configured to charge an energy storage component during an on-phase period and discharge the energy storage component during an off-phase period to generate the output voltage, wherein the on-phase and the off-phase are set according to the switch control signal; and The voltage summing circuit is configured as follows: A ramp voltage is generated based on the first clock signal; as well as From the falling edge of the second clock signal until the end of the turn-on phase, the summed voltage is generated to represent the sum of the ramp voltage and a voltage representing a current signal carrying information about the storage component current flowing in the energy storage component during the turn-on phase; however, from the beginning of the turn-off phase until the next falling edge of the second clock signal, the summed voltage is generated to represent only the ramp voltage, the turn-off phase beginning at the end of the turn-on phase.

2. The DC-DC converter of claim 1, wherein the summing voltage circuitry generates the ramp voltage at the edge of the first clock signal.

3. The DC-DC converter according to claim 1, wherein the first clock signal and the second clock signal are out of phase, such that the falling edge of the first clock signal and the rising edge of the second clock signal occur substantially simultaneously.

4. The DC-DC converter according to claim 1, wherein the first clock signal and the second clock signal have the same frequency and the same duty cycle.

5. The DC-DC converter according to claim 1, wherein the first clock signal and the second clock signal have the same frequency but different duty cycles.

6. A DC-DC converter that boosts an input voltage to an output voltage, the DC-DC converter comprising: A clock generation circuit is configured to generate a first clock signal and a second clock signal that are out of phase with each other; A control signal generator is configured to generate a switch control signal at the edge of the second clock signal based on a comparison between the error voltage and the summed voltage. A boost circuit is configured to charge an energy storage component during an on-phase period and discharge the energy storage component during an off-phase period to generate the output voltage, wherein the on-phase and the off-phase are set according to the switch control signal; and The voltage summing circuit is configured as follows: Generate ramp voltage; as well as The summed voltage is generated at the edge of the second clock signal. This summed voltage represents the sum of the ramp voltage and a voltage representing a current signal carrying information about the storage component current flowing in the energy storage component during the turn-on phase. The summing voltage circuit device includes a ramp voltage generator configured to cause the ramp voltage to rise at the edge of the first clock signal and to cause the ramp voltage to fall at the next edge of the first clock signal.

7. The DC-DC converter according to claim 6, wherein the first clock signal and the second clock signal are out of phase, such that the falling edge of the first clock signal and the rising edge of the second clock signal occur substantially simultaneously.

8. The DC-DC converter of claim 6, wherein the first clock signal and the second clock signal have the same frequency and the same duty cycle.

9. The DC-DC converter of claim 6, wherein the first clock signal and the second clock signal have the same frequency but different duty cycles.

10. A DC-DC converter that boosts an input voltage to an output voltage, the DC-DC converter comprising: A clock generation circuit is configured to generate a first clock signal and a second clock signal that are out of phase with each other; A control signal generator is configured to generate a switch control signal at the edge of the second clock signal based on a comparison between the error voltage and the summed voltage. A boost circuit is configured to charge an energy storage component during an on-phase period and discharge the energy storage component during an off-phase period to generate the output voltage, wherein the on-phase and the off-phase are set according to the switch control signal; and The voltage summing circuit is configured as follows: Generate ramp voltage; as well as The summed voltage is generated at the edge of the second clock signal. This summed voltage represents the sum of the ramp voltage and a voltage representing a current signal carrying information about the storage component current flowing in the energy storage component during the turn-on phase. The boost circuit device is coupled to the energy storage component at an intermediate node; and The summing voltage circuit device includes: A first voltage-to-current converter circuit is configured to convert the ramp voltage into a ramp current. A second voltage-to-current converter circuit is configured to convert the voltage at the intermediate node into the current signal in response to the edge of the second clock signal. A summing node is configured to sum the ramp current with the current signal to generate a summing current; and A branch or element is configured to convert the summing current into the summing voltage.

11. The DC-DC converter of claim 10, further comprising a first switch controlled by the second clock signal to selectively couple the intermediate node to the second voltage-to-current converter.

12. The DC-DC converter of claim 11, wherein the first switch closes in response to the edge of the second clock signal, and the first switch opens at the beginning of the turn-off phase.

13. The DC-DC converter of claim 10, further comprising: A first current mirror is configured to mirror the ramp current to the summing node; And a second current mirror, configured to mirror a copy of the current signal to the summing node.

14. The DC-DC converter of claim 10, wherein the first clock signal and the second clock signal are out of phase, such that the falling edge of the first clock signal and the rising edge of the second clock signal occur substantially simultaneously.

15. The DC-DC converter of claim 10, wherein the first clock signal and the second clock signal have the same frequency and the same duty cycle.

16. The DC-DC converter of claim 10, wherein the first clock signal and the second clock signal have the same frequency but different duty cycles.

17. A DC-DC converter that boosts an input voltage to an output voltage, the DC-DC converter comprising: A clock generation circuit is configured to generate a first clock signal and a second clock signal that are out of phase with each other; A control signal generator is configured to generate a switch control signal at the edge of the second clock signal based on a comparison between the error voltage and the summed voltage. A boost circuit is configured to charge an energy storage component during an on-phase period and discharge the energy storage component during an off-phase period to generate the output voltage, wherein the on-phase and the off-phase are set according to the switch control signal; and The voltage summing circuit is configured as follows: Generate ramp voltage; as well as The summed voltage is generated at the edge of the second clock signal. This summed voltage represents the sum of the ramp voltage and a voltage representing a current signal carrying information about the storage component current flowing in the energy storage component during the turn-on phase. The boost circuit device is coupled to the energy storage component at an intermediate node; The boost circuit device includes: The low-side transistor is configured to couple the intermediate node to ground during the turn-on phase; and A high-side transistor is configured to couple the intermediate node to the load during the turn-off phase to generate the output voltage. A digital controller is configured to: in response to the switch control signal, generate a low-side turn-on signal asserted during the turn-on phase and generate a high-side turn-on signal asserted during the turn-off phase, thereby setting the switch duty cycle; and A gate driver is configured to turn on the low-side transistor during the turn-on phase but turn off the low-side transistor during the turn-off phase, and is configured to turn on the high-side transistor during the turn-off phase but turn off the high-side transistor during the turn-on phase.

18. The DC-DC converter of claim 17, wherein the first clock signal and the second clock signal are out of phase, such that the falling edge of the first clock signal and the rising edge of the second clock signal occur substantially simultaneously.

19. The DC-DC converter of claim 17, wherein the first clock signal and the second clock signal have the same frequency and the same duty cycle.

20. The DC-DC converter of claim 17, wherein the first clock signal and the second clock signal have the same frequency but different duty cycles.

21. A DC-DC converter that boosts an input voltage at an input to an output voltage at an output, the DC-DC converter comprising: An energy storage component is coupled between the input voltage and the intermediate node; A control signal generator is configured to provide a switching control signal based on a comparison of an error voltage and a summed voltage, the summed voltage varying according to a ramp voltage and a voltage representing a current signal, the error voltage representing the difference between the desired operating point and the output voltage, the current signal carrying information about the storage component current flowing in the energy storage component during the turn-on phase; A boost circuit device is configured to charge the energy storage component during the on-phase and discharge the energy storage component during the off-phase to generate the output voltage, wherein the on-phase and the off-phase are set according to the switch control signal. as well as A summing voltage circuit device, configured to generate the summing voltage, the summing voltage circuit device comprising: The ramp voltage generator is configured to: In response to the falling edge of the first clock signal, the ramp voltage rises; and In response to the rising edge of the first clock signal, the ramp voltage is reduced; A first voltage-to-current converter circuit is configured to convert the ramp voltage into a ramp current. A second voltage-to-current converter circuit is configured to convert the voltage at the intermediate node into the current signal in response to the falling edge of a second clock signal, wherein the second clock signal is out of phase with the first clock signal; and A branch or element is configured to generate the summed voltage based on the sum of the ramp current and the current signal; The ramp voltage generator, in response to the falling edge of the first clock signal, causes the ramp voltage to rise, resulting in the ramp current stabilizing before the falling edge of the second clock signal.

22. The DC-DC converter of claim 21, wherein the ramp voltage generator comprises: A current source generates charging current; A capacitor, across which the ramp voltage is stored, is coupled to the first voltage-to-current converter; as well as The switch is configured to: In response to the falling edge of the first clock signal, the current source is coupled to the capacitor to charge the capacitor; as well as In response to the rising edge of the first clock signal, the capacitor is coupled to a discharge voltage to discharge the capacitor.

23. The DC-DC converter of claim 21, wherein the first voltage-to-current converter comprises: transistor; A resistor is coupled to the transistor and configured to generate a voltage indicating the drain current of the transistor; as well as The amplifier has a first input coupled to the ramp voltage, a second input coupled to the resistor, and an output coupled to the control terminal of the transistor.

24. The DC-DC converter of claim 21, wherein the second voltage-to-current converter comprises: transistor; A resistor is coupled to the transistor and configured to generate a voltage indicating the drain current of the transistor; as well as An amplifier having a first input, a second input coupled to the resistor, and an output coupled to the control terminal of the transistor, the first input being switched to the intermediate node in response to the falling edge of the second clock signal.

25. The DC-DC converter according to claim 21, The first voltage-to-current converter includes: First transistor; A first resistor is coupled to the first transistor and configured to generate a first voltage, the first voltage indicating the drain current of the first transistor; as well as A first amplifier has a first input coupled to the ramp voltage, a second input coupled to the first resistor, and an output coupled to the control terminal of the first transistor. The second voltage-to-current converter includes: Second transistor; A second resistor, coupled to the second transistor, is configured to generate a second voltage indicating the drain current of the second transistor; and The second amplifier has a first input, a second input coupled to the second resistor, and an output coupled to the control terminal of the second transistor, the first input being switched to the intermediate node in response to the falling edge of the second clock signal; Also includes: A first current mirror mirrors the drain current of the first transistor to the summing node; and The second current mirror mirrors the drain current of the second transistor onto the summing node; and The branch or element said therein includes a resistor coupled between the summing node and ground.

26. The DC-DC converter according to claim 21, The switching control signal mentioned above is a PWM control signal; The energy storage component mentioned above includes an inductor; and The boost circuit device includes: drive; A first n-channel transistor has a drain coupled to the intermediate node, a source coupled to ground, and a gate coupled to and controlled by the driver; and The first p-channel transistor has a source coupled to the output to generate the output voltage, a drain coupled to the intermediate node, and a gate coupled to the driver and controlled by the driver. The driver is configured to: turn on the first n-channel transistor and turn off the first p-channel transistor during the turn-on phase based on the PWM control signal, and is configured to: turn off the first n-channel transistor and turn on the first p-channel transistor during the turn-off phase.

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