A MCU architecture with scalable functionality

Abstract

A MCU architecture with expandable functions is divided into a core control module and a peripheral function module according to the different functions of the MCU chip, wherein the core control module includes a processor CPU, a system control module, an SRAM and a ROM; the peripheral function module includes an analog function unit, an I / O unit and a timer, and the core control module and the peripheral function module are connected in a dedicated connection method, and the dedicated connection method is: connecting a peripheral function dedicated chip through a communication interface to freely expand the function of the MCU, so that the peripheral function module can adapt to the corresponding function block according to user needs, so that when the user needs multi-functions, there is no need to redesign the chip, re-flow the chip, etc., so as to achieve the purpose of improving product diversity and saving costs.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a microcontroller architecture with expandable functions. Background Art

[0002] Microcontroller is also called MCU or μC for short, and some people call it single chip microcontroller. It combines ROM, SRAM, CPU and I / O in the same chip to provide different combination control for different application occasions. Figure 1 As shown in the figure, it is a single-chip architecture of MCU. Once the chip design is completed, the functions of the chip (see Figure 1 The light blue part (such as the type and number of serial ports, the number of timers, analog functions and the number of I / O ports) is fixed. However, with the continuous development of Internet of Things technology, it is found in practical applications that the MCU with the above single-chip architecture can no longer meet the existing user needs, and there are technical problems such as poor versatility and flexibility of the chip.

[0003] At present, if you want to change certain functions of an existing MCU, the common method is to spend a lot of manpower and material resources to redesign it, which will inevitably lead to an increase in the cost of chip design and manufacturing. Summary of the invention

[0004] The purpose of this application is to provide an MCU architecture with expandable functions to address the technical problem that the peripheral functions of the single-chip MCU architecture in the prior art are solidified, resulting in low versatility and flexibility of the MCU chip.

[0005] To achieve the above-mentioned purpose, the present invention adopts the following technical scheme: an MCU architecture with expandable functions, which is divided into a peripheral function module and a core control module according to the different functions of the MCU, wherein the peripheral function module includes an analog function unit, an I / O unit and a timer, and the core control module includes a processor CPU, a system control unit, an SRAM and a ROM; the core control module and the peripheral function module are connected using a dedicated connection method, and the dedicated connection method is: connecting a peripheral function dedicated chip through a communication interface to freely expand the functions of the MCU.

[0006] Preferably, the communication interface can automatically map the functions of the peripheral function dedicated chip to the address bus of the MCU, so that the CPU can access the peripheral function dedicated chip as easily as accessing the functions in the MCU. Furthermore, the communication interface is a serial peripheral interface SPI.

[0007] The beneficial effect of the present invention is that after the MCU design is completed, the peripheral functional parts can be flexibly added according to the needs, thereby improving the diversity of products and reducing the design risk. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 Existing conventional MCU single-chip architecture;

[0009] Figure 2 According to an MCU chip architecture with expandable functions shown in an embodiment of the present application;

[0010] Figure 3 According to the embodiment of the present application, the method of using an MCU chip to implement the expansion of a virtual address from 4 bits to 16 bits;

[0011] Figure 4 According to the structure of a CMS32X chip designed using an MCU architecture shown in an embodiment of the present application;

[0012] Figure 5 Another specific chip structure shown in an embodiment of the present application;

[0013] Figure 6 A communication method using an MCU chip is shown according to an embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Unless otherwise specified, the technical means used in the embodiments are conventional means well known to those skilled in the art.

[0015] In the description of the present invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0016] like Figure 1As shown, it is a conventional MCU single-chip architecture in the field. Based on the MCU single-chip architecture design, users can access all the modules inherent in the chip through peripheral pins, so that the functional modules solidified in the chip can work normally. Once the solidified functional module cannot adapt to the needs in the actual application scenario, only another functional chip that meets the needs can be added to meet the requirements. This is bound to have limitations in the application of diversified, high-tech, and diversified modern society. As smart Internet of Things is an inevitable trend of social development in the future, multi-periphery and multi-function will inevitably lead the new direction of chip design architecture. Therefore, in order to solve the technical problems of low versatility and flexibility in the existing MCU single-chip architecture, the present invention proposes an MCU chip design architecture with expandable functions.

[0017] like Figure 2 As shown, an MCU chip architecture with expandable functions shown in an embodiment of the present application is based on the existing MCU single chip for realizing the core control module, by adding a multi-functional wafer in the chip design, and the multi-functional wafer is used to realize peripheral functional modules adapted to different needs; the MCU realizes the transmission of data and instructions with the multi-functional wafer through a prescribed communication method. In practical applications, the multifunctional wafer can select a function-rich wafer to realize the expansion of the existing 4-bit MCU chip to a 16-bit MCU chip function. Specifically, the communication pin of the multifunctional wafer and the communication pin of the MCU can be connected internally, and then the remaining pins of the MCU and the multifunctional wafer are connected to the periphery of the chip, so as to realize the control of the MCU (core control module) through the pins outside the chip; then the MCU receives the peripheral instructions and data and determines whether the instructions are to control the MCU or the multifunctional wafer. If the MCU is to be accessed, the same instructions and data as those for controlling the single chip are executed inside the chip; if the instructions and data are to access the multifunctional wafer, the MCU will establish a communication channel with the multifunctional wafer through the specified communication method, and transmit the instructions and data to the multifunctional wafer based on the communication channel, so that the multifunctional wafer can control the periphery connected to its pins and output the required signals.

[0018] When the system starts working, the MCU and the communication module between the MCU and the multifunctional wafer are initialized to allow the MCU and the multifunctional wafer to reach a handshake signal. The multifunctional wafer that receives the handshake signal will process the expansion and mapping of the 4-bit address to the 16-bit MCU chip address, such as Figure 3As shown, the virtual address is then matched to the physical address of the MCU chip, and the MCU sends instructions to the corresponding virtual address to directly control the multifunctional wafer. The above steps are used to implement the initialization of the two wafers.

[0019] During operation, if the system wants to access the multifunctional wafer, the system will control the communication module in the MCU, and then send the control instructions and data to the multifunctional wafer through the communication module. After receiving the instructions, the multifunctional wafer controls its internal functional modules through the corresponding instructions and data, and drives the external devices corresponding to the MCU chip, thereby realizing various peripheral functions. Compared with the conventional MCU single-chip working mode, the above working mode is different only in that the working mode provided by this application needs to initialize the communication module between the two wafers, and then turn on the enable of the multifunctional wafer when accessing the multifunctional wafer, thereby realizing the function of the extended MCU chip based on the communication module.

[0020] The key to this design is that the multifunctional wafer contains multiple functional modules, and users can allocate the modules they need according to their own needs, so that one chip can be used normally by users with different purposes; when users need multi-functions, there is no need to redesign the chip, re-flow the chip, etc., thus saving considerable costs.

[0021] like Figure 4 As shown, the structure of the CMS32X chip designed for another MCU architecture shown in the embodiment of the present application, wherein the CMS32X chip is one of the chips designed using the present invention. The CMS32X chip uses an MCU as the main chip, and a multifunctional wafer containing multiple functions as an auxiliary chip; the multifunctional wafer has various functional modules for driving various peripheral functional blocks to work, and as long as the multifunctional wafer is enabled, it will work like a normal chip; if the internal functional module is enabled, the internal functional module will open the corresponding chip and then output various related signals to the periphery. This design is equivalent to having two wafers in a chip, and the functions of the two wafers can work normally. The user allocates the corresponding functional module according to what function he needs, instead of fixing all the functions in the chip after the single-chip design is completed. In other words, the chip designed according to the present invention can adapt to the various functional requirements of customers, making it more suitable for various functions that need to be possessed in the Internet of Things, smart home, artificial intelligence, factory automation and other application fields.

[0022] Further, Figure 4 The two wafers in the design use the serial peripheral interface (SPI) to achieve communication. Specifically, Figure 6As shown, a communication method using an MCU chip is shown in an embodiment of the present application. The interrupt of the multifunctional wafer is transmitted to the MCU through the INT pin, and the reset function realizes the input of the reset signal through the RESOUT pin; the clock is provided to the multifunctional wafer through the MCU; the communication port MOSI of the MCU is connected to the multifunctional wafer MISO, the communication port MISO of the MCU is connected to the MOSI of the multifunctional wafer, and the clock CLK of the MCU is connected to the multifunctional wafer CLK; an I / O port controls the enabling of the multifunctional wafer.

[0023] like Figure 5 As shown, another specific chip structure according to an embodiment of the present application is shown, in which the digital function and the analog function of the chip are independently isolated by two wafers, one is the main wafer MCU, which is used as a core chip using digital functions, and the other is a multi-functional wafer, which is used as a peripheral function dedicated chip including an analog function unit. The two wafers in the chip are implemented using another communication method in conventional communication. Furthermore, the core chip can use a chip with relatively few pins and low cost; the communication pins are not limited to Figure 4 The SPI communication mode of the CMS32X chip is used. The main wafer MCU and the multifunctional wafer transmit instructions and data through conventional communication mode. The address mapping still uses Figure 3 Then the chip is accessed and controlled by accessing the virtual address.

[0024] The embodiments described above are only descriptions of the preferred modes of the present invention and are not intended to limit the scope of the present invention. Without departing from the design spirit of the present invention, various deformations, modifications, and substitutions made to the technical solutions of the present invention by ordinary technicians in this field should all fall within the protection scope determined by the claims of the present invention.

Claims

1. An MCU architecture with scalable functions, characterized by: According to the different functions of the MCU chip, it is divided into a core control module and a peripheral function module; the core control module includes a processor CPU, a system control unit, SRAM and ROM; the peripheral function module includes an analog function unit, an I / O unit and a timer; The core control module and the peripheral function modules are connected in a dedicated connection manner; The dedicated connection method is to connect a peripheral function dedicated chip through a communication interface to freely expand the function of the MCU; The communication interface automatically maps the function of the peripheral function dedicated chip to the address bus of the MCU; The MCU chip is divided into a core control module and a peripheral function module according to its different functions, specifically including: The core control module uses an MCU as a main chip to implement the MCU core control function, and the peripheral function module uses a multifunctional wafer containing different function modules as an auxiliary chip to drive various peripheral function blocks to work; The communication interface is a serial peripheral interface SPI, specifically comprising: The interrupt of the multifunctional wafer is transmitted to the MCU through the INT pin; the reset function realizes the input of the reset signal through the RESOUT pin; the clock is provided to the multifunctional wafer through the MCU; the communication port MOSI of the MCU is connected to the MISO of the multifunctional wafer; the communication port MISO of the MCU is connected to the MOSI of the multifunctional wafer; the clock CLK of the MCU is connected to the CLK of the multifunctional wafer; Alternatively, the core control module uses an MCU main wafer as a core chip using digital functions; the peripheral function module uses a multifunctional wafer as a peripheral function dedicated chip, wherein the peripheral function dedicated chip includes the analog function unit.

2. The architecture according to claim 1, characterized in that: The analog functional unit includes: ADC, CMP and / or OPA.

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