Hot plug control method, hot plug system, medium and program product

Abstract

The invention discloses a hot plug control method, a hot plug system, a medium and a program product, and relates to the technical field of servers. A substrate management controller sends interrupt signal state information to a peripheral interconnection component slot corresponding to a target device based on an obtained trigger instruction of the target device; and the central processing unit determines a status bit numerical value of the interrupt status register based on the interrupt signal status information, and controls the target equipment to be in a hot plug state based on the status bit numerical value of the interrupt status register. Therefore, the hot plug state of the PCI device is controlled, the problem that the PCI device is replaced by manual physical disassembly after the server is shut down and powered off, and the service operation of the server is affected is solved, and the operation and maintenance cost of the server is reduced. Besides, interrupt signal state information sent to the peripheral interconnection component slot is regulated and controlled by using the substrate management controller, a general input and output chip does not need to be introduced, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a hot-swap control method, a hot-swap system, a medium, and a program product. Background Art

[0002] In the field of server technology, the core components of a server include central processing unit (CPU), memory, NVME (Non Volatile Memory Express), hard disk and other devices. In addition, depending on the main functions of the server, the server can also be connected to external devices, such as PCI (Peripheral Component Interconnect) devices.

[0003] During the use of the PCI device, if the PCI device fails, the user replaces the PCI device. However, when replacing the PCI device, the server needs to be shut down and powered off to replace the PCI device, which affects the service operation of the server. Summary of the invention

[0004] The present application provides a hot-swap control method, a hot-swap system, a medium and a program product, so as to at least solve the problem that the server needs to be shut down and powered off before the PCI device can be replaced, which affects the business operation of the server.

[0005] In a first aspect, the present application provides a hot-swap control method, the method being executed by a baseboard management controller, the method comprising: Get the trigger instruction of the target device; Based on the trigger instruction, interrupt signal status information is sent to the peripheral interconnect component slot corresponding to the target device; wherein the interrupt signal status information is used by the central processing unit to determine the status bit value of the interrupt status register, and control the target device to be in a hot plug state based on the status bit value of the interrupt status register.

[0006] In a second aspect, the present application provides a hot-swap control method, which is executed by a central processing unit; the method comprises: Get interrupt signal status information; According to the interrupt signal status information, the status bit value of the interrupt status register is determined, and based on the status bit value of the interrupt status register, the target device is controlled to be in a hot-plug state; wherein the interrupt signal status information is sent by the baseboard management controller to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction of the target device.

[0007] In a third aspect, the present application further provides a baseboard management controller, comprising: a processor and a memory, wherein the processor executes the steps of the method provided in any one of the first aspects by calling a program or instruction stored in the memory.

[0008] In a fourth aspect, the present application further provides a central processing unit, comprising: a processor and a memory, wherein the processor executes the steps of the method provided in any one of the second aspects by calling a program or instruction stored in the memory.

[0009] In a fifth aspect, the present application also provides a hot-swap system, including: a baseboard management controller, a central processing unit, and a peripheral interconnect component slot; The baseboard management controller and the central processing unit are both electrically connected to the peripheral interconnect component slot.

[0010] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of the hot plug control method provided in the first aspect are implemented, or the steps of the hot plug control method provided in the second aspect are implemented.

[0011] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the hot plug control method provided in the first aspect, or implements the steps of the hot plug control method provided in the second aspect.

[0012] The present application uses a baseboard management controller to send interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the acquired trigger instruction of the target device. The central processing unit connected to the peripheral interconnect component slot determines the status bit value of the interrupt status register based on the interrupt signal status information, and controls the target device to be in a hot-swappable state based on the status bit value of the interrupt status register. In this way, the hot-swappable state of the PCI device is controlled, avoiding the problem of the server shutting down and powering off and then manually physically disassembling the machine to replace the PCI device, which affects the operation of the server business, reduces the operation and maintenance cost of the server, and improves the energy efficiency of PCI device management and the work efficiency of users, ensuring the operation reliability of the server. In addition, the baseboard management controller is used to regulate the interrupt signal status information sent to the peripheral interconnect component slot, without the need to introduce a general input and output chip, thereby reducing the hardware cost of the server. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 A flow chart of a hot-swap control method provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a hot-swap system provided in an embodiment of the present application; Figure 3 A schematic diagram of the connection relationship between the general input and output pins of a baseboard management controller and the peripheral interconnect component slot provided in an embodiment of the present application; Figure 4 A flow chart of another hot-swap control method provided in an embodiment of the present application; Figure 5 A schematic diagram of a specific process of a hot-swap control method provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of a hot-swap control device provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of another hot-swap control device provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a substrate control manager provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a central processing unit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0015] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0016] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0017] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0018] In the server field, the core components of the server are central processing units, memory, NVME hard disks and other devices. In addition, PCI interface devices are also required, such as PCI network cards, PCI RAID (Redundant Arrays of Independent Disks) cards, PCI GPU (Graphics Processing Unit) cards, PCI interface acceleration cards, etc. These components are combined in the server configuration to form different configuration models, and the applicable scenarios are also different. For example, servers for network services require more network card devices, such as PCI network cards or OCP (Open Compute Project) network cards; for servers for storage data, in this server we will use a large number of NVME hard disks or RAID cards to transfer more hard disk devices for storage; for computing servers or AI artificial intelligence servers, more GPUs are needed to assemble GPU servers to meet the computing power requirements. When some servers have high requirements for computing performance or high requirements for read and write speed and timeliness, the memory quantity and capacity requirements are also large, which are usually solved by increasing the capacity of a single memory stick or increasing the number of memories. Regardless of the configuration, the server needs to be assembled when it leaves the factory and shipped to each customer's computer room or data center to meet customer use. End customers will operate various devices during use. For example, if the server's storage medium NVME hard disk encounters a fault during use, the NVME hard disk's hot-swap function can be used to unplug the faulty hard disk and insert a new hard disk for replacement, ensuring that the server does not need to be powered off and disassembled for replacement. For example, if the server has a large amount of memory configuration and in actual business applications, the memory controller can be controlled to shut down the redundant and unused memory due to excessive memory energy consumption or less use, so as to reduce the overall power consumption of the server or extend the server's memory life. For example, when we use network cards, especially OCP network cards, we also need to perform hot-swap actions according to actual conditions during actual use.

[0019] In addition to the hot-swap functions of traditional OCP network cards and NVME hard disks that support the system, we also need to support the hot-swap functions of other PCI devices, such as PCI network cards, PCI RAID cards, PCI GPU cards, etc. Traditional NVME hard disks, OCP network cards and other devices are connected through external slots, while PCI devices are set inside the chassis; on the other hand, traditional hot-swap functions require conventional means such as reserving memory resources in advance, and the resources required by PCI devices are more than those required by NVME hard disks and other devices. The traditional hot-swap method is not suitable for PCI devices. Therefore, the embodiment of the present application provides a control method for hot-swapping of PCI devices.

[0020] Figure 1 The flow chart of a hot-swap control method provided in the embodiment of the present application is a flow chart of a hot-swap control method provided in the embodiment of the present application. The method can be executed by the hot-swap control device of the server provided in the embodiment of the present application. The hot-swap control device of the server can be implemented in software and / or hardware, for example, it can be integrated on the baseboard management controller. The hot-swap control method provided in the embodiment of the present application is applied to the scene where the hot-swap state of the PCI device needs to be controlled. Figure 1 As shown, the method comprises the following steps: S101, obtaining a trigger instruction of a target device.

[0021] S102: Send interrupt signal status information to a peripheral interconnect component slot corresponding to the target device based on the trigger instruction.

[0022] The interrupt signal status information is used by the central processor to determine the status bit value of the interrupt status register, and to control the target device to be in a hot-plug state based on the status bit value of the interrupt status register.

[0023] Figure 2 A schematic diagram of the structure of a hot-swap system provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the hot-swap system may include, for example, a baseboard management controller (BMC), at least one central processor, and at least one peripheral interconnect component slot. Figure 2 2, CPU 0 and CPU 1 are shown as examples, wherein CPU 0 is connected to multiple peripheral interconnect component slots (such as Figure 2 The CPU 1 is electrically connected to multiple peripheral interconnect component slots (such as Slot0, Slot× and SlotN). Figure 2 Each peripheral interconnect component slot electrically connected to the CPU 0 is electrically connected to the baseboard management controller, and each peripheral interconnect component slot electrically connected to the CPU 1 is electrically connected to the baseboard management controller. The baseboard management controller may include multiple general purpose input and output (GPIO) pins (such as Figure 2Each peripheral interconnect component slot may include at least one system control interrupt (SCI) pin, and a general input and output pin of the baseboard management controller may be electrically connected to a system control interrupt pin and interact with the system control interrupt pin through an LPC (Low Pin Count) protocol or a PCI protocol.

[0024] The CPU 0 and the CPU 1 are electrically connected, with the CPU 0 serving as the master processor and the CPU 1 serving as the slave processor, and communicating and interacting through the CCIX (Cache Coherent Interconnect for Accelerators) protocol, the UPI (Ultra Path Interconnect) protocol, and the GMI (Gemini Memory Interface) protocol. The CPU 0 can use the operating system stored in the memory and interact with the Basic Input / Output System (BIOS) to complete related operations. The CPU 0 can interact with the Basic Input / Output System through LPC, SPI (Serial Peripheral Interface), and QSPI (Quad Serial Peripheral Interface).

[0025] It is understandable that the hot-swap system may be a component of a server, and the number of CPU and PI slots provided in the embodiments of the present application is not limited.

[0026] In some embodiments, a general purpose input / output pin of the baseboard management controller is electrically connected to a system control interrupt pin at a minimum bandwidth of the peripheral interconnect component slot.

[0027] Figure 3 A schematic diagram of the connection relationship between the general input and output pins of a baseboard management controller and the peripheral interconnect component slot provided in an embodiment of the present application. Figure 3As shown, the general input and output pins of the baseboard management controller are electrically connected to the peripheral interconnect component slots in a one-to-one correspondence. The peripheral interconnect component slots can be slots with different bandwidths, for example, the peripheral interconnect component x1 slot (theoretical maximum bandwidth is 1GB / s), the peripheral interconnect component x4 slot (theoretical maximum bandwidth is 4GB / s), the peripheral interconnect component x8 slot (theoretical maximum bandwidth is 8GB / s), the peripheral interconnect component x16 slot (theoretical maximum bandwidth is 16GB / s), etc. Each peripheral interconnect component slot can be connected to one or more PCI devices.

[0028] The general input and output pins of the embodiment of the present application need to be electrically connected to the system control interrupt pins of the smallest peripheral interconnect component x1 slot. This physical solution is set for one peripheral interconnect component slot. If a PCI link is split into multiple peripheral interconnect component slots, it is necessary to design a system control interrupt pin to be electrically connected to the general input and output pins on the minimum bandwidth link of each peripheral interconnect component slot to achieve the electrical connection between the general input and output pins and the system control interrupt pins. For example, if the peripheral interconnect component x16 slot is split into two peripheral interconnect component x8 slots, two general input and output pins need to be electrically connected to the two peripheral interconnect component x8 slots respectively.

[0029] The target device in the embodiment of the present application can be, for example, any PCI device that needs to be in a hot-plug state. The trigger instruction of the target device can be used to indicate that the target device is in a hot-removal state, or can be used to indicate that the target device is in a hot-plug state. The baseboard management controller sends interrupt signal status information to the peripheral interconnect component slot corresponding to the target device that needs to be in a hot-plug state based on the acquired trigger instruction of the target device. The central processing unit detects the interrupt signal status information, determines the interrupt status register status bit value under the central processing unit according to the interrupt signal status information, and the operating system under the central processing unit controls the target device to be in a hot-plug state based on the status bit value of the interrupt status register.

[0030] It should be noted that the central processing unit mentioned in the embodiments of the present application may be a central processing unit electrically connected to a peripheral interconnect component slot corresponding to the target device, or may be other central processing units, which is not limited here.

[0031] In the embodiment of the present application, the baseboard management controller sends interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction of the acquired target device. The central processor connected to the peripheral interconnect component slot determines the status bit value of the interrupt status register based on the interrupt signal status information, and controls the target device to be in a hot-swappable state based on the status bit value of the interrupt status register. Thus, the hot-swappable state of the PCI device is controlled, and the problem of the server shutting down and powering off and then manually physically disassembling the machine to replace the PCI device affects the operation of the server business, reduces the operation and maintenance cost of the server, improves the energy efficiency of PCI device management, improves the work efficiency of users, and ensures the operation reliability of the server. In addition, the baseboard management controller itself belongs to the management chip, and can use the general input and output pins to send interrupt signal status information to the peripheral interconnect component slot. There is no need to introduce a general input and output chip to send interrupt signal status information to the peripheral interconnect component slot. The baseboard management controller needs to read the general input and output address through the I2C bus to control the general input and output chip, which improves the control efficiency of the baseboard management controller and reduces the hardware cost of the server.

[0032] Optionally, obtaining a trigger instruction of the target device includes: obtaining a trigger instruction of the target device triggered on a remote management interface.

[0033] Exemplarily, the user can remotely log in to the WEB management platform of the server baseboard management controller and enter the remote management interface of the server. The remote management interface is displayed on the display device of the server, for example. An option is added to the remote management interface, that is, a control option for a system control interrupt is set for each PCI device, for example, the two options of enable and disable can be included. When the user selects the enable option for the target device on the remote management interface, it means that the user needs to control the target device to be in a hot removal state. When the user selects the disable option for the target device on the remote management interface, it means that the user needs to put the target device in a hot insertion state. If the user first selects the enable option for the target device on the remote management interface and then selects the disable option, it means that the user needs to restore the use of the hot removed target device.

[0034] It should be noted that the options on the web page interface of the baseboard management controller and the operations corresponding to the options can be set according to the actual usage requirements of the server, and the embodiments of the present application do not limit this.

[0035] Optionally, obtaining a trigger instruction of the target device includes: obtaining a trigger instruction of the target device corresponding to the intelligent platform management interface protocol.

[0036] Exemplarily, parameters may be input through the Intelligent Platform Management Interface (IPMI) protocol in the baseboard management controller to determine the target device that needs to be hot-swapped, and to control the target device to be in a hot-removal state or to be in a hot-insertion state.

[0037] IPMI uses a standard command format, IPMI tool.exe –I lanplus –H XX.xx.xx.xx (IP address) –U BMC username –P BMC password raw 0x3F 0x04 0x10 0xF0 0x10; the instructions before the Raw string are general commands, and the values ​​after the Raw string can be customized. 0x3F is the baseboard management controller command channel, 0x04 represents GPIO0 to GPIO7 corresponding to bit0 to bit7, and 1 represents the system control interrupt enable corresponding to the GPIO set to high, that is, bit2. 0x10 represents the system control interrupt control of the PCI link of the central processing unit 0 or the central processing unit 1. Bit4-7 is 1 for the central processing unit 1, and bit0 to bit3 are 1 for the central processing unit 0. The central processing unit 0 and the central processing unit 1 must be set separately and cannot be set together. The value 0xF0 represents that 4-7 of GPI0 is set to the output state, and 0x10 represents the output value enable setting of the general input and output pins of the central processing unit 1.

[0038] Optionally, the trigger instruction of the target device is a hot removal instruction of the target device; sending interrupt signal status information to a peripheral interconnect component slot corresponding to the target device based on the trigger instruction, including: sending a first signal level to the peripheral interconnect component slot corresponding to the target device based on the hot removal instruction of the target device; wherein the first signal level is used by the central processing unit to set the status bit value of the interrupt status register to a first preset value, and control the target device to be in a hot removal state based on the first preset value.

[0039] Exemplarily, the baseboard management controller sends a first signal level, such as a high-level signal, to a peripheral interconnect component slot corresponding to the target device based on a hot removal instruction of the target device. For example, the baseboard management controller receives the hot removal instruction of the target device, and sets the register value in the internal chip of the baseboard manager to, for example, 1, so that the baseboard management controller outputs a high-level signal and sends it to the peripheral interconnect component slot corresponding to the target device. The central processing unit detects the high-level signal of the peripheral interconnect component slot, and sets the status bit value of the interrupt status register to a first preset value, such as 1, based on the high-level signal. For example, the interrupt status register can automatically set the status bit value to 1 based on the high-level signal. The central processing unit can detect that the status bit value of the interrupt status register is the first preset value through the OSPM (Operating System Power Management) driver under the operating system, and control the target device to be in a hot removal state. For example, after each power-on startup and entry into the operating system, the server will use the ACPI (Advanced Configuration and Power Management Interface) protocol DSDT (Differentiated System Description Table) to determine the value in the interrupt status register corresponding to each PCI device (that is, each PCI link) to determine whether the hot removal function of each PCI device is enabled. If the status bit value in the corresponding interrupt status register is determined to be the first preset value through the ACPI protocol DSDT, the target device is controlled to be in the hot removal state through the _EJ0 method of OSPM. The hot removal state is, for example, that the target device is still in the chassis of the server, but is removed from the device list, and the user cannot view the status of the target device.

[0040] Thus, the hot removal operation of the PCI device is realized, avoiding the problem that the server is shut down and powered off and then physically disassembled to replace the PCI device, which affects the operation of the server business. The purpose of controlling the power consumption of the entire server can also be achieved by hot-removing the PCI device. Although the PCI device is still in the power supply state on the server, because the operating system cannot continue to use the PCI device, the power consumption of the PCI device is reduced, which indirectly reduces the power consumption of the server PCI device, that is, reduces the functional requirements of the entire server, and saves the cost of use and application. In addition, the embodiment of the present application does not need to use a universal input and output chip to send a first signal level to the peripheral interconnect component slot to realize the subsequent hot removal operation. The baseboard controller can use the universal input and output pin to directly send the first signal level to the peripheral interconnect component slot, which improves the control efficiency of the baseboard management controller. After the universal input and output chip is introduced, if the universal input and output chip fails, the entire hot-swap system will fail, and if the baseboard management controller is damaged, the management board of the baseboard management controller can be replaced, which reduces the cost of development, maintenance, and use, and is convenient and fast.

[0041] Optionally, the trigger instruction of the target device is a hot plug instruction of the target device; sending interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction, including: sending a second signal level to the peripheral interconnect component slot corresponding to the target device based on the hot plug instruction of the target device; wherein the second signal level is used by the central processing unit to set the status bit value of the interrupt status register to a second preset value, and control the target device to be in a hot plug state based on the second preset value.

[0042] Exemplarily, for example, if a PCI device that has been hot-removed needs to be restored, the baseboard management controller sends a low-level signal to the peripheral interconnect component slot corresponding to the target device based on the hot-plug instruction of the target device. For example, the baseboard management controller receives the hot-plug instruction of the target device, and sets the register value in the internal chip of the baseboard manager to 0, so that the baseboard management controller outputs a low-level signal and sends it to the peripheral interconnect component slot corresponding to the target device. The central processing unit detects the low-level signal of the peripheral interconnect component slot, and sets the status bit value of the interrupt status register to a second preset value, such as 0, based on the low-level signal. For example, the interrupt status register can automatically set the status bit value to 0 based on the low-level signal. The central processing unit can detect that the status bit value of the interrupt status register is 0 through the OSPM driver under the operating system, and control the target device to be in a hot-plug state. The hot-plug state is, for example, the state in which the target device is restored from the device list.

[0043] Thus, the hot-plug operation of the PCI device is realized, avoiding the problem that the server is shut down and powered off and then physically disassembled to replace the PCI device, which affects the operation of the server business. In addition, the embodiment of the present application does not need to use a universal input and output chip to send a second signal level to the peripheral interconnect component slot to realize the subsequent hot-plug operation. The baseboard controller can use the universal input and output pin to directly send the second signal level to the peripheral interconnect component slot, which improves the control efficiency of the baseboard management controller. After the universal input and output chip is introduced, if the universal input and output chip fails, the entire hot-plug system will fail, and if the baseboard management controller is damaged, the management board of the baseboard management controller can be replaced, which reduces the cost of development, maintenance, and use, and is convenient and fast.

[0044] Optionally, after sending the second signal level to the peripheral interconnect component slot corresponding to the target device based on the hot-plug instruction, the method further includes: sending a restart instruction to the central processing unit; the restart instruction is used to instruct the central processing unit to control the server to restart.

[0045] For example, when the interrupt status register uses a read-only memory, after performing a hot removal operation, once the status bit value of the interrupt status register is set to 1, it cannot be cleared, and the server needs to be restarted to update the value of the interrupt status register. Therefore, after the target device is hot-removed and needs to be restored, the baseboard management controller sends a low-level signal to the peripheral interconnect component slot corresponding to the target device based on the hot-plug instruction, and then sends a restart instruction to the central processing unit. The central processing unit controls the server to restart. After the restarted server enters the operating system again, the central processing unit can detect that the status bit value of the interrupt status register is 0 through the OSPM driver under the operating system, and control the target device to be in a hot-plug state. As a result, hot-plugging of the hot-removed target device can still be achieved when using a read-only memory, and the PCI device can be used normally when the operating system is entered again, thereby improving the energy efficiency of PCI device management.

[0046] Optionally, interrupt signal status information is sent to the peripheral interconnect component slot corresponding to the target device based on a trigger instruction, including: based on the trigger instruction, changing the signal state of the level signal of the general input / output pin electrically connected to the peripheral interconnect component slot corresponding to the target device, and sending the changed level signal to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device; wherein the signal state of the level signal of the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device is used by the central processing unit to change the status bit value in the interrupt status register corresponding to the target device, and control the target device to be in a hot-plug state based on the status bit value of the interrupt status register corresponding to the target device.

[0047] Exemplarily, based on the hot removal instruction of the target device, the baseboard management controller sets the level signal of the general input / output pin electrically connected to the peripheral interconnect component slot corresponding to the target device to a high level signal, and sends the high level signal to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device, so that the system control interrupt signal of the peripheral interconnect component slot corresponding to the target device is a high level signal. The central processing unit connected to the peripheral interconnect component slot sets the status bit value in the interrupt status register corresponding to the target device to 1 according to the system control interrupt signal being a high level signal. The central processing unit can detect that the status bit value of the interrupt status register is 1 through the OSPM driver under the operating system, and control the target device to be in a hot removal state.

[0048] Exemplarily, based on the hot-plug instruction of the target device, the baseboard management controller sets the level signal of the general input / output pin electrically connected to the peripheral interconnect component slot corresponding to the target device to a low-level signal, and sends the low-level signal to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device, so that the system control interrupt signal of the peripheral interconnect component slot corresponding to the target device is a low-level signal. The central processing unit connected to the peripheral interconnect component slot sets the status bit value in the interrupt status register corresponding to the target device to 0 according to the system control interrupt signal being a low-level signal. The central processing unit can detect that the status bit value of the interrupt status register is 0 through the OSPM driver under the operating system, and control the target device to be in a hot-plug state.

[0049] Figure 4 This is a flow chart of another hot-swap control method provided in an embodiment of the present application. This method can be executed by a hot-swap control device for a server provided in an embodiment of the present application. The hot-swap control device for the server can be implemented in software and / or hardware, for example, it can be integrated on a central processing unit. The hot-swap control method provided in an embodiment of the present application is applied to a scenario where a PCI device needs to be in a hot-swap state. Figure 4 As shown, the method comprises the following steps: S401: Obtain interrupt signal status information of a peripheral interconnect component slot corresponding to a target device.

[0050] S402: Determine a status bit value of an interrupt status register according to the interrupt signal status information, and control the target device to be in a hot-plug state based on the status bit value of the interrupt status register.

[0051] The interrupt signal status information is sent by the baseboard management controller to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction of the target device.

[0052] Exemplarily, the baseboard management controller sends interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction of the target device. After the central processing unit connected to the peripheral interconnect component slot obtains the interrupt signal status information, it determines the status bit value of the interrupt status register. The operating system under the central processing unit controls the target device to be in a hot-swappable state according to the status bit value of the interrupt status register.

[0053] In the embodiment of the present application, the baseboard management controller sends interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction of the target device, and the central processing unit connected to the peripheral interconnect component slot determines the status bit value of the interrupt status register based on the interrupt signal status information, and controls the target device to be in a hot-swappable state based on the status bit value of the interrupt status register. In this way, the hot-swappable state of the PCI device is controlled, and the problem of manually physically disassembling the PCI device to replace the PCI device after the server is shut down and powered off is avoided, which affects the operation of the server business, reduces the operation and maintenance cost of the server, improves the energy efficiency of PCI device management, improves the work efficiency of users, and ensures the operation reliability of the server.

[0054] Optionally, according to the interrupt signal status information, the status bit value of the interrupt status register is determined, and the target device is controlled to be in a hot plug state based on the status bit value of the interrupt status register, including: according to a first signal level, the status bit value of the interrupt status register is set to a first preset value, and the target device is controlled to be in a hot removal state based on the first preset value; wherein the first signal level is sent by the baseboard management controller to the peripheral interconnect component slot corresponding to the target device based on the hot removal instruction of the target device.

[0055] Specifically, after receiving the hot removal instruction of the target device, the baseboard management controller sends a first signal level, such as a high-level signal, to the peripheral interconnect component slot corresponding to the target device based on the hot removal instruction of the target device. The central processing unit electrically connected to the peripheral interconnect component slot corresponding to the target device sets the status bit value of the interrupt status register to a first preset value, such as 1, based on the high-level signal of the peripheral interconnect component slot and the high-level signal. For example, the interrupt status register can automatically set the status bit value to 1 based on the high-level signal. The central processing unit detects that the status bit value of the interrupt status register is 1 through the OSPM driver under the operating system, and controls the target device to be in a hot removal state. For example, after each power-on startup and entering the operating system, the server will use the ACPI protocol DSDT to determine whether the hot removal function of each PCI device is turned on for the value in the interrupt status register corresponding to each PCI device (that is, each PCI link). If the status bit value in the corresponding interrupt status register is determined to be the first preset value through the ACPI protocol DSDT, the target device is controlled to be in a hot removal state through the _EJ0 method of OSPM. Thus, the PCI device can be hot-removed, avoiding the problem of shutting down the server and then physically dismantling the machine to replace the PCI device, which affects the operation of the server business. The purpose of controlling the power consumption of the entire server can also be achieved by hot-removing the PCI device. Although the PCI device is still powered on the server, the operating system can no longer use the PCI device, so the power consumption of the PCI device is reduced, which indirectly reduces the power consumption of the server PCI device, that is, reduces the functional requirements of the entire server, and saves the cost of operation and application.

[0056] Optionally, according to the interrupt signal status information, the status bit value of the interrupt status register is determined, and the target device is controlled to be in a hot plug state based on the status bit value of the interrupt status register, including: according to the second signal level, the status bit value of the interrupt status register is set to a second preset value, and the target device is controlled to be in a hot plug state based on the second preset value; wherein the second signal level is sent by the baseboard management controller to the peripheral interconnect component slot corresponding to the target device based on the hot plug instruction of the target device.

[0057] For example, if it is necessary to restore a removed PCI device, the baseboard management controller sends a second level signal, such as a low level signal, to the peripheral interconnect component slot corresponding to the target device based on the hot plug instruction of the target device. The central processing unit electrically connected to the peripheral interconnect component slot corresponding to the target device detects the low level signal of the peripheral interconnect component slot, and sets the status bit value of the interrupt status register to a second preset value, such as 0, based on the low level signal. For example, the interrupt status register can automatically set the status bit value to 0 based on the low level signal. The central processing unit can detect that the status bit value of the interrupt status register is 0 through the OSPM driver under the operating system, and control the target device to be in a hot plug state. In this way, the hot plug operation of the PCI device is realized, avoiding the problem of shutting down the server and then manually physically disassembling the machine to replace the PCI device, which affects the operation of the server business.

[0058] Optionally, before setting the status bit value of the interrupt status register to a second preset value according to the second signal level and controlling the target device to be in a hot-plug state based on the second preset value, it also includes: controlling the server to restart based on a restart instruction sent by the baseboard management controller.

[0059] For example, when the interrupt status register uses a read-only memory, after performing a hot removal operation, once the status bit value of the interrupt status register is set to 1, it cannot be cleared, and the server needs to be restarted to update the value of the interrupt status register. Therefore, after the target device is hot-removed and needs to be restored, the baseboard management controller sends a low-level signal to the peripheral interconnect component slot corresponding to the target device based on the hot plug instruction, and then sends a restart instruction to the central processing unit. After receiving the restart instruction, the central processing unit controls the server to restart. After the restarted server enters the operating system again, the interrupt status register sets the status bit value to 0 based on the low-level signal. The central processing unit can detect that the status bit value of the interrupt status register is 0 through the OSPM driver under the operating system, and controls the target device to be in a hot plug state. As a result, hot insertion of the hot-removed target device can still be achieved when using a read-only memory, and the PCI device can be used normally when the operating system is entered again, thereby improving the energy efficiency of PCI device management.

[0060] Optionally, after controlling the target device to be in the hot-plug state based on the status bit value of the interrupt status register, the method further includes: obtaining a device list; and judging whether the control of the hot-plug state of the target device is successful according to whether the target device exists in the device list.

[0061] Exemplarily, the CPU can verify whether the hot plug of the target device is successful through OSPM. After performing the hot removal operation, the CPU can obtain the device list of the device manager through OSPM. When the target device does not exist on the device list, it is determined that the control of the hot removal state of the target device is successful. After performing the hot plug operation on the hot removed device again, the CPU can obtain the device list of the device manager through OSPM. When the target device exists on the device list, it is determined that the control of the hot plug state of the target device is successful. Thus, the reliability of the hot plug state is improved.

[0062] Optionally, controlling the target device to be in a hot-plug state includes: controlling the target device to be in a hot-plug state using a target control method in power management of the operating system.

[0063] Exemplarily, when the central processing unit detects through the OSPM driver under the operating system that the status bit value of the interrupt status register is 1, it can be determined that the trigger control target device is in the hot removal state. At this time, the central processing unit can use the target control method in OSPM to control the target device to be in the hot removal state, where the target control method can be the _EJ0 control method.

[0064] For example, the relevant code in the hot plug state can be as follows: / / Tell OS to run thru the new status of this device (Software SCIgenerated from SMM for all Hot plug events) Method (_L62, 0x0, Not Serialized) { if(L Equal(SCI0, 3)) { / / Device ejection (Invoked with _EJ0 methodcalled) / / NTFM(SCI1,3) NTFC (SCI2,3) Store (0, SCI0) } Else If (L Equal(SCI0, 1)) { / / Device check (OS can still rejectonline request based on resources and capability) NTFC (CPHP, 0) NTFI (IIOP, 0) Store (0,CPHP) Store (0,IIOP) Store (0,SCI0) } Name(_HPP,Package(){0x08,0x40,0x01,0x00}) / / Device definitions for Slot 1- HOT PLUG SLOT Device (S1F0) { / / Slot 1,Func#0 on bus P2P2 Name(_ADR,0x00020000) Method(_EJ0,1) { } Device (S1F1) { / / Remove all power to device} / / Slot 1,Func#1 on bus P2P2 Name(_ADR,0x00020001) Method(_EJ0,1) { } Device (S1F2) { / / Remove all power to device} / / Slot 1,Func#2 on bus P2P2 Name(_ADR,0x000200 02) Method(_EJ0,1) { } Device (S1F3) { / / Remove all power to device} / / Slot 1,Func#3 on bus P2P2 Name(_ADR,0x00020003) Method(_EJ0,1) { } Device (S1F4) { / / Remove all power to device} / / Slot 1,Func#4 on bus P2P2 Name(_ADR,0x00020004) Method(_EJ0,1) { } Device (S1F5) { / / Remove all power to device} / / Slot 1,Func#5 on bus P2P2 Name(_ADR,0x00020005) Method(_EJ0,1) { } Device (S1F6) { / / Remove all power to device} / / Slot 1,Func#6 on bus P2P2 Name(_ADR,0x00020006) Method(_EJ0,1) { } Device (S1F7) { / / Remove all power to device} / / Slot 1,Func#7 on bus P2P2 Name(_ADR,0x00020007) Method(_EJ0,1) { } / / Remove all power to device} / / Device definitions for Slot 2- HOT PLUG SLOT Device (S2F0) { / / Slot 2,Func#0 on bus P2P2 Name(_ADR,0x00030000) Method(_EJ0,1) { } Device (S2F1) { / / Remove all power to device} / / Slot 2,Func#1 on bus P2P2 Name(_ADR,0x00030001) Method(_EJ0,1) { } Device (S2F2) { / / Remove all power to device} / / Slot 2,Func#2 on bus P2P2 Name(_ADR,0x00030002) Method(_EJ0,1) { } Device (S2F3) / / Remove all power to device} / / Slot 2,Func#3 on bus P2P2 Name(_ADR,0x00030003) Method(_EJ0,1) { } Device (S2F4) { / / Remove all power to device} / / Slot 2,Func#4 on bus P2P2 Name(_ADR,0x00030004) ) Method(_EJ0,1) { / / Remove all power to device} } Device (S2F5) { / / Slot 2, Func#5 on bus P2P2 Name(_ADR,0x00030005) Method(_EJ0,1) { / / Remove all power to device} } Device (S2F6) { / / Slot 2, Func#6 on bus P2P2 Name(_ADR,0x00030006) Method(_EJ0,1) { / / Remove all power to device} } Device (S2F7) { / / Slot 2, Func#7 on bus P2P2 Name(_ADR,0x00030007) Method(_EJ0,1) { / / Remove all power to device} } } Optionally, controlling the target device to be in a hot-plug state based on a status bit value of an interrupt status register includes: polling the status bit of the interrupt status register to determine a position of the target device, and controlling the target device to be in a hot-plug state.

[0065] Specifically, each time the server is powered on and starts entering the operating system, it will poll the status bits of each interrupt status register in each central processor through the ACPI protocol DSDT to determine whether the hot removal function or hot insertion function corresponding to each device is enabled, and use the device corresponding to the hot removal function as the target device to control the target device to be in the hot removal state, or use the device corresponding to the hot insertion function as the target device to control the target device to be in the hot insertion state.

[0066] Therefore, omission of a PCI device that needs to be hot-plugged is avoided, and the accuracy of the hot-plugging state is improved.

[0067] Optionally, according to the interrupt signal status information, the status bit value of the interrupt status register is determined, and the target device is controlled to be in a hot-plug state based on the status bit value of the interrupt status register, including: according to the signal state of the level signal detected from the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device, the status bit value in the interrupt status register corresponding to the target device is changed, and the target device is controlled to be in a hot-plug state based on the status bit value of the interrupt status register corresponding to the target device; wherein the signal state of the level signal is generated by the baseboard management controller after changing the signal state of the level signal of the general input and output pin based on the trigger instruction and outputting it to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device.

[0068] Exemplarily, based on the hot removal instruction of the target device, the baseboard management controller sets the level signal of the general input / output pin electrically connected to the peripheral interconnect component slot corresponding to the target device to a high level signal, and the high level signal is sent to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device, so that the system control interrupt signal of the peripheral interconnect component slot corresponding to the target device is a high level signal. The central processing unit connected to the peripheral interconnect component slot sets the status bit value in the interrupt status register corresponding to the target device to 1 according to the high level signal of the system control interrupt signal. For example, the interrupt status register can be automatically set to 1 according to the high level signal, and the central processing unit can detect that the status bit value of the interrupt status register is 1 through the OSPM driver under the operating system, and control the target device to be in the hot removal state.

[0069] Exemplarily, based on the hot-plug instruction of the target device, the baseboard management controller sets the level signal of the general input / output pin electrically connected to the peripheral interconnect component slot corresponding to the target device to a low-level signal, and the low-level signal is sent to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device, so that the system control interrupt signal of the peripheral interconnect component slot corresponding to the target device is a low-level signal. The central processing unit connected to the peripheral interconnect component slot sets the status bit value in the interrupt status register corresponding to the target device to 0 according to the low-level signal of the system control interrupt signal. For example, the interrupt status register can be automatically set to 0 according to the low-level signal, and the central processing unit can detect that the status bit value of the interrupt status register is 0 through the OSPM driver under the operating system, and control the target device to be in a hot-plug state.

[0070] Figure 5 A specific flow chart of a hot-swap control method provided in an embodiment of the present application is provided. The whole process in the hot-swap state is described in detail below. The specific steps can be as follows: Figure 5 shown.

[0071] When the server is powered on but not started, the general input / output system activates the management firmware of the baseboard management controller, and controls the baseboard management controller through IPMI commands or remote management interfaces to change the signal state of the level signal of the general input / output pin, thereby controlling the signal state of the level signal of the system control interrupt pin of each PCI link, and the interrupt status register sets its status bit value according to the level signal of the system control interrupt pin. After that, the server starts and enters the operating system. The ACPI protocol DSDT determines whether the interrupt status register corresponding to each PCI link is set to the first preset value, such as 1. If so, the target device is controlled to be in a hot removal state through the _EJ0 method of OSPM. If not, the corresponding PCI device is used normally. During the operation of the server, the user can still choose to hot remove a device. The method for obtaining the trigger instruction and the method for setting the status to a value of the interrupt status register can refer to the relevant method when the server is powered on but not started. When the status bit value of the interrupt status register is set to the first preset value, such as 1, the target device is controlled to be in a hot removal state through the _EJ0 method of OSPM. It can be understood that Figure 5 The server restart step executed after the step of controlling the target device to be in a hot removal state through the _EJ0 method of OSPM can be selected whether to be executed according to the actual usage of the server, and the embodiment of the present application is not limited here.

[0072] In the embodiment of the present application, the baseboard management controller sends interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction of the target device obtained. The central processor connected to the peripheral interconnect component slot determines the status bit value of the interrupt status register based on the interrupt signal status information, and controls the target device to be in a hot-swappable state based on the status bit value of the interrupt status register. As a result, the hot removal or hot insertion function of the PCI device can be realized without powering off and disassembling the hardware device of the server, which reduces the operation and maintenance cost of the server, improves the energy efficiency of PCI device management, improves the work efficiency of users, and ensures the operation reliability of the server. In addition, the baseboard management controller itself belongs to the management chip, and can use the general input and output pins to send interrupt signal status information to the peripheral interconnect component slot, without the need to introduce a general input and output chip. Due to the introduction of the general input and output chip, the baseboard management controller needs to read the GPIO address through the I2C bus to control the general input and output chip, which improves the control efficiency of the baseboard management controller and reduces the hardware cost of the server.

[0073] An embodiment of the present application also provides a hot-swap system, comprising: a baseboard management controller, a central processing unit and a peripheral interconnect component slot; the baseboard management controller and the central processing unit are both electrically connected to the peripheral interconnect component slot.

[0074] The baseboard management controller itself is a management chip, which can use the general input and output pins to send interrupt signal status information to the peripheral interconnect component slot. There is no need to introduce a general input and output chip to send interrupt signal status information to the peripheral interconnect component slot. The baseboard management controller needs to read the GPIO address through the I2C bus to control the general input and output chip, which improves the control efficiency of the baseboard management controller. After the introduction of the general input and output chip, if the general input and output chip fails, the entire hot-swap system will fail, and if the baseboard management controller is damaged, the management board of the baseboard management controller can be replaced, which reduces the cost of development, maintenance, and use of the hot-swap system, and is convenient and fast.

[0075] The embodiment of the present application also provides a hot-swap control device. Figure 6 A schematic diagram of the structure of a hot-swap control device provided in an embodiment of the present application is shown in FIG. Figure 6As shown, the hot-swap control device includes: a trigger instruction acquisition module 601 and a sending module 602, wherein the trigger instruction acquisition module 601 is used to acquire the trigger instruction of the target device, and the sending module 602 is used to send interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction, so that the central processor connected to the peripheral interconnect component slot determines the status bit value of the interrupt status register based on the interrupt signal status information, and controls the target device to be in a hot-swap state based on the status bit value of the interrupt status register.

[0076] In some embodiments, the trigger instruction acquisition module 601 is specifically used to: acquire a trigger instruction of a target device triggered on a remote management interface.

[0077] In some embodiments, the trigger instruction acquisition module 601 is specifically used to: acquire the trigger instruction of the target device corresponding to the intelligent platform management interface protocol.

[0078] In some embodiments, the sending module 602 is specifically used to: send a first signal level to a peripheral interconnect component slot corresponding to the target device based on a hot removal instruction of the target device; wherein the first signal level is used by the central processor to set the status bit value of the interrupt status register to a first preset value, and control the target device to be in a hot removal state based on the first preset value.

[0079] In some embodiments, the sending module 602 is specifically used to: send a second signal level to the peripheral interconnect component slot corresponding to the target device based on the hot plug instruction of the target device, so that the central processor connected to the peripheral interconnect component slot is based on the second signal level; wherein the second signal level is used for the central processor to set the status bit value of the interrupt status register to a second preset value, and control the target device to be in a hot plug state based on the second preset value.

[0080] In some embodiments, the sending module 602 is specifically used to send a restart instruction to the central processing unit so that the central processing unit controls the server to restart.

[0081] In some embodiments, the sending module 602 is specifically used to: based on a trigger instruction, change the signal state of a level signal output by a general input / output pin electrically connected to a peripheral interconnect component slot corresponding to a target device, and send the changed level signal to a system control interrupt pin of a peripheral interconnect component slot corresponding to the target device; wherein the signal state of the level signal of the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device is used by the central processing unit to change the status bit value in an interrupt status register corresponding to the target device, and control the target device to be in a hot-plug state based on the status bit value of the interrupt status register corresponding to the target device.

[0082] The device provided in the above-mentioned embodiment of the present application and the method provided in the embodiment of the present application are based on the same inventive concept and have the same beneficial effects, which will not be elaborated here.

[0083] An embodiment of the present application provides another hot-swap control device. Figure 7 A schematic diagram of the structure of another hot-swap control device provided in an embodiment of the present application is shown in FIG. Figure 7 As shown, the hot-swap control device includes: an information acquisition module 701 and a control module 702, the information acquisition module 701 is used to obtain the interrupt signal status information of the peripheral interconnect component slot corresponding to the target device, and the control module 702 is used to determine the status bit value of the interrupt status register according to the interrupt signal status information, and control the target device to be in a hot-swap state based on the status bit value of the interrupt status register; wherein the interrupt signal status information is sent by the baseboard management controller to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction of the target device.

[0084] In some embodiments, the control module 702 is specifically used to: set the status bit value of the interrupt status register to a first preset value according to the first signal level, and control the target device to be in a hot removal state based on the first preset value.

[0085] In some embodiments, the control module 702 is specifically used to: set the status bit value of the interrupt status register to a second preset value according to the second signal level, and control the target device to be in a hot plug state based on the second preset value.

[0086] In some embodiments, the control module 702 is specifically used to: set the status bit value of the interrupt status register to a second preset value according to the second signal level, and control the target device to be in a hot-plug state based on the second preset value, and control the server to restart based on the restart instruction sent by the baseboard management controller.

[0087] In some embodiments, the control module 702 is specifically used to: obtain a device list after controlling the target device to be in a hot-plug state based on the status bit value of the interrupt status register; and determine whether the hot-plug state of the target device is successfully controlled based on whether the target device exists in the device list.

[0088] In some embodiments, the control module 702 is specifically used to: control the target device to be in a hot-swappable state by using a target control method in the power management of the operating system.

[0089] In some embodiments, the control module 702 is specifically used to: poll the status bit of the interrupt status register to determine the location of the target device, and control the target device to be in a hot-plug state.

[0090] In some embodiments, the control module 702 is specifically used to: change the status bit value in the interrupt status register corresponding to the target device according to the signal state of the level signal detected from the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device, and control the target device to be in a hot plug state based on the status bit value of the interrupt status register corresponding to the target device; wherein the signal state of the level signal is generated by the baseboard management controller after changing the signal state of the level signal of the general input and output pin based on the trigger instruction, and then output to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device.

[0091] The device provided in the above-mentioned embodiment of the present application and the method provided in the embodiment of the present application are based on the same inventive concept and have the same beneficial effects, which will not be elaborated here.

[0092] Based on the above implementation, the present application embodiment further provides a substrate control manager. Figure 8 A schematic diagram of the structure of a substrate control manager provided in an embodiment of the present application. Figure 8 As shown, the substrate control manager includes a processor 801 and a memory 802. The processor 801 executes the steps of the methods of the above embodiments by calling the program or instructions stored in the memory 802. Therefore, it has the beneficial effects of the above embodiments and will not be repeated here.

[0093] Specifically, Figure 8 As shown, the baseboard control manager can be configured to include at least one processor 801, at least one memory 802, and at least one communication interface 803. The various components in the baseboard control manager are coupled together via a bus system 804. The communication interface 803 is used to transmit information with external devices. It can be understood that the bus system 804 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 804 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus system 804 is not described in detail. Figure 8 Various buses are labeled as bus system 804 .

[0094] It is understood that the memory 802 in this embodiment may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. In some implementations, the memory 802 stores the following elements: executable units or data structures, or their subsets, or their extended set operating systems and applications. In the embodiment of the present application, the processor 801 executes the steps of each embodiment of the method provided in the embodiment of the present application by calling the program or instruction stored in the memory 802.

[0095] The method provided in the embodiment of the present application can be applied to the processor 801, or implemented by the processor 801. The processor 801 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 801 or an instruction in the form of software. The above-mentioned processor 801 can be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0096] The steps of the method provided in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or being executed by a combination of hardware and software units in the decoding processor. The software unit can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 802, and the processor 801 reads the information in the memory 802 and completes the steps of the method in combination with its hardware.

[0097] The substrate control manager may also include one entity component, or multiple entity components, according to the instructions generated by the processor 801 when executing the method provided in the embodiment of the present application. Different entity components may be set inside the substrate control manager, or outside the substrate control manager, such as a cloud server, etc. Each entity component cooperates with the processor 801 and the memory 802 to implement the functions of the substrate control manager in this embodiment.

[0098] Based on the above implementation, the present application embodiment further provides a central processing unit, Fig. 9 A schematic diagram of the structure of a central processing unit provided in an embodiment of the present application. Fig. 9 As shown, the central processing unit includes a processor 901 and a memory 902. The processor 901 executes the steps of the methods of the above embodiments by calling the program or instructions stored in the memory 902, so it has the beneficial effects of the above embodiments and will not be repeated here.

[0099] Specifically, Fig. 9As shown, the central processing unit can be configured to include at least one processor 901, at least one memory 902, and at least one communication interface 903. The various components in the central processing unit are coupled together via a bus system 904. The communication interface 903 is used to transmit information with external devices. It can be understood that the bus system 904 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 904 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, the bus system 904 is not described in detail. Fig. 9 Various buses are labeled as bus system 904.

[0100] It is understood that the memory 902 in this embodiment may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. In some implementations, the memory 902 stores the following elements: executable units or data structures, or their subsets, or their extended set operating systems and applications. In the embodiment of the present application, the processor 901 executes the steps of each embodiment of the method provided in the embodiment of the present application by calling the program or instruction stored in the memory 902.

[0101] The method provided in the embodiment of the present application can be applied to the processor 901, or implemented by the processor 901. The processor 901 can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 901 or an instruction in the form of software. The above-mentioned processor 901 can be a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0102] The steps of the method provided in the embodiment of the present application can be directly embodied as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software units in the decoding processor. The software unit can be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 902, and the processor 901 reads the information in the memory 902 and completes the steps of the method in combination with its hardware.

[0103] The central processor may also include one entity component, or multiple entity components, according to the instructions generated by the processor 901 when executing the method provided in the embodiment of the present application. Different entity components can be set in the central processor, or outside the central processor, such as a cloud server, etc. Each entity component cooperates with the processor 901 and the memory 902 to realize the functions of the central processor in this embodiment.

[0104] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned hot-swap control method embodiments when running.

[0105] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0106] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned hot-swap control method embodiments are implemented.

[0107] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned hot-swap control method embodiments are implemented.

[0108] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0109] The above is a detailed introduction to a hot-swap control method, hot-swap system, medium and program product provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A hot-swap control method, characterized in that: The method is performed by a baseboard management controller; the method comprises: Get the trigger instruction of the target device; Based on the trigger instruction, interrupt signal status information is sent to the peripheral interconnect component slot corresponding to the target device; wherein the interrupt signal status information is used by the central processing unit to determine the status bit value of the interrupt status register, and control the target device to be in a hot plug state based on the status bit value of the interrupt status register.

2. The hot-swap control method according to claim 1, characterized in that: The step of obtaining a trigger instruction of a target device includes: Get the trigger command of the target device triggered on the remote management interface.

3. The hot-swap control method according to claim 1, characterized in that: The step of obtaining a trigger instruction of a target device includes: Get the trigger instruction of the target device corresponding to the intelligent platform management interface protocol.

4. The hot-swap control method according to claim 1, characterized in that: The trigger instruction of the target device is a hot removal instruction of the target device; The sending interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction includes: Based on the hot removal instruction of the target device, a first signal level is sent to the peripheral interconnect component slot corresponding to the target device; wherein the first signal level is used by the central processing unit to set the status bit value of the interrupt status register to a first preset value, and control the target device to be in a hot removal state based on the first preset value.

5. The hot-swap control method according to claim 1, characterized in that: The trigger instruction of the target device is a hot plug instruction of the target device; The sending interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction includes: Based on the hot-plug instruction of the target device, a second signal level is sent to the peripheral interconnect component slot corresponding to the target device; wherein the second signal level is used by the central processing unit to set the status bit value of the interrupt status register to a second preset value, and control the target device to be in a hot-plug state based on the second preset value.

6. The hot-swap control method according to claim 5, characterized in that: After sending a second signal level to the peripheral interconnect component slot corresponding to the target device based on the hot plug instruction of the target device, the method further includes: Sending a restart instruction to the central processing unit; the restart instruction is used to instruct the central processing unit to control the server to restart.

7. The hot-swap control method according to claim 1, characterized in that: The sending interrupt signal status information to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction includes: Based on the trigger instruction, the signal state of the level signal output by the general input / output pin electrically connected to the peripheral interconnect component slot corresponding to the target device is changed, and the changed level signal is sent to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device; wherein the signal state of the level signal of the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device is used by the central processing unit to change the status bit value in the interrupt status register corresponding to the target device, and control the target device to be in a hot-swappable state based on the status bit value of the interrupt status register corresponding to the target device.

8. A hot-swap control method, characterized in that: The method is executed by a central processing unit; the method comprises: Obtain interrupt signal status information of the peripheral interconnect component slot corresponding to the target device; According to the interrupt signal status information, the status bit value of the interrupt status register is determined, and based on the status bit value of the interrupt status register, the target device is controlled to be in a hot-plug state; wherein the interrupt signal status information is sent by the baseboard management controller to the peripheral interconnect component slot corresponding to the target device based on the trigger instruction of the target device.

9. The hot-swap control method according to claim 8, characterized in that: Determining the status bit value of the interrupt status register according to the interrupt signal status information, and controlling the target device to be in a hot plug state based on the status bit value of the interrupt status register, includes: According to a first signal level, the status bit value of the interrupt status register is set to a first preset value, and the target device is controlled to be in a hot removal state based on the first preset value; wherein the first signal level is sent by the baseboard management controller to the peripheral interconnect component slot corresponding to the target device based on the hot removal instruction of the target device.

10. The hot-swap control method according to claim 8, characterized in that: Determining the status bit value of the interrupt status register according to the interrupt signal status information, and controlling the target device to be in a hot plug state based on the status bit value of the interrupt status register, includes: According to the second signal level, the status bit value of the interrupt status register is set to a second preset value, and the target device is controlled to be in a hot plug state based on the second preset value; wherein the second signal level is sent by the baseboard management controller to the peripheral interconnect component slot corresponding to the target device based on the hot plug instruction of the target device.

11. The hot-swap control method according to claim 10, characterized in that: Before setting the state bit value of the interrupt state register to a second preset value according to the second signal level and controlling the target device to be in a hot plug state based on the second preset value, the method further includes: Based on the restart instruction sent by the baseboard management controller, the server is controlled to restart.

12. The hot-swap control method according to claim 8, characterized in that: After the target device is controlled to be in a hot-plug state based on the status bit value of the interrupt status register, the method further includes: Get the device list; Whether the hot-swap state of the target device is successfully controlled is determined according to whether the target device exists in the device list.

13. The hot-swap control method according to claim 8, characterized in that: The controlling the target device to be in a hot-swap state comprises: The target device is controlled to be in a hot-swap state by utilizing a target control method in power management of the operating system.

14. The hot-swap control method according to claim 8, characterized in that: The controlling the target device to be in a hot-plug state based on the status bit value of the interrupt status register includes: The status bit of the interrupt status register is polled to determine the position of the target device, and the target device is controlled to be in a hot plug state.

15. The hot-swap control method according to claim 8, characterized in that: Determining the status bit value of the interrupt status register according to the interrupt signal status information, and controlling the target device to be in a hot plug state based on the status bit value of the interrupt status register, includes: According to the signal state of the level signal detected from the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device, the status bit value in the interrupt status register corresponding to the target device is changed, and the target device is controlled to be in a hot-plug state based on the status bit value of the interrupt status register corresponding to the target device; wherein the signal state of the level signal is generated by the baseboard management controller after changing the signal state of the level signal of the general input / output pin based on the trigger instruction of the target device, and then output to the system control interrupt pin of the peripheral interconnect component slot corresponding to the target device.

16. A baseboard management controller, characterized in that: include: A processor and a memory, wherein the processor executes the steps of the method according to any one of claims 1 to 7 by calling a program or instruction stored in the memory.

17. A central processing unit, characterized in that: include: A processor and a memory, wherein the processor executes the steps of the method according to any one of claims 8 to 15 by calling a program or instruction stored in the memory.

18. A hot-swap system, characterized in that: include: Baseboard management controller, central processing unit and peripheral interconnect component slots; The baseboard management controller and the central processing unit are both electrically connected to the peripheral interconnect component slot.

19. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the hot-swap control method according to any one of claims 1 to 7, or implements the steps of the hot-swap control method according to any one of claims 8 to 15.

20. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the steps of the hot-swap control method according to any one of claims 1 to 7, or implements the steps of the hot-swap control method according to any one of claims 8 to 15.

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