A method and device for inter-core communication based on virtual data bus

Abstract

A method for inter-core communication based on a virtual data bus, characterized in that it includes the following steps: Step 1, based on a multi-core processor, define data topology information for inter-core communication, and generate a multi-core resource configuration file based on the data topology information; Step 2, guide the master core to parse the multi-core resource configuration file, and create a data exchange pipeline in the inter-core shared space between the master core and multiple slave cores based on the parsing; Step 3, instruct the virtual data bus controller to implement the communication interaction of the inter-core communication data based on the data exchange pipeline and the business data type of the inter-core communication. Based on the method of the present invention, the business data of the inter-core communication can be divided according to type, and the routing table of the inter-core communication can be constructed through unified modeling, thereby realizing communication interaction.

Description

Technical Field

[0001] The present invention relates to inter-core communication of a multi-core processor, and more specifically, to an inter-core communication method and device based on a virtual data bus. Background Art

[0002] At present, with the continuous improvement of CPU performance requirements for various businesses, single-core processors can no longer meet business needs because the high-speed operation of their single-core chips will cause a lot of heat generation and performance degradation. Therefore, multi-core processors are increasingly being used in various industries. In the power industry, due to the more stringent requirements on the real-time and security of communications during the operation of the power grid, multi-core processors in the power industry usually run in AMP (Asymmetric Multi-processing) mode, and multiple cores can run different applications independently, and different applications can run without an operating system, thereby ensuring the real-time and reliability of program operation.

[0003] However, although this isolation design of using independent cores to run applications can improve the security of applications, it also increases the difficulty of inter-core data communication. Developers need to understand the target core and source core of inter-core communication, how to divide shared memory resources, and how to use shared memory to achieve inter-core application communication. For the above reasons, the overall design difficulty of the application increases. Due to the lack of a unified multi-core communication framework, the program cannot flexibly respond to business changes. In addition, when business data changes, the data of inter-core communication will also change, which also makes the communication program non-portable. At present, applications in multi-core processors running in AMP mode all implement multi-core communication based on shared memory and inter-core interrupts. However, this method can only meet the basic communication requirements of multi-core communication, and cannot simultaneously meet the needs of rapid inter-core deployment and flexible configuration of inter-core communication of power secondary equipment.

[0004] Therefore, there is an urgent need for a new inter-core communication method and device based on a virtual data bus. Summary of the invention

[0005] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide an inter-core communication method and device based on a virtual data bus, which can divide the business data of inter-core communication according to type, and construct a routing table for inter-core communication through unified modeling, thereby realizing communication interaction.

[0006] The present invention adopts the following technical scheme. The first aspect of the present invention relates to an inter-core communication method based on a virtual data bus, comprising the following steps: Step 1, based on a multi-core processor, defining data topology information of inter-core communication, and generating a multi-core resource configuration file according to the data topology information; Step 2, guiding the master core to parse the multi-core resource configuration file, and based on the parsing, creating a data exchange pipeline in the inter-core shared space of the master core and multiple slave cores; Step 3, instructing the virtual data bus controller to implement the communication interaction of the inter-core communication data based on the data exchange pipeline and the business data type of the inter-core communication.

[0007] Preferably, step 1 also includes: the data topology information of the inter-core communication is obtained based on the deployment requirement definition of the application service deployed in the master core or the slave core; the data topology information of the inter-core communication includes: pipeline information for receiving data, data type of the inter-core communication, and subscription relationship between the pipeline and the data type of the inter-core communication.

[0008] Preferably, step 2 also includes: the master core and the slave core are divided from a homogeneous multi-core processor running in an asymmetric multi-processing manner; and the master core is used to parse the multi-core resource configuration file and generate inter-core shared configuration information, and start the slave core of the homogeneous multi-core processor; the master core and the slave core generate a data exchange pipeline based on the inter-core shared configuration information.

[0009] Preferably, step 2 also includes: the pipeline is created in the data shared memory area of ​​the homogeneous multi-core processor based on the information in the multi-core resource configuration file; each pipeline occupies a memory space of a preset size in the data shared memory area of ​​the homogeneous multi-core processor.

[0010] Preferably, step 3 also includes: each master core and each slave core respectively has a corresponding virtual data bus controller; and the virtual data bus controller reads the inter-core shared configuration information obtained by the master core by parsing the multi-core resource configuration file, and constructs a data forwarding routing table based on the inter-core shared configuration information.

[0011] Preferably, step 3 also includes: the virtual data bus controller detects the inter-core communication data existing in the pipeline by polling; when the virtual data bus controller is in the data receiving state and detects the inter-core communication data existing in the pipeline, it triggers the current data receiving interruption; or, when the virtual data bus controller is in the data receiving state and detects the inter-core communication data existing in the pipeline, it triggers the inter-core communication data to suspend and wait.

[0012] Preferably, step 3 also includes: the virtual data bus controller queries the data forwarding routing table and obtains the sending pipeline of the business data; filters the current data based on the filtering rules of the sending pipeline of the business data, and sends the filtered business data to the sending pipeline.

[0013] Preferably, step 3 also includes: copying the filtered current data to the circular queue of the sending pipeline, and sending the data according to the status information of the sending pipeline.

[0014] The second aspect of the present invention relates to an inter-core communication device based on a virtual data bus, comprising a multi-core processor, multiple virtual data bus controllers and a virtual data bus, characterized in that: the multi-core processor is a homogeneous multi-core processor running based on an asymmetric multi-processing mode, and the processor includes a master core and multiple slave cores; each of the multiple virtual data bus controllers is interconnected with each core in the multi-core processor at one end and interconnected with the virtual data bus at the other end; the virtual data bus occupies a memory space of a preset size in the data shared memory area of ​​the homogeneous multi-core processor.

[0015] Preferably, the virtual data bus controller includes a routing table generation module, a sending module consisting of a routing forwarding submodule and a filtering submodule, and a receiving module; and the routing table generation module is used to build a routing table according to the received inter-core shared configuration information, and forward the routing table to the sending module; the routing forwarding submodule in the sending module is used to query the corresponding pipeline of the corresponding core or multiple cores that subscribe to the business data in the routing table according to the type of business data to be sent; the filtering submodule in the sending module is used to obtain the filtering rules of the corresponding pipeline according to the corresponding pipeline queried by the routing forwarding submodule, and filter the business data based on the filtering rules, and send the filtered business data to the sending pipeline; the receiving module is used to detect and receive the inter-core communication data existing in the pipeline.

[0016] The beneficial effect of the present invention is that, compared with the prior art, the inter-core communication method and device based on a virtual data bus in the present invention can divide the business data of inter-core communication according to type, and construct a routing table for inter-core communication through unified modeling, thereby realizing communication interaction.

[0017] The beneficial effects of the present invention also include:

[0018] 1. The framework of publishing and subscribing is adopted to realize the decoupling of applications between the sending core and the receiving core of multi-core data communication, which reduces the difficulty of managing shared data between cores during application development, avoids tedious and repetitive inter-core communication development work, and improves the reusability of technology;

[0019] 2. The use of a unified virtual bus controller reduces the difficulty of managing shared data between cores when developing multi-core applications on different cores, as well as the difficulty of developing multi-core programs, and improves the efficiency of inter-core communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a method flow of an inter-core communication method and device based on a virtual data bus according to the present invention;

[0021] Figure 2 It is a schematic diagram of the overall device of a method and device for inter-core communication based on a virtual data bus of the present invention;

[0022] Figure 3 The present invention is a schematic diagram of a virtual data bus controller in a method and device for inter-core communication based on a virtual data bus. DETAILED DESCRIPTION

[0023] The present application is further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present application.

[0024] Figure 1 The present invention is a method flow diagram of a method and device for inter-core communication based on a virtual data bus. Figure 1 As shown, the first aspect of the present invention relates to an inter-core communication method based on a virtual data bus, comprising steps 1 to 3.

[0025] Step 1: Based on a multi-core processor, define data topology information for inter-core communication, and generate a multi-core resource configuration file according to the data topology information.

[0026] In one embodiment of the present invention, electric power secondary equipment can be used, and a multi-core processor can be used to run in an AMP manner, with different applications running in each core. In the present invention, a deployment plan for a multi-core processor can be formulated according to the application business, and an application to be run can be assigned to each core. At the same time, the memory space of each core can also be defined, a location can be reserved for inter-core shared memory, and its memory address can be defined. In addition, the data topology information of multi-core communication can also be defined according to the business requirements of the application, so as to abstractly model the application business data that needs to communicate between cores.

[0027] It is worth noting that the business data of the multi-core application program's inter-core communication can be abstractly modeled according to the pre-defined application business requirements to form a topological relationship for the inter-core forwarding of the application business data. At the same time, the data pipeline configuration information can be defined according to the pre-defined data receiving requirements of the application.

[0028] Specifically, the data topology information of inter-core communication is obtained based on the deployment requirement definition of the application business deployed in the master core or the slave core; the data topology information of inter-core communication includes: pipeline information for receiving data, data type of inter-core communication, and subscription relationship between pipeline and data type of inter-core communication.

[0029] The pipeline information for receiving data may include subordinate core definition, pipeline depth, memory space occupied by the pipeline, data type defined by the pipeline, filtering rules for data type defined by the pipeline, and the like.

[0030] By generating data topology information of inter-core communication in the application business space, a multi-core resource configuration file can be generated. Generally, the generated multi-core resource configuration file can be deployed in the main core of the multi-core processor.

[0031] Step 2: guide the master core to parse the multi-core resource configuration file, and create a data exchange pipeline in the inter-core shared space of the master core and the multiple slave cores based on the parsing.

[0032] Specifically, the master core and the slave core are divided from a homogeneous multi-core processor that runs in an asymmetric multi-processing mode; and the master core is used to parse the multi-core resource configuration file and generate inter-core shared configuration information, and start the slave core of the homogeneous multi-core processor; the master core and the slave core generate a data exchange pipeline based on the inter-core shared configuration information.

[0033] When the main core of a multi-core processor is started, it will first parse the multi-core resource configuration file. As a resource management core, the main core can allocate space for different resources in the pre-planned inter-core shared memory space according to the resource configuration information contained in the multi-core resource configuration file. The process of allocating space is essentially the process of creating a pipeline in the pre-planned data shared memory area and determining the memory space occupied by the pipeline. Usually, in the process of allocating space, it is necessary to ensure that the address space occupied by each pipeline is independent.

[0034] Preferably, the pipeline is created in the data shared memory area of ​​the homogeneous multi-core processor based on the information in the multi-core resource configuration file; each pipeline occupies a preset size of memory space in the data shared memory area of ​​the homogeneous multi-core processor.

[0035] According to the subscription relationship between the pipeline in the multi-core resource configuration file and the inter-core communication data type, a data structure of the overall topology configuration information of the inter-core communication can also be generated in the configuration shared memory area predefined between the cores.

[0036] When the master core completes parsing of the multi-core resource configuration file, all shared memory resources can be allocated and slave core processors deployed by other applications can be started. After the slave core processors are started, the overall topology configuration information data structure of inter-core communication can be obtained from the shared memory.

[0037] Step 3, instructing the virtual data bus controller to implement communication interaction of inter-core communication data based on the data exchange pipeline and the service data type of the inter-core communication.

[0038] Preferably, each master core and each slave core has a corresponding virtual data bus controller; and the virtual data bus controller reads the inter-core shared configuration information obtained by the master core by parsing the multi-core resource configuration file, and constructs a data forwarding routing table based on the inter-core shared configuration information.

[0039] Generally, in the data forwarding routing table, there is a correspondence between the inter-core communication data and the receiving pipeline. In the data forwarding routing table, a key-value pair table can be constructed according to the inter-core communication data type as the key value and the pipeline number as the value. Among them, one type of inter-core communication data can be sent to one or more specific data channels.

[0040] When both the master core and the slave core have successfully obtained the overall topology configuration information of the inter-core communication, the virtual data bus controller running independently on each core can be initialized. Usually, each core is responsible for starting the virtual data bus controller that is interconnected with the core. The virtual data bus controller can read the inter-core shared configuration information in the predefined shared memory area, generate the multi-core communication data forwarding routing table of the virtual data bus controller, and complete the initialization of the virtual data bus controller. After the virtual data bus controller is started, it is responsible for sending and receiving the inter-core communication data transmitted on the virtual data bus.

[0041] Since, in the present invention, the virtual data bus controller running in each core can generate different types of inter-core communication data core pipeline mapping tables according to the multi-core resource configuration file, it is possible to implement inter-core data routing and forwarding, and complete one-to-one, many-to-many or many-to-one data interaction between multiple cores.

[0042] Preferably, the virtual data bus controller detects the inter-core communication data in the pipeline by polling; when the virtual data bus controller is in the data receiving state and detects the inter-core communication data in the pipeline, it triggers the current data receiving interrupt; or, when the virtual data bus controller is in the data receiving state and detects the inter-core communication data in the pipeline, it triggers the inter-core communication data to suspend and wait.

[0043] Usually, as a consumer of the pipeline, the virtual data bus controller can obtain data from the pipeline and is responsible for maintaining the read status in the pipeline status information to complete the actual dequeue operation of the data. The virtual data bus controller can provide an interrupt trigger mode for data reception, providing the application with the ability to quickly obtain data. When receiving data, the application can use two programming modes, polling and interrupt, according to the business needs of receiving data.

[0044] Among them, the polling mode refers to querying the data receiving pipeline that needs to receive business data through the receiving module to check whether there is new data to be received, so as to realize data polling reception. The interrupt mode refers to creating a task to receive data and suspending it, that is, blocking and waiting for new data from the data receiving pipeline. When new data arrives on the pipeline, the virtual data bus controller will generate a data receiving interrupt. The application can wake up the task of receiving data by responding to the interrupt and process the received data.

[0045] It is worth noting that the virtual data bus controller can also query whether the pipeline is configured with an interrupt trigger flag. If the flag is configured, the inter-core soft interrupt corresponding to the pipeline can be triggered, and the virtual bus controllers of other cores can be notified to trigger the receive data interrupt.

[0046] Preferably, the virtual data bus controller queries the data forwarding routing table and obtains the sending pipeline of the business data; filters the current data based on the filtering rules of the sending pipeline of the business data, and sends the filtered business data to the sending pipeline.

[0047] Preferably, the filtered current data can be copied to the circular queue of the sending pipeline, and data sending can be realized according to the state information of the sending pipeline. Specifically, sending data by means of a circular queue can better support the sending and receiving of edge length data. Usually, the pipeline state information and the actual data are stored in a shared memory. Sending data to a pipeline is actually copying the data to the circular queue corresponding to the pipeline. As the producer of the pipeline, the sending module can copy the sent data to the pipeline and update the write state of the pipeline state information at the same time to complete the actual enqueuing operation of the data.

[0048] The second aspect of the present invention relates to an inter-core communication device based on a virtual data bus, comprising a multi-core processor, a plurality of virtual data bus controllers and a virtual data bus. The multi-core processor is a homogeneous multi-core processor running in an asymmetric multi-processing mode, wherein the processor comprises a master core and a plurality of slave cores; each of the plurality of virtual data bus controllers is interconnected with each core in the multi-core processor at one end and interconnected with the virtual data bus at the other end; the virtual data bus occupies a preset size of memory space in the data shared memory area of ​​the homogeneous multi-core processor.

[0049] like Figure 1 and Figure 2 As shown, the virtual data bus controller, as an important inter-core communication component, can operate normally regardless of whether there is an operating system in the multi-core processor, so it has good portability.

[0050] Preferably, the virtual data bus controller includes a routing table generation module, a sending module consisting of a routing forwarding submodule and a filtering submodule, and a receiving module; and the routing table generation module is used to build a routing table according to the received inter-core shared configuration information, and forward the routing table to the sending module; the routing forwarding submodule in the sending module is used to query the corresponding pipeline of the corresponding core or multiple cores that subscribe to the business data in the routing table according to the type of business data to be sent; the filtering submodule in the sending module is used to obtain the filtering rules of the corresponding pipeline according to the corresponding pipeline queried by the routing forwarding submodule, and filter the business data based on the filtering rules, and send the filtered business data to the sending pipeline; the receiving module is used to detect and receive the inter-core communication data existing in the pipeline.

[0051] The beneficial effect of the present invention is that, compared with the prior art, the inter-core communication method and device based on a virtual data bus in the present invention can divide the business data of inter-core communication according to type, and construct a routing table for inter-core communication through unified modeling, thereby realizing communication interaction.

[0052] The beneficial effects of the present invention also include:

[0053] 1. The framework of publishing and subscribing is adopted to realize the decoupling of applications between the sending core and the receiving core of multi-core data communication, which reduces the difficulty of managing shared data between cores during application development, avoids tedious and repetitive inter-core communication development work, and improves the reusability of technology;

[0054] 2. The use of a unified virtual bus controller reduces the difficulty of managing shared data between cores when developing multi-core applications on different cores, as well as the difficulty of developing multi-core programs, and improves the efficiency of inter-core communication.

[0055] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, but not to limit the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A method for inter-core communication based on a virtual data bus, characterized in that: The following steps are involved: Step 1: Based on a multi-core processor, define data topology information for inter-core communication, and generate a multi-core resource configuration file according to the data topology information; Step 2, guiding the master core to parse the multi-core resource configuration file, and based on the parsing, creating a data exchange pipeline in the inter-core shared space of the master core and the plurality of slave cores; Step 3, instructing the virtual data bus controller to implement communication interaction of the inter-core communication data based on the data exchange pipeline and the business data type of the inter-core communication.

2. According to the inter-core communication method based on virtual data bus described in claim 1, it is characterized in that: The step 1 also includes: The data topology information of the inter-core communication is obtained based on the deployment requirement definition of the application service deployed in the master core or the slave core; The data topology information of the inter-core communication includes: pipeline information for receiving data, data type of the inter-core communication, and a subscription relationship between the pipeline and the data type of the inter-core communication.

3. According to the inter-core communication method based on virtual data bus described in claim 1, it is characterized in that: The step 2 also includes: The master core and the slave core are divided from a homogeneous multi-core processor running in an asymmetric multi-processing manner; and The master core is used to parse the multi-core resource configuration file and generate inter-core sharing configuration information, and start the slave cores of the homogeneous multi-core processor; The master core and the slave core generate a data exchange pipeline based on the inter-core shared configuration information.

4. According to the inter-core communication method based on virtual data bus as described in claim 3, it is characterized in that: The step 2 also includes: The pipeline is created in the data shared memory area of ​​the homogeneous multi-core processor based on the information in the multi-core resource configuration file; Each pipeline occupies a memory space of a preset size in the data shared memory area of ​​the homogeneous multi-core processor.

5. The inter-core communication method based on a virtual data bus according to claim 1, characterized in that: The step 3 also includes: Each master core and each slave core has a corresponding virtual data bus controller; and, The virtual data bus controller reads the inter-core shared configuration information obtained by the master core through parsing the multi-core resource configuration file, and constructs a data forwarding routing table based on the inter-core shared configuration information.

6. The inter-core communication method based on a virtual data bus according to claim 5, characterized in that: The step 3 also includes: The virtual data bus controller detects the inter-core communication data existing in the pipeline by polling; When the virtual data bus controller is in a data receiving state and detects the inter-core communication data in the pipeline, a current data receiving interrupt is triggered; or, When the virtual data bus controller is in a data receiving state and detects the inter-core communication data in the pipeline, the inter-core communication data is triggered to suspend and wait.

7. The inter-core communication method based on a virtual data bus according to claim 5, characterized in that: The step 3 also includes: The virtual data bus controller queries the data forwarding routing table and obtains a sending channel for the service data; The current data is filtered based on the filtering rules of the sending pipeline of the business data, and the filtered business data is sent to the sending pipeline.

8. The inter-core communication method based on a virtual data bus according to claim 7, characterized in that: The step 3 also includes: The filtered current data is copied to the circular queue of the sending pipeline, and data sending is implemented according to the state information of the sending pipeline.

9. An inter-core communication device based on a virtual data bus, comprising a multi-core processor, a plurality of virtual data bus controllers and a virtual data bus, characterized in that: The device is implemented by an inter-core communication system based on a virtual data bus as described in any one of claims 1 to 8; The multi-core processor is a homogeneous multi-core processor running in an asymmetric multi-processing mode, and the processor includes a master core and multiple slave cores; Each of the plurality of virtual data bus controllers has one end interconnected with each core of the multi-core processor and the other end interconnected with the virtual data bus; The virtual data bus occupies a memory space of a preset size in the data shared memory area of ​​the homogeneous multi-core processor.

10. The inter-core communication device based on a virtual data bus according to claim 9, characterized in that: The virtual data bus controller includes a routing table generating module, a sending module composed of a routing forwarding submodule and a filtering submodule, and a receiving module; and, The routing table generating module is used to construct a routing table according to the received inter-core shared configuration information, and forward the routing table to the sending module; The routing forwarding submodule in the sending module is used to query the corresponding pipeline of the corresponding core or multiple cores subscribing to the service data in the routing table according to the type of service data to be sent; The filtering submodule in the sending module is used to obtain the filtering rules of the corresponding pipeline according to the corresponding pipeline queried by the routing forwarding submodule, filter the business data based on the filtering rules, and send the filtered business data to the sending pipeline; The receiving module is used to detect and receive the inter-core communication data existing in the pipeline.

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