Embedded component package structure and method of manufacturing the same
By using encapsulating materials and dry sandblasting technology, a thicker dielectric structure is formed, which solves the chip warpage problem caused by the thickness limitation of resin sheets, and achieves higher electrical insulation and anti-inductive coupling, making it suitable for 5G communication component packaging.
CN112466833BActive Publication Date: 2026-06-26ADVANCED SEMICON ENG INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ADVANCED SEMICON ENG INC
- Filing Date
- 2019-11-12
- Publication Date
- 2026-06-26
AI Technical Summary
Technical Problem
In the prior art, the thickness limitation of the resin sheet cannot provide a sufficiently thick dielectric structure, causing the semiconductor chip to warp after thinning, resulting in difficulties in subsequent processes.
Method used
A sealing material is used to replace the resin sheet to form a thicker dielectric structure, and openings are formed by dry sandblasting to expose the electrical pads. A patterned conductive layer is then combined to achieve electrical connection.
Benefits of technology
It solves the chip warpage problem, improves the thickness and electrical insulation of the dielectric structure, reduces inductive coupling interference, and is suitable for component packaging for 5G communication technology.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN112466833B_ABST
Abstract
An embedded component package structure and a method for fabricating the same. The embedded component package structure includes a dielectric structure, a semiconductor chip and a patterned conductive layer. The semiconductor chip is embedded in the dielectric structure, the dielectric structure covers the semiconductor chip and has a first thickness, the semiconductor chip has a second thickness, the first thickness is greater than the second thickness, and the ratio of the first thickness to the second thickness is between 1.1 and 28.4. The patterned conductive layer covers an upper surface of the dielectric structure and extends into a first opening of the dielectric structure, the first opening exposes an electrical contact pad of the semiconductor chip, and the patterned conductive layer is electrically connected to the electrical contact pad of the semiconductor chip.
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