Semiconductor device and method for preparing semiconductor device

Abstract

The present invention discloses a semiconductor device and a method for preparing a semiconductor device. The semiconductor device is provided with a contact pad structure in a contact hole. The contact pad structure is configured to include a first contact pad, a second contact pad conformally covering the first contact pad, and a contact plug located on the second contact pad. The first contact pad is in full contact with an active area in a substrate, which can effectively reduce the contact resistance. Moreover, by providing a contact pad with a stacked structure, the first contact pad can serve as a buffer layer for the second contact pad, thereby preventing doped ions in the second contact pad from penetrating into the substrate and affecting the conductivity. In addition, a gap in the contact hole is formed between the first contact pad and a side wall of the contact hole, which can effectively reduce the influence of the gap on the conductivity, thereby greatly improving the conductive properties of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] With technological advancements, the demand for miniaturized semiconductor devices has led to a gradual increase in their integration level. This increased integration requires a reduction in the size of contact holes within semiconductor devices. However, smaller contact holes have larger aspect ratios, making it difficult to control the bottom morphology of the contact holes during fabrication, leading to deformation or oxidation. Consequently, when forming contact pad structures within contact holes with large aspect ratios, the bottom of the contact pad structures suffers from poor contact with the active area exposed by the contact holes, resulting in poor conductivity and a significant impact on semiconductor device performance. Summary of the Invention

[0003] The technical problem to be solved by the present invention is: in a semiconductor device having a contact hole with a large aspect ratio, how to achieve effective contact between the contact pad structure and the active area, so as to greatly improve the conductive characteristics of the semiconductor device.

[0004] In order to solve the above technical problems, the present invention provides a semiconductor device and a method for preparing the semiconductor device.

[0005] A first aspect of the present invention provides a semiconductor device comprising:

[0006] A substrate, the substrate comprising at least an active area and a shallow trench isolation area;

[0007] a bit line structure, the bit line structure being located on the substrate and extending in a first direction;

[0008] Isolation fences, the isolation fences being located between adjacent bit line structures and spaced apart in the first direction;

[0009] a contact hole located in an area defined by the bit line structure adjacent to the second direction and adjacent to the isolation fence in the first direction, wherein the second direction is perpendicular to the first direction, and a bottom of the contact hole extends into the substrate and exposes at least a portion of the active area and a portion of the shallow trench isolation area;

[0010] A contact pad structure is located in the contact hole, and the contact pad structure includes a first contact pad, a second contact pad conformally covering the first contact pad, and a contact plug located on the second contact pad, wherein a gap is formed between the first contact pad and a side wall of the contact hole.

[0011] Optionally, the first contact pad and the second contact pad have different chemical compositions.

[0012] Optionally, the first contact pad contacts a portion of the substrate surface of the contact hole.

[0013] Optionally, the bottom of the first contact pad only contacts the active area.

[0014] Optionally, the contact plug covers the second contact pad and contacts a portion of the surface of the first contact pad.

[0015] Optionally, the contact plug includes a first contact plug and a second contact plug located on the first contact plug.

[0016] Optionally, the contact pad structure further includes: a heavily doped semiconductor layer located between the first contact plug and the second contact plug.

[0017] Optionally, the bit line structure includes: a bit line and an insulating dielectric layer located on the bit line;

[0018] The upper surface of the second contact pad is higher than the lower surface of the bit line, and the upper surface of the first contact plug is higher than the upper surface of the bit line.

[0019] A second aspect of the present invention provides a method for preparing a semiconductor device, comprising:

[0020] forming a bit line structure extending along a first direction on a substrate, wherein the substrate includes at least an active area and a shallow trench isolation area, and the bit line structures are arranged at intervals in a second direction, the second direction being perpendicular to the first direction;

[0021] Etching the substrate between adjacent bit line structures to form a contact opening extending into the substrate and exposing at least a portion of the active area and a portion of the shallow trench isolation region;

[0022] forming isolation fences in the contact opening, wherein the isolation fences are spaced apart in the first direction to isolate the contact opening into a plurality of contact holes;

[0023] Pre-treating the bottom of the contact hole by using germane gas;

[0024] forming a first contact pad in the contact hole after the pretreatment;

[0025] forming a second contact pad on the first contact pad to conformally cover the first contact pad, with a gap formed between the first contact pad and a side wall of the contact hole;

[0026] A contact plug is formed in the contact hole.

[0027] Optionally, forming a first contact pad in the contact hole after the pre-processing includes:

[0028] A first contact pad is formed in the pre-processed contact hole, wherein the first contact pad contacts a portion of the substrate surface in the contact hole.

[0029] Optionally, forming a first contact pad in the contact hole after the pretreatment, wherein the first contact pad contacts a portion of the substrate surface of the contact hole, includes:

[0030] forming the first contact pad on the pre-treated active area in the contact hole by a selective epitaxial growth process;

[0031] Forming a second contact pad on the first contact pad to conformally cover the first contact pad, comprising:

[0032] A selective epitaxial growth process is used to form the second contact pad on the first contact pad and conformally cover the first contact pad, wherein the first contact pad and the second contact pad have different chemical compositions.

[0033] Optionally, forming a contact plug in the contact hole includes: forming the contact plug in the contact hole to cover the second contact pad and to contact a portion of the surface of the first contact pad.

[0034] Optionally, forming a contact plug in the contact hole includes:

[0035] A polysilicon layer, a metal silicide or a metal layer is formed in the contact hole as a first contact plug, and a metal layer is deposited in the contact hole to form a second contact plug covering the first contact plug.

[0036] Optionally, when the first contact plug and the second contact pad are made of the same material, a growth rate of the first contact plug is greater than a growth rate of the second contact pad.

[0037] Optionally, after forming a polysilicon layer, a metal silicide or a metal layer in the contact hole as a first contact plug, the method further includes:

[0038] A heavily doped semiconductor layer is deposited to cover the first contact plug.

[0039] Optionally, the bit line structure includes: a bit line and an insulating dielectric layer located on the bit line;

[0040] The upper surface of the second contact pad is higher than the lower surface of the bit line, and the upper surface of the first contact plug is higher than the upper surface of the bit line.

[0041] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects:

[0042] The semiconductor device and semiconductor device preparation method provided by the present invention are applied. The semiconductor device is provided with a contact pad structure in a contact hole. The contact pad structure is configured to include a first contact pad, a second contact pad conformally covering the first contact pad, and a contact plug located on the second contact pad. The first contact pad is in full contact with the active area in the substrate, which can effectively reduce the contact resistance. Moreover, by providing a contact pad with a stacked structure, the first contact pad can serve as a buffer layer for the second contact pad, preventing the doped ions in the second contact pad from penetrating into the substrate and affecting the conductivity. In addition, a gap in the contact hole is formed between the first contact pad and one side wall of the contact hole, which can effectively reduce the influence of the gap on the conductivity, thereby greatly improving the conductive characteristics of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings, which include:

[0044] Figure 1 FIG2 shows a schematic top view of a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 2A The embodiment of the present invention provides Figure 1 Schematic diagram of the cross-sectional structure along line A-A'; Figure 2B Another embodiment of the present invention provides a Figure 1 Schematic diagram of the cross-sectional structure along line A-A'; Figure 2C Another embodiment of the present invention provides a Figure 1 Schematic diagram of the cross-sectional structure along line A-A';

[0046] Figure 3 The embodiment of the present invention provides Figure 1 Schematic diagram of the cross-sectional structure along line BB';

[0047] Figure 4 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown;

[0048] Figure 5A 1 shows a schematic diagram of the top structure of the substrate 10; Figure 5B Shown along Figure 5A Schematic diagram of the cross-sectional structure along line A-A'; Figure 5C Shown along Figure 5A Schematic diagram of the cross-sectional structure along line BB';

[0049] Figure 6AA schematic diagram of a top view of a semiconductor device having a bit line structure is shown; Figure 6B Shown along Figure 6A Schematic diagram of the cross-sectional structure along line A-A'; Figure 6C Shown along Figure 6B Schematic diagram of the cross-sectional structure along line BB';

[0050] Figure 7A A schematic diagram of a top view of a semiconductor device having contact openings formed therein is shown; Figure 7B Shown along Figure 7A Schematic diagram of the cross-sectional structure along line A-A'; Figure 7C Shown along Figure 7A Schematic diagram of the cross-sectional structure along line BB';

[0051] Figure 8A 1 shows a schematic top view of the structure of a semiconductor device having a contact hole 15 formed therein; Figure 8B Shown along Figure 8A Schematic diagram of the cross-sectional structure along line A-A'; Figure 8C Shown along Figure 8A Schematic diagram of the cross-sectional structure along line BB';

[0052] Figure 9A shows a schematic cross-sectional structure diagram of a semiconductor device having a first contact pad 161 formed along line AA'; Figure 9B shows a schematic cross-sectional structure diagram of a semiconductor device having a first contact pad 161 formed along line BB';

[0053] Figure 10A 1 shows a schematic cross-sectional structure diagram of a semiconductor device having a second contact pad 162 formed along line AA'; Figure 10B shows a schematic cross-sectional structure diagram of a semiconductor device having a second contact pad 162 formed along line BB';

[0054] Figure 11A FIG. 1 shows a schematic top view of the structure of a semiconductor device having contact plugs 163 formed thereon; Figure 11B Shown along Figure 11A Schematic diagram of the cross-sectional structure along line A-A'; Figure 11C Shown along Figure 11A Schematic diagram of the cross-sectional structure along line BB'. DETAILED DESCRIPTION

[0055] In order to make the objectives, technical solutions and advantages of the present invention clearer, the implementation method of the present invention will be described in detail below with reference to the accompanying drawings and embodiments, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly.

[0056] With technological advancements, the demand for miniaturized semiconductor devices has led to a gradual increase in their integration level. This increased integration requires a reduction in the size of contact holes within semiconductor devices. However, smaller contact holes have larger aspect ratios, making it difficult to control the bottom morphology of the contact holes during fabrication, leading to deformation or oxidation. Consequently, when forming contact pad structures within contact holes with large aspect ratios, the bottom of the contact pad structures suffers from poor contact with the active area exposed by the contact holes, resulting in poor conductivity and a significant impact on semiconductor device performance.

[0057] In view of this, the present invention provides a semiconductor device and a method for preparing a semiconductor device, wherein a contact pad structure is provided in a contact hole of the semiconductor device, and the contact pad structure is configured to include a first contact pad, a second contact pad conformally covering the first contact pad, and a contact plug located on the second contact pad. The first contact pad is in full contact with the active area in the substrate, which can effectively reduce the contact resistance. Moreover, by providing a contact pad with a stacked structure, the first contact pad can serve as a buffer layer for the second contact pad, thereby preventing the doped ions in the second contact pad from penetrating into the substrate and affecting the conductivity. In addition, a gap in the contact hole is formed between the first contact pad and one side wall of the contact hole, which can effectively reduce the influence of the gap on the conductivity, thereby greatly improving the conductive properties of the semiconductor device.

[0058] Example 1

[0059] See also Figure 1 As shown, Figure 1 A schematic diagram of a top view of a semiconductor device provided by an embodiment of the present invention is shown, which includes:

[0060] A substrate 10, the substrate 10 at least including an active region 11 and a shallow trench isolation region 12;

[0061] A bit line structure 13, the bit line structure 13 is located on the substrate 10 and extends in a first direction;

[0062] Isolation fences 14, the isolation fences 14 are located between adjacent bit line structures 13 and spaced apart in a first direction;

[0063] a contact hole 15, the contact hole 15 being located in a region defined by the bit line structure 13 adjacent in the second direction and the isolation fence 14 adjacent in the first direction, wherein the second direction is perpendicular to the first direction, and the bottom of the contact hole 15 extending into the substrate 10 and exposing at least a portion of the active area 11 and a portion of the shallow trench isolation region 12;

[0064] The contact pad structure 16 is located in the contact hole 15 and includes a first contact pad 161, a second contact pad 162 conformally covering the first contact pad 161, and a contact plug 163 located on the second contact pad 162. A gap 17 is formed between the first contact pad 161 and a side wall of the contact hole 15.

[0065] The substrate 10 may include a semiconductor substrate, for example, a silicon substrate, a silicon-germanium substrate, or a silicon-on-insulator substrate. The substrate 10 may include an active region 11 and shallow trench isolation regions 12. The shallow trench isolation regions 12 may define the active region 11 into a plurality of regions.

[0066] In an embodiment of the present invention, D1 can be used to represent a first direction, and D2 can be used to represent a second direction perpendicular to the first direction. The bitline structure 13 extends in the D1 direction, and multiple bitline structures are arranged at intervals in the D2 direction. As an example, the bitline structure 13 may include a bitline 131 and an insulating dielectric layer 132 located on the bitline 131, wherein a portion of the bitline structure 13 may contact the substrate 10 through a bitline contact plug 133, and the bitline contact plug 133 is disposed in a bitline contact hole 133' inside the substrate 10, and the bitline contact hole 133' may have a lateral dimension wider than the bitline contact plug 133. In addition, a bitline insulating layer 134 may be provided, which conformally covers the bitline structure 13 and fills the gap between the bitline contact plug 133 and the bitline contact hole 133'. The upper surface of the bitline contact plug 133 may be at the same height as the upper surface of the substrate 10. For details, see Figure 2A or Figure 2B As shown, Figure 2A The embodiment of the present invention provides Figure 1 Schematic diagram of the cross-sectional structure along line A-A'. Figure 2B Another embodiment of the present invention provides a Figure 1 The cross-sectional structure diagram of the A-A' line in FIG. Figure 2A and Figure 2B In order to facilitate observation, the size of the gap 17 is enlarged, and the size of the gap 17 is not specifically limited.

[0067] As an example, the isolation fence 14 may be formed by depositing an insulating material. Specifically, the isolation fence 14 may be formed by depositing silicon nitride.

[0068] It should be noted that the isolation fence 14 can be formed before or after the contact hole 15 is formed. In the embodiment of the present invention, the isolation fence 14 will be described as being formed after the contact hole 15 is formed. Figure 3 The embodiment of the present invention provides Figure 1Schematic diagram of the cross-sectional structure along line BB'.

[0069] See also Figure 2A or Figure 2B As shown, contact pad structure 16 is located within contact hole 15. As an example, before depositing first contact pad 161, contact hole 15 can be pretreated using germane gas to remove impurities from the upper surface of active area 11 within contact hole 15, ensuring good contact between first contact pad 161 and active area 11 and improving conductivity. First contact pad 161 is then formed within pretreated contact hole 15 using chemical vapor deposition or physical vapor deposition. By selecting appropriate deposition conditions, first contact pad 161 can be controlled to contact a portion of the substrate surface within contact hole 15. As an example, first contact pad 161 can contact active area 11 and a portion of the surface of shallow trench isolation region 12 within contact hole 15 (not shown). As another example, first contact pad 161 can be formed on the pretreated active area 11 within contact hole 15 using a selective epitaxial growth process, where first contact pad 161 only contacts active area 11.

[0070] In addition, in the embodiment of the present invention, a polygonal first contact pad 161 having a planar top surface can be formed by controlling the growth rate along different directions. In other embodiments, a first contact pad 161 having an elliptical cross-section with a gap between the first contact pad 161 and the sidewall of the contact hole 15 can also be formed. The first contact pad 161 can include a silicon germanium layer, and can also be an n-type doped silicon germanium layer.

[0071] The second contact pad 162 conformally covers the first contact pad 161. For example, the second contact pad 162 can be formed on the upper surface of the first contact pad 161 via a selective epitaxial growth process. The upper surface of the second contact pad 162 can be higher than the lower surface of the bitline structure 13. The second contact pad 162 can have a different chemical composition from the first contact pad 161. For example, the second contact pad 162 can be formed of a different material than the first contact pad 161, or it can be formed of the same material as the first contact pad 161 but with a different ion doping concentration. As a specific example, the second contact pad 162 can include a silicon phosphide layer. By forming the first contact pad 161 via a selective epitaxial growth process, the bottom of the first contact pad 161 contacts only the active area 11. After the second contact pad 162 is formed via the selective epitaxial growth process, a gap is formed between the first contact pad 161 and the second contact pad 162 and a sidewall of the contact hole 15. In this structure, the first contact pad 161 can serve as a buffer layer for the second contact pad 162, preventing the doped ions in the second contact pad 162 from penetrating into the substrate and affecting the conductivity. The gap 17 in the contact hole 15 is located between the first contact pad 162 and one side wall of the contact hole 15, which can effectively reduce the impact of the gap 17 on the conductivity, thereby greatly improving the performance of the semiconductor device.

[0072] In the embodiment of the present invention, since the first contact pad 161 contacts a portion of the substrate surface of the contact hole 15, after the first contact pad 161 and the second contact pad 162 are formed, a gap is formed between the first contact pad 161 and a sidewall of the contact hole 15 and the bottom surface of the contact hole 15. When the contact plug 163 is subsequently formed using a deposition process, the gap may not be completely filled. As an example, a chemical vapor deposition or physical vapor deposition process can be used to form the contact plug 163 on the second contact pad 162. By controlling the process conditions, the contact plug 163 can be formed to only cover a portion of the surface of the second contact pad 162, forming a gap 17 between the first contact pad 161, the second contact pad 162, and the contact hole 15. For details, see Figure 2A As another example, a deposition process with good step coverage can be selected to form a contact plug 163 on the second contact pad 162. The contact plug 163 covers the second contact pad 162 and contacts a portion of the first contact pad 161, partially filling the gap between the first contact pad 161, the second contact pad 162, and the contact hole 15. A gap 17 is still retained between the first contact pad 161 and the bottom of the contact hole 15. For details, see Figure 2B shown.

[0073] As an example, the contact plug 163 may include a first contact plug 1631 and a second contact plug 1632 located on the first contact plug 1631, wherein the upper surface of the first contact plug 1631 may be set to be higher than the upper surface of the bit line 131, so that the contact interface between the first contact plug 1631 and the second contact plug 1632 is higher than the bit line 131, thereby preventing ions at the contact interface from penetrating into the bit line 131 and affecting device performance.

[0074] In an embodiment of the present invention, the first contact plug 1631 may include a polysilicon layer, a metal silicide or a metal layer, and the second contact plug 1632 may include a metal layer. As a specific example, the first contact plug 1631 may be a silicon phosphide layer, and the second contact plug 1632 may be metal tungsten.

[0075] As another example, see Figure 2C As shown, Figure 2C Another embodiment of the present invention provides a Figure 1 In the cross-sectional structural diagram of the A-A' line, the contact pad structure 16 may further include a semiconductor heavily doped layer 18 located between the first contact plug 1631 and the second contact plug 1632. By setting the semiconductor heavily doped layer, the contact resistance between the first contact plug 1631 and the second contact plug 1632 can be effectively reduced.

[0076] The above is a semiconductor device provided by an embodiment of the present invention. The semiconductor device is provided with a contact pad structure 16 in the contact hole 15. The contact pad structure 16 is configured to include a first contact pad 161, a second contact pad 162 that conformally covers the first contact pad 161, and a contact plug 163 located on the second contact pad 162. The first contact pad 161 is in full contact with the active area 11 in the substrate 10, which can effectively reduce the contact resistance. Moreover, by providing a contact pad with a stacked structure, the first contact pad 161 can serve as a buffer layer for the second contact pad 162, thereby preventing the doped ions in the second contact pad 162 from penetrating into the substrate 10 and affecting the conductivity. In addition, the gap 17 in the contact hole 15 is formed between the first contact pad 161 and one side wall of the contact hole 15, which can effectively reduce the influence of the gap 17 on the conductivity, thereby greatly improving the conductive characteristics of the semiconductor device.

[0077] Another aspect of the present invention provides a method for preparing a semiconductor device. Please refer to the description in the second embodiment for details.

[0078] Example 2

[0079] See also Figure 4 As shown, Figure 4 The figure shows a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, which includes:

[0080] Step S401: forming a bit line structure 13 extending along a first direction on a substrate 10, wherein the substrate 10 includes at least an active area 11 and a shallow trench isolation area 12, and the bit line structures 13 are arranged at intervals in a second direction perpendicular to the first direction.

[0081] Step S402 : etching the substrate 10 between adjacent bit line structures 13 to form a contact opening extending into the substrate 10 and exposing at least a portion of the active area 11 and a portion of the shallow trench isolation region 12 ;

[0082] Step S403 : forming isolation fences 14 in the contact opening. The isolation fences 14 are spaced apart in the first direction to isolate the contact opening into a plurality of contact holes 15 .

[0083] Step S404 : pre-treating the bottom of the contact hole 15 with germane gas.

[0084] Step S405 : forming a first contact pad 161 in the pre-processed contact hole 15 .

[0085] Step S406 : forming a second contact pad 162 on the first contact pad 161 to conformally cover the first contact pad 161 , with a gap 17 formed between the first contact pad 161 and a sidewall of the contact hole 15 .

[0086] Step S407 : forming a contact plug 163 in the contact hole 15 .

[0087] Among them, see Figure 5A and Figure 5B As shown, Figure 5A 1 shows a schematic diagram of the top structure of the substrate 10, Figure 5B Shown along Figure 5A In the cross-sectional structural diagram along line AA', substrate 10 may include a semiconductor substrate. Specifically, substrate 10 may include a silicon substrate, a silicon-germanium substrate, or a silicon-on-insulator substrate. Substrate 10 may include an active region 11 and shallow trench isolation regions 12. Shallow trench isolation regions 12 may define active region 11 into multiple regions.

[0088] In the embodiment of the present invention, D1 may be used to represent a first direction, and D2 may be used to represent a second direction perpendicular to the first direction. Figure 5C As shown, Figure 5C Shown along Figure 5AA schematic cross-sectional structure diagram of line BB' is shown. A buried word line structure 19 may also be provided in substrate 10. Buried word line structure 19 extends in direction D2 and may include a word line 191 and an insulating isolation layer 192 located above word line 191. Buried word line structure 19 may be implemented using conventional methods in the art and will not be described further herein for the sake of brevity. Furthermore, a dielectric layer 193 may be provided outside buried word line structure 19. This dielectric layer 193 may be an oxide layer or a nitride layer.

[0089] Step S401 may specifically include depositing a hard mask layer on the substrate 10 and patterning the hard mask layer; etching the substrate 10 using the patterned hard mask layer as a mask to form a bit line contact hole 133' in the substrate 10; depositing a conductive material covering the bit line contact hole 133', wherein the upper surface of the conductive material may be at the same height as the upper surface of the substrate 10; then depositing a conductive layer covering the substrate 10 and the conductive material and a hard mask layer covering the conductive layer; patterning the hard mask layer and etching the conductive layer and the conductive material in the bit line contact hole 133' using the patterned hard mask layer as a mask to form a bit line structure 13 extending in the D1 direction, wherein the patterned conductive layer serves as the bit line 131, the patterned hard mask layer serves as the insulating dielectric layer 132, and the patterned conductive material serves as the bit line contact plug 133. In addition, a bit line insulating layer 134 may be conformally deposited, see Figures 6A-6C As shown, Figure 6A shows a schematic top view of the bit line structure, Figure 6B Shown along Figure 6A Schematic diagram of the cross-sectional structure along line A-A'. Figure 6C Shown along Figure 6B In the cross-sectional structural diagram along line BB', the bit line structure 13 and the bit line contact plug 133 may have the same line width in the direction D2, and the conformally deposited bit line insulation layer 134 may also fill the gap between the bit line contact plug 133 and the bit line contact hole 133'.

[0090] Step S402 may specifically include etching the substrate 10 between adjacent bit line structures 13 using a wet etching or dry etching process to form a contact opening extending into the substrate 10 and exposing at least a portion of the active area 11 and a portion of the shallow trench isolation area 12. Figures 7A-7C As shown, Figure 7A FIG. 1 shows a schematic top view of a semiconductor device having contact openings formed therein. Figure 7B Shown along Figure 7A Schematic diagram of the cross-sectional structure along line A-A'. Figure 7C Shown along Figure 7AThe line width of the contact opening along the D1 direction may be the distance between the bit line insulation layers 134 of adjacent bit line structures 13. In other embodiments, the line width of the contact opening along the D1 direction may also be smaller than the distance between the bit line insulation layers 134 of adjacent bit line structures 13.

[0091] Step S403 may specifically include depositing an isolation material layer 14' in the contact opening. The isolation material layer 14' may have the same height as the bit line insulation layer 134 on the top surface of the bit line structure 13; depositing a mask layer covering the bit line insulation layer 134 and the isolation material layer 14', patterning the mask layer, and etching the isolation material layer 14' using the patterned mask layer as a mask to form isolation fences 14 spaced apart in the first direction. Adjacent bit line structures 13 in the D2 direction and adjacent isolation fences 14 in the D1 direction may isolate the contact opening into a plurality of contact holes 15. For details, see Figures 8A-8C As shown, Figure 8A FIG. 1 shows a schematic top view of a semiconductor device having a contact hole 15 formed therein. Figure 8B Shown along Figure 8A Schematic diagram of the cross-sectional structure along line A-A'. Figure 8C Shown along Figure 8A Schematic diagram of the cross-sectional structure along line BB'.

[0092] The isolation material layer 14 ′ may be an insulating material layer. As a specific example, the isolation material layer 14 ′ may be a silicon nitride layer.

[0093] Step S404 may specifically involve introducing germane gas to pre-treat the bottom of the contact hole 15. The active area 11 exposed in the contact hole 15 is easily oxidized to form an insulating layer. For example, when the substrate 10 is a silicon layer, silicon oxide will form on the upper surface of the active area 11. The germanium atoms in the germane gas can break the silicon-oxygen bonds to form easily volatile germanium oxide, thereby removing the insulating material in the active area 11 and promoting good electrical conductivity between the contact pad and the active area 11.

[0094] Step S405 can specifically be to form a first contact pad 161 in the pre-treated contact hole 15 using a chemical vapor deposition or physical vapor deposition process, wherein the first contact pad 161 can be controlled to contact a portion of the substrate surface of the contact hole 15 by selecting appropriate deposition conditions. As an example, the first contact pad 161 can contact the active area 11 in the contact hole 15 and a portion of the surface of the shallow trench isolation region 12 (not shown in the figure); as another example, the first contact pad 161 can be formed on the pre-treated active area 11 in the contact hole 15 using a selective epitaxial growth process, wherein the first contact pad 161 only contacts the active area 11. As a specific example, silane and germane are used as precursors to form the first contact pad 161 on the pre-treated active area 11 in the contact hole 15 using a selective epitaxial growth process. In addition, the first contact pad 161 can be controlled to have a polygonal cross-section along the D2 direction by optimizing the growth conditions. By using the selective epitaxial growth process, the bottom of the first contact pad 161 only contacts the active area 11. For details, please refer to Figure 9A As shown, Figure 9A shows a schematic cross-sectional structure diagram of a semiconductor device having a first contact pad 161 formed along line AA'; Figure 9B A schematic cross-sectional structure diagram of a semiconductor device with a first contact pad 161 formed along line BB′ is shown.

[0095] Step S406 may specifically include forming a second contact pad 162 on the first contact pad 161 to conformally cover the first contact pad 161 using a selective epitaxial growth process. The second contact pad 162 may have a different chemical composition from the first contact pad 161. For example, the second contact pad 162 may be formed of a material different from that of the first contact pad 161. The second contact pad 162 may also be formed of a material that is the same as that of the first contact pad 161 but has a different ion doping concentration. As a specific example, a selective epitaxial growth process is used with silane and phosphine as precursors to form the second contact pad 162 on the first contact pad 161 to conformally cover the first contact pad 161. For details, please refer to Figure 10A As shown, Figure 10A FIG2 shows a schematic cross-sectional structure diagram of a semiconductor device having a second contact pad 162 formed along line AA'. As an example, the upper surface of the second contact pad 162 may be higher than the lower surface of the bit line 131. Figure 10B The cross-sectional structure of the semiconductor device is shown along line BB' with the second contact pad 162 formed thereon. After the second contact pad 162 is formed by the selective epitaxial growth process, a gap is formed between the first contact pad 161 and the second contact pad 162 and one sidewall of the contact hole 15.

[0096] It should be noted that since the contact hole 15 has a large aspect ratio and the first contact pad 161 contacts part of the substrate surface of the contact hole 15, after the first contact pad 161 and the second contact pad 162 are formed, a gap will be formed between the first contact pad 161 and one side wall of the contact hole 15 and the bottom surface of the contact hole 15, resulting in the gap being unable to be completely filled when the contact plug 163 is subsequently formed using a deposition process.

[0097] As an example, step S407 may be specifically to form a contact plug 163 on the second contact pad 162 by using a chemical vapor deposition or physical vapor deposition process. By controlling the process conditions, the contact plug 163 may be formed to cover only a portion of the surface of the second contact pad 162, and a gap 17 may be formed between the first contact pad 161, the second contact pad 162 and the contact hole 15. For details, see Figure 11B As another example, step S407 may be specifically as follows: forming a contact plug 163 on the second contact pad 162 by selecting a deposition process with good step coverage characteristics; the contact plug 163 covers the second contact pad 162 and contacts a portion of the first contact pad 161; and partially fills the gap between the first contact pad 161, the second contact pad 162, and the contact hole 15; a gap 17 is still retained between the first contact pad 161 and the bottom of the contact hole 15. For details, see the first embodiment described above. Figure 2B In the following description, the description will be based on an example in which a contact plug 163 covering a portion of the surface of the second contact pad 162 is formed in the contact hole 15, see Figures 11A-11C As shown, Figure 11A FIG. 1 shows a schematic top view of a semiconductor device having contact plugs 163 formed thereon. Figure 11B Shown along Figure 11A Schematic diagram of the cross-sectional structure along line AA', wherein the upper surface of the first contact plug 1631 can be higher than the upper surface of the bit line 131, so that the contact interface between the first contact plug 1631 and the second contact plug 1632 is higher than the bit line 131, thereby preventing ions at the contact interface from penetrating into the bit line 131 and affecting device performance. Figure 11C Shown along Figure 11A Schematic diagram of the cross-sectional structure along line BB'.

[0098] Step S407 may further specifically include depositing a polysilicon layer, metal silicide, or metal layer in the contact hole 15 using a chemical vapor deposition or physical vapor deposition process to form the first contact plug 1631; and depositing a metal layer in the contact hole 15 to form a second contact plug 1632 covering the first contact plug 1631. The first contact pad 161, the second contact pad 162, the first contact plug 1631, and the second contact plug 1632 may constitute the contact pad structure 16.

[0099] As an example, the first contact plug 1631 may be a silicon phosphide layer, and the second contact plug 1632 may be metal tungsten. When the first contact plug 1631 and the second contact pad 162 are made of the same material, the growth rate of the first contact plug 1631 may be greater than the growth rate of the second contact pad 162 .

[0100] It should be noted that after forming a polysilicon layer, a metal silicide or a metal layer in the contact hole 15 to serve as the first contact plug 1631 , a heavily doped semiconductor layer 18 may be deposited to cover the first contact plug 1631 .

[0101] The above is a method for preparing a semiconductor device provided by an embodiment of the present invention, which pre-treats the bottom of the contact hole 15 with germane gas, and adopts a selective epitaxial growth method to grow a first contact pad 161 and a second contact pad 162 that conformally covers the first contact pad 161 on the active area 11, thereby forming a contact plug 163 in the contact hole 15. In this method, the first contact pad 161 is in full contact with the active area 11 in the substrate 10, which can effectively reduce the contact resistance. Moreover, by providing a contact pad with a stacked structure, the first contact pad can serve as a buffer layer for the second contact pad 162, thereby preventing the doped ions in the second contact pad 162 from penetrating into the substrate 10 and affecting the conductivity. In addition, the gap 17 in the contact hole 15 is formed between the first contact pad 161 and one side wall of the contact hole 15, which can effectively reduce the influence of the gap 17 on the conductivity, thereby greatly improving the conductive properties of the semiconductor device.

[0102] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, the substrate comprising at least an active area and a shallow trench isolation area; A bit line structure, the bit line structure is located on the substrate and extends in a first direction, the bit line structure comprising: a bit line and an insulating dielectric layer located on the bit line; a bit line contact plug, wherein the bit line structure is in contact with the substrate through the bit line contact plug; Isolation fences, the isolation fences being located between adjacent bit line structures and spaced apart in the first direction; a contact hole located in an area defined by the bit line structure adjacent to the second direction and adjacent to the isolation fence in the first direction, wherein the second direction is perpendicular to the first direction, and a bottom of the contact hole extends into the substrate and exposes at least a portion of the active area and a portion of the shallow trench isolation area; A contact pad structure is located in the contact hole, and the contact pad structure includes a first contact pad, a second contact pad conformally covering the first contact pad, and a contact plug located on the second contact pad, a gap is formed between the first contact pad and a side wall of the contact hole, the gap exposes a portion of the top surface of the shallow trench isolation area, and the bottom surface of the gap is lower than the top surface of the active area, and the top surface of the gap is lower than the top surface of the bit line.

2. The semiconductor device according to claim 1, wherein The first contact pad and the second contact pad have different chemical compositions.

3. The semiconductor device according to claim 1, wherein The first contact pad contacts a portion of the substrate surface of the contact hole.

4. The semiconductor device according to claim 3, wherein The bottom of the first contact pad only contacts the active area.

5. The semiconductor device according to claim 4, wherein The contact plug covers the second contact pad and contacts a portion of the surface of the first contact pad.

6. The semiconductor device according to claim 5, wherein The contact plugs include a first contact plug and a second contact plug located on the first contact plug.

7. The semiconductor device according to claim 6, wherein: The contact pad structure further includes a heavily doped semiconductor layer located between the first contact plug and the second contact plug.

8. The semiconductor device according to claim 6, wherein: An upper surface of the second contact pad is higher than a lower surface of the bit line, and an upper surface of the first contact plug is higher than an upper surface of the bit line.

9. A method for preparing a semiconductor device, characterized in that: include: forming a bit line structure extending along a first direction on a substrate, the bit line structure comprising: a bit line and an insulating dielectric layer located on the bit line, wherein the substrate comprises at least an active area and a shallow trench isolation area, and the bit line structures are arranged at intervals in a second direction, the second direction being perpendicular to the first direction; Etching the substrate between adjacent bit line structures to form a contact opening extending into the substrate and exposing at least a portion of the active area and a portion of the shallow trench isolation region; forming isolation fences in the contact opening, wherein the isolation fences are spaced apart in the first direction to isolate the contact opening into a plurality of contact holes; Pre-treating the bottom of the contact hole by using germane gas; forming a first contact pad in the contact hole after the pretreatment; forming a second contact pad on the first contact pad and conformally covering the first contact pad, wherein a gap is formed between the first contact pad and a sidewall of the contact hole, the gap exposing a portion of a top surface of the shallow trench isolation region, and the bottom surface of the gap is lower than the top surface of the active region, and the top surface of the gap is lower than the top surface of the bit line; A contact plug is formed in the contact hole.

10. The method according to claim 9, characterized in that Forming a first contact pad in the contact hole after the pre-processing, comprising: A first contact pad is formed in the pre-processed contact hole, wherein the first contact pad contacts a portion of the substrate surface in the contact hole.

11. The method according to claim 10, characterized in that Forming a first contact pad in the pre-treated contact hole, wherein the first contact pad contacts a portion of the substrate surface of the contact hole, comprises: forming the first contact pad on the pre-treated active area in the contact hole by a selective epitaxial growth process; Forming a second contact pad on the first contact pad to conformally cover the first contact pad, comprising: A selective epitaxial growth process is used to form the second contact pad on the first contact pad and conformally cover the first contact pad, wherein the first contact pad and the second contact pad have different chemical compositions.

12. The method according to claim 10 or 11, characterized in that Forming a contact plug in the contact hole includes: forming the contact plug in the contact hole to cover the second contact pad and to contact a portion of the surface of the first contact pad.

13. The method according to claim 12, characterized in that forming a contact plug in the contact hole, comprising: A polysilicon layer, a metal silicide or a metal layer is formed in the contact hole as a first contact plug, and a metal layer is deposited in the contact hole to form a second contact plug covering the first contact plug.

14. The method according to claim 13, characterized in that When the first contact plug and the second contact pad are made of the same material, a growth rate of the first contact plug is greater than a growth rate of the second contact pad.

15. The method according to claim 13, characterized in that After forming a polysilicon layer, a metal silicide or a metal layer in the contact hole as a first contact plug, the method further includes: A heavily doped semiconductor layer is deposited to cover the first contact plug.

16. The method according to claim 13, characterized in that An upper surface of the second contact pad is higher than a lower surface of the bit line, and an upper surface of the first contact plug is higher than an upper surface of the bit line.

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