Packaging structure and forming method thereof

Abstract

Some embodiments of the present disclosure provide a packaging structure and a method for forming the same. The packaging structure includes a packaging substrate, an interposer substrate located above the packaging substrate, and a plurality of semiconductor devices located above the interposer substrate. The interposer substrate also has one or more grooves to accommodate or hold additional semiconductor devices that are not allowed to be mounted on the surface of the interposer substrate. The grooves make the overall packaging structure thinner. Some semiconductor devices accommodated in the grooves of the interposer substrate can also be electrically connected to the interposer substrate and / or the semiconductor devices above the interposer substrate to improve the electrical performance of the overall packaging structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to a semiconductor packaging technology, and more particularly to a chip packaging structure and a method for forming the same. Background Art

[0002] Integrated circuits (ICs) are made possible by advances in semiconductor device manufacturing technology. Driven by advances in technology that allow more and more components to be mounted on the same size chip, the size, speed, and capacity of chips have made tremendous progress. Continuous advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and / or higher integration. Functional density (i.e., the number of interconnected devices per chip area) generally increases, while feature size (i.e., the smallest component that can be produced using a manufacturing process) decreases. Generally speaking, this size reduction process provides benefits through increased production efficiency and reduced manufacturing costs.

[0003] A chip package not only protects a semiconductor device from environmental pollution, but also provides a connection interface for the semiconductor device packaged therein. Smaller package structures using less area or lower height have been developed to package semiconductor devices.

[0004] While existing packaging technologies are generally adequate for their intended purposes, they are still not satisfactory in all respects. Summary of the invention

[0005] Some embodiments of the present disclosure provide a packaging structure, including a packaging substrate, an interposer substrate, a first semiconductor device, and a second semiconductor device. The interposer substrate is disposed above the packaging substrate. The interposer substrate includes a silicon substrate and has a bottom surface facing and adjacent to the packaging substrate and a first groove formed on the bottom surface. The first semiconductor device is received in the first groove and is electrically connected to the interposer substrate. The second semiconductor device is disposed on a top surface of the interposer substrate opposite to the bottom surface.

[0006] Some embodiments of the present disclosure provide a packaging structure, including a packaging substrate, an interposer substrate, a first semiconductor device, and a second semiconductor device. The interposer substrate is disposed above the packaging substrate. The interposer substrate includes a silicon substrate and has a bottom surface facing and adjacent to the packaging substrate, a top surface opposite to the bottom surface, and a groove formed on the top surface. The first semiconductor device is disposed on the top surface of the interposer substrate. The second semiconductor device is received in the groove and is electrically connected to the first semiconductor device and / or the interposer substrate.

[0007] Some embodiments of the present disclosure provide a method for forming a packaging structure. The method includes forming a groove on a surface of an interposer substrate, the interposer substrate including a silicon substrate. The method also includes disposing a first semiconductor device in the groove and on a bottom surface of the groove. The method also includes stacking the interposer substrate and the first semiconductor device above the packaging substrate. In addition, the method also includes disposing a second semiconductor device above the interposer substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A-1G are cross-sectional views of various stages of a process for forming a package structure according to some embodiments.

[0009] Figure 2 is a cross-sectional view of a package structure according to some embodiments.

[0010] Figure 3 is a cross-sectional view of a package structure according to some embodiments.

[0011] Figures 4A-4F are cross-sectional views of various stages of a process for forming a package structure according to some embodiments.

[0012] Figure 5 is a cross-sectional view of a package structure according to some embodiments.

[0013] The following are the descriptions of the reference numerals:

[0014] 100: Carrier substrate

[0015] 102:Packaging substrate

[0016] 102A: Top surface

[0017] 104: Insulation layer

[0018] 106: Conductive characteristics

[0019] 108: Conductive element

[0020] 110: Intermediary substrate

[0021] 110A: First surface

[0022] 110B: Second surface

[0023] 111:Through hole

[0024] 112: Interconnection structure layer

[0025] 112A: Top surface

[0026] 113: Conductive structure

[0027] 113A:Metal column

[0028] 113B: Metal cover

[0029] 116: Conductive structure

[0030] 118: Groove

[0031] 1182: Bottom surface

[0032] 120:Semiconductor device

[0033] 122: Conductive element

[0034] 123: Conductive structure

[0035] 123A:Metal column

[0036] 123B: Metal cover

[0037] 124: Bottom filling component

[0038] 126: Bottom filling component

[0039] 128:Semiconductor device

[0040] 128A: Top surface

[0041] 130: Conductive element

[0042] 132: Bottom filling component

[0043] 134: Protective layer

[0044] 134A: Top surface

[0045] 136: Conductive bump

[0046] 138: Groove

[0047] 1382: Bottom surface

[0048] 140: Conductive structure

[0049] 140A:Metal column

[0050] 140B: Metal cover

[0051] 141: Conductive element

[0052] 502: Groove

[0053] 5022: Bottom surface

[0054] 504:Semiconductor device

[0055] 504A: Top surface

[0056] 506:Semiconductor device

[0057] 506A: Top surface

[0058] 508: Conductive element

[0059] 509: Conductive structure

[0060] 509A:Metal column

[0061] 509B: Metal cover

[0062] 510: Bottom filling component

[0063] 512: Protective layer

[0064] 512A: Top surface

[0065] 514: Conductive bump

[0066] 516: Conductive structure

[0067] 516A:Metal column

[0068] 516B:Metal cover

[0069] 517: Conductive element

[0070] T: Cutting tape

[0071] G: Cutting groove

[0072] Z, Z1: Depth

[0073] Z', Z1': thickness

[0074] D1: Direction DETAILED DESCRIPTION

[0075] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following describes embodiments of specific components and their arrangements to illustrate the present disclosure. Of course, these embodiments are merely examples and should not be used to limit the scope of the present disclosure. For example, the specification describes a first feature formed on or above a second feature, which may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, repeated reference symbols and / or marks may be used in different examples of the present disclosure. This repetition is for the purpose of simplicity and clarity, and is not used to limit the specific relationship between the various embodiments and / or structures discussed.

[0076] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, are used to facilitate describing the relationship of one element or feature to another element or feature in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in different orientations (rotated 90 degrees or at other orientations), and the spatially relative terms used herein should be interpreted accordingly.

[0077] The term "substantially" in the specification, such as "substantially flat" or "substantially coplanar", etc., can be understood by those skilled in the art. In some embodiments, the adjective substantially can be removed. Where applicable, the term "substantially" can also include embodiments of "entirely", "completely", "all", etc. Where applicable, the term "substantially" can also refer to 90% or higher, such as 95% or higher, in particular 99% or higher, including 100%. In addition, terms such as "substantially parallel" or "substantially perpendicular" should be interpreted as not excluding slight deviations from a specific arrangement, and may, for example, include deviations of up to 10°. The term "substantially" does not exclude "completely", for example, a composition that is "substantially free" of Y may be completely free of Y.

[0078] Terms such as "about" used in conjunction with a specific distance or size should be interpreted as not excluding minor deviations from the specific distance or size and may include deviations of up to 10%, for example. The term "about" used for a numerical value X may mean X ± 5 or 10%.

[0079] Some embodiments of the present disclosure are described below. Additional operations may be provided before, during, and / or after the stages described in these embodiments. In different embodiments, some of the stages described may be replaced or eliminated. Additional features may be added to the packaging structure. In different embodiments, some of the features described may be replaced or eliminated. Although some embodiments are discussed below with operations performed in a specific order, these operations may also be performed in other logical orders.

[0080] Embodiments of the present disclosure may relate to 3D packages (sometimes also referred to as 2.5D packages) or 3D-IC devices. Other features or processes may also be included. For example, a test structure may be included to assist in verification testing of the 3D package or 3D-IC device. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, which allow the use of a probe and / or a probe card, etc., to test the 3D package or 3D-IC device. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of a known good die, thereby increasing yield and reducing costs.

[0081] Figures 1A-1G is a cross-sectional view of various stages of a process for forming a package structure according to some embodiments. Figure 1A As shown, according to some embodiments, a packaging substrate 102 is formed on a carrier substrate 100. The carrier substrate 100 may be a glass substrate, a semiconductor substrate, or other suitable substrates. Figure 1E After the subsequent stage shown in FIG. 1 , the package substrate 102 may be used to provide electrical connections between the semiconductor device (to be described later) in the package structure and external electronic devices.

[0082] The packaging substrate 102 may be used for routing. In some embodiments, the packaging substrate 102 is a redistribution substrate. In some alternative embodiments, the packaging substrate 102 is a build-up substrate (e.g., a printed circuit board) including a core and build-up layers on opposite sides of the core. In the subsequent discussion of the embodiments of the present disclosure, the redistribution substrate is used as an example of the packaging substrate 102, but the teachings disclosed in the exemplary embodiments may also be easily applied to the build-up substrate. Figure 1A As shown, the package substrate 102 includes a plurality of laminated insulating layers 104 and a plurality of conductive features 106 surrounded by the insulating layers 104. The conductive features 106 may include wires, conductive vias, and / or conductive pads. In some embodiments, some conductive vias are stacked on top of each other, and the upper conductive vias are substantially aligned with the lower conductive vias, thereby having a shorter wiring length. However, in some wiring-constrained situations, some conductive vias are staggered vias, and the upper conductive vias are not aligned with the lower conductive vias.

[0083] The insulating layer 104 may include or be made of one or more polymer materials. The polymer material may include polybenzoxazole (PBO), polyimide (PI), epoxy resin, one or more other suitable polymer materials or a combination thereof. In some embodiments, the polymer material is photosensitive. Therefore, an opening having a desired pattern can be formed in the insulating layer 104 using a photolithography process.

[0084] In some other embodiments, part or all of the insulating layer 104 includes or is made of a dielectric material other than a polymer material. The dielectric material may include silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof.

[0085] Conductive features 106 may include conductive lines that provide electrical connections in the horizontal direction and conductive vias that provide electrical connections in the vertical direction. Conductive features 106 may include or be made of copper, aluminum, gold, cobalt, titanium, nickel, silver, graphene, one or more other suitable conductive materials, or combinations thereof. In some embodiments, conductive features 106 include multiple sublayers. For example, each conductive feature 106 includes multiple sublayers, including Ti / Cu, Ti / Ni / Cu, Ti / Cu / Ti, Al / Ti / Ni / Ag, other suitable multiple sublayers, or combinations thereof.

[0086] The formation of the package substrate 102 may involve multiple deposition or coating processes, multiple patterning processes, and / or multiple planarization processes.

[0087] Deposition or coating processes may be used to form the insulating layer and / or the conductive layer. The deposition or coating process may include a spin coating process, an electroplating process, an electroless process, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, one or more other suitable processes, or a combination thereof.

[0088] The patterning process may be used to pattern the formed insulating layer and / or the formed conductive layer. The patterning process may include a photolithography process, an energy beam drilling process (e.g., a laser beam drilling process, an ion beam drilling process, or an electron beam drilling process), an etching process, a mechanical drilling process, one or more other applicable processes, or a combination thereof.

[0089] The planarization process may be used to provide a flat top surface for the formed insulating layer and / or the formed conductive layer to facilitate subsequent processes. The planarization process may include a mechanical polishing process, a chemical mechanical polishing (CMP) process, one or more other applicable processes or a combination thereof.

[0090] like Figure 1A As shown, according to some embodiments, the package substrate 102 further includes conductive elements 108 formed thereon. Each conductive element 108 (e.g., a conductive pillar) may be exposed at or protrude from the topmost surface of the insulating layer 104 and may be electrically connected to one of the conductive features 106. The conductive elements 108 may be used to electrically couple, hold, or receive conductive structures, which will be described later.

[0091] The conductive element 108 may include or be made of copper, aluminum, gold, cobalt, titanium, tin, one or more other suitable materials or a combination thereof. The conductive element 108 may be formed using an electroplating process, an electroless plating process, a placement process, a printing process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, one or more other suitable processes or a combination thereof.

[0092] like Figure 1B As shown, according to some embodiments, a package substrate 102 (see Figure 1A). In some embodiments, the interposer substrate 110 may be an interposer wafer that does not contain active devices (e.g., transistors and diodes) and passive devices (e.g., resistors, capacitors, inductors, etc.). In some embodiments, the interposer substrate 110 may be a device wafer that includes active devices and / or passive devices thereon. The interposer substrate 110 may be a semiconductor substrate or a dielectric substrate. When it is a semiconductor substrate, the interposer substrate 110 may be a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The semiconductor material of the interposer substrate 110 may be silicon, germanium, a compound semiconductor including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The interposer substrate 110 may be doped or undoped. In some other embodiments, the interposer substrate 110 may be a package substrate, which may include a core or may be a coreless substrate, or may be a glass substrate.

[0093] According to some embodiments, through-vias (TVs) 111 are formed to extend from a first surface 110A of the interposer substrate 110 to a second surface 110B opposite to the first surface 110A of the interposer substrate 110 , such as Figure 1B As shown. The through via 111 is sometimes also referred to as a through substrate via or a through silicon via (when the interposer substrate 110 is a silicon substrate). The through via 111 may be formed by forming an opening in the interposer substrate 110 by, for example, etching, milling, laser technology, a combination thereof, and / or the like. A thin dielectric material may be formed in the opening, for example, by using an oxidation process or a conformal deposition process. A thin barrier layer may be conformally deposited in the opening, for example, by CVD, ALD, PVD, thermal oxidation, a combination thereof, and / or the like. Conductive materials such as copper, tungsten, aluminum, silver, gold, a combination thereof, and / or the like may be deposited over the thin barrier layer and in the opening. Conductive materials may be formed by electrochemical plating processes, CVD, ALD, PVD, a combination thereof, and / or the like. Excess portions of the conductive material and barrier layer may be removed from the first surface 110A and the second surface 110B of the interposer substrate 110 by, for example, CMP. Therefore, the through via 111 may include a conductive material and a thin barrier layer between the conductive material and the interposer substrate 110 .

[0094] According to some embodiments, Figure 1B As shown, an interconnect structure layer 112 (sometimes referred to as a redistribution layer (RDL)) is formed on the second surface 110B, which is used to electrically connect to the internal circuits (e.g., through-holes 111) of the interposer substrate 110. Although not shown, the interconnect structure layer 112 may include multiple dielectric layers. Metal lines may be formed in the dielectric layer. Conductive vias may be formed between the metal lines above and below, and interconnect the metal lines above and below. According to some embodiments, the dielectric layer is formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof, and / or multilayers thereof. Alternatively, the dielectric layer may include one or more low-k dielectric layers having a low-k value. The materials of the metal lines and conductive vias (collectively referred to as conductive features) of the interconnect structure layer 112 may be the same as those of the dielectric layer 112. Figure 1A The materials of the conductive features 106 shown are the same or similar.

[0095] In addition, according to some embodiments, conductive structures 113 (sometimes also referred to as electrical connectors) may be formed at the top surface 112A of the interconnect structure layer 112 and used to electrically couple conductive features therein and interconnect to subsequently attached semiconductor devices (described later). Figure 1B As shown, each conductive structure 113 may include a metal pillar 113A and a metal capping layer 113B (e.g., a solder cap) above the metal pillar 113A. The conductive structure 113 including the metal pillar 113A and the metal capping layer 113B is sometimes referred to as a micro bump. The metal pillar 113A may include a conductive material such as copper, aluminum, gold, nickel, palladium, the like, or a combination thereof, and may be formed by sputtering, printing, electroplating, chemical plating, CVD, or a similar method thereof. The metal pillar 113A may be solder-free and have a substantially vertical sidewall. According to some embodiments, the metal capping layer 113B is formed on top of the metal pillar 113A. The metal capping layer 113B may include nickel, tin, tin-lead, gold, copper, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process such as an electroplating process. One of ordinary skill in the art will appreciate that the above examples of the conductive structure 113 are provided for illustrative purposes, and other structures of the conductive structure 113 may also be used.

[0096] like Figure 1BAs shown, according to some embodiments, a plurality of semiconductor devices 128 (for simplicity, only two semiconductor devices 128 are shown) are bonded to the first side of the interposer substrate 110 by means of the conductive structure 113 and the conductive elements 130 on the semiconductor devices 128 through a flip-chip bonding method to form conductive joints. Before the bonding process, the conductive elements 130 (e.g., conductive pillars) may be formed on the exposed contact pads (not shown) on the active surface of each semiconductor device 128. The conductive elements 130 may be similar to Figure 1A The conductive element 108 is shown, so it will not be repeated here. The semiconductor device 128 can be placed on the conductive structure 113 above the interposer substrate 110 using, for example, a pick-and-place tool.

[0097] According to some embodiments, each semiconductor device 128 includes a semiconductor chip, an active device (e.g., a transistor, a diode, a photodiode, etc.), a passive device (e.g., a resistor, a capacitor, an inductor, etc.), or a combination thereof. The semiconductor chip may include any type of functional integrated circuit, such as a processor, a logic circuit, a memory, an analog circuit, a digital circuit, a mixed signal, or the like. In some alternative embodiments, each semiconductor device 128 includes a packaging module, which includes a packaging substrate and one or more semiconductor chips or dies mounted thereon. In some embodiments, the semiconductor devices 128 include different types of electronic devices. For example, some semiconductor devices 128 are memory devices, while other semiconductor devices 128 are processor devices, but other combinations may also be used. In some other embodiments, the semiconductor devices 128 include the same type of electronic devices.

[0098] The bonding between the semiconductor device 128 and the interposer substrate 110 may be solder bonding or direct metal-to-metal (e.g., copper-to-copper) bonding. In some embodiments, the semiconductor device 128 is bonded to the interposer substrate 110 by a reflow process. In the reflow process, the conductive bonding points (conductive structures 113 and conductive elements 130) are respectively in contact with the exposed contact pads of the semiconductor device 128 and the exposed contact pads of the interconnect structure layer 112 (composed of some conductive features in the interconnect structure layer 112) to physically and electrically couple the semiconductor device 128 to the interposer substrate 110.

[0099] In some embodiments, Figure 1BAs shown, an underfill element 132 is formed to surround and protect the conductive joints (conductive structures 113 and conductive elements 130) and strengthen the connection between the semiconductor device 128 and the interposer substrate 110. The underfill element 132 may include or be made of an insulating material, such as an underfill material. The underfill material may include epoxy, resin, filler material, stress release agent (SRA), adhesion promoter, another suitable material or a combination thereof. In some embodiments, a liquid underfill material is dispensed into the gap between each semiconductor device 128 and the interposer substrate 110 to strengthen the strength of the conductive joints and even the entire package structure. After dispensing, the underfill material is cured to form the underfill element 132. The underfill element 132 may also provide a heat conduction path for the package structure. In this embodiment, the underfill element 132 fills the entire gap between the semiconductor device 128 and the interposer substrate 110 and covers all lower surfaces of the semiconductor device 128. In some other embodiments, the underfill element 132 is not formed, or the underfill element 132 only covers a portion of the lower surface of the semiconductor device 128 .

[0100] like Figure 1C As shown, according to some embodiments, a protection layer 134 is formed to surround and protect the semiconductor device 128 above the interposer substrate 110. In some embodiments, the protection layer 134 is separated from the conductive joints below the semiconductor device 128 by the bottom filling element 132. However, the embodiments of the present disclosure are not limited thereto. In some other embodiments, the bottom filling element 132 is not formed. In these cases, the protection layer 134 can be in direct contact with the conductive joints below the individual semiconductor devices 128.

[0101] In some embodiments, the protective layer 134 includes or is made of an insulating material, such as a molding material. The molding material may include a polymer material, such as an epoxy resin having a filler dispersed therein. In some embodiments, the molding material (e.g., a liquid molding material) is dispensed over the interposer substrate 110 and / or over the semiconductor device 128. In some embodiments, a heat treatment is then used to cure the liquid molding material and convert it into the protective layer 134.

[0102] In some embodiments, a planarization process is performed on the protection layer 134 to partially remove the protection layer 134. As a result, Figure 1CAs shown, the top surface 128A of each semiconductor device 128 is exposed (i.e., the top surface 128A of each semiconductor device 128 is substantially flush with the top surface 134A of the protection layer 134) for heat dissipation. The planarization process may include a mechanical grinding process, a chemical mechanical polishing (CMP) process, an etching process, a dry grinding process, one or more other applicable processes or a combination thereof. In some other embodiments where the semiconductor devices 128 have different heights, after the planarization process, one of the semiconductor devices 128 may be buried in the protection layer 134, while the other semiconductor devices 128 may be exposed from the protection layer 134.

[0103] like Figure 1D As shown, according to some embodiments, Figure 1C The resulting structure in the embodiment is inverted, and the semiconductor device 128 side is fixed on the dicing tape T. Afterwards, a plurality of grooves 118 are formed on the first surface 110A of the interposer substrate 110 (for simplicity, only two grooves 118 are shown). In some embodiments, each groove 118 extends from the first surface 110A to the interior of the interposer substrate 110, but does not penetrate the interposer substrate 110 (for example, the bottom surface 1182 of each groove 118 is spaced apart from the second surface 110B of the interposer substrate 110 that is adjacent to the semiconductor device 128). Each groove 118 may have an appropriate depth Z in a direction D1 that is substantially perpendicular to the first surface 110A of the interposer substrate 110 to accommodate or hold one or more other semiconductor devices that will be described later. In some embodiments, the (maximum) depth Z of the groove 118 does not exceed 90% of the thickness Z' of the interposer substrate 110 in the direction D1 to allow at least one conductive layer in the interposer substrate 110 to be retained for wiring.

[0104] The groove 118 may be formed using a wet or dry etching process, an energy beam drilling process (e.g., a laser beam drilling process, an ion beam drilling process, or an electron beam drilling process), a mechanical drilling process, one or more other applicable processes, or a combination thereof. The sidewall of the groove 118 may be perpendicular to the bottom surface 1182 or inclined relative to the bottom surface 1182.

[0105] like Figure 1E As shown, according to some embodiments, the semiconductor device 120 is placed or received in the groove 118 of the interposer substrate 110. There can be one semiconductor device 120 in each groove 118. In some other embodiments, there is more than one semiconductor device 120 in at least one groove 118. The shape and size of each groove 118 can be designed to correspond to the shape and size (in a cross section perpendicular to the direction D1) of the received semiconductor device 120.

[0106] In some embodiments, each semiconductor device 120 includes a semiconductor chip, an active device (e.g., a transistor, a diode, a photodiode, etc.), a passive device (e.g., a resistor, a capacitor, an inductor, etc.), a semiconductor die with only metal wiring (i.e., no functional chip), a package module (including a package substrate and one or more semiconductor chips or dies mounted thereon), or a combination thereof. The semiconductor chip may include any type of functional integrated circuit, such as a processor, a logic circuit, a memory, an analog circuit, a digital circuit, a mixed signal, or the like. In some embodiments, the semiconductor devices 120 include different types of electronic devices. For example, some semiconductor devices 120 are memory devices, while other semiconductor devices 120 are semiconductor dies with only metal wiring, but other combinations may also be used. In some other embodiments, the semiconductor devices 120 include the same type of electronic devices. In various embodiments, the semiconductor devices 120 and the semiconductor devices 128 on the opposite sides of the interposer substrate 110 may be or include the same or different types of electronic devices.

[0107] like Figure 1E As shown, according to some embodiments, the semiconductor device 120 is placed (eg, by a pick and place tool) on the bottom surface 1182 of the recess 118 (see Figure 1D ), and by means of the conductive structures 123 formed on the bottom surface 1182 (each including a metal pillar 123A and a metal capping layer 123B above the metal pillar 123A) and the conductive elements 122 (e.g., conductive pillars) on the semiconductor device 120, they are bonded to the interposer substrate 110 (e.g., electrically connected to some internal through-holes 111) by a flip-chip bonding method to form a conductive joint. The materials and formation methods of the conductive structures 123 and the conductive elements 122 can be respectively Figure 1B The conductive structure 113 and the conductive element 130 are shown to have the same or similar materials and formation methods. In some embodiments, the bonding between the semiconductor device 120 and the interposer substrate 110 can be a solder bonding or a direct metal-to-metal (e.g., copper-to-copper) bonding, similar to the bonding between the semiconductor device 128 and the interposer substrate 110 described above.

[0108] In some embodiments, Figure 1E As shown, a bottom fill element 124 (similar to Figure 1BThe bottom filling element 132 shown in the figure is used to surround and protect the conductive joints (conductive structures 123 and conductive elements 122) and strengthen the connection between the semiconductor device 120 and the interposer substrate 110. In the present embodiment, the bottom filling element 124 fills the entire gap between each semiconductor device 120 and the bottom surface 1182 of the corresponding groove 118, and covers all the lower surfaces of the semiconductor device 120. The bottom filling element 124 can also provide a heat conduction path for the packaging structure. In some other embodiments, the bottom filling element 124 is not formed, or the bottom filling element 124 only covers a portion of the lower surface of the semiconductor device 120.

[0109] Thereafter, according to some embodiments, along Figure 1E The cutting groove G shown in the figure is subjected to a singulation process (also called a sawing process) to form a plurality of separate package structures. Figure 1E , one of the package structures is shown. Afterwards, each package structure is removed from the dicing tape T by using a pick and place tool (not shown).

[0110] like Figure 1F As shown, according to some embodiments, Figure 1E The resulting package structure in the embodiment is placed (e.g., by a pick and place tool) over the package substrate 102 such that the first surface 110A of the interposer substrate 110 faces the package substrate 102. Thereafter, the interposer substrate 110 (integrated with the semiconductor device 120 and the semiconductor device 128) is bonded to the conductive element 108 via the conductive structure 116. The conductive structure 116 may include solder bumps, solder balls, conductive pillars, other suitable conductive elements, or combinations thereof. According to some embodiments, the material and formation method of the conductive structure 116 may be similar to that of the conductive structure 116. Figure 1B The conductive structure 113 shown in the figure has the same material and the same formation method. Although not shown in the figure, the conductive structure 116 can be Figure 1E The dicing tape T is formed on the first surface 110A of the interposer substrate 110 in the illustrated processing step (before removing the dicing tape T) and is electrically connected to the internal circuitry thereof.

[0111] In some embodiments, the interposer substrate 110 and the package substrate 102 are then pressed against each other at high temperature. As a result, the interposer substrate 110 is bonded to the package substrate 102 via the conductive structure 116. In some embodiments, a thermal compression process is used to achieve the above bonding process.

[0112] like Figure 1FAs shown, according to some embodiments, when the interposer substrate 110 is stacked above the package substrate 102, a gap is spaced between each semiconductor device 120 below the interposer substrate 110 and the package substrate 102. Since the groove 118 is formed on the first surface 110A of the interposer substrate 110 to accommodate the semiconductor device 120, the size of the conductive structure 116 (e.g., the height in the direction D1) can be smaller than that using an interposer substrate without a groove, because the size of the conductive structure 116 no longer needs to be larger than the thickness of the semiconductor device 120. As a result, a thinner overall package structure can be obtained.

[0113] like Figure 1F As shown, according to some embodiments, an underfill element 126 is also formed to surround and protect the conductive structure 116 and the conductive element 108 between the interposer substrate 110 and the package substrate 102, and to strengthen the connection between the interposer substrate 110 and the package substrate 102. In some embodiments, the underfill element 126 also surrounds and protects the semiconductor device 120 below the interposer substrate 110. In some embodiments, as Figure 1F As shown, a portion of the bottom filling element 126 is in the gap between each semiconductor device 120 and the package substrate 102. In the case where the bottom filling element 124 is omitted, the bottom filling element 126 can be formed in the groove 118 and directly contact the conductive joint (conductive structure 123 and conductive element 122) under the individual semiconductor device 120. The material and formation method of the bottom filling element 126 can be different from Figure 1E The materials and the forming methods of the underfill elements 124 shown are the same or similar.

[0114] Then, according to some embodiments, Figure 1G As shown, the carrier substrate 100 is removed to expose the surface of the package substrate 102. In some embodiments, before forming the package substrate 102, a release film (not shown) is pre-formed on the carrier substrate 100. The release film is a temporary bonding material that facilitates the separation operation between the carrier substrate 100 and the package substrate 102.

[0115] In some embodiments, Figure 1G As shown, conductive bumps 136 are then formed above the surface of the package substrate 102 originally covered by the carrier substrate 100. Each conductive bump 136 can be electrically connected to one of the conductive features 106 of the package substrate 102. The conductive bumps 136 enable the package structure to be electrically connected to an external device (not shown). The conductive bumps 136 can be or include solder bumps such as tin-containing solder bumps. The tin-containing solder bumps can further include copper, silver, gold, aluminum, lead, one or more other suitable materials or combinations thereof. In some embodiments, the tin-containing solder bumps are lead-free.

[0116] In some embodiments, after removing the carrier substrate 100, a solder ball (or solder element) is disposed on the exposed conductive feature 106. Then, a reflow process is performed to melt the solder ball and transform it into a conductive bump 136. In some other embodiments, before disposing the solder ball, an under bump metallization (UBM) element is formed over the exposed conductive feature 106. In some other embodiments, the solder element is electroplated onto the exposed conductive feature 106. Thereafter, a reflow process is used to melt the solder element to form the conductive bump 136.

[0117] As a result, the formation Figure 1G The process of the resulting packaging structure (including the chip-on-wafer-on-substrate (CoWoS) packaging structure) is shown. Figure 1G In the package structure, the semiconductor device 128 and the semiconductor device 120 can communicate with each other through the internal circuit of the interposer substrate 110. Therefore, RC delay and / or signal noise can be significantly reduced, and the signal transmission speed can be increased. As a result, the electrical performance of the overall package structure is improved. In addition, as described above, due to the groove 118 of the interposer substrate 110, a smaller overall package size can also be achieved.

[0118] Many variations and / or modifications may be made to the embodiments of the present disclosure. For example, the number of recesses 118 , semiconductor devices 128 , and / or semiconductor devices 120 in one package structure is not limited to the above embodiments and may vary in different embodiments.

[0119] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 2 1 is a cross-sectional view of a package structure according to some embodiments. In some embodiments, a groove 138 is further formed on the top surface 102A of the package substrate 102 facing and adjacent to the interposer substrate 110, and is aligned with a groove 118 of the interposer substrate 110 (for example, the groove 118 on the right side shown in the figure) to allow the semiconductor device 120 accommodated in the groove 118 to extend into the groove 138. In some embodiments, as Figure 2 As shown, a gap is spaced apart between the semiconductor device 120 and the bottom surface 1382 of the recess 138. Thus, a portion of the bottom filling element 126 is in the gap between the semiconductor device 120 and the bottom surface 1382 of the recess 138. Due to the recess 138, a thinner overall package structure can also be obtained for similar reasons as the recess 118 described above.

[0120] In some embodiments, the groove 138 of the package substrate 102 is formed before the interposer substrate 110 is stacked on the package substrate 102. The method for forming the groove 138 can be the same as that of Figure 1D The formation method of the groove 118 shown is similar. In some embodiments, the (maximum) depth Z1 of the groove 138 in the direction D1 does not exceed 50% of the thickness Z1' of the package substrate 102 in the direction D1 to maintain sufficient structural strength of the package substrate 102. The sidewall of the groove 138 can be perpendicular to the bottom surface 1382 or inclined relative to the bottom surface 1382.

[0121] In some other embodiments, one or more recesses 138 are formed on the top surface 102A of the package substrate 102 and aligned with corresponding recesses 118 of the interposer substrate 110 to accommodate a plurality of semiconductor devices 120 mounted on the underside of the interposer substrate 110 .

[0122] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 3 is a cross-sectional view of a package structure according to some embodiments. Figure 3 As shown, at least one semiconductor device 120 (eg, the one on the right side shown in the figure) received in a groove 118 of the interposer substrate 110 extends into a corresponding groove 138 of the package substrate 102 (similar to Figure 2 Embodiments). Moreover, according to some embodiments, the semiconductor device 120 is also bonded to the exposed contact pads (composed of some conductive features 106) at the bottom surface 1382 of the groove 138 by means of a conductive structure 140 (each including a metal pillar 140A and a metal cap layer 140B above the metal pillar 140A) formed on the bottom surface 1382 and a conductive element 141 (e.g., a conductive pillar) on the semiconductor device 120 through a flip-chip bonding method to form a conductive joint. After the interposer substrate 110 is stacked on the packaging substrate 102, the conductive joint enables the semiconductor device 120 (and the connected interposer substrate 110 and the semiconductor device 128 thereon) to be electrically connected to the packaging substrate 102. The bonding between the semiconductor device 120 and the packaging substrate 102 can be a solder bonding or a direct metal-to-metal (e.g., copper-to-copper) bonding. The materials and formation methods of the conductive structures 140 and the conductive elements 141 can be respectively the same as those of the packaging substrate 102. Figure 1E The conductive structure 123 and the conductive element 122 are made of the same or similar materials and are formed by the same methods.

[0123] In some embodiments, before the interposer substrate 110 is stacked over the package substrate 102, the conductive element 141 is formed on a surface of the semiconductor device 120 opposite to the conductive element 122 and electrically connected to an exposed contact pad of the semiconductor device 120. The conductive element 141 is also electrically connected to an internal circuit of the semiconductor device 120. For example, a plurality of conductive through vias may be formed in the semiconductor device 120 and penetrate the semiconductor device 120 to interconnect the conductive element 122 and the conductive element 141 on opposite surfaces of the semiconductor device 120.

[0124] like Figure 3 As shown, according to some embodiments, the bottom filling element 126 formed also surrounds and protects the conductive joints (conductive structures 140 and conductive elements 141) below the semiconductor device 120, and strengthens the connection between the semiconductor device 120 and the package substrate 102. For example, a portion of the bottom filling element 126 is in the gap between the semiconductor device 120 and the bottom surface 1382 of the groove 138, as shown in FIG. Figure 3 Portions of the underfill element 126 may also help provide a thermal path for the semiconductor device 120 .

[0125] like Figure 3 As shown, at least one semiconductor device 120 is not only electrically connected to the interposer substrate 110 , but also electrically connected to the package substrate 102 , thereby improving the electrical performance of the overall package structure.

[0126] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figures 4A-4F is a cross-sectional view of various stages of a process for forming a package structure according to some embodiments. Figure 4A As shown, according to some embodiments, a structure including a package substrate 102 on a carrier substrate 100 is provided or received (similar to Figure 1A structure shown).

[0127] like Figure 4B As shown, according to some embodiments, a package substrate 102 (see Figure 4A ) above the interposer substrate 110 (similar to Figure 1A10). In some embodiments, as described above, the interposer substrate 110 may include an interconnect structure layer 112 (also referred to as a redistribution layer (RDL)) formed on the second surface 110B thereof. In some embodiments, a plurality of grooves 502 are formed in the interposer substrate 110 (it should be understood that, for simplicity, only two grooves 502 are shown). In some embodiments, each groove 502 extends from the top surface 112A of the interconnect structure layer 112 to the interior of the interposer substrate 110, but does not penetrate the interposer substrate 110. For example, the bottom surface 5022 of each groove 502 is spaced apart from the first surface 110A of the interposer substrate 110 relative to the second surface 110B, as shown in FIG. Figure 4B Each groove 502 may have an appropriate depth in a direction D1 substantially perpendicular to the second surface 110B to accommodate or contain one or more other semiconductor devices to be described later, as previously described with reference to Figure 1D The groove 118 shown is discussed.

[0128] The groove 502 may be formed using a wet or dry etching process, an energy beam drilling process (e.g., a laser beam drilling process, an ion beam drilling process, or an electron beam drilling process), a mechanical drilling process, one or more other applicable processes, or a combination thereof. The sidewall of the groove 502 may be perpendicular to the bottom surface 5022 or inclined relative to the bottom surface 5022.

[0129] like Figure 4C As shown, according to some embodiments, a plurality of semiconductor devices 504 (for simplicity, only two semiconductor devices 504 are shown) are placed (e.g., by a pick and place tool) in recesses 502 of an interposer substrate 110. There may be one semiconductor device 504 in each recess 502. In some other embodiments, there may be more than one semiconductor device 504 in at least one recess 502. The shape and size of each recess 502 may be designed to correspond to the shape and size of the received semiconductor device 504. In some embodiments, each recess 502 is designed to have an appropriate depth so that after the semiconductor device 504 is placed in the recess 502 (e.g., disposed on the bottom surface 5022 of the corresponding recess 502), the top surface 504A of the respective semiconductor device 504 is substantially flush with the top surface 110B of the interposer substrate 110. In some embodiments, each semiconductor device 504 may be fixed on the bottom surface 5022 of the respective recess 502 by an adhesive (not shown). In these embodiments, the semiconductor devices 504 are electrically isolated from the interposer substrate 110. Examples of the material of the adhesive may include organic adhesive materials such as resin, polyimide (PI), polybenzoxazole (PBO), benzo-cyclo-butene (BCB), but are not limited thereto.

[0130] In some embodiments, each semiconductor device 504 includes a semiconductor chip, an active device (e.g., a transistor, a diode, a photodiode, etc.), a passive device (e.g., a resistor, a capacitor, an inductor, etc.), a semiconductor die with only metal wiring (i.e., no functional chip), a package module (including a package substrate and one or more semiconductor chips or dies mounted thereon), or a combination thereof. The semiconductor chip may include any type of functional integrated circuit, such as a processor, a logic circuit, a memory, an analog circuit, a digital circuit, a mixed signal, or the like. In some embodiments, the semiconductor device 504 includes different types of electronic devices. For example, some semiconductor devices 504 are memory devices, while other semiconductor devices 504 are semiconductor dies with only metal wiring. In some other embodiments, the semiconductor devices 504 include the same type of electronic devices.

[0131] like Figure 4D As shown, according to some embodiments, a plurality of semiconductor devices 506 (for simplicity, only two semiconductor devices 506 are shown) are then stacked above the interposer substrate 110 (e.g., by a pick and place tool). In some embodiments, each semiconductor device 506 includes a semiconductor chip, an active device (e.g., a transistor, a diode, a photodiode, etc.), a passive device (e.g., a resistor, a capacitor, an inductor, etc.), or a combination thereof. The semiconductor chip may include any type of functional integrated circuit, such as a processor, a logic circuit, a memory, an analog circuit, a digital circuit, a mixed signal, or the like. In some alternative embodiments, each semiconductor device 506 includes a packaging module, which includes a packaging substrate and one or more semiconductor chips or dies mounted thereon. In some embodiments, the semiconductor devices 506 include different types of electronic devices. For example, some semiconductor devices 506 are memory devices, while other semiconductor devices 506 are processor devices. In some other embodiments, the semiconductor devices 506 include the same type of electronic devices. In various embodiments, the semiconductor device 506 over the interposer substrate 110 and the semiconductor device 504 received in the cavity 502 may be or include the same or different types of electronic devices.

[0132] like Figure 4DAs shown, according to some embodiments, each semiconductor device 506 is disposed on the top surface 112A of the interconnect structure layer 112, and is bonded to some exposed contact pads of the interconnect structure layer 112 (composed of some conductive features of the interconnect structure layer 112) and some exposed contact pads of the semiconductor device 504 by means of a flip chip bonding method with the aid of a conductive structure 509 (each including a metal pillar 509A and a metal capping layer 509B above the metal pillar 509A) formed on the top surface 112A of the interconnect structure layer 112 or on one or more semiconductor devices 504 received in the groove 502 and a conductive element 508 (e.g., a conductive pillar) on the semiconductor device 506, so as to form a conductive joint. The materials and formation methods of the conductive structure 509 and the conductive element 504 may be respectively the same as those of the conductive structure 509 and the conductive element 504. Figure 1B The conductive structures 113 and conductive elements 130 are shown to have the same or similar materials and formation methods. In some embodiments, the bonding between the semiconductor device 506 and the interposer substrate 110 and between the semiconductor device 506 and the semiconductor device 504 can be solder bonding or direct metal-to-metal (eg, copper-to-copper) bonding.

[0133] According to some embodiments, Figure 4D As shown, after the semiconductor devices 506 are disposed on the interposer substrate 110, one semiconductor device 504 housed in one recess 502 (e.g., the recess 502 on the left shown in the figure) is located directly below one of the semiconductor devices 506 (e.g., the semiconductor device 506 on the left shown in the figure), and the semiconductor device 506 is bonded to the exposed contact pads of the semiconductor device 504 (through some conductive bonding points between the semiconductor device 506 and the semiconductor device 504). In addition, another semiconductor device 504 housed in another recess 502 (e.g., the recess 502 on the right shown in the figure) is located between and below two adjacent semiconductor devices 506, and the two adjacent semiconductor devices 506 are bonded to the exposed contact pads of the semiconductor devices 504 through conductive bonding points between the semiconductor device 504 and one semiconductor device 506 and through conductive bonding points between the semiconductor device 504 and the other semiconductor device 506, respectively.

[0134] Thereafter, according to some embodiments, an underfill element 510 is formed to surround and protect the conductive joints (conductive structures 509 and conductive elements 508) and to strengthen the connection between the semiconductor device 506 and the interposer substrate 110 and / or between the semiconductor device 506 and the semiconductor device 504. According to some embodiments, the underfill element 510 also surrounds and protects the semiconductor device 504 received in the recess 502 of the interposer substrate 110, such as Figure 4DIn this embodiment, the bottom filling element 510 fills the entire gap between each semiconductor device 506 and the interposer substrate 110 and covers all the bottom surfaces of the semiconductor devices 506. In some other embodiments, the bottom filling element 510 is not formed, or the bottom filling element 510 only covers a portion of the bottom surface of the semiconductor device 506. The material and formation method of the bottom filling element 510 can be different from those of the embodiment of the present invention. Figure 1B The material and the forming method of the underfill element 132 are the same or similar.

[0135] like Figure 4D As shown, according to some embodiments, a protective layer 512 is then formed to surround and protect the semiconductor device 506. In some embodiments, the protective layer 512 is separated from the conductive joints between the semiconductor device 506 and the interposer substrate 110 and / or between the semiconductor device 506 and the semiconductor device 504 received in the recess 502 by the bottom filling element 510. However, the embodiments of the present disclosure are not limited thereto. In some other embodiments, the bottom filling element 510 is not formed. In these cases, the protective layer 512 can be in direct contact with the conductive joints. The material and formation method of the protective layer 512 can be different from those of the embodiment of the present disclosure. Figure 1C The material and forming method of the protection layer 134 are the same or similar.

[0136] In some embodiments, a planarization process is performed on the protection layer 512 to partially remove the protection layer 512. As a result, Figure 4D As shown, the top surface 506A of each semiconductor device 506 is exposed (i.e., the top surface 506A of each semiconductor device 506 is substantially flush with the top surface 512A of the protection layer 512). The planarization process may include a mechanical grinding process, a chemical mechanical polishing (CMP) process, an etching process, a dry grinding process, one or more other applicable processes, or a combination thereof. In some other embodiments where the semiconductor devices 506 have different heights, after the planarization process, one of the semiconductor devices 506 may be buried in the protection layer 512, while the other semiconductor devices 506 may be exposed from the protection layer 512.

[0137] Then, according to some embodiments, when the above structure is fixed on the dicing tape T, along Figure 4D The cutting groove G shown in the figure is subjected to a singulation process (also called a sawing process) to form a plurality of separate package structures. Figure 4D , one of the package structures is shown. Afterwards, each package structure is removed from the dicing tape T by using a pick and place tool (not shown).

[0138] like Figure 4E As shown, according to some embodiments, placing (via a pick and place tool) Figure 4D The resulting package structure in FIG. 1 is such that the first surface 110A of the interposer substrate 110 faces the package substrate 102. Thereafter, the interposer substrate 110 (integrated with the semiconductor device 504 and the semiconductor device 506) is stacked over the package substrate 102 and then bonded to the conductive element 108 via the conductive structure 116, similar to the previous Figure 1F The embodiments discussed in .

[0139] In some embodiments, the interposer substrate 110 and the package substrate 102 are then pressed against each other at high temperature. As a result, the interposer substrate 110 is bonded to the package substrate 102 via the conductive structure 116. In some embodiments, a thermal compression process is used to achieve the above bonding process. In some embodiments, an underfill element 126 is formed to surround and protect the conductive structure 116 and the conductive element 108 between the interposer substrate 110 and the package substrate 102, similar to the previous Figure 1F The embodiments discussed in .

[0140] Then, according to some embodiments, Figure 4F As shown, the carrier substrate 100 is removed to expose the surface of the package substrate 102. In some embodiments, conductive bumps 514 are then formed over the surface of the package substrate 102 that was originally covered by the carrier substrate 100. Figure 4F Each conductive bump 514 can be electrically connected to one of the conductive features 106 of the package substrate 102. The conductive bump 514 enables electrical connection between the package structure and an external device (not shown). The material and formation method of the conductive bump 514 can be different from the material of the conductive bump 514. Figure 1G The conductive bumps 136 shown are made of the same or similar materials and are formed by the same or similar methods.

[0141] As a result, the formation Figure 4F The process of the resulting package structure (including the chip on wafer on substrate (CoWoS) package structure) is shown. Figure 4F In the package structure, the semiconductor device 504 is housed in a groove 502 formed on the second surface 110B of the interposer substrate 110, and the second surface 110B faces and is adjacent to the semiconductor device 506. Each semiconductor device 504 can be directly interconnected to one or more semiconductor devices 506 (note that one of the semiconductor devices 504 can be a bridge device for bridging two or more semiconductor devices 506). Therefore, RC delay and / or signal noise can be significantly reduced, and the signal transmission speed can be improved. As a result, the electrical performance of the overall package structure is improved. In addition, due to the groove 502 of the interposer substrate 110, it can also be based on the above-mentioned groove 118 (see Figure 1D ) to achieve a smaller overall package size for similar reasons.

[0142] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figure 5 is a cross-sectional view of a package structure according to some embodiments. In some embodiments, one or more semiconductor devices 504 received in the groove 502 of the interposer substrate 110 are not only electrically connected to the semiconductor device 506 above the interposer substrate 110, but also directly electrically connected to the interposer substrate 110. For example, according to some embodiments, Figure 5 As shown, a semiconductor device 504 housed in a groove 502 (e.g., the groove 502 on the left shown in the figure) is further bonded to the interposer substrate 110 (e.g., electrically connected to some internal through-holes 111) by a flip-chip bonding method with the aid of conductive structures 516 (each including a metal pillar 516A and a metal capping layer 516B above the metal pillar 516A) formed on the bottom surface 5022 of the groove 502 and conductive elements 517 (e.g., conductive pillars) on the semiconductor device 504 to form a conductive joint. In some embodiments, the bonding between the semiconductor device 504 and the interposer substrate 110 can be a solder bonding or a direct metal-to-metal (e.g., copper-to-copper) bonding. The materials and formation methods of the conductive structures 516 and the conductive elements 517 can be respectively Figure 4D The conductive structure 509 and the conductive element 508 are made of the same or similar materials and are formed by the same or similar methods. Figure 4C In the aforementioned processing steps shown in FIG. 1 (before the semiconductor device 506 is stacked on the interposer substrate 110), the semiconductor device 504 is placed in the recess 502 and then bonded to the interposer substrate 110 via the conductive joints (conductive structures 516 and conductive elements 517) between the semiconductor device 504 and the bottom surface 5022 of the recess 502. The semiconductor device 504 of this embodiment may have a Figure 3 The structure of the semiconductor device 120 is similar to that of the previously discussed embodiment.

[0143] like Figure 5 As shown, the semiconductor device 504 received in the groove 502 is electrically connected to the semiconductor device 506 stacked on the interposer substrate 110 and the interposer substrate 110 itself. Therefore, the electrical performance of the overall package structure can be further improved.

[0144] In some other embodiments, one or more semiconductor devices 504 received in the recess 502 of the interposer substrate 110 may be electrically connected only to the interposer substrate 110 (i.e., not directly electrically connected to the semiconductor device 506 above the interposer substrate 110), which may be implemented in accordance with Figure 1G and Figure 2 The embodiment of the package structure shown has the same effect.

[0145] Many variations and / or modifications may be made to the embodiments of the present disclosure. For example, in some other embodiments, grooves may also be formed on both the first surface 110A and the second surface 110B of the interposer substrate 110 (e.g., by combining the above embodiments) to accommodate or hold additional semiconductor devices. Additionally or alternatively, the semiconductor device accommodated in the groove of the interposer substrate may also be electrically connected to the package substrate 102, the interposer substrate 110, and / or the semiconductor device above the interposer substrate 110.

[0146] Some embodiments of the present disclosure form a packaging structure, including a packaging substrate, an interposer substrate located above the packaging substrate, and a plurality of semiconductor devices located above the interposer substrate. The interposer substrate also has one or more grooves to accommodate or hold additional semiconductor devices that are not allowed to be mounted on the surface of the interposer substrate. The grooves make the overall packaging structure thinner. Some semiconductor devices accommodated in the grooves of the interposer substrate can also be electrically connected to the interposer substrate and / or the semiconductor devices above the interposer substrate to improve the electrical performance of the overall packaging structure.

[0147] According to some embodiments of the present disclosure, a packaging structure is provided, including a packaging substrate, an interposer substrate, a first semiconductor device, and a second semiconductor device. The interposer substrate is disposed above the packaging substrate. The interposer substrate includes a silicon substrate and has a bottom surface facing and adjacent to the packaging substrate and a first groove formed on the bottom surface. The first semiconductor device is accommodated in the first groove and is electrically connected to the interposer substrate. The second semiconductor device is disposed on a top surface of the interposer substrate opposite to the bottom surface. In some embodiments, the first semiconductor device is disposed on the bottom surface of the first groove, and the bottom surface of the first groove is spaced apart from the top surface of the interposer substrate. In some embodiments, a gap is spaced apart between the first semiconductor device and the packaging substrate. In some embodiments, the packaging substrate has a top surface facing and adjacent to the interposer substrate, and a second groove is formed on the top surface of the packaging substrate and aligned with the first groove of the interposer substrate, wherein the second groove is configured to accommodate the first semiconductor device. In some embodiments, the first semiconductor device extends into the second groove and is electrically connected to the packaging substrate. In some embodiments, the first semiconductor device and the second semiconductor device include different types of electronic devices. In some embodiments, the packaging structure further includes a bottom filling element formed in the first groove and between the first semiconductor device and the bottom surface of the first groove. In some embodiments, the underfill element surrounds and protects a plurality of conductive structures between the first semiconductor device and a bottom surface of the first recess.

[0148] According to some embodiments of the present disclosure, a packaging structure is provided, including a packaging substrate, an interposer substrate, a first semiconductor device, and a second semiconductor device. The interposer substrate is disposed above the packaging substrate. The interposer substrate includes a silicon substrate and has a bottom surface facing and adjacent to the packaging substrate, a top surface opposite to the bottom surface, and a groove formed on the top surface. The first semiconductor device is disposed on the top surface of the interposer substrate. The second semiconductor device is received in the groove and is electrically connected to the first semiconductor device and / or the interposer substrate. In some embodiments, the second semiconductor device is electrically connected to the first semiconductor device through a plurality of first conductive structures between the first semiconductor device and the second semiconductor device. In some embodiments, the second semiconductor device is electrically connected to the interposer substrate through a plurality of second conductive structures between the second semiconductor device and the bottom surface of the groove. In some embodiments, the second semiconductor device is electrically connected to the first semiconductor device through a plurality of first conductive structures between the first semiconductor device and the second semiconductor device, and is also electrically connected to the interposer substrate through a plurality of second conductive structures between the second semiconductor device and the bottom surface of the groove. In some embodiments, the package structure further includes a third semiconductor device disposed on the top surface of the interposer substrate, wherein the second semiconductor device is electrically connected to the first semiconductor device through a plurality of first conductive structures between the first semiconductor device and the second semiconductor device, and is also electrically connected to the third semiconductor device through a plurality of second conductive structures between the third semiconductor device and the second semiconductor device. In some embodiments, the second semiconductor device and the recess are located between and below the first semiconductor device and the third semiconductor device.

[0149] According to some embodiments of the present disclosure, a method for forming a packaging structure is provided. The method includes forming a groove on the surface of an interposer substrate, the interposer substrate including a silicon substrate. The method also includes disposing a first semiconductor device in the groove and on the bottom surface of the groove. The method also includes stacking the interposer substrate and the first semiconductor device above the packaging substrate. In addition, the method also includes disposing a second semiconductor device above the interposer substrate. In some embodiments, the groove is formed on the surface of the interposer substrate facing and adjacent to the packaging substrate, wherein, after the first semiconductor device is disposed in the groove, the method also includes electrically connecting the first semiconductor device to the interposer substrate, and then stacking the interposer substrate and the first semiconductor device above the packaging substrate. In some embodiments, after the interposer substrate and the first semiconductor device are stacked above the packaging substrate, the method also includes electrically connecting the first semiconductor device to the packaging substrate. In some embodiments, the second semiconductor device is disposed on the surface of the interposer substrate having the groove, wherein, after the first semiconductor device is disposed in the groove, the method also includes electrically connecting the first semiconductor device to the interposer substrate. In some embodiments, the second semiconductor device is disposed on a surface of the interposer substrate having a groove, wherein after the second semiconductor device is disposed above the interposer substrate, the method further comprises electrically connecting the first semiconductor device to the second semiconductor device. In some embodiments, the second semiconductor device is disposed on a surface of the interposer substrate having a groove, wherein the method further comprises disposing a third semiconductor device on the surface of the interposer substrate, and after the second and third semiconductor devices are disposed above the interposer substrate, the method further comprises electrically bridging the second and third semiconductor devices by connecting the first semiconductor device disposed in the groove to the second and third semiconductor devices.

[0150] The foregoing text summarizes the features of many embodiments so that those skilled in the art can better understand the present disclosure from various aspects. Those skilled in the art should understand and can easily design or modify other processes and structures based on the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention of the present disclosure. Various changes, substitutions or modifications may be made to the present disclosure without departing from the spirit and scope of the invention of the present disclosure.

Claims

1. A packaging structure, comprising: a packaging substrate; an interposer substrate disposed above the package substrate, wherein the interposer substrate comprises a silicon substrate and has a bottom surface facing and adjacent to the package substrate and a first groove formed on the bottom surface; a first semiconductor device received in the first cavity and electrically connected to the interposer substrate; and a second semiconductor device disposed on a top surface of the interposer substrate opposite to the bottom surface, The package substrate has a top surface facing and adjacent to the interposer substrate, and a second groove is formed on the top surface of the package substrate and aligned with the first groove of the interposer substrate, wherein the second groove is configured to accommodate the first semiconductor device.

2. The packaging structure according to claim 1, wherein: The first semiconductor device is disposed on a bottom surface of the first groove, and the bottom surface of the first groove is spaced apart from the top surface of the interposer substrate.

3. The packaging structure according to claim 1, wherein: A gap is spaced apart between the first semiconductor device and the package substrate.

4. The packaging structure according to claim 1, wherein: The first semiconductor device extends into the second groove and is electrically connected to the package substrate.

5. The packaging structure according to claim 1, wherein: The first semiconductor device and the second semiconductor device include different types of electronic devices. 6 . The package structure as claimed in claim 1 , further comprising an underfill element formed in the first cavity and interposed between the first semiconductor device and a bottom surface of the first cavity.

7. The packaging structure according to claim 6, wherein: The underfill element surrounds and protects a plurality of conductive structures between the first semiconductor device and the bottom surface of the first cavity.

8. A packaging structure, comprising: a packaging substrate; an interposer substrate disposed above the package substrate, wherein the interposer substrate comprises a silicon substrate and has a bottom surface facing and adjacent to the package substrate, a top surface opposite to the bottom surface, a first groove formed on the top surface, and a second groove formed on the bottom surface; a first semiconductor device disposed on the top surface of the interposer substrate; a second semiconductor device disposed in the first recess and electrically connected to the first semiconductor device and / or the interposer substrate; and a third semiconductor device disposed in the second groove, The package substrate has a top surface facing and adjacent to the interposer substrate, and a third groove is formed on the top surface of the package substrate and aligned with the second groove of the interposer substrate, wherein the third groove is configured to accommodate the third semiconductor device.

9. The packaging structure according to claim 8, wherein: The second semiconductor device is electrically connected to the first semiconductor device through a plurality of first conductive structures interposed between the first semiconductor device and the second semiconductor device.

10. The package structure according to claim 8, wherein: The second semiconductor device is electrically connected to the interposer substrate through a plurality of second conductive structures between the second semiconductor device and a bottom surface of the first cavity.

11. The package structure according to claim 8, wherein: The second semiconductor device is electrically connected to the first semiconductor device through a plurality of first conductive structures between the first semiconductor device and the second semiconductor device, and is also electrically connected to the interposer substrate through a plurality of second conductive structures between the second semiconductor device and a bottom surface of the first recess.

12. The package structure of claim 8, further comprising a fourth semiconductor device disposed on the top surface of the interposer substrate, wherein The second semiconductor device is electrically connected to the first semiconductor device through a plurality of first conductive structures interposed between the first semiconductor device and the second semiconductor device, and is also electrically connected to the fourth semiconductor device through a plurality of second conductive structures interposed between the fourth semiconductor device and the second semiconductor device.

13. The package structure according to claim 12, wherein: The second semiconductor device and the first groove are located between and below the first semiconductor device and the fourth semiconductor device.

14. A method for forming a package structure, comprising: forming a groove on a bottom surface of an interposer substrate, wherein the interposer substrate comprises a silicon substrate; Disposing a first semiconductor device in the groove and on a bottom surface of the groove; forming a second groove on a top surface of a packaging substrate; stacking the interposer substrate and the first semiconductor device above the package substrate so that the bottom surface of the interposer substrate faces the top surface of the package substrate and the first semiconductor device is received in the second recess; as well as A second semiconductor device is disposed above the interposer substrate.

15. The method for forming a package structure according to claim 14, in, After the first semiconductor device is disposed in the groove, the method for forming a package structure further includes electrically connecting the first semiconductor device to the interposer substrate, and then stacking the interposer substrate and the first semiconductor device above the package substrate.

16. The method for forming a package structure according to claim 15, wherein: After stacking the interposer substrate and the first semiconductor device over the package substrate, the method of forming a package structure further includes electrically connecting the first semiconductor device to the package substrate.

17. The method for forming a package structure according to claim 14, wherein: The second semiconductor device is disposed on a top surface of the interposer substrate; The method for forming a package structure further includes forming a third groove on the top surface of the interposer substrate, and disposing a third semiconductor device in the third groove and electrically connecting the third semiconductor device to the interposer substrate.

18. The method for forming a package structure according to claim 14, wherein: The second semiconductor device is disposed on a top surface of the interposer substrate; The method for forming a packaging structure also includes forming a third groove on the top surface of the interposer substrate and disposing a third semiconductor device in the third groove, wherein after disposing the second semiconductor device above the interposer substrate, the method for forming a packaging structure also includes electrically connecting the third semiconductor device to the second semiconductor device.

19. The method for forming a package structure according to claim 14, wherein: The second semiconductor device is disposed on a top surface of the interposer substrate; Among them, the method for forming a packaging structure also includes forming a third groove on the top surface of the interposer substrate, disposing a third semiconductor device in the third groove, and disposing a fourth semiconductor device on the top surface of the interposer substrate, and after disposing the second semiconductor device and the fourth semiconductor device above the interposer substrate, the method for forming a packaging structure also includes electrically bridging the second semiconductor device and the fourth semiconductor device by connecting the third semiconductor device disposed in the third groove to the second semiconductor device and the fourth semiconductor device.

Images