Semiconductor Devices

Abstract

A semiconductor device includes a trigger unit. The trigger unit is formed on a semiconductor substrate, includes a trigger circuit, and includes a scan multiplexer circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan multiplexer circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices that output a result signal of the circuit together based on an input, is a subcircuit of the trigger circuit, and occupies a continuous boundary area of ​​the trigger circuit when viewed from a plan view. When viewed from a plan view, at least a first subcircuit and a second subcircuit of the subcircuits overlap in a first overlapping area, and the first overlapping area includes a portion of a first continuous boundary area for the first subcircuit and a portion of a second continuous boundary area for the second subcircuit.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and in particular, to a semiconductor device including a field effect transistor. Background Art

[0002] Semiconductor devices are being considered as important components in the electronics industry due to their small size, multifunctionality and / or low cost. Semiconductor devices can be classified into semiconductor memory devices for storing data, semiconductor logic devices for processing data, and hybrid semiconductor devices including both storage elements and logic elements. With the development of the electronics industry, the demand for semiconductor devices with improved characteristics is growing. For example, the demand for semiconductor devices with high reliability, high performance and / or multifunctionality is growing. In order to meet this demand, the complexity and / or integration density of semiconductor devices are improved. Summary of the invention

[0003] An embodiment of the inventive concept provides a semiconductor device in which a logic device such as a flip flop having improved electrical characteristics is provided.

[0004] According to some aspects, a semiconductor device includes a trigger unit. The trigger unit is formed on a semiconductor substrate, includes a trigger circuit, and includes various circuits. When viewed from a plan view, a scan multiplexer (MUX) circuit is formed in a first continuous boundary region of the trigger unit. When viewed from a plan view, a master latch circuit is formed in a second continuous boundary region of the trigger unit, and the master latch circuit is formed to be adjacent to the scan MUX circuit in a plane length direction. When viewed from a plan view, a clock driver circuit is formed in a third continuous boundary region of the trigger unit, and the third continuous boundary region partially overlaps with the first continuous boundary region in a first overlapping region, so that the first part of the scan MUX circuit in the first overlapping region overlaps with the first part of the clock driver circuit in the first overlapping region, and the second part of the scan MUX circuit is adjacent to the second part of the clock driver circuit across the first overlapping region in a plane height direction. When viewed from a plan view, an output circuit is formed in a fourth continuous boundary region of the trigger unit. The trigger unit also includes a slave latch circuit. Each of the scan MUX circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices that together output a result signal of the circuit based on an input, and is a sub-circuit of the flip-flop circuit.

[0005] According to some aspects, a semiconductor device includes a trigger unit. The trigger unit is formed on a semiconductor substrate, includes a trigger circuit, and includes a scan MUX circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan MUX circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices that output a result signal of the circuit together based on an input, is a subcircuit of the trigger circuit, and occupies a continuous boundary area of ​​the trigger circuit when viewed from a plan view. When viewed from a plan view, at least a first subcircuit and a second subcircuit of the subcircuits overlap in a first overlapping area, and the first overlapping area includes a portion of a first continuous boundary area for the first subcircuit and a portion of a second continuous boundary area for the second subcircuit.

[0006] According to some aspects, a semiconductor device includes a trigger unit formed on a semiconductor substrate and including a trigger circuit. The trigger unit includes: a scan MUX circuit including a plurality of active devices that output a scan MUX signal together; a master latch circuit including a plurality of active devices that output a first latch signal together; a slave latch circuit including a plurality of active devices that output a second latch signal together; a clock driver circuit including a plurality of active devices that output a clock driver signal together; and an output circuit including a plurality of active devices that output an output signal of the trigger circuit together. Each of the scan MUX circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit forms a corresponding subcircuit. When viewed from a plan view, each of the scan MUX circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit occupies a corresponding boundary area of ​​the trigger circuit. When viewed from a plan view, a first corresponding boundary area for a first subcircuit in the subcircuit overlaps a second corresponding boundary area for a second subcircuit in the subcircuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Example embodiments will be more clearly understood from the following brief description taken in conjunction with the accompanying drawings.The accompanying drawings illustrate non-limiting example embodiments as described herein.

[0008] Figure 1 is a plan view illustrating a logic region of a semiconductor device according to an embodiment of the inventive concept.

[0009] Figure 2 is a logic circuit diagram illustrating a flip-flop circuit of a semiconductor device according to an embodiment of the inventive concept.

[0010] Figure 3 is a plan view illustrating a trigger unit of a semiconductor device according to an embodiment of the inventive concept.

[0011] Figure 4 It shows the composition Figure 3 A plan view of multiple blocks of a trigger unit.

[0012] Figure 5 It shows the composition Figure 4 A plan view of multiple blocks of a trigger unit.

[0013] FIG. 6A to FIG. 6D are respectively along Figure 3 Cross-sectional views taken along lines A-A', B-B', CC' and D-D'.

[0014] FIG. 7A to FIG. 7D are respectively along Figure 3 sectional views taken along lines AA′, BB′, CC′, and DD′ to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0015] Figure 8 is a logic circuit diagram illustrating a flip-flop circuit of a semiconductor device according to an embodiment of the inventive concept.

[0016] Fig. 9 is a plan view illustrating a plurality of blocks constituting a flip-flop unit of a semiconductor device according to an embodiment of the inventive concept.

[0017] Fig.10 It shows the composition Fig. 9 A plan view of multiple blocks of a trigger unit.

[0018] Fig.11 It is along Figure 3 8 is a cross-sectional view taken along line AA′ of FIG. 1 to illustrate a semiconductor device according to an embodiment of the inventive concept.

[0019] Fig. 12A and Fig. 12B It is along Figure 3 sectional views taken along lines AA′ and BB′ are shown to illustrate semiconductor devices according to other embodiments of the inventive concept.

[0020] Fig.13A and Fig. 13B It is along Figure 3 sectional views taken along lines AA′ and BB′ are shown to illustrate semiconductor devices according to other embodiments of the inventive concept.

[0021] FIG. 14A to FIG. 14C are enlarged plan views each showing a portion of a semiconductor device according to an embodiment of the inventive concept (eg Figure 3 'M').

[0022] Fig.15 , Fig.16 and Fig.17 are plan views each showing a plurality of blocks constituting a trigger unit according to an embodiment of the inventive concept.

[0023] It should be noted that these drawings are intended to illustrate the general characteristics of methods, structures and / or materials used in certain example embodiments and to supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as limiting the range of values ​​or characteristics covered by the example embodiments. For example, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or enlarged for clarity. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0024] Figure 1 is a plan view showing a logic area of ​​a semiconductor device according to an embodiment of the inventive concept. As used herein, a semiconductor device may refer to, for example, a device such as a semiconductor chip (e.g., a memory chip and / or a logic chip formed on a die), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a stacked package device including multiple packages. These devices may be formed using ball grid arrays, wire bonding, through-substrate vias or other electrical connection elements, and may include memory devices such as volatile memory devices or non-volatile memory devices. The semiconductor package may include a package substrate, one or more semiconductor chips, and an encapsulant formed on the package substrate and covering the semiconductor chip. In one embodiment, the trigger unit described herein is included in a logic chip such as an application processor.

[0025] Reference Figure 1 , a plurality of trigger cells FF1-FF4 may be provided on a logic region of the substrate 100. The trigger cells FF1-FF4 may be two-dimensionally arranged on the logic region of the substrate 100. The trigger cells FF1-FF4 may include first to fourth trigger cells FF1-FF4. For example, each of the first to fourth trigger cells FF1-FF4 may be a one-bit trigger cell.

[0026] The second trigger unit FF2 may be adjacent to the first trigger unit FF1 in the second direction D2. The first trigger unit FF1 may be adjacent to the third trigger unit FF3 in the first direction D1. The fourth trigger unit FF4 may be adjacent to the third trigger unit FF3 in the second direction D2. For the purpose of description here, the first direction D1 may also be described as a plane height direction, and the second direction D2 may also be described as a plane length direction.

[0027] A plurality of power lines M1_R may be provided on a logic region of the substrate 100. The power lines M1_R may include first to fifth power lines M1_R1-M1_R5. The first to fifth power lines M1_R1-M1_R5 may extend in the second direction D2 and may be parallel to each other. A power supply voltage VDD may be applied to the first power line M1_R1, the third power line M1_R3, and the fifth power line M1_R5. A ground voltage VSS may be applied to the second power line M1_R2 and the fourth power line M1_R4. In some embodiments, a ground voltage VSS may be applied to the first power line M1_R1, the third power line M1_R3, and the fifth power line M1_R5, and a power supply voltage VDD may be applied to the second power line M1_R2 and the fourth power line M1_R4, but the inventive concept is not limited to this example. For example, the VDD line and the VSS line may be arranged at different positions relative to each other in other ways.

[0028] The first to third power lines M1_R1, M1_R2, and M1_R3 may be arranged to intersect the first trigger unit FF1 and the second trigger unit FF2. The third to fifth power lines M1_R3, M1_R4, and M1_R5 may be arranged to intersect the third trigger unit FF3 and the fourth trigger unit FF4. The second power line M1_R2 may intersect the center of each of the first trigger unit FF1 and the second trigger unit FF2. The fourth power line M1_R4 may intersect the center of each of the third trigger unit FF3 and the fourth trigger unit FF4.

[0029] In the following and similar to the discussion above, Figure 1 The length in the first direction D1 may be defined as a 'plane height'. Each of the first to fifth power lines M1_R1-M1_R5 may have a first plane height H1. A distance between adjacent power lines of the first to fifth power lines M1_R1-M1_R5 may be a second plane height H2.

[0030] The number of steps of the trigger unit can be determined depending on the number of active regions CAR included in a single trigger unit. A trigger unit including one active region CAR can be a single-step trigger unit. Figure 1In the illustrated case where each of the flip-flop cells FF1 - FF4 includes two active regions CAR, each of the flip-flop cells FF1 - FF4 may be a two-step flip-flop cell.

[0031] The plane height of the N-step trigger unit can be (N+1)×H1+N×H2. For example, the height of the single-step trigger unit can be (1+1)×H1+1×H2 (i.e., 2H1+H2). The height of the two-step trigger units FF1-FF4 can be (2+1)×H1+2×H2 (i.e., 3H1+2H2). The height of the three-step trigger unit can be (3+1)×H1+3×H2 (i.e., 4H1+3H2).

[0032] The filling unit FC may be inserted between the trigger units FF1-FF4 adjacent to each other in the second direction D2. The filling unit FC may be a dummy unit that does not have a separate function in terms of the circuit. The distance between the trigger units FF1-FF4 adjacent to each other in the second direction D2 (for example, in the plane length direction) may be a first distance DI1.

[0033] As another example, the trigger cells FF1-FF4 adjacent to each other in the second direction D2 may contact each other. For example, the filling cell FC may be omitted between the trigger cells FF1-FF4 adjacent to each other in the second direction D2. In this case, the first distance DI1 may be zero.

[0034] Figure 2 is a logic circuit diagram showing a trigger circuit of a semiconductor device according to an embodiment of the inventive concept. Figure 2 , Figure 1 Each of the flip-flop units FF1-FF4 may include Figure 2 Hereinafter, the first flip-flop unit FF1 will be described as a representative example of the flip-flop units FF1-FF4.

[0035] The first trigger unit FF1 may include a scan multiplexer (MUX) block SCM, a master latch block MAL, a slave latch block SLL, a clock driver block CLD, and an output block OUT. Each of these blocks includes a circuit, so the first trigger unit FF1 is also described here as including a scan MUX circuit SCM, a master latch circuit MAL, a slave latch circuit SLL, a clock driver circuit CLD, and an output circuit OUT. Each of these circuits may also be described as a sub-circuit, such as a sub-circuit of a trigger unit.

[0036] In more detail, the clock driver block CLD may be connected to the trigger circuit and may include a clock circuit to which the external clock signal CK is input. The clock driver block CLD may be configured to invert the external clock signal CK into a clock inversion signal nclk. The clock driver block CLD may also be configured to invert the clock inversion signal nclk into a clock signal bclk.

[0037] The scan MUX block SCM may be a core circuit for performing scan and flip-flop functions. The scan MUX block SCM may select one of the external input signal D and the scan input signal SI in response to the scan enable signal SE, and may then provide an internal signal to the first node N1 based on the selected signal.

[0038] Each of the master latch block MAL and the slave latch block SLL may be a buffer. The master latch block MAL may latch an internal signal based on a clock signal bclk and a clock inversion signal nclk. The output of the master latch may be input to the slave latch block SLL through a second node N2.

[0039] The slave latch block SLL can latch the output of the master latch based on the clock signal bclk and the clock inversion signal nclk. The output of the slave latch block SLL can be provided as an output signal Q through the third node N3 and the output block OUT. In addition, Figure 2 The R in here refers to the reset signal.

[0040] Figure 3 is a plan view illustrating a trigger unit of a semiconductor device according to an embodiment of the inventive concept. Figure 4 It shows the composition Figure 3 A plan view of multiple blocks of a trigger unit. Figure 5 It shows the composition Figure 4 A plan view of multiple blocks of a trigger unit. In detail, Figure 5 Only the components in Figure 4 shown in the plan view but omitted from it Figure 3 The specific pattern of the flip-flop unit block shown. Since the continuous boundary surrounds each block in these figures, Figure 4 and Figure 5 The blocks depicted in are also described as continuous boundary regions.

[0041] Figure 1 Each of the flip-flop units FF1-FF4 may include Figure 3 The trigger cell is provided on the substrate 100. Hereinafter, the first trigger cell FF1 may be described as a representative example of the trigger cells FF1-FF4.

[0042] Reference Figures 1 to 5, the first trigger unit FF1 may be provided on the substrate 100. The first trigger unit FF1 may include a plurality of logic transistors. The first interconnection line M1 may be provided on the logic transistor. The second interconnection line M2 may be provided on the first interconnection line M1. The first interconnection line M1 may constitute a first metal layer, and the second interconnection line M2 may constitute a second metal layer. The second metal layer may be placed at a higher vertical height than the first metal layer. FIG. 6A to FIG. 6D A detailed structure of the first flip-flop unit FF1 is described.

[0043] The first interconnection line M1 may include first to third power lines M1_R1, M1_R2, and M1_R3 extending in the second direction D2 and parallel to each other. Each of the first to third power lines M1_R1, M1_R2, and M1_R3 may have first and second side walls SW3 and SW4 opposite to each other. The first and second side walls SW3 and SW4 may extend in the second direction D2 and may be parallel to each other.

[0044] The first active region CAR1 may be defined between the first power line M1_R1 and the second power line M1_R2. The second active region CAR2 may be defined between the second power line M1_R2 and the third power line M1_R3 (see, for example, Figure 5 ). Each of the first active region CAR1 and the second active region CAR2 may include a p-type metal oxide semiconductor field effect transistor (PMOSFET) region PR and an n-type metal oxide semiconductor field effect transistor (NMOSFET) region NR of the substrate 100. For example, each of the first active region CAR1 and the second active region CAR2 may be a complementary metal oxide semiconductor field effect transistor (CMOSFET) region.

[0045] The first flip-flop unit FF1 may include a scan MUX block SCM, a master latch block MAL, a first slave latch block SLL1, a second slave latch block SLL2, a clock driver block CLD, and an output block OUT. Each of these blocks may include a boundary region, such as a continuous boundary region. For example, each of these blocks may include a continuous boundary region that includes all or part of a sub-circuit (e.g., a scan MUX circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, or all or part of an output circuit). The first slave latch block SLL1 and the second slave latch block SLL2 may constitute Figure 2The slave latch circuit SLL. Each of the scan MUX block SCM, the master latch block MAL, the first slave latch block SLL1, the second slave latch block SLL2, the clock driver block CLD and the output block OUT may include a circuit configured to independently perform its own function. For example, each of the scan MUX circuit, the master latch circuit, the slave latch circuit, the clock driver circuit and the output circuit represented by the scan MUX block SCM, the master latch block MAL, the combined first slave latch block SLL1 and the second slave latch block SLL2, the clock driver block CLD and the output block OUT can be a sub-circuit of the trigger circuit (which occupies the boundary area of ​​the trigger circuit when viewed from a plan view) and includes a plurality of active devices, such as transistors, which output the result signal of the sub-circuit together based on the input.

[0046] The unit including the first active area CAR1 and the second active area CAR2 can be defined as a multi-plane height unit. When viewed in a plan view, the functional blocks SCM, MAL, SLL1, SLL2, CLD and OUT of the first trigger unit FF1 can be two-dimensionally arranged on the multi-plane height unit. According to an embodiment of the inventive concept, the functional blocks SCM, MAL, SLL1, SLL2, CLD and OUT can be efficiently arranged on the multi-plane height unit, which can make it possible to improve the integration density and electrical characteristics of the first trigger unit FF1.

[0047] The scan MUX block SCM may be provided on the first active area CAR1. The scan MUX block SCM may include a portion of the first power line M1_R1 and a portion of the second power line M1_R2. In detail, the scan MUX block SCM may have a first boundary BD1 and a second boundary BD2. The first boundary BD1 and the second boundary BD2 may be opposite to each other in the first direction D1. The first boundary BD1 and the second boundary BD2 may extend in the second direction D2. The first boundary BD1 of the scan MUX block SCM may be aligned with the first side wall SW3 of the first power line M1_R1, and the second boundary BD2 of the scan MUX block SCM may be aligned with the second side wall SW4 of the second power line M1_R2. When viewed from a plan view, the scan MUX block SCM may have a rectangular shape to form a continuous boundary area of ​​the trigger circuit.

[0048] The master latch block MAL may be provided on the first active area CAR1 and the second active area CAR2. The master latch block MAL may be adjacent to the scan MUX block SCM in the second direction D2. The scan MUX circuit SCM and the master latch circuit MAL may be arranged at the same plane height as each other and adjacent to each other in the plane length direction. The master latch block MAL may include a portion of the first power line M1_R1, a portion of the second power line M1_R2, and a portion of the third power line M1_R3.

[0049] The master latch block MAL may include a first region RG1 on the first active region CAR1 and a second region RG2 on the second active region CAR2. In this manner, the master latch block MAL may extend from the first active region CAR1 to the second active region CAR2.

[0050] The first region RG1 of the master latch block MAL may have a third boundary BD3 and a fourth boundary BD4. The third boundary BD3 and the fourth boundary BD4 may be opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2. The third boundary BD3 may be aligned with the first side wall SW3 of the first power line M1_R1, and the fourth boundary BD4 may be aligned with the second side wall SW4 of the second power line M1_R2. The second region RG2 of the master latch block MAL may have a fifth boundary BD5. The fifth boundary BD5 may be aligned with the second side wall SW4 of the third power line M1_R3. When viewed from a plan view, the master latch block MAL may have a polygonal shape and may form a continuous boundary region of a trigger circuit.

[0051] The first slave latch block SLL1 may be provided on the second active area CAR2. The first region RG1 of the master latch block MAL may be adjacent to the first slave latch block SLL1 in the first direction D1. The second region RG2 of the master latch block MAL may be adjacent to the first slave latch block SLL1 in the second direction D2. The first slave latch block SLL1 may include a portion of the second power line M1_R2 and a portion of the third power line M1_R3.

[0052] The first slave latch block SLL1 may have a sixth boundary BD6 and a seventh boundary BD7. The sixth boundary BD6 and the seventh boundary BD7 may be opposite to each other in the first direction D1. The sixth boundary BD6 and the seventh boundary BD7 may extend in the second direction D2. The sixth boundary BD6 may be aligned with the first side wall SW3 of the second power line M1_R2, and the seventh boundary BD7 may be aligned with the second side wall SW4 of the third power line M1_R3. When viewed from a plan view, the first slave latch block SLL1 may have a rectangular shape and may form a continuous boundary region of the trigger circuit.

[0053] In the second overlapping region OR2, the first region RG1 of the master latch block MAL and the first slave latch block SLL1 overlap each other. The second overlapping region OR2 may extend in the second direction D2. The second overlapping region OR2 may substantially overlap with the second power line M1_R2. The second overlapping region OR2 may have a second width W2 in the first direction D1. The master latch block MAL and the first slave latch block SLL1 may share the second power line M1_R2 through the second overlapping region OR2. In this way, at least a first sub-circuit (e.g., a master latch circuit MAL) and a second sub-circuit (e.g., a slave latch circuit SLL including a first slave latch block SLL1 and a second latch block SLL2) in a sub-circuit forming a trigger circuit overlap in a second overlapping region (e.g., OR2) in a plan view. The first overlapping region includes a portion of a first continuous boundary region for the first sub-circuit and a portion of a second continuous boundary region for the second sub-circuit.

[0054] In the fourth overlap region OR4, the second region RG2 of the master latch block MAL and the first slave latch block SLL1 overlap each other. The fourth overlap region OR4 may extend in the first direction D1. The fourth overlap region OR4 may have a fourth width W4 in the second direction D2. The fourth width W4 may be smaller than the second width W2.

[0055] The master latch block MAL and the first slave latch block SLL1 may share the second active region CAR2 through the fourth overlap region OR4. The second active region CAR2 shared by the master latch block MAL and the first slave latch block SLL1 may be a region to which the second and third power lines M1_R2 and M1_R3 are electrically connected.

[0056] The clock driver block CLD may be provided on the second active area CAR2. The scan MUX block SCM may be adjacent to the clock driver block CLD in the first direction D1. The first slave latch block SLL1 may be adjacent to the clock driver block CLD in the second direction D2. The clock driver block CLD may include a portion of the second power line M1_R2 and a portion of the third power line M1_R3.

[0057] The clock driver block CLD may have an eighth boundary BD8 and a ninth boundary BD9. The eighth boundary BD8 and the ninth boundary BD9 may be opposite to each other in the first direction D1. The eighth boundary BD8 and the ninth boundary BD9 may extend in the second direction D2. The eighth boundary BD8 may be aligned with the first side wall SW3 of the second power line M1_R2, and the ninth boundary BD9 may be aligned with the second side wall SW4 of the third power line M1_R3. When viewed from a plan view, the clock driver block CLD may have a rectangular shape and may form a continuous boundary region of the trigger circuit.

[0058] The second slave latch block SLL2 may be provided on the second active area CAR2. The scan MUX block SCM may be adjacent to the second slave latch block SLL2 in the first direction D1. The clock driver block CLD may be adjacent to the second slave latch block SLL2 in the second direction D2. The clock driver block CLD may be interposed between the first slave latch block SLL1 and the second slave latch block SLL2. The first slave latch block SLL1 may be spaced apart from the second slave latch block SLL2 in the second direction D2. The second slave latch block SLL2 may include a portion of the second power line M1_R2 and a portion of the third power line M1_R3.

[0059] The second slave latch block SLL2 may have a tenth boundary BD10 and an eleventh boundary BD11. The tenth boundary BD10 and the eleventh boundary BD11 may be opposite to each other in the first direction D1. The tenth boundary BD10 and the eleventh boundary BD11 may extend in the second direction D2. The tenth boundary BD10 may be aligned with the first side wall SW3 of the second power line M1_R2, and the eleventh boundary BD11 may be aligned with the second side wall SW4 of the third power line M1_R3. When viewed from a plan view, the second slave latch block SLL2 may have a rectangular shape and may form a continuous boundary region of the trigger circuit.

[0060] The output block OUT may be provided on the second active area CAR2. The scan MUX block SCM may be adjacent to the output block OUT in the first direction D1. The second slave latch block SLL2 may be adjacent to the output block OUT in the second direction D2. The slave latch circuit SLL and the output circuit OUT may be arranged at the same plane height as each other below the plane height of the first area RG1 of the scan MUX circuit SCM and the master latch circuit MAL, and may be arranged adjacent to each other along the plane length direction. When the slave (such as, for example Figure 5 When viewed in a plan view (shown in FIG), the scan MUX circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit may be arranged in a rectangular area. The output block OUT may include a portion of the second power line M1_R2 and a portion of the third power line M1_R3.

[0061] The output block OUT may have a twelfth boundary BD12 and a thirteenth boundary BD13. The twelfth boundary BD12 and the thirteenth boundary BD13 may be opposite to each other in the first direction D1. The twelfth boundary BD12 and the thirteenth boundary BD13 may extend in the second direction D2. The twelfth boundary BD12 may be aligned with the first side wall SW3 of the second power line M1_R2, and the thirteenth boundary BD13 may be aligned with the second side wall SW4 of the third power line M1_R3. The output block OUT may have a rectangular shape.

[0062] In the third overlap region OR3, the output block OUT and the second slave latch block SLL2 overlap each other. The third overlap region OR3 may extend in the first direction D1. The third overlap region OR3 may have a third width W3 in the second direction D2. The third width W3 may be less than the second width W2. The third width W3 may be substantially equal to the fourth width W4.

[0063] The output block OUT and the second slave latch block SLL2 may share the second active region CAR2 through the third overlap region OR3. The second active region CAR2 shared by the output block OUT and the second slave latch block SLL2 may be a region to which the second power line M1_R2 and the third power line M1_R3 are electrically connected. In addition, as shown below, for example, Figure 6B As further described, the third overlap region OR3 may include a first active device (such as a transistor) that is part of a sub-circuit forming the output circuit OUT and is also part of a sub-circuit forming the slave latch circuit SLL. The transistor may include a source / drain region (e.g., a source / drain pattern to be described below) shared by the output circuit OUT and the slave latch circuit SLL.

[0064] Therefore, if Figure 5 As can be seen from the example implementation of the present invention, when viewed from a plan view, at least a first sub-circuit (such as an output circuit OUT or a scan MUX circuit SCM) and a second sub-circuit (such as a slave latch circuit SLL) overlap in a first overlapping region (e.g., OR3 or OR1). Note that terms such as "first", "second", "third", etc. may be used as naming conventions here and may be used differently to describe different parts of circuits and devices based on the context of the discussion. For example, the first overlapping region (e.g., OR3 or OR1) includes a portion of a first continuous boundary region for the first sub-circuit (e.g., an output block OUT or a scan MUX block SCM) and a portion of a second continuous boundary region for the second sub-circuit (e.g., a second slave latch block SLL2). The second sub-circuit (e.g., a slave latch circuit SLL) includes a third continuous boundary region (e.g., a first slave latch block SLL1). A first group of active devices among the plurality of active devices that together output the result signal of the second sub-circuit (e.g., for the slave latch circuit SLL) is located in the second continuous boundary region (e.g., the second slave latch block SLL2), and the rest of the plurality of active devices that together output the result signal of the second sub-circuit is located in the third continuous boundary region (e.g., the first slave latch block SLL1). In addition, at least a portion of the third sub-circuit (e.g., the clock driver circuit CLD) of the flip-flop circuit is located in a fourth continuous boundary region (e.g., the clock driver block CLD) between the second continuous boundary region and the third continuous boundary region.

[0065] In the first overlapping region OR1, the scan MUX block SCM overlaps with the clock driver block CLD, the second slave latch block SLL2, and the output block OUT. The first overlapping region OR1 may extend in the second direction D2. The first overlapping region OR1 may extend from the output block OUT to the clock driver block CLD in the second direction D2. The first overlapping region OR1 may substantially overlap with the second power line M1_R2. The first overlapping region OR1 may have a first width W1 in the first direction D1. The first width W1 may be substantially equal to the second width W2.

[0066] The scan MUX block SCM can share the second power line M1_R2 with the clock driver block CLD, the second slave latch block SLL2 and the output block OUT through the first overlapping area OR1. As shown, the first portion of the scan MUX circuit SCM in the first overlapping area (e.g., OR1) overlaps with the first portion of the clock driver circuit CLD in the first overlapping area, and shares the portion of the second power line M1_R2 in the first overlapping area with it, and the second portion of the scan MUX circuit SCM is adjacent to the second portion of the clock driver circuit (CLD) in the plane height direction across the first overlapping area without overlapping.

[0067] FIG. 6A to FIG. 6D are respectively along Figure 3 Cross-sectional views taken along lines A-A', B-B', CC' and D-D'. Figure 3 and FIG. 6A to FIG. 6D The semiconductor device shown may be a trigger circuit actually implemented on a substrate (for example, see Figures 1 to 5 An example of a method described in .

[0068] Reference Figure 3 , Figure 4 , Figure 5 and FIG. 6A to FIG. 6D , the first flip-flop cell FF1 may be provided on the substrate 100. Logic transistors constituting a logic circuit may be provided on the first flip-flop cell FF1.

[0069] The substrate 100 may include a PMOSFET region PR and an NMOSFET region NR. The substrate 100 may be a semiconductor substrate or a compound semiconductor substrate including silicon, germanium, silicon germanium, etc. For example, the substrate 100 may be a silicon wafer.

[0070] The PMOSFET region PR and the NMOSFET region NR may constitute a first active region CAR1. The PMOSFET region PR of the first active region CAR1 may be adjacent to the NMOSFET region NR in the first direction D1. The PMOSFET region PR and the NMOSFET region NR may constitute a second active region CAR2. The NMOSFET region NR of the second active region CAR2 may be adjacent to the PMOSFET region PR in the first direction D1. Each of the PMOSFET region PR and the NMOSFET region NR may be described as an active region.

[0071] The PMOSFET region PR and the NMOSFET region NR may be defined by a second trench TR2 formed in an upper portion of the substrate 100. The second trench TR2 may be located between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D1, with the second trench TR2 interposed therebetween. Each of the PMOSFET region PR and the NMOSFET region NR may extend in a second direction D2 intersecting the first direction D1.

[0072] The first active pattern AP1 and the second active pattern AP2 may be provided on the PMOSFET region PR and the NMOSFET region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2 and may be parallel to each other. The first active pattern AP1 and the second active pattern AP2 may protrude vertically from the surface of the substrate 100 and may be a portion of the substrate (e.g., a portion formed in an etching process), or may be epitaxially grown from the substrate. The first trench TR1 may be provided between adjacent first active patterns in the first active pattern AP1 and between adjacent second active patterns in the second active pattern AP2. The first trench TR1 may be shallower than the second trench TR2.

[0073] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may be formed of or include silicon oxide. The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may vertically protrude beyond the device isolation layer ST (eg, see Fig.6D ). Each of the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may be shaped like a fin. The device isolation layer ST may not cover the upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2. The device isolation layer ST may cover the lower sidewall of the first active pattern AP1 and the lower sidewall of the second active pattern AP2.

[0074] A first source / drain pattern SD1 may be provided on an upper portion of the first active pattern AP1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., p-type). A first channel pattern CH1 may be interposed between a pair of first source / drain patterns SD1. A second source / drain pattern SD2 may be provided on an upper portion of the second active pattern AP2. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., n-type). A second channel pattern CH2 may be interposed between a pair of second source / drain patterns SD2.

[0075] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth process. As an example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may have top surfaces coplanar with top surfaces of the first channel pattern CH1 and the second channel pattern CH2. As another example, the top surfaces of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surfaces of the first channel pattern CH1 and the second channel pattern CH2.

[0076] The first source / drain pattern SD1 may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of a semiconductor element in the substrate 100. Therefore, the first source / drain pattern SD1 may apply compressive stress to the first channel pattern CH1. As an example, the second source / drain pattern SD2 may include the same semiconductor material (e.g., Si) as the substrate 100.

[0077] The width of the upper portion of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 in the second direction D2 may be a third width W3. The width of the upper portion of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be substantially equal to the third width W3 of the third overlap region OR3. Terms such as "same", "equal", "planar" or "coplanar" as used herein encompass being exactly the same or nearly exactly the same (including variations that may occur, for example, due to manufacturing processes). Unless otherwise indicated by the context or other statements, the term "substantially" may be used here to emphasize this meaning.

[0078] The gate electrode GE may be provided to cross the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1. The gate electrode GE may be arranged in the second direction D2. When viewed in a plan view, the gate electrode GE may overlap the first channel pattern CH1 and the second channel pattern CH2. Each gate electrode GE may surround the top surface and opposite side surfaces of each of the first channel pattern CH1 and the second channel pattern CH2.

[0079] Return to reference Fig.6D , the first gate electrode GE may be provided on the first top surface TS1 of the first channel pattern CH1 and on at least one of the first sidewalls SW1 of the first channel pattern CH1. The second gate electrode GE may be provided on the second top surface TS2 of the second channel pattern CH2 and on at least one of the second sidewalls SW2 of the second channel pattern CH2. For example, the transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., FinFET) in which the gate electrode GE is disposed to three-dimensionally surround the channel patterns CH1 and CH2. In some embodiments, as Fig.6D As shown, one gate electrode GE spans across the overlap region (eg, OR2 ), and two of the active regions are separated by the overlap region.

[0080] Return to reference Figure 3 , Figure 4 , Figure 5 and FIG. 6A to FIG. 6D , a pair of gate spacers GS may be disposed on opposite side surfaces of each gate electrode GE. The gate spacer GS may extend along the gate electrode GE and in the first direction D1. The top surface of the gate spacer GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer insulating layer 110 to be described below. The gate spacer GS may be formed of at least one of SiCN, SiCON, and SiN, or include at least one of SiCN, SiCON, and SiN. In one embodiment, the gate spacer GS may be a multilayer structure including at least two different materials selected from SiCN, SiCON, and SiN.

[0081] The gate electrode GE may be divided into a plurality of gate electrodes GE by a gate separation pattern GDP. For example, the gate separation pattern GDP may divide the gate electrode GE extending in the first direction D1 into two gate electrodes GE arranged in the first direction D1. The gate separation pattern GDP may include an insulating material (e.g., at least one of SiO, SiON, SiCN, SiCON, and SiN).

[0082] A gate capping pattern GP may be provided on each gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE in the first direction D1. The gate capping pattern GP may be formed of or include at least one of materials having an etching selectivity with respect to a first interlayer insulating layer 110 and a second interlayer insulating layer 120 to be described below. Specifically, the gate capping pattern GP may be formed of or include at least one of SiON, SiCN, SiCON, and SiN.

[0083] The gate dielectric pattern GI may be interposed between the gate electrode GE and the first active pattern AP1 and between the gate electrode GE and the second active pattern AP2. The gate dielectric pattern GI may extend along the bottom surface of the gate electrode GE thereon. As an example, the gate dielectric pattern GI may cover the first top surface TS1 and two opposite first sidewalls SW1 of the first channel pattern CH1. The gate dielectric pattern GI may cover the second top surface TS2 and two opposite second sidewalls SW2 of the second channel pattern CH2. The gate dielectric pattern GI may cover the top surface of the device isolation layer ST below the gate electrode GE (see, for example, FIG. 1 ). Fig.6D ).

[0084] In one embodiment, the gate dielectric pattern GI may be formed of a high-k dielectric material having a dielectric constant higher than that of the silicon oxide layer, or include the high-k dielectric material. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0085] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be provided on the gate dielectric pattern GI and may be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The first metal pattern may include a work function metal, which can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage may be achieved.

[0086] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W) and molybdenum (Mo) and nitrogen (N). The first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0087] The second metal pattern may include a metallic material having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0088] A first interlayer insulating layer 110 may be provided on the substrate 100. The first interlayer insulating layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. A top surface of the first interlayer insulating layer 110 may be substantially coplanar with a top surface of the gate capping pattern GP and a top surface of the gate spacer GS. A second interlayer insulating layer 120 may be provided on the first interlayer insulating layer 110 to cover the gate capping pattern GP. A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130. In one embodiment, the first to fourth interlayer insulating layers 110-140 may be formed of or include silicon oxide.

[0089] Active contacts AC may be provided to penetrate the first and second interlayer insulating layers 110 and 120 and may be electrically connected to the first and second source / drain patterns SD1 and SD2, respectively. Each active contact AC may be provided between a pair of gate electrodes GE.

[0090] The active contact AC may be a self-aligned contact. For example, the active contact AC may be formed by a self-aligned process using the gate capping pattern GP and the gate spacer GS. For example, the active contact AC may cover at least a portion of the side surface of the gate spacer GS. Although not shown, in some embodiments, the active contact AC may cover a portion of the top surface of the gate capping pattern GP.

[0091] The silicide pattern SC may be interposed between the active contact AC and the first source / drain pattern SD1 and between the active contact AC and the second source / drain pattern SD2. The active contact AC may be electrically connected to the source / drain pattern SD1 or SD2 through the silicide pattern SC. The silicide pattern SC may be formed of or include at least one of metal silicide materials such as titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0092] The active contact AC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of at least one metal of aluminum, copper, tungsten, molybdenum, and cobalt, or include at least one metal of aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the side surface and the bottom surface of the conductive pattern FM. The barrier pattern BM may include at least one of a metal layer and a metal nitride layer. The metal layer may be formed of at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum, or include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may be formed of at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN), or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0093] The maximum width of the active contact AC on the third overlap region OR3 may be substantially equal to the third width W3. In detail, the upper portion of the active contact AC on the third overlap region OR3 may have the third width W3. The width of the active contact AC on the third overlap region OR3 may gradually decrease in a downward direction from top to bottom.

[0094] A first metal layer composed of first interconnection lines M1 may be provided in the third interlayer insulating layer 130. The first interconnection lines M1 may extend in the second direction D2 and may be parallel to each other. Each first interconnection line M1 may be a line or stripe pattern extending in the second direction D2.

[0095] The first interconnection line M1 may include first to third power lines M1_R1, M1_R2, and M1_R3. The width of each of the first to third power lines M1_R1, M1_R2, and M1_R3 in the first direction D1 may be a first width W1 or a second width W2. In other words, the width of each of the first to third power lines M1_R1, M1_R2, and M1_R3 may be substantially equal to the first width W1 of the first overlap region OR1. The width of each of the first to third power lines M1_R1, M1_R2, and M1_R3 may be substantially equal to the second width W2 of the second overlap region OR2.

[0096] The first lower vias V1_a may be respectively interposed between the first interconnection lines M1 and the active contacts AC to electrically connect them to each other. The second lower vias V1_b may be respectively interposed between the first interconnection lines M1 and the gate electrodes GE to electrically connect them to each other.

[0097] As from Figure 6CIt can be seen that in some embodiments, the shared conductive path (e.g., V1_a) contacts and is electrically connected to a first interconnect line, such as a power line (e.g., M1_R2 (VSS)), and is disposed below the first interconnect line. The first active contact (e.g., AC) is connected to the shared conductive path and the source / drain pattern (e.g., one of the second source / drain patterns SD2) of the first sub-circuit (e.g., the scan MUX circuit SCM). The second active contact (e.g., AC) is connected to the shared conductive path and the source / drain pattern (e.g., another of the second source / drain patterns SD2) of the second sub-circuit (e.g., the clock driver circuit CLD). Figure 6C As shown, in the plan view, the overlap region (e.g., OR1) is horizontally between the source / drain pattern of the first sub-circuit and the source / drain pattern of the second sub-circuit. In addition, the source / drain pattern (e.g., SD2) of the first sub-circuit (e.g., the scan MUX circuit SCM) is in the continuous boundary region for the first sub-circuit and outside the overlap region, and the source / drain pattern (e.g., SD2) of the second sub-circuit (e.g., the clock driver circuit CLD) is in the continuous boundary region for the second sub-circuit and outside the overlap region. As can be seen, the first active contact is horizontally separated from the second active contact.

[0098] As from Figure 6C It can also be seen that a plurality of active regions (e.g., PR of CAR1, NR of CAR1, NR of CAR2, and PR of CAR2) are arranged on the substrate in the first direction, a plurality of active contacts (e.g., AC) are respectively formed on the plurality of active regions and electrically connected to the plurality of active regions, and the active contacts adjacent to each other are separated by a separation distance in the first direction D1. In one embodiment, as Figure 6C As shown, adjacent active contacts are located in overlapping regions (e.g. Figure 6C The separation distance in OR1) is smaller than the separation distance between adjacent active contacts outside the overlapping region. Figure 6C As shown, the adjacent active region is a fin-type active region. However, in some embodiments, the adjacent active region may be, for example, a gate-all-around active region.

[0099] Each of the first to third power lines M1_R1, M1_R2, and M1_R3 may be commonly connected to active contacts AC adjacent to each other in the first direction D1. Figure 6C , the second power line M1_R2 may be commonly connected to the active contact AC on the NMOSFET region NR of the first active region CAR1 and the active contact AC on the NMOSFET region NR of the second active region CAR2 through the first lower via V1_a.

[0100] Each of the first interconnection lines M1 on the first and second active regions CAR1 and CAR2 may have a fifth width W5 in the first direction D1. The first width W1 of each of the first to third power lines M1_R1, M1_R2, and M1_R3 may be 1.5 to 5 times greater than the fifth width W5.

[0101] A second metal layer composed of second interconnects M2 may be provided in the fourth interlayer insulating layer 140. The second interconnects M2 may extend in the first direction D1 and may be parallel to each other. Each second interconnect M2 may be a linear or stripe pattern extending in the first direction D1. The second vias V2 may be respectively interposed between the second interconnects M2 and the first interconnects M1, and may electrically connect the first interconnects M1 and the second interconnects M2 to each other.

[0102] In one embodiment, the first interconnection line M1, the first lower via V1_a and the second lower via V1_b, the second interconnection line M2 and the second via V2 may include the same conductive material or may be formed of the same conductive material. For example, the first interconnection line M1, the first lower via V1_a and the second lower via V1_b, the second interconnection line M2 and the second via V2 may be formed of at least one metallic material selected from aluminum, copper, tungsten, molybdenum and cobalt, or include at least one metallic material selected from aluminum, copper, tungsten, molybdenum and cobalt. Although not shown, a plurality of stacked metal layers may be further disposed on the fourth interlayer insulating layer 140. Each stacked metal layer may include a routing line.

[0103] FIG. 7A to FIG. 7D is a cross-sectional view, which is along Figure 3 The lines A-A', B-B', CC' and D-D' are cut to illustrate a semiconductor device according to an embodiment of the inventive concept. In the following description, the previous reference Figure 3 , Figure 4 , Figure 5 and FIG. 6A to FIG. 6D Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0104] Reference Figure 3 , Figure 4 , Figure 5 and FIG. 7A to FIG. 7D , the first trigger cell FF1 may be provided on a substrate 100. The substrate 100 may include a first active region CAR1 and a second active region CAR2. Each of the first active region CAR1 and the second active region CAR2 may include a PMOSFET region PR and an NMOSFET region NR.

[0105] A device isolation layer ST may be provided on the substrate 100. The device isolation layer ST may define first and second active patterns AP1 and AP2 in an upper portion of the substrate 100. The first and second active patterns AP1 and AP2 may be defined on the PMOSFET region PR and the NMOSFET region NR, respectively.

[0106] The first active pattern AP1 may include vertically stacked first channel patterns CH1. The stacked first channel patterns CH1 may be spaced apart from each other in the third direction D3. When viewed in a plan view, the stacked first channel patterns CH1 may overlap each other. The second active pattern AP2 may include vertically stacked second channel patterns CH2. The stacked second channel patterns CH2 may be spaced apart from each other in the third direction D3. When viewed in a plan view, the stacked second channel patterns CH2 may overlap each other. The first channel pattern CH1 and the second channel pattern CH2 may be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

[0107] The first active pattern AP1 may further include a first source / drain pattern SD1. A stacked first channel pattern CH1 may be interposed between each pair of adjacent first source / drain patterns SD1. The stacked first channel pattern CH1 may connect the pair of adjacent first source / drain patterns SD1 to each other.

[0108] The second active pattern AP2 may further include a second source / drain pattern SD2. A stacked second channel pattern CH2 may be interposed between each pair of adjacent second source / drain patterns SD2. The stacked second channel pattern CH2 may connect the pair of adjacent second source / drain patterns SD2 to each other.

[0109] The gate electrode GE may be provided to cross the first channel pattern CH1 and the second channel pattern CH2 and extend in the first direction D1. When viewed in a plan view, the gate electrode GE may overlap the first channel pattern CH1 and the second channel pattern CH2. A pair of gate spacers GS may be provided on opposite side surfaces of the gate electrode GE. A gate capping pattern GP may be provided on the gate electrode GE.

[0110] The gate electrode GE may surround each of the first channel pattern CH1 and the second channel pattern CH2 (eg, see Fig.7D). The gate electrode GE may be provided on the first top surface TS1 of the first channel pattern CH1, at least one of the first side walls SW1, and the first bottom surface BS1. The gate electrode GE may be provided on the second top surface TS2 of the second channel pattern CH2, at least one of the second side walls SW2, and the second bottom surface BS2. In other words, the gate electrode GE may surround the top surface, the bottom surface, and the opposite side surfaces of each of the first channel pattern CH1 and the second channel pattern CH2. The transistor according to the present embodiment may be a three-dimensional field effect transistor (e.g., a multi-bridge channel field effect transistor (MBCFET)) in which the gate electrode GE is provided to three-dimensionally surround the channel patterns CH1 and CH2.

[0111] The gate dielectric pattern GI may be provided between each of the first and second channel patterns CH1 and CH2 and the gate electrode GE. The gate dielectric pattern GI may surround each of the first and second channel patterns CH1 and CH2.

[0112] On the NMOSFET region NR, the insulating pattern IP may be interposed between the gate dielectric pattern GI and the second source / drain pattern SD2. The gate electrode GE may be spaced apart from the second source / drain pattern SD2 by the gate dielectric pattern GI and the insulating pattern IP. On the contrary, on the PMOSFET region PR, the insulating pattern IP may be omitted.

[0113] First and second interlayer insulating layers 110 and 120 may be provided on the entire top surface of the substrate 100. Active contacts AC may be provided to penetrate the first and second interlayer insulating layers 110 and 120 and to be connected to the first and second source / drain patterns SD1 and SD2, respectively.

[0114] A third interlayer insulating layer 130 may be provided on the second interlayer insulating layer 120. A fourth interlayer insulating layer 140 may be provided on the third interlayer insulating layer 130. A first metal layer may be provided in the third interlayer insulating layer 130. The first metal layer may include a first interconnection line M1, a first lower via V1_a, and a second lower via V1_b. A second metal layer may be provided in the fourth interlayer insulating layer 140. The second metal layer may include a second interconnection line M2 and a second via V2.

[0115] Figure 8 1 is a logic circuit diagram showing a trigger circuit of a semiconductor device according to an embodiment of the inventive concept. Figure 2 Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0116] Reference Figure 8, the first flip-flop unit FF1 may include a scan MUX block SCM, a master latch block MAL, a slave latch block SLL, a clock driver block CLD, and an output block OUT. Figure 8 The slave latch block SLL can be used with Figure 2 The slave latch block SLL differs in that the NOR gate is replaced by an inverter. In addition to this difference, Figure 8 The circuit diagram of the first flip-flop unit FF1 can be Figure 2 The circuit diagram of the first flip-flop unit FF1 is basically the same.

[0117] Fig. 9 is a plan view illustrating a plurality of blocks constituting a flip-flop unit of a semiconductor device according to an embodiment of the inventive concept. Fig.10 It shows the composition Fig. 9 A plan view of multiple blocks of a trigger unit. Specifically, Fig.10 Only briefly shows the composition Fig. 9 In the following description, the previous reference Figures 1 to 5 Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0118] Reference Figures 8 to 10 , the first flip-flop unit FF1 may be provided on the substrate 100. The first flip-flop unit FF1 may include a scan MUX block SCM, a master latch block MAL, a first slave latch block SLL1, a second slave latch block SLL2, a first clock driver block CLD1, a second clock driver block CLD2, and an output block OUT. The first slave latch block SLL1 and the second slave latch block SLL2 may constitute Figure 8 The slave latch block (eg, slave latch circuit) SLL of the first clock driver block CLD1 and the second clock driver block CLD2 may constitute Figure 8 A clock driver block (eg, clock driver circuit) CLD.

[0119] In this embodiment, each of the scan MUX block SCM, the master latch block MAL, the first slave latch block SLL1, the second slave latch block SLL2, the first clock driver block CLD1, the second clock driver block CLD2, and the output block OUT may have a rectangular shape. Figure 1-5 and Figures 6A-6D , these blocks include circuits, so these blocks are also described here as scan MUX circuit SCM, master latch circuit MAL, slave latch circuit SLL, clock driver circuit CLD and output circuit OUT. Each of these circuits can also be described as a sub-circuit, such as a sub-circuit of a trigger unit.

[0120] The scan MUX block SCM may be provided on the first active region CAR1. The master latch block MAL may be provided on the first active region CAR1. The master latch block MAL may not overlap with the second active region CAR2 and may be spaced apart from the second active region CAR2. The master latch block MAL may be adjacent to the scan MUX block SCM in the second direction D2.

[0121] The master latch block MAL may include a portion of the first power line M1_R1 and a portion of the second power line M1_R2. The master latch block MAL may not include the third power line M1_R3. For example, the master latch block MAL may not overlap with the third power line M1_R3 and may be spaced apart from the third power line M1_R3. The master latch block MAL according to the present embodiment may not include the third power line M1_R3 as previously described. Figure 5 The second region RG2 is described.

[0122] The master latch block MAL may have a third boundary BD3 and a fourth boundary BD4. The third boundary BD3 and the fourth boundary BD4 may be opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend in the second direction D2. The third boundary BD3 may be aligned with the first side wall SW3 of the first power line M1_R1, and the fourth boundary BD4 may be aligned with the second side wall SW4 of the second power line M1_R2. The master latch block MAL may not have the previously referenced Figure 5 A fifth boundary BD5 is described.

[0123] The first clock driver block CLD1 may be provided on the second active area CAR2. The master latch block MAL may be adjacent to the first clock driver block CLD1 in the first direction D1. The first clock driver block CLD1 may have a fourteenth boundary BD14 and a fifteenth boundary BD15. The fourteenth boundary BD14 and the fifteenth boundary BD15 may extend in the second direction D2. The fourteenth boundary BD14 may be aligned with the first side wall SW3 of the second power line M1_R2, and the fifteenth boundary BD15 may be aligned with the second side wall SW4 of the third power line M1_R3.

[0124] The first slave latch block SLL1 may be provided on the second active region CAR2. The master latch block MAL may be adjacent to the first slave latch block SLL1 in the first direction D1.

[0125] In the second overlapping region OR2, the master latch block MAL overlaps the first clock driver block CLD1 and the first slave latch block SLL1. The second overlapping region OR2 may extend in the second direction D2. The second overlapping region OR2 may substantially overlap the second power line M1_R2. The second overlapping region OR2 may have a second width W2 in the first direction D1. The master latch block MAL, together with the first clock driver block CLD1 and the first slave latch block SLL1, may share the second power line M1_R2 through the second overlapping region OR2.

[0126] The second clock driver block CLD2 is provided on the second active region CAR2. The scan MUX block SCM is adjacent to the second clock driver block CLD2 in the first direction D1. The first slave latch block SLL1 is adjacent to the second clock driver block CLD2 in the second direction D2.

[0127] The second slave latch block SLL2 is provided on the second active region CAR2. The second clock driver block CLD2 is adjacent to the second slave latch block SLL2 in the second direction D2. The second clock driver block CLD2 is interposed between the first slave latch block SLL1 and the second slave latch block SLL2.

[0128] The output block OUT is provided on the second active region CAR2. According to this embodiment, the Figure 5 A third overlapping region OR3 in which the output block OUT and the second slave latch block SLL2 overlap each other.

[0129] In the first overlapping region OR1, the scan MUX block SCM overlaps with the second clock driver block CLD2, the second slave latch block SLL2, and the output block OUT. The first overlapping region OR1 extends in the second direction D2. The first overlapping region OR1 may extend from the output block OUT to the second clock driver block CLD2 in the second direction D2. The first overlapping region OR1 may substantially overlap with the second power line M1_R2. The first overlapping region OR1 may have a first width W1 in the first direction D1. The first width W1 may be substantially equal to the second width W2.

[0130] Fig.11 is a cross-sectional view along Figure 3 , is taken along line AA′ to illustrate a semiconductor device according to an embodiment of the inventive concept. Fig. 12A and Fig. 12B is a cross-sectional view along Figure 3 AA′ and BB′ are taken to illustrate a semiconductor device according to another embodiment of the inventive concept. Fig.13A and Fig. 13B is a cross-sectional view along Figure 3The lines AA' and BB' are taken to illustrate a semiconductor device according to another embodiment of the inventive concept. In the following description, the previous reference Figure 3 , Figure 4 , Figure 5 and FIG. 6A to FIG. 6D The described elements may be identified by the same reference numerals without repeating their repeated descriptions. Fig.11 , 12A , 12B, 13A do not show the active contact AC, and in Fig. 13B Only part of the active contacts AC are shown.

[0131] Reference Fig.11 The gate contact GC may be provided to penetrate the second interlayer insulating layer 120 and the gate capping pattern GP and may be electrically connected to the gate electrode GE, respectively. The gate contact GC may have a top surface coplanar with a top surface of the second interlayer insulating layer 120. For example, the top surface of the gate contact GC may be coplanar with the top surface of the second interlayer insulating layer 120. Figure 6B The top surfaces of the active contacts AC are coplanar.

[0132] The gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. The conductive pattern FM and the barrier pattern BM of the gate contact GC may be configured to have substantially the same features as those of the active contact AC described above.

[0133] The second lower via V1_b may be provided on the gate contact GC. The gate electrode GE and the first interconnection line M1 may be electrically connected to each other through the gate contact GC and the second lower via V1_b.

[0134] Reference Fig. 12A and Fig. 12B , a fifth interlayer insulating layer 150 may be additionally interposed between the second interlayer insulating layer 120 and the third interlayer insulating layer 130. Intermediate contacts IMC may be provided in the fifth interlayer insulating layer 150. At least one of the intermediate contacts IMC may be interposed between the active contact AC and the first lower via V1_a. At least one of the intermediate contacts IMC may be interposed between the gate contact GC and the second lower via V1_b.

[0135] Reference Fig.13A and 13B , the first lower via V1_a and the second lower via V1_b may be omitted. The top surface of the active contact AC may contact the bottom surface of the first interconnect line M1. The top surface of the gate contact GC may contact the bottom surface of the first interconnect line M1. As used herein, items described as being in contact with each other or in contact with each other are directly connected (e.g., touching).

[0136] FIG. 14A to FIG. 14Care enlarged plan views, each of which shows a portion of a semiconductor device according to an embodiment of the inventive concept (eg Figure 3 In the following description, the previous reference Figure 3 , Figure 4 , Figure 5 and FIG. 6A to FIG. 6D Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0137] Reference Fig.14A The gate separation pattern GDP may be interposed between the gate electrodes GE adjacent to each other in the first direction D1. The gate separation pattern GDP may have an elliptical shape.

[0138] In detail, the gate separation pattern GDP may have an end GDPd facing the gate electrode GE. The gate electrode GE may have an end GEd facing the gate separation pattern GDP. The end GDPd of the gate separation pattern GDP may protrude convexly toward the gate electrode GE. The end GEd of the gate electrode GE may be concavely recessed to fitly engage with the end GDPd of the gate separation pattern GDP. Fig.14A As shown, the gate separation pattern GDP may be adjacent to the first gate electrode (eg Fig.14A The position of the upper gate electrode in the first direction D1 protrudes toward the first gate electrode and can be adjacent to the second gate electrode (for example Fig.14A The position of the lower gate electrode in the first direction D1 protrudes convexly toward the second gate electrode in the direction opposite to the first direction D1.

[0139] Reference Fig. 14B The gate separation pattern GDP may be interposed between the gate electrodes GE adjacent to each other in the first direction D1. The gate separation pattern GDP may have a rectangular shape. In detail, an end GDPd of the gate separation pattern GDP may be parallel to the second direction D2. An end GEd of the gate electrode GE may be parallel to the second direction D2.

[0140] Reference Fig. 14C The gate separation pattern GDP may be interposed between the gate electrodes GE adjacent to each other in the first direction D1. Specifically, the end GEd of the gate electrode GE may protrude convexly toward the gate separation pattern GDP. The end GDPd of the gate separation pattern GDP may be concavely recessed to cooperatively engage with the end Ged of the gate electrode GE.

[0141] Fig.15 , Fig.16 and Fig.17 are plan views, each of which shows a plurality of blocks constituting a trigger unit according to an embodiment of the inventive concept. Figures 1 to 5Described elements may be identified by the same reference numerals without repeating their repeated descriptions.

[0142] Reference Fig.15 , the first flip-flop unit FF1 includes a scan MUX block SCM, a master latch block MAL, a slave latch block SLL, a clock driver block CLD, and an output block OUT. In the present embodiment, each of the scan MUX block SCM, the master latch block MAL, the slave latch block SLL, the clock driver block CLD, and the output block OUT has a rectangular shape.

[0143] The scan MUX block SCM and the master latch block MAL are provided on the first active region CAR1. The master latch block MAL is adjacent to the scan MUX block SCM in the second direction D2.

[0144] In the third overlap region OR3, the scan MUX block SCM and the master latch block MAL overlap each other. The third overlap region OR3 extends in the first direction D1. The scan MUX block SCM and the master latch block MAL share the first active region CAR1 through the third overlap region OR3. The first active region CAR1 shared by the scan MUX block SCM and the master latch block MAL is an area to which the first power line M1_R1 and the second power line M1_R2 are electrically connected.

[0145] The slave latch block SLL, the clock driver block CLD, and the output block OUT are provided on the second active region CAR2. The output block OUT, the clock driver block CLD, and the slave latch block SLL are sequentially arranged in the second direction D2.

[0146] In the fourth overlapping region OR4, the clock driver block CLD and the slave latch block SLL overlap each other. The fourth overlapping region OR4 extends in the first direction D1. The clock driver block CLD and the slave latch block SLL share the second active region CAR2 through the fourth overlapping region OR4. The second active region CAR2 shared by the clock driver block CLD and the slave latch block SLL is a region to which the second power line M1_R2 and the third power line M1_R3 are electrically connected.

[0147] In the first overlapping region OR1, the scan MUX block SCM overlaps with the clock driver block CLD and the output block OUT. In the second overlapping region OR2, the master latch block MAL and the slave latch block SLL overlap each other. Each of the first overlapping region OR1 and the second overlapping region OR2 may extend in the second direction D2. The first overlapping region OR1 and the second overlapping region OR2 may substantially overlap with the second power line M1_R2.

[0148] Reference Fig.16, the first flip-flop unit FF1 may include a scan MUX block SCM, a first master latch block MAL1, a second master latch block MAL2, a slave latch block SLL, a first clock driver block CLD1, a second clock driver block CLD2, and an output block OUT. In the present embodiment, each of the scan MUX block SCM, the first master latch block MAL1, the second master latch block MAL2, the slave latch block SLL, the first clock driver block CLD1, the second clock driver block CLD2, and the output block OUT has a rectangular shape.

[0149] The scan MUX block SCM, the first master latch block MAL1, and the first clock driver block CLD1 are provided on the first active region CAR1. The scan MUX block SCM, the first master latch block MAL1, and the first clock driver block CLD1 are sequentially arranged in the second direction D2.

[0150] In the fourth overlap region OR4, the scan MUX block SCM and the first master latch block MAL1 overlap each other. In the fifth overlap region OR5, the first master latch block MAL1 and the first clock driver block CLD1 overlap each other. Each of the fourth overlap region OR4 and the fifth overlap region OR5 extends in the first direction D1.

[0151] The second master latch block MAL2, the slave latch block SLL, the second clock driver block CLD2 and the output block OUT are provided on the second active region CAR2. The output block OUT, the second clock driver block CLD2, the slave latch block SLL and the second master latch block MAL2 are sequentially arranged in the second direction D2.

[0152] In the sixth overlap region OR6, the slave latch block SLL and the second master latch block MAL2 overlap each other. The sixth overlap region OR6 extends in the first direction D1.

[0153] In the first overlapping region OR1, the scan MUX block SCM overlaps with the slave latch block SLL, the second clock driver block CLD2, and the output block OUT. In the second overlapping region OR2, the first master latch block MAL1 and the slave latch block SLL overlap each other. In the third overlapping region OR3, the first clock driver block CLD1 and the second master latch block MAL2 overlap each other. Each of the first to third overlapping regions OR1, OR2, and OR3 extends in the second direction D2. The first to third overlapping regions OR1, OR2, and OR3 may substantially overlap with the second power line M1_R2.

[0154] Reference Fig.17, the first flip-flop unit FF1 may include a scan MUX block SCM, a first master latch block MAL1, a second master latch block MAL2, a first slave latch block SLL1, a second slave latch block SLL2, a first clock driver block CLD1, a second clock driver block CLD2, and an output block OUT. In the present embodiment, each of the scan MUX block SCM, the first master latch block MAL1, the second master latch block MAL2, the first slave latch block SLL1, the second slave latch block SLL2, the first clock driver block CLD1, the second clock driver block CLD2, and the output block OUT has a rectangular shape.

[0155] The second master latch block MAL2, the first slave latch block SLL1, the second slave latch block SLL2, the second clock driver block CLD2, and the output block OUT are provided on the second active area CAR2. The output block OUT, the second slave latch block SLL2, the second clock driver block CLD2, the first slave latch block SLL1, and the second master latch block MAL2 are sequentially arranged in the second direction D2.

[0156] In the sixth overlap region OR6, the first slave latch block SLL1 and the second master latch block MAL2 overlap each other. In the seventh overlap region OR7, the second clock driver block CLD2 and the first slave latch block SLL1 overlap each other. Each of the sixth overlap region OR6 and the seventh overlap region OR7 extends in the first direction D1.

[0157] In the first overlapping region OR1, the scan MUX block SCM overlaps with the second slave latch block SLL2, the second clock driver block CLD2, and the output block OUT. In the second overlapping region OR2, the first master latch block MAL1 and the first slave latch block SLL1 overlap each other. In the third overlapping region OR3, the first clock driver block CLD1 and the second master latch block MAL2 overlap each other. Each of the first to third overlapping regions OR1, OR2, and OR3 extends in the second direction D2. The first to third overlapping regions OR1, OR2, and OR3 may substantially overlap with the second power line M1_R2.

[0158] According to an embodiment of the inventive concept, a semiconductor device may include functional blocks constituting a flip-flop cell and efficiently disposed on the cell, and thus, performance of the flip-flop circuit may be improved.

[0159] Although example embodiments of the inventive concept have been specifically shown and described, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. Ordinals such as "first", "second", "third", etc. may be simply used as marks for certain elements, steps, etc. to distinguish such elements, steps, etc. from each other. Terms that are not described using "first", "second", etc. in the specification may still be referred to as "first" or "second" in the claims. In addition, terms referenced by a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere using a different ordinal number (e.g., "second" in the specification or another claim).

[0160] This application claims the priority of Korean Patent Application No. 10-2019-0110556 filed on September 6, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising a trigger unit, wherein the trigger unit is formed on a semiconductor substrate and comprises a trigger circuit, wherein the trigger unit comprises: a scan multiplexer circuit formed in a first continuous boundary region of the flip-flop unit when viewed in plan view; a master latch circuit, which is formed in a second continuous boundary region of the flip-flop unit when viewed from a plan view, the master latch circuit being formed adjacent to the scan multiplexer circuit in a planar length direction; a clock driver circuit, when viewed from a plan view, the clock driver circuit being formed in a third continuous boundary region of the flip-flop unit, the third continuous boundary region partially overlapping with the first continuous boundary region in a first overlapping region, so that a first portion of the scanning multiplexer circuit in the first overlapping region overlaps with a first portion of the clock driver circuit in the first overlapping region, and a second portion of the scanning multiplexer circuit is adjacent to the second portion of the clock driver circuit across the first overlapping region in a plane height direction; an output circuit formed in a fourth continuous boundary region of the flip-flop unit when viewed in plan view; as well as From the latch circuit, wherein each of the scan multiplexer circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit: including a plurality of active devices that together output a resultant signal of the circuit based on the input, and It is a sub-circuit of the trigger circuit.

2. The semiconductor device according to claim 1, wherein: The first portion of the scan multiplexer circuit and the first portion of the clock driver circuit share a power supply line disposed in the first overlapping region.

3. The semiconductor device according to claim 1, wherein: In a second overlapping region, a portion of the fourth continuous boundary region overlaps a portion of a fifth continuous boundary region including at least a portion of the slave latch circuit; as well as The output circuit and the slave latch circuit share a source / drain region in the second overlapping region.

4. The semiconductor device according to claim 3, wherein: The fifth continuous boundary region includes only a portion of the slave latch circuit, and the remaining portion of the slave latch circuit is formed in a sixth continuous boundary region spaced apart from the fifth continuous boundary region along the plane length direction.

5. A semiconductor device comprising a trigger unit, the trigger unit being formed on a semiconductor substrate and comprising a trigger circuit, the trigger unit comprising: Scanning multiplexer circuit; master latch circuit; Slave latch circuit; Clock driver circuit; as well as Output circuit, wherein each of the scan multiplexer circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit: including a plurality of active devices which together output a resultant signal of the circuit based on the input, is a sub-circuit of the flip-flop circuit, and When viewed in plan view, occupying a continuous boundary area of ​​the flip-flop circuit, wherein the scanning multiplexer circuit, the master latch circuit, the slave latch circuit, the clock driver circuit and the output circuit are arranged in a rectangular area when viewed from a plan view, wherein the output circuit and the slave latch circuit are arranged at the same plane height as each other below the plane height of the scanning multiplexer circuit when viewed from a plan view, and the scanning multiplexer circuit is adjacent to the output circuit in a plane height direction, and Wherein when viewed from a plan view, at least a first subcircuit and a second subcircuit of the subcircuits overlap in a first overlapping region, the first overlapping region comprising a portion of a first continuous boundary region for the first subcircuit and a portion of a second continuous boundary region for the second subcircuit.

6. The semiconductor device according to claim 5, further comprising: A first active device, which is part of the first sub-circuit and is part of the second sub-circuit, is located in the first overlapping region.

7. The semiconductor device according to claim 6, wherein: The first active device is a transistor including a source / drain region shared by the first sub-circuit and the second sub-circuit.

8. The semiconductor device according to claim 6, wherein: The first sub-circuit is the output circuit, and the second sub-circuit is the slave latch circuit.

9. The semiconductor device according to claim 5, wherein: The second subcircuit includes a third continuous boundary region, a first group of the plurality of active devices that together output a result signal of the second sub-circuit is located in the second continuous boundary region, The remaining portion of the plurality of active devices that together output the result signal of the second sub-circuit is located in the third continuous boundary region, and At least a portion of the third sub-circuit of the flip-flop circuit is located in a fourth continuous boundary region between the second continuous boundary region and the third continuous boundary region.

10. The semiconductor device according to claim 9, wherein: The second sub-circuit is the slave latch circuit; and The third sub-circuit is the clock driver circuit.

11. The semiconductor device according to claim 10, wherein: The first sub-circuit is the scan multiplexer circuit.

12. The semiconductor device according to claim 9, wherein: The second sub-circuit is the clock driver circuit; and The third sub-circuit is the slave latch circuit.

13. The semiconductor device according to claim 5, wherein: The scan multiplexer circuit and the master latch circuit are arranged at the same plane height as each other and are arranged adjacent to each other in a plane length direction; as well as The slave latch circuit and the output circuit are arranged adjacent to each other along the planar length direction.

14. The semiconductor device according to claim 13, wherein: The first subcircuit is the scan multiplexer circuit, and The second sub-circuit is one of the output circuit, the slave latch circuit, and the clock driver circuit.

15. The semiconductor device according to claim 13, wherein: The first sub-circuit is the master latch circuit, and The second sub-circuit is one of the slave latch circuit and the clock driver circuit.

16. The semiconductor device according to claim 5, further comprising: A first power supply line is connected to the first sub-circuit and the second sub-circuit and is located in the first overlapping region.

17. The semiconductor device according to claim 16, further comprising: a common conductive path, which contacts and is electrically connected to the first power line, and is disposed below the first power line; a first active contact connected to the common conductive path and a source / drain pattern of the first sub-circuit; as well as a second active contact connected to the common conductive path and the source / drain pattern of the second sub-circuit, The first overlapping region is horizontally between the source / drain pattern of the first sub-circuit and the source / drain pattern of the second sub-circuit.

18. The semiconductor device according to claim 16, further comprising: a common conductive path, which contacts and is electrically connected to the first power line, and is disposed below the first power line; a first active contact connected to the common conductive path and a source / drain pattern of the first sub-circuit; as well as a second active contact connected to the common conductive path and the source / drain pattern of the second sub-circuit, wherein the source / drain pattern of the first sub-circuit is in the continuous boundary region for the first sub-circuit and outside the first overlap region, wherein the source / drain pattern of the second sub-circuit is in the continuous boundary region for the second sub-circuit and outside the first overlapping region, and Wherein the first active contact is horizontally spaced apart from the second active contact.

19. The semiconductor device according to claim 5, further comprising: a plurality of active regions arranged on the semiconductor substrate in a first direction; and a plurality of active contacts, which are respectively formed on the plurality of active regions and electrically connected to the plurality of active regions, wherein adjacent active contacts are separated by a separation distance in the first direction, The separation distance between adjacent active contacts in the first overlapping region is smaller than the separation distance between adjacent active contacts outside the first overlapping region.

20. The semiconductor device according to claim 5, further comprising: a plurality of active regions arranged on the semiconductor substrate in a first direction; a plurality of active contacts, which are respectively formed on the plurality of active regions and electrically connected to the plurality of active regions, wherein adjacent active contacts are separated by a separation distance in the first direction; as well as A first gate electrode crosses two active regions of the first overlapping region and the active region that are separated by the first overlapping region.

21. The semiconductor device according to claim 20, further comprising: a second gate electrode adjacent to the first gate electrode in the first direction; as well as A gate separation pattern is between the first gate electrode and the second gate electrode, wherein the gate separation pattern protrudes toward the first gate electrode in the first direction at a position where the gate separation pattern is adjacent to the first gate electrode, and protrudes toward the second gate electrode in a direction opposite to the first direction at a position where the gate separation pattern is adjacent to the second gate electrode.

22. The semiconductor device according to claim 20, wherein: The plurality of active regions are fin-type active regions.

23. The semiconductor device according to claim 20, wherein: The plurality of active regions are gate-all-around active regions.

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