Integrated circuit comprising integrated standard cell structures

Abstract

An integrated circuit includes a first active region and a second active region, a first standard cell and a second standard cell on the first active region and the second active region, and a filler cell between the first standard cell and the second standard cell and including a first insulative spacer and a second insulative spacer. The filler cell has a pitch dimension. The first insulative spacer and the second insulative spacer are spaced apart from each other by the pitch dimension. The first insulative spacer of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulative spacer of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first insulative spacer and the second insulative spacer separate at least a portion of the first active region and separate at least a portion of the second active region.

Description

TECHNICAL FIELD

[0001] The present inventive concept relates to an integrated circuit including integrated standard cell structures. BACKGROUND

[0002] An integrated circuit can be designed using standard cells. Specifically, a layout of an integrated circuit can be generated by arranging standard cells according to data defining the integrated circuit and by wiring the arranged standard cells. Such standard cells are pre-designed and stored in a cell library.

[0003] As a semiconductor manufacturing process is miniaturized, a size of a pattern in a standard cell can be reduced, and a size of the standard cell can also be reduced. SUMMARY

[0004] Embodiments of the present inventive concept provide an integrated circuit that can use a fill cell to increase integration of a layout and improve performance and reliability of a designed semiconductor device.

[0005] However, embodiments of the present inventive concept are not limited to the embodiments set forth herein. The above and other embodiments of the present inventive concept will become more fully understood from the detailed description given herein below, taken in conjunction with the accompanying drawings.

[0006] According to an exemplary embodiment of the present inventive concept, an integrated circuit includes a first active region extending in a first direction, a second active region extending in the first direction and spaced apart from the first active region in a second direction different from the first direction, a first standard cell disposed on the first active region and the second active region, the first standard cell including a first p-type transistor on the first active region and a first n-type transistor on the second active region, a second standard cell disposed on the first active region and the second active region, the second standard cell including a second p-type transistor on the first active region and a second n-type transistor on the second active region, and a fill cell disposed between the first standard cell and the second standard cell and including a first insulating spacer and a second insulating spacer, each of the first insulating spacer and the second insulating spacer extending in the second direction. The fill cell has a pitch size. The first insulating spacer and the second insulating spacer are spaced apart from each other by the pitch size in the first direction. The first insulating spacer of the fill cell is disposed at a first boundary between the first standard cell and the fill cell. The second insulating spacer of the fill cell is disposed at a second boundary between the second standard cell and the fill cell. The first insulating spacer and the second insulating spacer separate at least a portion of the first active region and at least a portion of the second active region.

[0007] According to an exemplary embodiment of the present invention, an integrated circuit includes a first standard cell including a first p-type transistor and a first n-type transistor, a second standard cell including a second p-type transistor and a second n-type transistor and spaced apart from the first standard cell in a first direction, a fill cell disposed between the first standard cell and the second standard cell and including a first insulating spacer and a second insulating spacer, and a third standard cell spaced apart from the first standard cell and the fill cell in a second direction different from the first direction and including a third p-type transistor and a third n-type transistor. The fill cell has a pitch size. The first insulating spacer and the second insulating spacer are spaced apart from each other by the pitch size in the first direction. The first insulating spacer of the fill cell is disposed at a boundary between the first standard cell and the fill cell. The second insulating spacer of the fill cell is disposed at a boundary between the second standard cell and the fill cell. The first p-type transistor and the second p-type transistor are formed on a first active region. The first n-type transistor and the second n-type transistor are formed on a second active region. The third standard cell includes a third insulating spacer disposed at a first boundary of the third standard cell. The first insulating spacer and the second insulating spacer separate at least a portion of the first active region. The first insulating spacer and the second insulating spacer separate at least a portion of the second active region. The third insulating spacer is aligned with the second insulating spacer in the second direction.

[0008] According to an exemplary embodiment of the present invention, an integrated circuit includes a first standard cell including a first p-type transistor and a first n-type transistor, a second standard cell including a second p-type transistor and a second n-type transistor and spaced apart from the first standard cell in a first direction, a fill cell disposed between the first standard cell and the second standard cell and including a first insulating spacer and a second insulating spacer, and a third standard cell spaced apart from the first standard cell and the fill cell in a second direction different from the first direction and including a third p-type transistor and a third n-type transistor. The fill cell has a pitch size. The first insulating spacer and the second insulating spacer are spaced apart from each other by the pitch size in the first direction. The first insulating spacer of the fill cell is disposed at a boundary between the first standard cell and the fill cell. The second insulating spacer of the fill cell is disposed at a boundary between the second standard cell and the fill cell. The third standard cell includes a first gate stack and a second gate stack spaced apart from each other by the pitch size. The first gate stack is aligned with the first insulating gate of the fill cell in the second direction. The second gate stack is aligned with the second insulating gate of the fill cell in the second direction.

[0009] According to an exemplary embodiment of the present invention, an integrated circuit includes a first standard cell including a first p-type transistor and a first n-type transistor, a second standard cell including a second p-type transistor and a second n-type transistor and spaced apart from the first standard cell in a first direction, a fill cell including a first dummy gate stack and a second dummy gate stack, the fill cell disposed between the first standard cell and the second standard cell, wherein each of the first dummy gate stack and the second dummy gate stack extends in a second direction different from the first direction, a power rail extending in the first direction and connected to the first dummy gate stack and the second dummy gate stack, and a cell separation film extending in the first direction along a boundary of the first standard cell, a boundary of the fill cell, and a boundary of the second standard cell and overlapping the power rail. The fill cell has a pitch size. The first dummy gate stack and the second dummy gate stack are spaced apart from each other in the first direction by the pitch size. The first dummy gate stack of the fill cell is disposed at a boundary between the first standard cell and the fill cell. The second dummy gate stack of the fill cell is disposed at a boundary between the second standard cell and the fill cell. The fill cell includes a first fill contact connected to the first dummy gate stack and a second fill contact connected to the second dummy gate stack. The first fill contact and the second fill contact overlap the separation film.

[0010] According to an exemplary embodiment of the present invention, an integrated circuit includes a first standard cell including a first p-type transistor and a first n-type transistor, a second standard cell including a second p-type transistor and a second n-type transistor and disposed adjacent to each other in a first direction, a fill cell including a first dummy gate stack and a second dummy gate stack disposed between the first standard cell and the second standard cell, the first dummy gate stack and the second dummy gate stack extending in a second direction different from the first direction, and a power rail extending in the first direction and connected to the first dummy gate stack and the second dummy gate stack. The fill cell has a pitch size. The first dummy gate stack and the second dummy gate stack are spaced apart from each other in the first direction by the pitch size. The first dummy gate stack of the fill cell is disposed at a boundary between the first standard cell and the fill cell. The second dummy gate stack of the fill cell is disposed at a boundary between the second standard cell and the fill cell. The first standard cell includes a first gate stack extending in the second direction. The second standard cell includes a second gate stack extending in the second direction. A length of each of the first dummy gate stack and the second dummy gate stack is greater than a length of each of the first gate stack and the second gate stack.

[0011] According to an exemplary embodiment of the present application, an integrated circuit includes a first standard cell including a first p-type transistor and a first n-type transistor, a second standard cell including a second p-type transistor and a second n-type transistor and spaced apart from the first standard cell in a first direction, a fill cell including a first dummy gate stack and a second dummy gate stack disposed between the first standard cell and the second standard cell, a first fill contact connected to the first dummy gate stack, and a second fill contact connected to the second dummy gate stack, the first dummy gate stack and the second dummy gate stack extending in a second direction different from the first direction, and a power rail extending in the first direction and connected to the first dummy gate stack via the first fill contact and to the second dummy gate stack via the second fill contact. The fill cell has a pitch size. The first dummy gate stack and the second dummy gate stack are spaced apart from each other by the pitch size in the first direction. The first dummy gate stack of the fill cell is disposed at a boundary between the first standard cell and the fill cell. The second dummy gate stack of the fill cell is disposed at a boundary between the second standard cell and the fill cell. The first p-type transistor and the second p-type transistor are formed on a first active region. The first n-type transistor and the second n-type transistor are formed on a second active region. The fill cell further includes a dummy gate cut pattern on an active region separation film, the active region separation film extending in the first direction and interposed between the first active region and the second active region. The first dummy gate stack includes a first portion and a second portion separated by the dummy gate cut pattern. The second dummy gate stack includes a first portion and a second portion separated by the dummy gate cut pattern. The first fill contact includes a first upper fill contact connected to the first portion of the first dummy gate stack and a first lower fill contact connected to the second portion of the first dummy gate stack. The second fill contact includes a second upper fill contact connected to the first portion of the second dummy gate stack and a second lower fill contact connected to the second portion of the second dummy gate stack. The first upper fill contact, the first lower fill contact, the second upper fill contact, and the second lower fill contact overlap a cell separation film extending in the first direction along a boundary of the first standard cell, a boundary of the fill cell, and a boundary of the second standard cell.

[0012] Other features and embodiments can become apparent from the following detailed description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0013] The above and other aspects and features of the present inventive concept will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, which illustrate several embodiments of the inventive concept by way of example.

[0014] Figures 1-3 , Figure 4A and Figure 4B , Figure 5A and Figure 5B ,Figures 6A-6C , Figure 7A and Figure 7B , Figure 8 , Figure 9 as well as Figure 10A and Figure 10B It is a diagram used to illustrate an integrated circuit according to some embodiments;

[0015] Figure 11 This is a top view used to illustrate an integrated circuit according to some embodiments;

[0016] Figure 12 This is a top view used to illustrate an integrated circuit according to some embodiments;

[0017] Figure 13 This is a top view used to illustrate an integrated circuit according to some embodiments;

[0018] Figure 14 This is a top view used to illustrate an integrated circuit according to some embodiments;

[0019] Figures 15-18 as well as Figure 19A and Figure 19B It is a diagram used to illustrate an integrated circuit according to some embodiments;

[0020] Figures 20-24 These are diagrams illustrating integrated circuits according to some implementation methods;

[0021] Figure 25 and Figure 26 These are top views illustrating an integrated circuit according to some embodiments;

[0022] Figure 27 and Figure 28 These are, respectively, top views illustrating an integrated circuit according to some embodiments; and

[0023] Figure 29 and Figure 30 It is a diagram related to a method for designing the layout of an integrated circuit according to some implementations. Detailed Implementation

[0024] In the following description, a substrate ( Figure 2 Integrated circuits in various embodiments on a semiconductor substrate (e.g., a semiconductor substrate). The integrated circuit has a layout including various standard cells. Standard cells are integrated circuit structures pre-designed for repeated use in the design of various integrated circuits. An efficient integrated circuit design layout includes predetermined rules relating to the arrangement of standard cells to enhance the performance of the pre-designed various standard cells and circuits and reduce circuit area.

[0025] An integrated circuit according to some embodiments includes one or more standard cells that are placed in an integrated circuit layout by predetermined rules. Such standard cells are repeatedly used in integrated circuit designs. Therefore, the standard cells are pre-designed according to manufacturing technology and stored in a standard cell library. An integrated circuit designer can search for such standard cells and cause them to be included in an integrated circuit design, and can place them in an integrated circuit layout according to predetermined placement rules.

[0026] The standard cells can include various basic circuit devices such as inverters, AND, NAND, OR, XOR, and NOR, which are frequently used in digital circuit designs for electronic devices such as central processing units (CPUs), graphics processing units (GPUs), and system on chips (SOCs). The standard cells can include other cells that are frequently used in circuit blocks such as flip-flops and latches.

[0027] The fill cells can be design blocks of the integrated circuit that are inserted between two adjacent standard cells to comply with integrated circuit design and integrated circuit manufacturing rules. Proper design and placement of the standard cells and the fill cells can improve packing density and circuit performance.

[0028] Figures 1-10B FIG. 1 is a diagram for explaining an integrated circuit according to some embodiments.

[0029] Figure 1 FIG. 2 is a top view of an FEOL (Front-End-of-Line) of an integrated circuit according to some embodiments. Figure 2 FIG. 3 is a cross-sectional view taken along line A-A of FIG. 2. Figure 1 FIG. 4 is a cross-sectional view taken along line B-B of FIG. 2. Figure 3 FIG. 5 is a cross-sectional view taken along line C-C of FIG. 2. Figure 1 FIG. 6 is a cross-sectional view taken along line D1-D1 of FIG. 2. Figure 4A FIG. 7 is a cross-sectional view taken along line D2-D2 of FIG. 2. Figure 4B FIG. 8 is a cross-sectional view taken along line E-E of FIG. 2. Figure 1 FIG. 9 is a top view of an integrated circuit according to some embodiments, showing up to a MOL (Middle-of-Line). Figure 5A FIG. 10 is a top view of an integrated circuit according to some embodiments, showing up to a BEOL (Back-End-of-Line). Figure 5B FIG. 11 is a cross-sectional view taken along line F1-F1 of FIG. 9. Figure 6A FIG. 12 is a cross-sectional view taken along line F2-F2 of FIG. 9. Figure 6B FIG. 13 is a cross-sectional view taken along line G-G of FIG. 9. Figure 5A FIG. 14 is a cross-sectional view taken along line H-H of FIG. 9. Figure 6C FIG. 15 is a cross-sectional view taken along line I-I of FIG. 9. Figure 5B FIG. 16 is a cross-sectional view taken along line J-J of FIG. 9. Figure 7A FIG. 17 is a cross-sectional view taken along line K-K of FIG. 9. Figure 7B FIG. 18 is a cross-sectional view taken along line L-L of FIG. 9. Figure 5A FIG. 19 is a cross-sectional view taken along line M-M of FIG. 9. Figure 5B FIG. 20 is a cross-sectional view taken along line N-N of FIG. 9. Figure 8 FIG. 21 is a top view of an integrated circuit according to some embodiments, showing up to a BEOL (Back-End-of-Line).Figure 9 is a cross-sectional view taken along lines E-E and F-F of Figure 8 Figure 10A and Figure 10B is another exemplary cross-sectional view taken along lines E-E and F-F of Figure 8

[0030] For reference, in Figure 4A and Figure 4B , X-X and Y-Y indicate a cutting direction. Figure 8 may be a view in which a wiring layer is formed on the top view shown in Figure 5A . Further, Figure 8 only a via connected to a gate contact and a source / drain contact and an M1 metal layer on the via are shown.

[0031] Referring to Figures 1-10B , an integrated circuit according to some embodiments includes a first standard cell 20, a second standard cell 22, and a first insulating fill cell 10 and a cell gate cut pattern 160.

[0032] In Figure 1 to FIG. 4, the first standard cell 20, the second standard cell 22, and the first insulating fill cell 10 can be formed on a substrate 100.

[0033] The substrate 100 can be a silicon substrate or an SOI (Silicon On Insulator). Alternatively, the substrate 100 can include, but is not limited to, silicon germanium, SGOI (Silicon Germanium On Insulator), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0034] The first active region 112 can be defined in a first direction X. The first active region 112 can be defined by a deep trench DT. The first active region 112 can be a region in which a p-type transistor (e.g., a pFET) is formed. The first active region 112 can include, for example, a well region doped with an n-type impurity.

[0035] The first active region 112 can include a first lower active region 112B, a first upper active region 112U, and a first nanosheet 112NS. The first lower active region 112B can have a sidewall defined by the deep trench DT. The first upper active region 112U can have a fin shape protruding from the first lower active region 112B. The first upper active region 112U can have a sidewall defined by a trench shallower than the deep trench DT. The first nanosheet 112NS can be disposed to be spaced apart from the first upper active region 112U. Although two first nanosheets 112NS are shown, this is only for the convenience of illustration, and the number thereof is not limited thereto.

[0036] ​​The second active region 114 can be defined in the first direction X. The second active region 114 can be defined as being spaced apart from the first active region 112 in the second direction Y. The first active region 112 and the second active region 114 can be separated by the deep trench DT. The second active region 114 can be a region in which an n-type transistor (e.g., nFET) is formed. The second active region 114 can include, for example, a well region doped with a p-type impurity.

[0037] In Figure 1 and Figure 8 , the second active region 114 can include a second lower active region 114B, a second upper active region 114U, and a second nanosheet 114NS. The second lower active region 114B can have a sidewall defined by the deep trench DT. The second upper active region 114U can have a fin shape protruding from the second lower active region 114B. The second upper active region 114U can have a sidewall defined by a trench shallower than the deep trench DT. The trench can be connected to the deep trench DT. The second nanosheet 114NS can be disposed to be spaced apart from the second upper active region 114U. Although two second nanosheets 114NS are shown, the number thereof is not limited thereto for the sake of convenience of illustration.

[0038] Each of the first standard cell 20, the second standard cell 22, and the first insulating fill cell 10 can include the first active region 112 and the second active region 114.

[0039] The active region separation film 105 can be formed on the substrate 100. The active region separation film 105 can be interposed between the first active region 112 and the second active region 114. The active region separation film 105 can extend in the first direction X between the first active region 112 and the second active region 114. The active region separation film 105 can fill the deep trench DT separating the first active region 112 and the second active region 114.

[0040] The cell separation film 106 can be formed on the substrate 100. The cell separation film 106 can fill the deep trench DT separating the first active region 112 and the second active region 114. The cell separation film 106 can extend in the first direction X along the boundary of the first standard cell 20, the boundary of the second standard cell 22, and the boundary of the first insulating fill cell 10. Each of the active region separation film 105 and the cell separation film 106 can include an insulating material.

[0041] The active region separation film 105 and the cell separation film 106 can include an insulating material that fills the deep trench DT defining the first active region 112 and the second active region 114. In the following description, the active region separation film 105 can be an insulating material film provided between the first active region 112 and the second active region 114 included in a single standard cell. For example, the active region separation film 105 will be described as an insulating material film provided inside the cell. The cell separation film 106 can be an insulating material film not provided inside the cell but extending along the cell boundary extending in the first direction X among the cell boundaries. For example, the cell separation film 106 will be described as an insulating material film provided along the cell boundary.

[0042] An integrated circuit according to some embodiments can include a plurality of gate stacks 120 and a plurality of insulating gates 150. The gate stacks 120 and the insulating gates 150 can extend in a second direction Y. The gate stacks 120 and the insulating gates 150 can be provided adjacent to each other in a first direction X. The plurality of insulating gates 150 can also be referred to as a plurality of insulating spacers.

[0043] The gate stacks 120 and the insulating gates 150 provided adjacent to each other in the first direction X can be spaced apart from each other by 1 CPP (contacted poly pitch). As an example, two adjacent gate stacks 120 can be spaced apart by 1 CPP. As another example, the gate stacks 120 and the insulating gates 150 adjacent to each other can be spaced apart from each other by 1 CPP. As another example, two adjacent insulating gates 150 can be spaced apart from each other by 1 CPP.

[0044] For example, assume that there are a first gate stack and a second gate stack adjacent to each other. If a distance between a center line of the first gate stack extending in the second direction Y and a center line of the second gate stack extending in the second direction Y is 1 CPP, this indicates that there is no other gate stack or insulating gate provided between the first gate stack and the second gate stack.

[0045] The gate stacks 120 and the insulating gates 150 can be provided over the first active region 112 and the second active region 114. The gate stacks 120 and the insulating gates 150 can extend from the first active region 112 to the second active region 114. The gate stacks 120 and the insulating gates 150 can cross the active region separation film 105. A portion of the gate stacks 120 and a portion of the insulating gates 150 can extend to a top of the cell separation film 106. As Figure 3 shown, a bottom surface of the insulating gate 150 is lower than an upper surface of the cell separation film 106, and the upper surface of the cell separation film 106 is higher than an upper surface of the active region separation film 105.

[0046] The gate stack 120 can include a gate electrode 122, a gate insulating film 124, a gate spacer 126, and a gate cover film 128. The present application is not limited thereto. In an example embodiment, the gate stack 120 can not include the gate cover film 128. The gate spacer 126 can define a gate trench in which the gate insulating film 124 and the gate electrode 122 can be formed. The gate spacer 126 can include, for example, an insulating material. The gate insulating film 124 can be formed along a periphery of the first nanosheet 112NS. Although not shown, the gate insulating film 124 can be formed along a periphery of the second nanosheet 114NS. The gate insulating film 124 can include, for example, at least one of silicon oxide or a high dielectric constant material. The high dielectric constant material can be, for example, a material having a dielectric constant greater than that of silicon oxide. The gate electrode 122 can be formed on the gate insulating film 124. The gate electrode 122 can wrap around a periphery of the first nanosheet 112NS. Although not shown, the gate electrode 122 can wrap around a periphery of the second nanosheet 114NS. The gate electrode 122 can include, for example, at least one of a metal (which denotes including a metal alloy including two or more metals), a metal nitride, a metal carbide, a metal silicide, and a semiconductor material. Figure 9 Figure 9

[0047] The insulating gate 150 can separate at least a portion of the first active region 112 and at least a portion of the second active region 114. The insulating gate 150 can separate a first upper active region 112U of the first active region 112. Although the insulating gate 150 is shown as separating a portion of a first lower active region 112B in the first active region 112, embodiments are not limited thereto. The insulating gate 150 can completely separate the first lower active region 112B for electrical separation of adjacent elements. Although not shown, the insulating gate 150 can separate a second upper active region 114U in the second active region 114 and can separate a portion of a second lower active region 114B. In consideration of a manufacturing process for forming the insulating gate 150, after removing at least a portion of the first active region 112 and at least a portion of the second active region 114, an insulating material is filled in a portion from which the first active region 112 and the second active region 114 are removed. Accordingly, the insulating gate 150 can be formed. Accordingly, a portion of a sidewall of the insulating gate 150 can be in contact with the first active region 112 and the second active region 114. A portion of the sidewall of the insulating gate 150 can be in contact with a semiconductor material film included in the first active region 112 and the second active region 114. Unless the context indicates otherwise, the term "contact" as used herein refers to direct connection (i.e., touching).

[0048] ​​The insulating gate 150 can cross the active region separation film 105. The insulating gate 150 can be disposed on the active region separation film 105. A portion of the insulating gate 150 can enter the active region separation film 105. In a process of forming the insulating gate 150, a portion of the active region separation film 105 can be removed. Accordingly, a portion of the insulating gate 150 can enter the active region separation film 105. The gate spacer 126 can be disposed on a sidewall of the insulating gate 150. The insulating gate 150 can include, for example, an insulating material. Although the insulating gate 150 is illustrated as a single film, embodiments are not limited thereto.

[0049] In the integrated circuit according to some embodiments, at least a portion of the insulating gate 150 extending in the second direction Y can be disposed at a boundary between two adjacent standard cells and separate the two adjacent standard cells. The insulating gate 150 can be disposed not only in the boundary of the standard cell but also inside the standard cell. However, hereinafter, the insulating gate 150 will be described as being disposed at the boundary of the standard cell extending in the second direction Y.

[0050] The semiconductor pattern 130 can be formed between the gate stack 120 and the insulating gate 150 adjacent to each other. The semiconductor pattern 130 can be formed by removing some of the active regions 112 and 114 to form a recess, and then filling the recess through an epitaxial growth process. The semiconductor pattern 130 can be formed on the first active region 112. In Figure 6A and Figure 6B In the semiconductor pattern 130 can be formed on the first active region 112 and the second active region 114. At least a portion of the semiconductor pattern 130 can be included in a source / drain region of a transistor. The semiconductor pattern 130 formed on the first active region 112 can be doped with impurities of a different conductive type from the semiconductor pattern 130 formed on the second active region 114. The semiconductor pattern 130 can also be formed between the insulating gates 150 adjacent to each other.

[0051] The cell gate cut pattern 160 can be disposed on the cell separation film 106. The cell gate cut pattern 160 can extend in the first direction X. The cell gate cut pattern 160 can extend in the first direction X along the boundary of the first standard cell 20, the boundary of the first insulating fill cell 10, and the boundary of the second standard cell 22. The gate stack 120 and the insulating gate 150 can be disposed between the cell gate cut patterns 160 spaced apart from each other in the second direction Y. The cell gate cut pattern 160 can include, for example, an insulating material.

[0052] The cell gate cut pattern 160 can cut the gate stack 120 or the insulating gate 150 at the boundary of the cell. The cell gate cut pattern 160 can be in contact with the gate stack 120 and the insulating gate 150. The cell gate cut pattern 160 can be in contact with the short side of the gate stack 120 extending in the first direction X and the short side of the insulating gate 150 extending in the first direction X. The first standard cell 20, the first insulative fill cell 10, and the second standard cell 22 can further include the cell gate cut pattern 160 formed along the boundary extending in the first direction X.

[0053] In Figure 4A , the gate insulating film 124 can not be formed on the sidewall of the cell gate cut pattern 160. The present application is not limited thereto. In an example embodiment as Figure 4B indicated, the gate insulating film 124 can extend along the sidewall of the cell gate cut pattern 160. Such a difference can vary depending on at which stage the cell gate cut pattern 160 is formed. When the cell gate cut pattern 160 is formed after the gate electrode 122 is formed, as Figure 4A indicated, the gate insulating film 124 can not be formed on the sidewall of the cell gate cut pattern 160. On the other hand, when the cell gate cut pattern 160 is formed before the gate electrode 122 is made (a mold gate stage for forming the gate electrode 122), as Figure 4B indicated, the gate insulating film 124 can extend along the sidewall of the cell gate cut pattern 160.

[0054] The first insulative fill cell 10 can be disposed between the first standard cell 20 and the second standard cell 22. The first standard cell 20 and the second standard cell 22 can be disposed adjacent to each other in the first direction X, and the first insulative fill cell 10 is interposed therebetween. The boundary between the first insulative fill cell 10 and the first standard cell 20 extends in the second direction Y, and the boundary between the first insulative fill cell 10 and the second standard cell 22 extends in the second direction Y.

[0055] The first insulative fill cell 10 can include two insulating gates 150 crossing the first active region 112 and the second active region 114 and adjacent to each other in the first direction X. Each insulating gate 150 can be located at the boundary of the first insulative fill cell 10 extending in the second direction Y.

[0056] The first insulative fill unit 10 can have a one pitch dimension in the first direction X. The one pitch dimension can be 1 CPP (contact poly pitch). For example, when the first insulative fill unit 10 has a first fill unit boundary and a second fill unit boundary extending in the second direction Y, the first insulative fill unit 10 can extend the one pitch dimension in the first direction X from the first fill unit boundary to the second fill unit boundary.

[0057] For ease of description, the first standard unit 20 can have a width of 5 CPPs in the first direction X. The first standard unit 20 can be defined by two insulative gates 150 spaced apart from each other by a distance of 5 CPPs. Four gate stacks 120 can be disposed in the first standard unit 20. For example, the four gate stacks 120 can be disposed between the two insulative gates 150 defining the first standard unit 20 in the first direction X. The first standard unit 20 can form a boundary with the first insulative fill unit 10. The first insulative fill unit 10 can form a boundary with the first standard unit 20 in one of the two insulative gates 150 of the first insulative fill unit 10. The first standard unit 20 and the first insulative fill unit 10 adjacent to each other can share an insulative gate 150 at a common boundary. The first standard unit 20 can also include an insulative gate 150 spaced apart from the one of the two insulative gates 150 by 5 CPPs and located at a different boundary from the first insulative fill unit 10. The first standard unit 20 can include one or more (e.g., four) gate stacks 120 disposed between the insulative gates 150 located at the boundary of the first standard unit 20. In Figure 1 In an embodiment, the first standard unit 20 can have a width of 5 CPPs.

[0058] The second standard unit 22 can form a boundary with the first insulative fill unit 10. The first insulative fill unit 10 can form a boundary with the second standard unit 22 in the other of the two insulative gates 150 of the first insulative fill unit 10. The second standard unit 22 and the first insulative fill unit 10 adjacent to each other can share an insulative gate 150 at a common boundary. The second standard unit 22 can also include an insulative gate 150 spaced apart from the other of the two insulative gates 150 by 5 CPPs and located at a different boundary from the first insulative fill unit 10. The second standard unit 22 can include one or more (e.g., four) gate stacks 120 disposed between the insulative gates 150 located at the boundary of the second standard unit 22. In Figure 1 In an embodiment, the second standard unit 22 can have a width of 5 CPPs.

[0059] The first standard cell 20 can also include a first portion of the first active region 112 and a first portion of the second active region 114. The gate stack 120 included in the first standard cell 20 can intersect the first portion of the first active region 112 and the first portion of the second active region 114. The first standard cell 20 can include integrated first p-type transistors 132 and first n-type transistors 134. In an example embodiment, the first p-type transistors 132 and the first n-type transistors 134 can be connected to each other to achieve the intended functionality of the first standard cell 20. The first p-type transistors 132 can be formed at locations where the gate stack 120 and the first portion of the first active region 112 intersect each other, and the first n-type transistors 134 can be formed at locations where the gate stack 120 and the first portion of the second active region 114 intersect each other. For example, each first p-type transistor 132 can include the gate electrode 122, the first nanosheet 112NS as a channel region, and the semiconductor pattern 130 as a source / drain region.

[0060] The second standard cell 22 can also include a second portion of the first active region 112 and a second portion of the second active region 114. The gate stack 120 included in the second standard cell 22 can intersect the second portion of the first active region 112 and the second portion of the second active region 114. The second standard cell 22 can include integrated second p-type transistors 136 and second n-type transistors 138. The second p-type transistors 136 can be formed at locations where the gate stack 120 and the second portion of the first active region 112 intersect each other, and the second n-type transistors 138 can be formed at locations where the gate stack 120 and the second portion of the second active region 114 intersect each other. For example, each second p-type transistor 136 can include the gate electrode 122, the first nanosheet 112NS as a channel region, and the semiconductor pattern 130 as a source / drain region.

[0061] The first p-type transistors 132 and the second p-type transistors 136 are formed on the first portion of the first active region 112 and the second portion of the first active region 112, respectively, and the first n-type transistors 134 and the second n-type transistors 138 are formed on the first portion of the second active region 114 and the second portion of the second active region 114, respectively.

[0062] The first insulating fill unit 10 disposed between the first standard unit 20 and the second standard unit 22 includes two insulating gates 150 spaced apart from each other by, for example, 1 CPP. Since each of the insulating gates 150 separates at least some of the first active region 112 and the second active region 114, the first active region 112 and the second active region 114 can be divided into at least three portions in the first direction X, respectively. For example, in addition to the first portion and the second portion of the first active region 112, the at least three portions of the first active region 112 can further include a third portion disposed in the first insulating fill unit 10. Similarly, in addition to the first portion and the second portion of the second active region 114, the at least three portions of the second active region 114 can further include a third portion disposed in the first insulating fill unit 10. The semiconductor pattern 130 can be disposed between the two insulating gates 150 included in the first insulating fill unit 10. In the first insulating fill unit 10, the semiconductor pattern 130 can be disposed in the first active region 112 and the second active region 114 and between the two insulating gates 150 of the first insulating fill unit 10.

[0063] The first standard unit 20, the second standard unit 22, and the first insulating fill unit 10 can further include a unit gate cut pattern 160. The unit gate cut pattern 160 can extend along a boundary of the first standard unit 20 extending in the first direction X, a boundary of the first insulating fill unit 10 extending in the first direction X, and a boundary of the second standard unit 22 extending in the first direction X. The unit gate cut pattern 160 can be in contact with the gate stack 120 included in the first standard unit 20, the gate stack 120 included in the second standard unit 22, and the insulating gate 150 included in the first insulating fill unit 10. In an example embodiment, the unit gate cut pattern 160 can include an upper unit gate cut pattern and a lower unit gate cut pattern spaced apart from each other in the second direction Y. The upper unit gate cut pattern can be in contact with a first side of the first standard unit 20, and the lower unit gate cut pattern can be in contact with a second side of the first standard unit 20 opposite the first side in the second direction Y. The upper unit gate cut pattern can be in contact with a first side of the second standard unit 22, and the lower unit gate cut pattern can be in contact with a second side of the second standard unit 22 opposite the first side in the second direction Y. The upper unit gate cut pattern can be in contact with a first side of the first insulating fill unit 10, and the lower unit gate cut pattern can be in contact with a second side of the first insulating fill unit 10 opposite the first side in the second direction Y.

[0064] In Figures 5A-7B In accordance with some embodiments, an integrated circuit can include source / drain contacts 170, 170_1 and 170_2 and gate contacts 175.

[0065] The source / drain contacts 170, 170_1 and 170_2 can be disposed on the first active region 112 and the second active region 114. The source / drain contacts 170, 170_1 and 170_2 can be connected to the semiconductor pattern 130 formed on the first active region 112 and the second active region 114. The source / drain contacts 170, 170_1 and 170_2 can include normal source / drain contacts 170, extended source / drain contacts 170_1 and fill source / drain contacts 170_2. The normal source / drain contacts 170 can generally overlap the first active region 112 or the second active region 114. For example, the normal source / drain contacts 170 can refer to source / drain contacts in the first active region 112 or source / drain contacts in the second active region 114. A portion of the extended source / drain contacts 170_1 can extend to the top of the cell separation film 106 and the cell gate cut pattern 160. The extended source / drain contacts 170_1 can be connected to the power supply rail (Vdd) 195_1 and 195_2 to be described later. Figure 8 The fill source / drain contacts 170_2 can be disposed between the insulating gates 150 of the first insulating fill cell 10. The fill source / drain contacts 170_2 can not be electrically connected to the wiring layer formed at a level higher than the fill source / drain contacts 170_2.

[0066] The gate contacts 175 are formed on the gate stack 120 but not on the insulating gate 150. The gate contacts 175 can be connected to the gate stack 120. For example, the gate contacts 175 can be electrically connected to the gate electrode 122 of the gate stack 120.

[0067] The gate contacts 175 can be disposed on the first active region 112, the second active region 114 or the active region separation film 105. In the integrated circuit according to some embodiments, some of the gate contacts 175 can be disposed on the first active region 112 and some of the gate contacts 175 can be disposed on the second active region 114.

[0068] Each of the first standard cell 20 and the second standard cell 22 can include the normal source / drain contacts 170, the extended source / drain contacts 170_1 and the gate contacts 175.

[0069] In the first insulating fill cell 10 of Figure 5A , Figure 6A and Figure 6B , the first insulating fill cell 10 can include the fill source / drain contacts 170_2. In the first insulating fill cell 10 of Figure 5B and Figure 6C , the first insulating fill cell 10 does not include the fill source / drain contacts 170_2.

[0070] In the first insulating fill cell 10 of Figure 6AIn some embodiments, the fill source / drain contact 170_2 can include a contact barrier film 170a and a contact fill film 170b. The contact fill film 170b can fill a trench defined by the contact barrier film 170a. On the other hand, in some embodiments, the contact barrier film 170a can be formed only between the semiconductor pattern 130 and the contact fill film 170b, and can not be formed between the interlayer insulating film 190 and the contact fill film 170b. The normal source / drain contact 170 and the extended source / drain contact 170_1 can also have shapes as shown in FIGS. 17A and 17B. In subsequent drawings, the contact barrier film 170a and the contact fill film 170b are shown as one film without distinction. Figure 6B Figure 6A Figure 6B

[0071] Figure 7A Figure 7B Exemplary cross sections of the source / drain contacts 170 and 170_1 are shown in FIGS. 18A and 18B. Figure 7A Figure 7B may be a cross-sectional view taken in the second direction Y. Since the gate contact 175 is disposed in the first active region 112 or the second active region 114, a tight margin between the gate contact 175 and the source / drain contacts 170 and 170_1 should be taken into account. For example, depending on whether the gate contact 175 is located around the source / drain contacts 170 and 170_1, the cross section of the source / drain contacts 170 and 170_1 can have an L shape (FIG. 18A) or can have an inverted T shape (FIG. 18B). If the gate contact 175 is not disposed around the source / drain contacts 170 and 170_1, the source / drain contacts 170 and 170_1 can have a cross section as shown in FIGS. 19A and 19B. Figure 7A Figure 7B Figure 6A Figure 6B

[0072] In some embodiments, an integrated circuit according to some embodiments can include the source / drain vias 180 and 180_1, the gate via 185, the wiring pattern 195, and the power rails 195_1 and 195_2. Each of the first standard cell 20 and the second standard cell 22 can include the source / drain vias 180 and 180_1, the gate via 185, the wiring pattern 195, and the power rails 195_1 and 195_2. Figures 8-10B

[0073] ​​​​​​​​​​A gate via 185 can be formed on the gate contact 175. The gate via 185 can connect the gate contact 175 and the wiring pattern 195. Source / drain vias 180 and 180_1 can be formed on the source / drain contacts 170 and 170_1. The source / drain vias 180 and 180_1 can be connected to at least some of the source / drain contacts 170 and 170_1. The source / drain vias 180 and 180_1 can include normal vias 180 connecting normal source / drain contacts 170 and the wiring pattern 195, and power rail vias 180_1 connecting extended source / drain contacts 170_1 and power rails 195_1 and 195_2. The power rail vias 180_1 can overlap a portion of the extended source / drain contacts 170_1, further extending from the extended source / drain contacts 170_1 onto the power rails 195_1 and 195_2 in the second direction Y.

[0074] The wiring pattern 195 and the power rails 195_1 and 195_2 can extend in the first direction X. The power rails 195_1 and 195_2 can include an upper power rail 195_1 to which a first voltage is supplied and a lower power rail 195_2 to which a second voltage is supplied. The upper power rail 195_1 can supply power to p-type transistors, and the lower power rail 195_2 can supply power to n-type transistors.

[0075] The structure connecting the gate contact 175 and the wiring pattern 195 and the structure connecting the source / drain contacts 170 and 170_1 and the wiring pattern 195 and the power rails 195_1 and 195_2 can not have the structure as shown in Figure 9 .

[0076] In Figure 10A , intermediate contacts 176 can be interposed between the source / drain vias 180 and 180_1 and the source / drain contacts 170 and 170_1. The intermediate contacts 176 can also be interposed between the gate via 185 and the gate contact 175. Although the wiring pattern 195 and the gate via 185 are shown as having an integrated structure, the present application is not limited thereto. The wiring pattern 195 and the gate via 185 can be separated by a barrier film.

[0077] In Figure 10B , the source / drain contacts 170 and 170_1 can be connected to the wiring pattern 195 and the power rails 195_1 and 195_2 without the source / drain vias 180 and 180_1. The gate contact 175 can be connected to the wiring pattern 195 without the gate via 185.

[0078] Figure 11is a top view for illustrating an integrated circuit according to some embodiments. In the following description and drawings, only the gate stack 120, the insulating gate 150, the first active region 112, the second active region 114, and the cell gate cut pattern 160 will be illustrated. Furthermore, the use of Figures 1-10B repetitive content of portions of the description.

[0079] Referring to Figure 11 , an integrated circuit according to some embodiments can include a first insulating fill unit 10, a second insulating fill unit 12, a third standard unit 24, a fourth standard unit 26, a fifth standard unit 28, and a sixth standard unit 30.

[0080] The first insulating fill unit 10 and the second insulating fill unit 12 can have a width of 1 CPP in the first direction X. The third standard unit 24, the fourth standard unit 26, and the fifth standard unit 28 can have a width of 3 CPP in the first direction X. The sixth standard unit 30 can have a width of 2 CPP in the first direction X. When the first insulating fill unit 10, the second insulating fill unit 12, the third standard unit 24, the fifth standard unit 28, and the sixth standard unit 30 have a height B in the second direction Y, the fourth standard unit 26 can have a height 2B.

[0081] Each of the first insulating fill unit 10, the second insulating fill unit 12, the third standard unit 24, the fourth standard unit 26, the fifth standard unit 28, and the sixth standard unit 30 can include an insulating gate 150 located on a boundary.

[0082] Each of the first insulating fill unit 10 and the second insulating fill unit 12 includes two insulating gates 150. The third standard unit 24 can be disposed between the first insulating fill unit 10 and the second insulating fill unit 12. The third standard unit 24 can be adjacent to the first insulating fill unit 10 and the second insulating fill unit 12 in the first direction X. The third standard unit 24 can form a first boundary with the first insulating fill unit 10 in one insulating gate 150 of the first insulating fill unit 10 and can form a second boundary with the second insulating fill unit 12 in one insulating gate 150 of the second insulating fill unit 12, the second boundary being opposite to the first boundary in the first direction X.

[0083] The sixth standard cell 30 can be adjacent to the first insulating fill cell 10 in the second direction Y. The fifth standard cell 28 can be adjacent to the sixth standard cell 30 in the first direction X. The fifth standard cell 28 can be adjacent to the second insulating fill cell 12 in the second direction Y. The fifth standard cell 28 can form a boundary with the sixth standard cell 30. An insulating gate 150 can be located at the boundary between the fifth standard cell 28 and the sixth standard cell 30. For example, the fifth standard cell 28 and the sixth standard cell 30 can share the insulating gate 150 at the common boundary.

[0084] The gate stack 120 included in the sixth standard cell 30 can be aligned with one of the two insulating gates 150 of the first insulating fill cell 10 that forms a boundary with the third standard cell 24 in the second direction Y. One of the two gate stacks 120 of the fifth standard cell 28 can be aligned with one of the two insulating gates 150 of the second insulating fill cell 12 that forms a boundary with the third standard cell 24 in the second direction Y.

[0085] A cell gate cut pattern 160 can be disposed between the third standard cell 24 and the fifth standard cell 28 and between the third standard cell 24 and the sixth standard cell 30. The cell gate cut pattern 160 can be in contact with the insulating gates 150 and / or the gate stacks 120 included in the first insulating fill cell 10, the second insulating fill cell 12, the third standard cell 24, the fifth standard cell 28, and the sixth standard cell 30. For example, the first insulating fill cell 10 can form a boundary with the sixth standard cell 30 in the cell gate cut pattern 160.

[0086] The fourth standard cell 26 can form a boundary with the first insulating fill cell 10 in the insulating gate 150 of the first insulating fill cell 10. Further, the fourth standard cell 26 can form a boundary with the sixth standard cell 30. The insulating gate 150 included in the fourth standard cell 26 can be located at the boundary between the fourth standard cell 26 and the sixth standard cell 30. The insulating gate 150 located at the boundary between the first insulating fill cell 10 and the fourth standard cell 26 can be spaced apart from the insulating gate 150 located at the boundary between the fourth standard cell 26 and the sixth standard cell 30 in the second direction Y. The insulating gate 150 located at the boundary between the first insulating fill cell 10 and the fourth standard cell 26 can be aligned with the insulating gate 150 located at the boundary between the fourth standard cell 26 and the sixth standard cell 30 in the second direction Y. The insulating gate 150 located at the boundary between the first insulating fill cell 10 and the fourth standard cell 26 can be separated from the insulating gate 150 located at the boundary between the fourth standard cell 26 and the sixth standard cell 30 by the cell gate cut pattern 160.

[0087] Since the fourth standard cell 26 forms a boundary with the first insulating fill cell 10 and the sixth standard cell 30, the height of the fourth standard cell 26 in the second direction Y can be the sum of the height of the first insulating fill cell 10 in the second direction Y and the height of the sixth standard cell 30 in the second direction Y.

[0088] In addition, the sum of the width of the first insulating fill cell 10 in the first direction X, the width of the third standard cell 24 in the first direction X, and the width of the second insulating fill cell 12 in the first direction X can be the same as the sum of the width of the fifth standard cell 28 in the first direction X and the width of the sixth standard cell 30 in the first direction X. For example, the density of the integrated circuit layout can be increased by appropriately using the insulating fill cells 10 and 12 having a 1 CPP width.

[0089] The cell gate cut pattern 160 disposed between the third standard cell 24 and the fifth standard cell 28 and between the third standard cell 24 and the sixth standard cell 30 can not extend to the inside of the fourth standard cell 26.

[0090] The third standard cell 24, the fourth standard cell 26, the fifth standard cell 28, and the sixth standard cell 30 can include p-type transistors and n-type transistors formed on the first active region 112 and the second active region 114, respectively.

[0091] The width in the first direction X and the height in the second direction Y of the above-described third standard cell 24, the fourth standard cell 26, the fifth standard cell 28, and the sixth standard cell 30 are exemplary, and thus are not limited thereto. In an exemplary embodiment, standard cells and insulating fill cells having different widths in the first direction X and different heights in the second direction X than those described above are combined to allow the integrated circuit layout to have a square or rectangular shape.

[0092] Figure 12 FIG. 1 is a plan view for explaining an integrated circuit according to some embodiments. Figure 13 FIG. 2 is a plan view for explaining an integrated circuit according to some embodiments. Figure 14 FIG. 3 is a plan view for explaining an integrated circuit according to some embodiments. In the following description and drawings, only the gate stack 120, the insulating gate 150, the first active region 112, the second active region 114, and the cell gate cut pattern 160 will be described. In addition, the repeated content of the components explained will be simplified or omitted. Figures 1-11 The repeated content of the components explained will be simplified or omitted.

[0093] Referring to Figures 12-14 , an integrated circuit according to some embodiments can include a first insulating fill cell 10, a third standard cell 24, a seventh standard cell 32, an eighth standard cell 34, and a ninth standard cell 36.

[0094] The third standard unit 24, the seventh standard unit 32, the eighth standard unit 34, and the ninth standard unit 36 ​​may have a width of 3 CPP in the first direction X. The third standard unit 24, the seventh standard unit 32, the eighth standard unit 34, and the ninth standard unit 36 ​​may have an insulated gate 150 located at the boundary. Furthermore, each of the third standard unit 24, the seventh standard unit 32, the eighth standard unit 34, and the ninth standard unit 36 ​​may include two gate stacks 120.

[0095] The first insulating fill cell 10 may form a boundary with the third standard cell 24 and the seventh standard cell 32 that are adjacent to each other in the first direction X. Each of the third standard cell 24 and the seventh standard cell 32 may form a boundary with the first insulating fill cell 10 in the insulating gate 150 included in the first insulating fill cell 10.

[0096] The eighth standard unit 34 can be configured to be adjacent to the first insulating filler unit 10 in the second direction Y. The ninth standard unit 36 ​​can be configured to be adjacent to the first insulating filler unit 10 in the second direction Y. The first insulating filler unit 10 can be disposed between the eighth standard unit 34 and the ninth standard unit 36.

[0097] exist Figure 12 In the first insulating filling unit 10, the insulating gate 150 can be aligned with the gate stack 120 included in the eighth standard unit 34 in the second direction Y. The insulating gate 150 of the first insulating filling unit 10 can be aligned with the gate stack 120 included in the ninth standard unit 36 ​​in the second direction Y.

[0098] exist Figure 13 In this configuration, one of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the third standard unit 24 can be aligned in the second direction Y with the gate stack 120 of the eighth standard unit 34. The other of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the seventh standard unit 32 can be aligned in the second direction Y with the insulating gate 150 located on the boundary of the eighth standard unit 34. However, the other of the two insulating gates 150 of the first insulating fill unit 10 can be aligned in the second direction Y with the gate stack 120 included in the ninth standard unit 36.

[0099] exist Figure 14Among them, one of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the third standard cell 24 can be aligned with the gate stack 120 of the eighth standard cell 34 in the second direction Y. The other of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the seventh standard cell 32 can be aligned with the insulating gate 150 located on the boundary of the eighth standard cell 34 in the second direction Y. The one of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the third standard cell 24 can be aligned with the insulating gate 150 located on the boundary of the ninth standard cell 36 in the second direction Y. The other of the two insulating gates 150 of the first insulating fill unit 10 located on the boundary with the seventh standard cell 32 can be aligned with the gate stack 120 of the ninth standard cell 36 in the second direction Y.

[0100] Each of the third standard cell 24, the seventh standard cell 32, the eighth standard cell 34, and the ninth standard cell 36 can include p-type transistors and n-type transistors formed on the first active region 112 and the second active region 114, respectively.

[0101] The width of the above-described third standard cell 24, the seventh standard cell 32, the eighth standard cell 34, and the ninth standard cell 36 in the first direction X is exemplary, and thus is not limited thereto.

[0102] Figures 15-19A and Figure 19B is a diagram for explaining an integrated circuit according to some embodiments.

[0103] Figure 15 is a top view of an integrated circuit for explaining an integrated circuit according to some embodiments. Figure 16 is a cross-sectional view taken along the line G-G of Figure 15 . Figure 17 is a cross-sectional view taken along the line H-H of Figure 15 . Figure 18 is a cross-sectional view taken along the line I-I of Figure 15 . Figure 19A and Figure 19B are exemplary views showing plan views of gate electrodes in a floating (or dummy) gate cut pattern. Repetitive descriptions of the above-explained components will be simplified or omitted in the following description.

[0104] Referring to Figures 15-19A and Figure 19B , an integrated circuit according to some embodiments can include a tenth standard cell 42, an eleventh standard cell 44, and a conductive fill unit 40.

[0105] The integrated circuit can include a plurality of gate stacks 120 and a plurality of floating gate stacks 125, 125_1 and 125_2. The gate stacks 120 and the floating gate stacks 125, 125_1 and 125_2 can extend along the second direction Y. The gate stacks 120 and the floating gate stacks 125, 125_1 and 125_2 can be disposed adjacent to each other in the first direction X. The gate stacks 120 and the floating gate stacks 125, 125_1 and 125_2 can be spaced apart from each other by 1 CPP in the first direction. The plurality of floating gate stacks 125, 125_1 and 125_2 can also be referred to as a plurality of dummy gate stacks. As used herein, the term "dummy" is used to refer to a component that has the same or similar structure and shape as other components but does not have a substantial function and exists in the device only as a pattern.

[0106] Each of the floating gate stacks 125, 125_1 and 125_2 can have the same stack structure as the stack structure of the gate stacks 120. Each of the floating gate stacks 125, 125_1 and 125_2 can include a gate electrode 122, a gate insulating film 124, a gate spacer 126 and a gate cover film 128. Figure 2 Figure 2 Figure 2

[0107] The floating gate stacks 125, 125_1 and 125_2 can be disposed over the first active region 112 and the second active region 114. The floating gate stacks 125, 125_1 and 125_2 can extend from the first active region 112 to the second active region 114 and can cross the active region separation film 105. Some of the floating gate stacks 125, 125_1 and 125_2 can extend to the top of the cell separation film 106. In the integrated circuit according to some embodiments, at least some of the floating gate stacks 125, 125_1 and 125_2 can be disposed at a boundary of a standard cell extending in the second direction Y to electrically separate the standard cell and other standard cells adjacent thereto. The floating gate stacks 125, 125_1 and 125_2 can electrically separate standard cells adjacent to each other, rather than physically separating the standard cells. Although the floating gate stacks 125, 125_1 and 125_2 have the same structure as the structure of the gate stacks 120, the floating gate stacks 125, 125_1 and 125_2 do not function as gates of transistors since the floating gate stacks 125, 125_1 and 125_2 are connected to the power supply rails 195_1 and 195_2. The floating gate stacks 125, 125_1 and 125_2 can be disposed not only at the boundaries of standard cells but also inside the standard cells. However, hereinafter, the floating gate stacks 125, 125_1 and 125_2 will be described as being disposed at the boundaries of standard cells extending in the second direction Y.​​​

[0108] A cell gate cut pattern 160 can be disposed on the cell separation film 106. The cell gate cut pattern 160 can extend in the first direction X along the boundary of the tenth standard cell 42, the boundary of the conductive fill cell 40, and the boundary of the eleventh standard cell 44. The gate stack 120 and the floating gate stacks 125, 125_1, and 125_2 can be disposed between the cell gate cut patterns 160 spaced apart from each other in the second direction Y. The cell gate cut pattern 160 can cut the gate stack 120 or the floating gate stacks 125, 125_1, and 125_2 at the boundary of the cell. The cell gate cut pattern 160 can be in contact with the gate stack 120 and the floating gate stacks 125, 125_1, and 125_2.

[0109] A floating (or dummy) gate cut pattern 165 can be disposed on the active region separation film 105. The floating gate cut pattern 165 can cut the floating gate stacks 125, 125_1, and 125_2 into two parts. The two parts of the floating gate stacks 125, 125_1, and 125_2 separated by the floating gate cut pattern 165 are electrically insulated from each other. The floating gate cut pattern 165 is in contact with the floating gate stacks 125, 125_1, and 125_2 divided into two parts. The floating gate cut pattern 165 can include, for example, an insulating material. The floating gate cut pattern 165 can be formed in the same manufacturing process as the cell gate cut pattern 160 at the time of the manufacturing process, but is not limited thereto.

[0110] The conductive fill cell 40 can be disposed between the tenth standard cell 42 and the eleventh standard cell 44. The tenth standard cell 42 and the eleventh standard cell 44 can be disposed adjacent to each other in the first direction X with the conductive fill cell 40 interposed therebetween. The boundary between the conductive fill cell 40 and the tenth standard cell 42 extends in the second direction Y, and the boundary between the conductive fill cell 40 and the eleventh standard cell 44 extends in the second direction Y.

[0111] The conductive fill cell 40 can include a first floating gate stack 125_1 and a second floating gate stack 125_2 crossing the first active region 112 and the second active region 114 and adjacent to each other in the first direction X. The first floating gate stack 125_1 and the second floating gate stack 125_2 can be located at opposite boundaries of the conductive fill cell 40 extending in the second direction Y, respectively. The conductive fill cell 40 can have a size of one pitch in the first direction X.

[0112] The conductive fill unit 40 can further include a floating gate cut pattern 165 disposed on the active region separation film 105. The first floating gate stack 125_1 includes a first upper floating gate stack 125_1U and a first lower floating gate stack 125_1L separated by the floating gate cut pattern 165. The second floating gate stack 125_2 includes a second upper floating gate stack 125_2U and a second lower floating gate stack 125_2L separated by the floating gate cut pattern 165.

[0113] The conductive fill unit 40 can further include first floating (or fill) contacts 201 and 202 and second floating (or fill) contacts 203 and 204. The first fill contacts 201 and 202 connect the first floating gate stack 125_1 to the power supply rails 195_1 and 195_2. The second fill contacts 203 and 204 connect the second floating gate stack 125_2 to the power supply rails 195_1 and 195_2. The first fill contacts 201 and 202 include a first upper fill contact 201 and a first lower fill contact 202. The second fill contacts 203 and 204 include a second upper fill contact 203 and a second lower fill contact 204. The first upper fill contact 201 connects the first upper floating gate stack 125_1U to the upper power supply rail 195_1. The first lower fill contact 202 connects the first lower floating gate stack 125_1L to the lower power supply rail 195_2. The second upper fill contact 203 connects the second upper floating gate stack 125_2U to the upper power supply rail 195_1. The second lower fill contact 204 connects the second lower floating gate stack 125_2L to the lower power supply rail 195_2.

[0114] In an integrated circuit according to some embodiments, the gate insulating film 124 included in each of the first floating gate stack 125_1 and the second floating gate stack 125_2 does not extend along the sidewall of the floating gate cut pattern 165.

[0115] The first fill contacts 201 and 202 and the second fill contacts 203 and 204 can be disposed at a location where the first floating gate stack 125_1 and the second floating gate stack 125_2 overlap the cell separation film 106. The first fill contacts 201 and 202 and the second fill contacts 203 and 204 are not disposed inside the cell, but can be located at the boundary of the cell. Thus, the wiring for connecting the power supply rails 195_1 and 195_2 with the floating gate stacks 125_1 and 125_2 can be simplified. For example, in an integrated circuit according to some embodiments of the present inventive concept, the connection between the power supply rails 195_1 and 195_2 and the floating gate stacks 125_1 and 125_2 does not pass through the source / drain contacts (170 and 170_1 of FIG. 5).

[0116] In an integrated circuit according to some embodiments, the first fill contacts 201 and 202 and the second fill contacts 203 and 204 can include contact portions 201_1, 202_1, 203_1, and 204_1 and via portions 201_2, 202_2, 203_2, and 204_2. The contact portions 201_1, 202_1, 203_1, and 204_1 can be similar to the gate contacts 175 of Figure 5A or Figure 5B The via portions 201_2, 202_2, 203_2, and 204_2 can be similar to the gate vias 185 of Figure 8 .

[0117] The tenth standard cell 42 can form a boundary with the conductive fill cell 40. The conductive fill cell 40 can form a boundary with the tenth standard cell 42 at a first floating gate stack 125_1. The tenth standard cell 42 can include a third floating gate stack 125 located at a different boundary than the conductive fill cell 40. The floating gate stacks 125 and 125_1 can be located at the boundary of the tenth standard cell 42. The tenth standard cell 42 can include one or more (e.g., two) gate stacks 120 disposed between the floating gate stacks 125 and 125_1 located at the boundary of the tenth standard cell 42.

[0118] The eleventh standard cell 44 can form a boundary with the conductive fill cell 40. The conductive fill cell 40 can form a boundary with the eleventh standard cell 44 at a second floating gate stack 125_2. The eleventh standard cell 44 can include a third floating gate stack 125 located at a different boundary than the conductive fill cell 40. The floating gate stacks 125 and 125_2 can be located at the boundary of the eleventh standard cell 44. The eleventh standard cell 44 can include one or more (e.g., two) gate stacks 120 disposed between the floating gate stacks 125 and 125_2 located at the boundary of the eleventh standard cell 44.

[0119] The third floating gate stack 125 located at the boundary of the tenth standard cell 42 and the eleventh standard cell 44 can be split into two portions by the floating gate cut pattern 165. The third floating gate stack 125 can also be connected to the power rails 195_1 and 195_2 by fill contacts similar to the fill contacts 201 and 203 and 202 and 204.

[0120] The tenth standard cell 42 and the eleventh standard cell 44 can also include a first active region 112 and a second active region 114. The tenth standard cell 42 and the eleventh standard cell 44 can include p-type transistors and n-type transistors formed on the first active region 112 and the second active region 114, respectively.

[0121] The tenth standard cell 42, the eleventh standard cell 44, and the conductive fill cell 40 can further include a cell gate cut pattern 160. The cell gate cut pattern 160 can extend along a boundary of the tenth standard cell 42 extending in the first direction X, a boundary of the conductive fill cell 40 extending in the first direction X, and a boundary of the eleventh standard cell 44 extending in the first direction X. The cell gate cut pattern 160 can be in contact with the gate stack 120 included in the tenth standard cell 42, the gate stack 120 included in the eleventh standard cell 44, and the first and second floating gate stacks 125_1 and 125_2.

[0122] In the integrated circuit according to some embodiments, the cell gate cut pattern 160 can have a linear shape of an "I" shape.

[0123] In Figure 19A a plan view, the gate electrode 122 of the first upper floating gate stack 125_1U can be spaced apart from the gate electrode 122 of the first lower floating gate stack 125_1L with the floating gate cut pattern 165 therebetween. A boundary between the gate electrode 122 of the first upper floating gate stack 125_1U and the floating gate cut pattern 165 can have a concave shape in the second direction Y. A boundary between the gate electrode 122 of the first lower floating gate stack 125_1L and the floating gate cut pattern 165 can have a concave shape in a direction opposite to the second direction Y. The same configuration can also apply to the gate electrode 122 of the second upper floating gate stack 125_2U and the gate electrode 122 of the second lower floating gate stack 125_2L.

[0124] In Figure 19B a plan view, the gate electrode 122 of the first upper floating gate stack 125_1U can be spaced apart from the gate electrode 122 of the first lower floating gate stack 125_1L with the floating gate cut pattern 165 therebetween. A boundary between the gate electrode 122 of the first upper floating gate stack 125_1U and the floating gate cut pattern 165 can have a flat shape. A boundary between the gate electrode 122 of the first lower floating gate stack 125_1L and the floating gate cut pattern 165 can have a flat shape. The same configuration can also apply to the gate electrode 122 of the second upper floating gate stack 125_2U and the gate electrode 122 of the second lower floating gate stack 125_2L.

[0125] Figures 20-24 FIGS. 1 to 3 are diagrams for illustrating an integrated circuit according to some embodiments. For convenience of explanation, differences from contents explained using Figures 15-19A and Figure 19B will be explained. As a reference, Figure 20 is a cross-sectional view taken along a line H-H of Figure 15 .Figure 21 and Figure 22 is a diagram for illustrating a relationship between the first upper fill contact 201 and the second upper fill contact 203. Figure 23 and Figure 24 is a diagram showing another structure of the first fill contacts 201 and 202.

[0126] Referring to Figure 20 In the integrated circuit according to some embodiments, the gate insulating film 124 included in the first floating gate stack 125_1 can extend along a sidewall of the floating gate cut pattern 165.

[0127] The gate insulating film 124 included in the second floating gate stack 125_2 can extend along a sidewall of the floating gate cut pattern, similarly to Figure 20 illustrated.

[0128] Referring to Figure 21 In the integrated circuit according to some embodiments, the via portion 201_2 of the first upper fill contact 201 and the via portion 203_2 of the second upper fill contact 203 can be a single conductive pattern connected to each other.

[0129] Similarly, the via portion 202_2 of the first lower fill contact 202 and the via portion 204_2 of the second lower fill contact 204 can also be a single conductive pattern connected to each other.

[0130] Referring to Figure 22 In the integrated circuit according to some embodiments, the contact portion 201_1 of the first upper fill contact and the contact portion 203_1 of the second upper fill contact can be a single conductive pattern connected to each other.

[0131] Similarly, the contact portion 202_1 of the first lower fill contact and the contact portion 204_1 of the second lower fill contact can also be a single conductive pattern connected to each other.

[0132] Referring to Figure 23 In the integrated circuit according to some embodiments, the first upper fill contact 201 and the first lower fill contact 202 can further include connection contact portions 201_3 and 202_3, respectively.

[0133] The connection contact portions 201_3 and 202_3 can be similar to the intermediate contact 176 of Figure 10A The second upper fill contact 203 and the second lower fill contact 204 can also further include connection contact portions.

[0134] Referring to Figure 24In the integrated circuit according to some embodiments, the power supply rails 195_1 and 195_2 can be connected to the contact portions 201_1 and 202_1 without the via portions 201_2 and 202_2 as described with reference to Figure 23 FIG. 1. Similarly, the power supply rails 195_1 and 195_2 can be connected to the contact portions 203_1 and 204_1 without the via portions 203_2 and 204_2.

[0135] Figure 25 and Figure 26 are top views for illustrating integrated circuits according to some embodiments. Differences from the contents illustrated using Figures 15-19B FIG. 1 will be explained for convenience of explanation.

[0136] Referring to Figure 25 and Figure 26 , in the integrated circuit according to some embodiments, the floating gate stacks 125, 125_1, and 125_2 can further extend beyond one end of the gate stack 120 in the second direction Y.

[0137] The floating gate stacks 125, 125_1, and 125_2 have lengths in the second direction Y that are greater than a length of the gate stack 120.

[0138] In the integrated circuit according to some embodiments, the cell gate cut pattern 160 can include a portion that protrudes toward the gate stack 120. A first sidewall of the cell gate cut pattern 160 that extends along the first direction X can have irregularities. Figure 25 However, a second sidewall of the cell gate cut pattern 160 opposite the first sidewall can be flat without irregularities.

[0139] In the integrated circuit according to some embodiments, the cell gate cut pattern 160 can have a shape in which a dumbbell shape is repeated.

[0140] Figure 26 and

[0141] are top views for illustrating integrated circuits according to some embodiments. Differences from the contents illustrated using Figure 27 FIG. 1 will be explained for convenience of explanation. Figure 28 Figures 15-19B Referring to and

[0142] , the integrated circuit according to some embodiments can further include a twelfth standard cell 46. Figure 27 Figure 28 The twelfth standard cell 46 can be adjacent to the conductive fill cell 40 in the second direction Y. The twelfth standard cell 46 can include a third floating gate stack 125 and the gate stack 120.

[0143] The twelfth standard cell 46 can be adjacent to the conductive fill cell 40 in the second direction Y. The twelfth standard cell 46 can include a third floating gate stack 125 and the gate stack 120. ​

[0144] The first lower fill contact 202 can be connected to the gate stack 120 included in the twelfth standard cell 46. The second lower fill contact 204 can be connected to the gate stack 120 included in the twelfth standard cell 46.

[0145] In Figure 27 , the gate stack 120 included in the twelfth standard cell 46 can be in contact with the cell gate cut pattern 160.

[0146] In Figure 28 , the gate stack 120 included in the twelfth standard cell 46 is not in contact with the cell gate cut pattern 160. The gate stack 120 included in the twelfth standard cell 46 can be in contact with the first floating gate stack 125_1 and the second floating gate stack 125_2.

[0147] Figure 29 and Figure 30 are diagrams related to a method for designing a layout of an integrated circuit according to some embodiments.

[0148] Referring to Figure 29 , a first cell CELL1 and a second cell CELL2 are disposed 1 CPP apart from each other in a first direction X.

[0149] Each of the first cell CELL1 and the second cell CELL2 includes a normal gate NG and a dummy gate DG spaced apart from each other in the first direction X. Each of the first cell CELL1 and the second cell CELL2 can include a first free active region ACT1 and a second free active region ACT2 spaced apart from each other in a second direction Y.

[0150] Each of the first cell CELL1 and the second cell CELL2 can include a gate removal mask GRM for removing the dummy gate DG. The gate removal mask GRM included in the first cell CELL1 is spaced apart from the gate removal mask GRM included in the second cell CELL2 by 1 CPP.

[0151] The first free active region ACT1 included in each of the first cell CELL1 and the second cell CELL2 is not connected to each other. The second free active region ACT2 included in each of the first cell CELL1 and the second cell CELL2 is not connected to each other.

[0152] Referring to Figure 30 , the first free active region ACT1 of the first cell CELL1 and the first free active region ACT1 of the second cell CELL2 can be connected to each other according to design. The second free active region ACT2 of the first cell CELL1 and the second free active region ACT2 of the second cell CELL2 can be connected to each other according to design.

[0153] Further, the gate remove mask GRM can be replaced with an active region remove mask ARM. Thus, SDB (single diffusion break) masks separated from each other can be changed to one DDB (double diffusion break) mask.

[0154] In the end of the detailed description, those skilled in the art will appreciate that many modifications and variations of the preferred embodiments can be effected without departing from the spirit and scope of the inventive concept. Thus, the disclosed preferred embodiments of the present application are intended to be illustrative only and not restrictive of the scope of the application.

[0155] This application claims priority to Korean Patent Application No. 10-2019-0111302, filed on September 9, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. An integrated circuit, comprising: The first active region extends in the first direction; The second active region extends in the first direction and is spaced apart from the first active region in a second direction different from the first direction; A first standard unit is disposed on the first active region and the second active region. The first standard unit includes a first p-type transistor on the first active region and a first n-type transistor on the second active region. A second standard unit is disposed on the first active region and the second active region. The second standard unit includes a second p-type transistor on the first active region and a second n-type transistor on the second active region. A filling unit is disposed between the first standard unit and the second standard unit, and includes a first insulating spacer and a second insulating spacer, each of the first insulating spacer and the second insulating spacer extending in the second direction; as well as A first filled semiconductor pattern and a second filled semiconductor pattern, wherein the first filled semiconductor pattern is disposed in the first active region between the first insulating isolator and the second insulating isolator, and the second filled semiconductor pattern is disposed in the second active region between the first insulating isolator and the second insulating isolator. in: The filling unit has a pitch dimension. The first insulating barrier and the second insulating barrier are spaced apart from each other by the specified pitch in the first direction. The first insulating spacer of the filling unit is disposed at the first boundary between the first standard unit and the filling unit. The second insulating spacer of the filling unit is disposed at the second boundary between the second standard unit and the filling unit, and The first insulating barrier and the second insulating barrier separate at least a portion of the first active region and at least a portion of the second active region.

2. The integrated circuit according to claim 1, The first standard unit is spaced apart from the second standard unit in the first direction, and Each of the first active region and the second active region is divided into three parts in the first direction.

3. The integrated circuit according to claim 2, further comprising: The first fill contact on the first filled semiconductor pattern and the second fill contact on the second filled semiconductor pattern. The first fill contact and the second fill contact are not connected to the wiring layer.

4. The integrated circuit according to claim 1, The first standard cell further includes a gate stack extending in the second direction and from the first active region to the second active region. The first active region includes nanosheets, and The gate stack is wrapped around the nanosheet.

5. The integrated circuit according to claim 1, further comprising: The upper unit separator membrane extending in the first direction; The lower unit separator membrane extending in the first direction; and An active region separation membrane extends in the first direction and is inserted between the first active region and the second active region. The active region separator, the first active region, and the second active region are disposed between the upper unit separator and the lower unit separator. The first insulating barrier and the second insulating barrier are disposed on the active partition membrane. The bottom surfaces of the first insulating separator and the second insulating separator are lower than the upper surface of the upper unit separator membrane, and The upper surface of the upper unit separator membrane is higher than the upper surface of the active region separator membrane.

6. The integrated circuit according to claim 5, The first standard cell includes a first gate stack extending from the first active region to the second active region in the second direction and a gate contact connected to the first gate stack. The gate contact is located at a position that overlaps with one of the first active region and the second active region.

7. The integrated circuit according to claim 6, further comprising: An upper cell gate dicing pattern extending in the first direction, the upper cell gate dicing pattern overlapping the upper cell separator film. The second standard cell further includes a second gate stack extending from the first active region to the second active region in the second direction, and The first insulating barrier, the second insulating barrier, the first gate stack, and the second gate stack are in contact with the upper unit gate dicing pattern.

8. The integrated circuit according to claim 7, further comprising: A lower cell gate dicing pattern extending in the first direction, the lower cell gate dicing pattern overlapping the lower cell separator film. The upper cell gate dicing pattern extends along the upper boundary of the first standard cell, the upper boundary of the filled cell, and the upper boundary of the second standard cell. The lower cell gate dicing pattern extends along the lower boundary of the first standard cell, the lower boundary of the filled cell, and the lower boundary of the second standard cell.

9. An integrated circuit, comprising: The first standard unit includes a first p-type transistor and a first n-type transistor; The second standard cell includes a second p-type transistor and a second n-type transistor and is spaced apart from the first standard cell in a first direction; A filling unit is disposed between the first standard unit and the second standard unit and includes a first insulating spacer and a second insulating spacer; as well as The third standard cell is spaced apart from the first standard cell and the filling cell in a second direction different from the first direction, and includes a third p-type transistor and a third n-type transistor. The filling unit has a pitch dimension. The first insulating spacer and the second insulating spacer are spaced apart from each other by a pitch dimension in the first direction, wherein the first insulating spacer of the filling unit is disposed at the boundary between the first standard unit and the filling unit. The second insulating spacer of the filling unit is disposed at the boundary between the second standard unit and the filling unit. The first p-type transistor and the second p-type transistor are formed on the first active region. The first n-type transistor and the second n-type transistor are formed on the second active region. The third standard unit includes a third insulating spacer disposed at the first boundary of the third standard unit. The first insulating barrier and the second insulating barrier separate at least a portion of the first active region. The first insulating barrier and the second insulating barrier separate at least a portion of the second active region, and The third insulating barrier is aligned with the second insulating barrier in the second direction.

10. The integrated circuit according to claim 9, The third insulating barrier of the third standard unit is disposed at the boundary between the second standard unit and the third standard unit.

11. The integrated circuit according to claim 10, The height of the second standard unit in the second direction is the sum of the height of the filling unit in the second direction and the height of the third standard unit in the second direction.

12. The integrated circuit according to claim 9, The third standard cell further includes a gate stack extending in the second direction, and The gate stack of the third standard cell is aligned with the first insulating barrier of the filled cell in the second direction.

13. The integrated circuit according to claim 12, further comprising: The cell gate dicing pattern extends in the first direction and is interposed between the first standard cell and the third standard cell, and between the fill cell and the third standard cell. The gate stack of the third standard cell and the first insulating barrier of the filled cell are in contact with the cell gate dicing pattern.

14. The integrated circuit according to claim 9, further comprising: The fourth standard cell, spaced apart from the first standard cell and the filling cell in the second direction, includes a fourth p-type transistor and a fourth n-type transistor. The filling unit is disposed between the third standard unit and the fourth standard unit.

15. The integrated circuit according to claim 14, The fourth standard cell includes a fourth insulating spacer on the boundary of the fourth standard cell and a gate stack spaced apart from the fourth insulating spacer by the dimension of one pitch. The fourth insulating barrier is aligned with the first insulating barrier in the second direction, and The gate stack of the fourth standard cell is aligned with the second insulating isolator in the second direction.

16. The integrated circuit according to claim 14, The fourth standard cell comprises a first gate stack and a second gate stack spaced apart from each other by the dimension of one pitch. The first gate stack of the fourth standard cell is aligned with the first insulating isolator of the filled cell in the second direction, and The second gate stack of the fourth standard cell is aligned with the second insulating spacer of the filled cell in the second direction.

17. An integrated circuit, comprising: The first standard unit includes a first p-type transistor and a first n-type transistor; The second standard cell includes a second p-type transistor and a second n-type transistor and is spaced apart from the first standard cell in a first direction; A filling unit is disposed between the first standard unit and the second standard unit and includes a first insulating spacer and a second insulating spacer; as well as The third standard cell is spaced apart from the first standard cell and the filling cell in a second direction different from the first direction, and includes a third p-type transistor and a third n-type transistor. The filling unit has a pitch dimension. The first insulating barrier and the second insulating barrier are spaced apart from each other by the specified pitch in the first direction. The first insulating spacer of the filling unit is disposed at the boundary between the first standard unit and the filling unit. The second insulating spacer of the filling unit is disposed at the boundary between the second standard unit and the filling unit. The third standard cell comprises a first gate stack and a second gate stack spaced apart from each other by the dimension of the one pitch. The first gate stack is aligned with the first insulating spacer of the filled cell in the second direction, and The second gate stack is aligned with the second insulating spacer of the filling cell in the second direction.

18. The integrated circuit according to claim 17, further comprising: The fourth standard cell, spaced apart from the first standard cell and the filling cell in the second direction, includes a fourth p-type transistor and a fourth n-type transistor. The filling unit is disposed between the third standard unit and the fourth standard unit.

19. The integrated circuit according to claim 18, The fourth standard cell includes a third insulating spacer on the boundary of the fourth standard cell and a third gate stack spaced apart from the third insulating spacer by the dimension of the one pitch. The third insulating spacer of the fourth standard unit is aligned with the first insulating spacer of the filling unit in the second direction, and The third gate stack of the fourth standard cell is aligned with the second insulating barrier of the filling cell in the second direction.

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