Drive circuit and semiconductor device

Abstract

The present application provides a drive circuit and a semiconductor device. Even if the potential applied to a low potential terminal varies, the drive circuit can be protected. A drive circuit is provided, which controls an output section that switches whether to supply a current to an output line in accordance with a potential difference between a first control signal input and a voltage of the output line, wherein the drive circuit includes: a control line that transmits the first control signal to the output section; a low potential line to which a predetermined reference potential is applied; a first connection switching section that switches whether to connect the control line and the low potential line in accordance with a second control signal; and a cutoff section that is provided in series with the first connection switching section between the control line and the low potential line, and cuts off the control line and the low potential line based on a potential of the low potential line.

Description

Technical Field

[0001] This invention relates to drive circuits and semiconductor devices. Background Technology

[0002] Previously, drive circuits for driving power semiconductors such as MOSFETs or IGBTs (Insulated Gate Bipolar Transistors) were known (see, for example, Patent Documents 1 and 2). The drive circuit has a low-potential terminal connected to a low potential such as ground.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2009-10477

[0004] Patent Document 2: Japanese Patent Application Publication No. 8-83909 Summary of the Invention

[0005] The technical problem that the invention aims to solve

[0006] It is expected that the drive circuit can be protected even if the potential applied to the low-potential terminal changes.

[0007] Technical solutions to solve technical problems

[0008] To address the aforementioned problems, a first aspect of the present invention provides a driving circuit that controls an output unit to switch whether to supply current to the output line based on the potential difference between an input first control signal and the voltage of the output line. The driving circuit may include a control line that transmits the first control signal to the output unit. The driving circuit may include a low-potential line to which a predetermined reference potential is applied. The driving circuit may include a first connection switching unit that switches whether to connect the control line and the low-potential line based on a second control signal. The driving circuit may include a cutting-off unit connected in series with the first connection switching unit between the control line and the low-potential line, cutting off the control line and the low-potential line based on the potential of the low-potential line.

[0009] The cutting section can cut off the control line and the low-potential line regardless of the value of the second control signal when the potential of the low-potential line is higher than the first threshold potential.

[0010] The driving circuit may include a high-potential line to which a high potential higher than a first threshold potential is applied. The driving circuit may include a pre-stage control unit disposed between the high-potential line and the low-potential line, which inputs the potential of one of the high-potential line and the low-potential line as a second control signal to a first connection switching unit. The first connection switching unit may have a MOSFET that is turned on when the potential input from the pre-stage control unit is higher than the second threshold potential.

[0011] The front-end control unit may include a first inverter, which is positioned between a high-potential line and a low-potential line. This first inverter selects the potential of either the high-potential line or the low-potential line based on the input signal and outputs the desired potential. The front-end control unit may also include a second inverter, which is positioned between the high-potential line and the low-potential line. This second inverter selects the potential of either the high-potential line or the low-potential line based on the output of the first inverter and inputs this potential as a second control signal to the MOSFET of the first connection switching unit. The cut-off unit may cut off the control line and the low-potential line if the output of the first inverter is higher than a first threshold potential.

[0012] The front-end control unit may include a first inverter, which is positioned between a high-potential line and a low-potential line. This first inverter selects and outputs the potential of either the high-potential line or the low-potential line based on an input signal. The front-end control unit may also include a second inverter, which is positioned between the high-potential line and the low-potential line. This second inverter selects the potential of either the high-potential line or the low-potential line based on the output of the first inverter, and inputs the potential of either the high-potential line or the low-potential line as a second control signal to the MOSFET of the first connection switching unit. The front-end control unit may also include a third inverter, which is positioned between the high-potential line and the low-potential line. This third inverter selects the potential of either the high-potential line or the low-potential line based on the output of the second inverter, and inputs the potential of either the high-potential line or the low-potential line to a cutoff unit. The cutoff unit may cut off the control line and the low-potential line if the output of the third inverter is higher than a first threshold potential.

[0013] The front-end control unit may include a first inverter, which is positioned between a high-potential line and a low-potential line. This first inverter selects and outputs the potential of either the high-potential line or the low-potential line based on an input signal. The front-end control unit may also include a second inverter, which is positioned between the high-potential line and the low-potential line. This second inverter selects the potential of either the high-potential line or the low-potential line based on the output of the first inverter and inputs this potential as a second control signal to the MOSFET of the first connection switching unit. The front-end control unit may also include a third inverter, which is positioned between the high-potential line and the low-potential line. This third inverter selects the potential of either the high-potential line or the low-potential line based on the input to the first inverter and inputs this potential to a cutoff unit. The cutoff unit may cut off the control line and the low-potential line if the output of the third inverter is higher than a first threshold potential.

[0014] The drive circuit may include a second connection switching unit that switches between connecting the control line and the output line. The drive circuit may include a subsequent control unit that, when the preceding control unit outputs a voltage higher than a predetermined third threshold potential, causes the second connection switching unit to connect the control line and the output line.

[0015] The post-stage control unit can be located between the high-potential line and the output line. Based on the voltage output by the pre-stage control unit, it selects the potential of one of the high-potential lines and the output line, and inputs the potential of that one of the high-potential lines and the output line to the second connection switching unit.

[0016] The front-end control unit may include a first inverter, which is positioned between the high-potential line and the low-potential line. This first inverter selects the potential of one of the high-potential line and the low-potential line based on the input signal and outputs that potential. The front-end control unit may also include a second inverter, which is positioned between the high-potential line and the low-potential line. This second inverter selects the potential of one of the high-potential line and the low-potential line based on the output of the first inverter and inputs that potential as a second control signal to the MOSFET of the first connection switching unit. The front-end control unit may also include a third inverter, which is positioned between the high-potential line and the low-potential line. This third inverter selects the potential of one of the high-potential line and the low-potential line based on the output of the second inverter and inputs that potential to the cutoff unit. The front-end control unit may include a fourth inverter positioned between the high-potential line and the low-potential line. This fourth inverter selects the potential of either the high-potential line or the low-potential line based on the output of the first inverter and inputs this potential to the subsequent control unit. The cut-off unit can disconnect the control line and the low-potential line if the output of the third inverter is higher than the first threshold potential.

[0017] The front-end control unit may include a first inverter positioned between a high-potential line and a low-potential line. This first inverter selects and outputs the potential of either the high-potential line or the low-potential line based on the input signal. The front-end control unit may also include a second inverter positioned between the high-potential line and the low-potential line. This second inverter selects the potential of either the high-potential line or the low-potential line based on the output of the first inverter and inputs the potential of either the high-potential line or the low-potential line to the MOSFET of the first connection switching unit and the subsequent control unit. The front-end control unit may also include a third inverter positioned between the high-potential line and the low-potential line. This third inverter selects the potential of either the high-potential line or the low-potential line based on the output of the second inverter and inputs the potential of either the high-potential line or the low-potential line to the cutoff unit. The cutoff unit may cut off the control line and the low-potential line if the output of the third inverter is higher than a first threshold potential.

[0018] The first connection switching section may have an n-channel MOSFET disposed between the control line and the low-potential line. The disconnection section may have a p-channel MOSFET disposed between the n-channel MOSFET and the low-potential line.

[0019] In a second aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising: an output line; an output section that switches whether to supply current to the output line based on a potential difference between an input first control signal and the voltage of the output line; and a driving circuit as described in the first aspect.

[0020] Furthermore, the above summary of the invention does not list all the essential features of the invention. Additionally, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0021] Figure 1 This is a diagram illustrating an example of a semiconductor device 100 according to one embodiment of the present invention.

[0022] Figure 2 This is a diagram showing an example of logic circuit 50, drive circuit 10, and output section 12.

[0023] Figure 3 This is a diagram illustrating a structural example of a drive circuit 10 according to one embodiment of the present invention.

[0024] Figure 4 This is a diagram showing other structural examples of the front-end control unit 20.

[0025] Figure 5 This is a diagram showing other structural examples of the front-end control unit 20.

[0026] Figure 6 This is a diagram showing other structural examples of the front-stage control unit 20 and the rear-stage control unit 24.

[0027] Figure 7 This describes an example of operation when a low potential GND is applied to the low potential line 38 and the control unit 54 outputs the logic value H.

[0028] Figure 8 This describes an example of operation when a low potential GND is applied to the low potential line 38 and the control unit 54 outputs an L logic value.

[0029] Figure 9 This describes an example of operation where an open-circuit potential Vop, equivalent to the H logic value, is applied to the low-potential line 38, and the control unit 54 outputs the H logic value.

[0030] Figure 10This describes an example of operation where an open-circuit potential Vop, equivalent to the H logic value, is applied to the low-potential line 38, and the control unit 54 outputs the L logic value.

[0031] Figure 11 This is a diagram showing other structural examples of the front-end control unit 20.

[0032] Figure 12 This is a cross-sectional view showing an example of the MOSFETs in the output section 12, the first connection switching section 27, and the cut-off section 29.

[0033] Figure 13 This is a cross-sectional view showing another example of the MOSFETs in the output section 12, the first connection switching section 27, and the cut-off section 29. Detailed Implementation

[0034] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the solution of the invention.

[0035] Figure 1 This diagram illustrates an example of a semiconductor device 100 according to one embodiment of the present invention. The semiconductor device 100 in this example is a semiconductor chip having an input terminal 101, an output terminal 102, a high-potential terminal 103, and a low-potential terminal 104. The semiconductor device 100 may also include a status terminal 105.

[0036] The semiconductor device 100 operates according to the input signal IN input to the input terminal 101, supplying power to the load 200 connected to the output terminal 102. In this example, the input signal IN can be a signal that uses a 2-valued logic value to represent whether power is supplied to the load 200 or not.

[0037] A specified high voltage VCC is applied to the high-potential terminal 103. In this example, the high-potential terminal 103 is connected to a power supply 110 that generates the high-potential VCC. A low potential lower than the high voltage VCC is applied to the low-potential terminal 104. In this example, the low potential is the ground potential GND.

[0038] Semiconductor device 100 outputs a status signal STo from status terminal 105, indicating the internal state of semiconductor device 100. Status signal STo can be a signal indicating, for example, the detection of an abnormality such as overcurrent. Status terminal 105 can be connected to a pull-up power supply 130 via an external resistor 140. Status signal STo is input to an external processing device. Based on status signal STo, the processing device can control semiconductor device 100, or other semiconductor devices 100. For example, the processing device is connected to multiple semiconductor devices 100, and if an abnormality is detected in any of the semiconductor devices 100, it stops the power supply from all of the semiconductor devices 100.

[0039] Semiconductor device 100 includes a drive circuit 10 and an output section 12. The output section 12 is connected to a load 200 via an output terminal 102, supplying power to the load 200. The output section 12 can be a switching element such as an IGBT or a power MOSFET. The output section 12 has a control terminal G (e.g., a gate terminal), a source terminal S, and a drain terminal D. In this example, the drain terminal D is connected to a high-potential terminal 103, and the source terminal S is connected to the output terminal 102. The output section 12 switches whether to apply a high-potential VCC to the load 200 based on the potential difference between a first control signal C1 input to the control terminal G and the source terminal S.

[0040] The drive circuit 10 inputs a first control signal C1 corresponding to the input signal IN input to the input terminal 101 to the control terminal G of the output unit 12. A signal with a potential based on a low potential GND is input to the drive circuit 10. The drive circuit 10 functions as a level conversion circuit that converts the signal based on the low potential GND to the first control signal C1 based on the output potential OUT of the output unit 12. The output potential OUT can be the potential of the source terminal S of the output unit 12.

[0041] The semiconductor device 100 in this example has a logic circuit 50. The logic circuit 50 inputs a control signal having a logic value pattern corresponding to the input signal IN to the drive circuit 10. The control signal output by the logic circuit 50 is a potential corresponding to the low potential GND in the case of an L logic value, and a potential corresponding to the high potential VCC in the case of an H logic value. The potential corresponding to the low potential GND can be a potential substantially equal to the low potential GND. The potential corresponding to the high potential VCC can be a potential substantially equal to the high potential VCC.

[0042] In this example, the logic circuit 50 controls the drive circuit 10 based on the internal state of the semiconductor device 100. The internal state of the semiconductor device 100 can be represented by at least one of the following parameters: voltage value, current value, and resistance value of a specified node, and temperature of a specified location. In this example, the semiconductor device 100 includes at least one of the following: a low voltage detection unit 72, a load open circuit detection unit 56, an overcurrent detection unit 58, and an overheat detection unit 60, which respectively monitor the internal state of the semiconductor device 100.

[0043] The low voltage detection unit 72 detects the voltage value of the high potential VCC at the high potential terminal 103. If the voltage value of the high potential VCC is lower than a specified reference value, the low voltage detection unit 72 notifies the logic circuit 50 that an abnormal state has occurred.

[0044] The load open-circuit detection unit 56 detects whether a load 200 is connected to the output terminal 102. The load open-circuit detection unit 56 can detect whether the output terminal 102 is in an open-circuit state based on the output resistance when a specified voltage or current is output from the output terminal 102. If the load open-circuit detection unit 56 detects that no load 200 is connected, it notifies the logic circuit 50 that it is in an abnormal state to prevent the output unit 12 from becoming conductive when no load 200 is connected to the output terminal 102.

[0045] The overcurrent detector 58 detects the current output from the output unit 12. If the output current value exceeds a specified reference value, the overcurrent detection unit 58 notifies the logic circuit 50 that an abnormal state has occurred.

[0046] The overheat detection unit 60 detects the temperature of one or more parts of the semiconductor device 100. If the temperature of any part exceeds a predetermined reference value, the overheat detection unit 60 notifies the logic circuit 50 that an abnormal state has occurred.

[0047] When the logic circuit 50 receives notification from the arbitrary detection unit that an abnormal state is in effect, it controls the output unit 12 to be in an off state, regardless of the logic value of the input signal IN. By setting the output unit 12 to an off state according to the internal state of the semiconductor device 100, the semiconductor device 100 can be protected.

[0048] The semiconductor device 100 in this example has a status signal output unit 62. When the logic circuit 50 is notified by an arbitrary detection unit that an abnormal state is in effect, the status signal output unit 62 outputs a predetermined logic value. In this example, the status signal output unit 62 is a MOSFET connected between the status terminal 105 and the low-potential terminal 104. When the logic circuit 50 is notified that an abnormal state is in effect, it inputs a predetermined signal to the gate terminal of the MOSFET, setting the MOSFET to an off state. In this case, the status signal STo output from the status terminal 105 becomes the voltage corresponding to the pull-up power supply 130. When the logic circuit 50 is not notified that an abnormal state is in effect, it sets the MOSFET to an on state. In this case, the status signal STo output from the status terminal 105 becomes the voltage corresponding to the low-potential GND. Thus, the internal state of the semiconductor device 100 can be notified to an external processing device. The logic circuit 50 can also control the on and off states of the MOSFET in a manner opposite to the example described above.

[0049] Semiconductor device 100 may include at least one of diode 64, diode 66, and diode 68. The anode terminal of diode 64 is connected to low potential terminal 104, and the cathode terminal is connected to status terminal 105. When a voltage above a specified value is input to status terminal 105, diode 64 connects status terminal 105 to low potential terminal 104, thereby protecting semiconductor device 100.

[0050] The anode terminal of diode 66 is connected to the low-potential terminal 104, and the cathode terminal is connected to the high-potential terminal 103. When a voltage above a specified value is applied to the high-potential terminal 103, diode 64 connects the high-potential terminal 103 to the low-potential terminal 104, thereby protecting the semiconductor device 100.

[0051] The anode terminal of diode 68 is connected to the low-potential terminal 104, and the cathode terminal is connected to the input terminal 101. When a voltage above a specified value is applied to the input terminal 101, diode 64 connects the input terminal 101 to the low-potential terminal 104, thereby protecting the semiconductor device 100.

[0052] The semiconductor device 100 may include an internal power supply 70. The internal power supply 70 is connected to a high-potential terminal 103. The internal power supply 70 can generate power supply voltages to various circuits of the semiconductor device 100 based on the high potential VCC. For example, the internal power supply 70 provides power supply voltages to various detection units.

[0053] Figure 2This diagram illustrates an example of the logic circuit 50, the drive circuit 10, and the output unit 12. The semiconductor device 100 in this example has a high-potential line 30 connected to a high-potential terminal 103, a low-potential line 38 connected to a low-potential terminal 104, and an output line 36 connected to an output terminal 102. In this example, the drain terminal D of the output unit 12 is connected to the high-potential line 30, and the source terminal S is connected to the output line 36. The output unit 12 switches whether to supply current to the output line 36 based on the potential difference between the first control signal C1 input to the control terminal G and the voltage on the output line 36.

[0054] The logic circuit 50 in this example has an output control unit 52 and an output control unit 54. An input signal IN, indicating the timing of switching the output unit 12 to on or off, is input to the output control unit 52. In this example, the output control unit 52 outputs a first control signal C1, which represents an H logic value when the output unit 12 is on and an L logic value when the output unit 12 is off. The first control signal C1 has a potential that enables the output unit 12 to perform a switching operation. For example, the first control signal C1 represents a potential corresponding to a high potential VCC when the output unit 12 is H logic, and a potential corresponding to an output potential OUT when the output unit 12 is L logic. The output control unit 52 may have a charge pump that generates the first control signal C1. The output terminal of the output control unit 52 and the control terminal G of the output unit 12 are connected via a control line 32. The control line 32 transmits the first control signal C1 to the control terminal G of the output unit 12.

[0055] The extraction control unit 54 receives a status signal ST from the status signal generation unit (not shown) of the logic circuit 50. The status signal generation unit (not shown) of the logic circuit 50 generates a status signal ST. Figure 1 The detection unit shown here notifies the user of a status signal ST indicating an abnormal state. The logical value of the status signal ST can be ANDed with... Figure 1 The logic value of the state signal STo described in the text is the same.

[0056] When an abnormal state is detected, the extraction control unit 54 connects the control line 32 to the low-potential line 38, extracting the charge from the control terminal G of the output unit 12 to the low-potential line 38, thus controlling the output unit 12 to be in an off state regardless of the logic value of the first control signal C1. This protects the semiconductor device 100 and its peripheral circuits. When no abnormal state is detected, the extraction control unit 54 disconnects the control line 32 and the low-potential line 38.

[0057] In this example, the extraction control unit 54 outputs a control signal C0. This control signal C0 represents a first logic value when the control line 32 and the low-potential line 38 are connected, and a second logic value when the control line 32 and the low-potential line 38 are disconnected. The control signal C0 represents the potential corresponding to the high potential VCC when it has one logic value, and the potential corresponding to the low potential GND when it has the other logic value.

[0058] The drive circuit 10 includes a first connection switching unit 27. The first connection switching unit 27 switches between connecting the control line 32 and the low-potential line 38 based on an input second control signal C2. In this example, the first connection switching unit 27 is a MOSFET with its drain terminal D connected to the control line 32, its source terminal S connected to the low-potential line 38, and its gate terminal G receiving the second control signal C2. In this example, the MOSFET of the first connection switching unit 27 is in an on-state when the potential input from the preceding control unit 20 is higher than a predetermined second threshold potential.

[0059] The drive circuit 10 may include a front-end control unit 20 that generates a second control signal C2 based on a control signal C0. The front-end control unit 20 selects either the potential of the high-potential line 30 or the potential of the low-potential line 38 according to the logic value of the control signal C0, and outputs this as the second control signal C2. In this example, the front-end control unit 20 includes a first inverter 22-1 that inputs the control signal C0, and a second inverter 22-2 that inputs the output of the first inverter 22-1 and outputs the second control signal C2. Both the first inverter 22-1 and the second inverter 22-2 select the potential of the low-potential line 38 when the input signal is a logic value of H, and select the potential of the high-potential line 30 when the input signal is a logic value of L for output.

[0060] The first inverter 22-1 is positioned between the high-potential line 30 and the low-potential line 38, and selects the potential of one of the high-potential lines 30 and 38 for output based on the control signal C0. The second inverter 22-2 is positioned between the high-potential line 30 and the low-potential line 38, and selects the potential of one of the high-potential lines 30 and 38 based on the output of the first inverter 22-1, and inputs the potential of the high-potential line 30 and the low-potential line 38 as the second control signal C2 to the MOSFET of the first connection switching unit 27.

[0061] In the event of an abnormal condition, the control line 32 and the low-potential line 38 are connected according to the control signal C0, thereby controlling the output unit 12 to be in an off state regardless of the value of the first control signal C1. This protects the semiconductor device 100 and its peripheral circuits. In the event of no abnormal condition, the control line 32 and the low-potential line 38 are disconnected according to the control signal C0, thereby causing the output unit 12 to operate according to the first control signal C1.

[0062] The drive circuit 10 may also include a downstream control unit 24 and a second connection switching unit 28. The second connection switching unit 28 switches whether to connect the control line 32 and the output line 36 according to the input fourth control signal C4. In this example, the second connection switching unit 28 is a MOSFET with its drain terminal D connected to the control line 32, its source terminal S connected to the output line 36, and its gate terminal G receiving the fourth control signal C4.

[0063] The downstream control unit 24 generates the fourth control signal C4 based on the control signal C0' output by the upstream control unit 20. In this example, the control signal C0' is the signal output by the first inverter 22-1. The downstream control unit 24 selects the potential of either the high-potential line 30 or the output line 36 according to the voltage output by the upstream control unit 20, and inputs it to the second connection switching unit 28. The downstream control unit 24 may include a downstream inverter 26 that inputs the control signal C0' and outputs the fourth control signal C4. The downstream inverter 26 selects the potential of the output line 36 when the input signal is an H logic value, and selects the potential of the high-potential line 30 for output when the input signal is an L logic value.

[0064] In the event of an abnormal condition, the second connection switching unit 28 is turned on according to the control signal C0, connecting the control line 32 and the output line 36. This allows the output unit 12 to be turned off regardless of the value of the first control signal C1. This protects the semiconductor device 100 and its peripheral circuits. In the event of no abnormal condition, the control line 32 and the output line 36 are cut off according to the control signal C0, allowing the output unit 12 to operate according to the first control signal C1.

[0065] Due to reasons such as the low-potential terminal 104 being in an open-circuit state, the potential of the low-potential GND may sometimes rise. When the low-potential terminal 104 is in an open-circuit state with the ground potential, the potential of the low-potential terminal 104 may sometimes be pulled up by the internal circuitry of the semiconductor device 100. When the potential of the low-potential GND rises, sometimes both the high-potential VCC and the low-potential GND applied to the front-end control unit 20 become potentials equivalent to the H logic value.

[0066] In this situation, the signals output by each inverter 22 of the front-end control unit 20 become H logic values, independent of the logic value of the control signal C0 input from the extraction control unit 54. Therefore, the first connection switching unit 27 is always in the ON state. Consequently, the potential of the control line 32 is essentially the same as that of the low-potential line 38. The potential of the low-potential line 38 is equivalent to an H logic value, therefore, regardless of the logic value of the first control signal C1, the output unit 12 is always in the ON state. Therefore, when the potential of the low-potential line 38 rises, the semiconductor device 100 may sometimes fail to be properly protected.

[0067] Figure 3 This is a diagram illustrating a structural example of a drive circuit 10 according to one embodiment of the present invention. Figure 3 The logic circuit 50 and the output section 12 are in Figure 2 The logic circuit 50 shown is the same as the output section 12.

[0068] In this example, the drive circuit 10 is... Figure 2 The drive circuit 10 shown also includes a cutoff section 29. The cutoff section 29 is connected in series with the first connection switching section 27 between the control line 32 and the low-potential line 38, and cuts off the control line 32 and the low-potential line 38 based on the potential of the low-potential line 38. In this example, the cutoff section 29 is a MOSFET whose source terminal S is connected to the drain terminal D of the first connection switching section 27, the drain terminal D is connected to the low-potential line 38, and the gate terminal G receives the third control signal C3. The back gate of the cutoff section 29 can be connected to the high-potential line 30. The third control signal C3 is a signal that, when the potential of the low-potential line 38 is higher than the first threshold potential, the control line 32 and the low-potential line 38 are cut off regardless of the value of the second control signal C2. The first threshold potential can be the threshold potential of the MOSFET in the cutoff section 29. Furthermore, the high potential VCC applied to the high-potential line 30 is higher than the first threshold potential. Additionally, the reference potential GND applied to the low-potential line 38 under normal conditions is lower than the first threshold potential.

[0069] According to this example, when the potential of the low-potential line 38 rises, the control line 32 and the low-potential line 38 can be disconnected regardless of the state of the first connection switching unit 27. Therefore, when the potential of the low-potential line 38 rises, it is possible to prevent the potential of the control line 32 from always being equivalent to the H logic value. When the potential of the low-potential line 38 is lower than the first threshold potential, the control line 32 and the low-potential line 38 can be connected or disconnected according to the control signal C0, and the semiconductor device 100 can be protected according to the control signal C0.

[0070] In this example, the front-end control unit 20 is... Figure 2Based on the structure of the front-end control unit 20 shown, a third inverter 22-3 is also included. The third inverter 22-3 receives the output of the second inverter 22-2 (i.e., the second control signal C2) as input and outputs the third control signal C3 to the cut-off unit 29. The third inverter 22-3 is positioned between the high-potential line 30 and the low-potential line 38, selects the potential of one of the high-potential lines 30 and 38 based on the output of the second inverter 22-2, and inputs the potential of that one of the high-potential lines 30 and 38 to the cut-off unit 29.

[0071] In this example, the third inverter 22-3 selects the low potential line 38 when the input signal is an H logic value, and selects the high potential line 30 for output when the input signal is an L logic value. The cut-off unit 29 cuts off the control line 32 and the low potential line 38 when the output of the third inverter 22-3 is higher than the first threshold potential. Therefore, the third inverter 22-3 sets the cut-off unit 29 to the off state when the low potential line 38 is equivalent to an H logic value, and when the low potential line 38 is equivalent to an L logic value, the on / off state of the cut-off unit 29 can be matched with the on / off state of the first connection switching unit 27.

[0072] In addition, Figure 3 In the example, the first connection switching section 27 has an n-channel MOSFET, and the cut-off section 29 has a p-channel MOSFET. However, the conductivity type of the channel of each MOSFET is not limited thereto.

[0073] Figure 4 This diagram illustrates other structural examples of the pre-stage control unit 20. In this example, the pre-stage control unit 20 is similar to... Figure 3 The difference in this example is that the control signal C0 input to the first inverter 22-1 is also input to the third inverter 22-3. Other structures are similar. Figure 3 The front-end control unit 20 is the same as that in the middle.

[0074] The third inverter 22-3 selects the potential of one of the high-potential line 30 and the low-potential line 38 according to the control signal C0, and inputs the potential of the high-potential line 30 and the low-potential line 38 to the cut-off section 29. With this structure, the cut-off section 29 can be cut off even when the potential of the low-potential line 38 is higher than the first threshold potential. Furthermore, when the potential of the low-potential line 38 is lower than the first threshold potential, the on / off state of the cut-off section 29 can be matched with the on / off state of the first connection switching section 27.

[0075] Figure 5This diagram illustrates other structural examples of the front-end control unit 20. In this example, the front-end control unit 20 does not have a third inverter 22-3. The output of the first inverter 22-1 is input to the cut-off unit 29 in this example. Other structures are similar to... Figure 3 The front-end control unit 20 shown is the same.

[0076] When the output of the first inverter 22-1 is higher than the first threshold potential, the cut-off section 29 cuts off the control line 32 and the low-potential line 38. With this structure, the cut-off section 29 can also be cut off when the potential of the low-potential line 38 is higher than the first threshold potential. Furthermore, when the potential of the low-potential line 38 is lower than the first threshold potential, the on / off state of the cut-off section 29 can be matched with the on / off state of the first connection switching section 27.

[0077] Figure 6 This diagram illustrates other structural examples of the front-end control unit 20 and the back-end control unit 24. In this example, when the front-end control unit 20 outputs a voltage higher than a predetermined third threshold potential, the back-end control unit 24 connects the control line 32 and the output line 36 via the second connection switching unit 28. In this example, the third threshold potential is the threshold potential of the back-end inverter 26 set in the back-end control unit 24. Furthermore, when the front-end control unit 20 outputs a voltage lower than the third threshold potential, the back-end control unit 24 disconnects the control line 32 and the output line 36 via the second connection switching unit 28.

[0078] In this example, the downstream control unit 24 has an even number of downstream inverters 26 connected in series. Figure 6 In this example, two downstream inverters 26 are connected in series. Each downstream inverter 26 is configured between the high-potential line 30 and the output line 36. The downstream inverter 26 selects the potential of the high-potential line 30 and outputs when the input voltage is higher than the third threshold potential, and selects the potential of the output line 36 and outputs when the input voltage is lower than the third threshold potential.

[0079] exist Figure 2 In the example, when the output voltage of the pre-stage control unit 20 is lower than the third threshold potential, the subsequent control unit 24 controls the second connection switching unit 28 to be in the conducting state, connecting the control line 32 and the output line 36. However, as described above, when the potential of the low-potential line 38 rises, regardless of the value of the control signal C0, the control signal C0' input to the subsequent control unit 24 becomes an H logic value. In this case, Figure 2 In the example, the second connection switching unit 28 is always in the disconnected state, which sometimes fails to properly protect the semiconductor device 100.

[0080] In contrast, in this example, the subsequent control unit 24 controls the second connection switching unit 28 to be in the conducting state when an H logic value is input. Therefore, when the potential of the low potential line 38 rises to a potential equivalent to the H logic value, the second connection switching unit 28 is controlled to be in the conducting state. Thus, in addition to detecting abnormal conditions, the drive circuit 10 can also control the output unit 12 to be in the off state when the potential of the low potential line 38 rises. This provides appropriate protection for the semiconductor device 100.

[0081] Furthermore, in the circuit disclosed in Patent Document 1, a potential difference generating circuit is provided between the output terminal and the ground terminal. However, when the load and inductive component are connected, and the load potential swings negatively, current flows from the ground terminal to the output terminal side, causing a change in the ground potential of the surrounding circuit. In addition, in the circuit disclosed in Patent Document 2, multiple ground terminals are provided, thus increasing the number of terminals on the chip. According to the drive circuit 10 of this example, the semiconductor device 100 can be protected using a simple structure.

[0082] In this example, the front-end control unit 20 is... Figures 3 to 5 Based on the structure shown, it also includes a fourth inverter 22-4. The structure other than the fourth inverter 22-4 is similar to... Figures 3 to 5 The front-end control unit 20 is the same as that described in any manner. Figure 6 The middle shows the Figure 3 The structure shown is that of the front-end control unit 20 with the fourth inverter 22-4 attached.

[0083] The fourth inverter 22-4 is positioned between the high-potential line 30 and the low-potential line 38. Based on the output of the first inverter 22-1, it selects the potential of either the high-potential line 30 or the low-potential line 38 and inputs this potential to the subsequent control unit 24. When the first inverter 22-1 outputs an H logic value, the fourth inverter 22-4 selects and outputs the potential of the low-potential line 38; when the first inverter 22-1 outputs an L logic value, it selects and outputs the potential of the high-potential line 30.

[0084] In this example, the extraction control unit 54 outputs a control signal C0 with an H logic value when an abnormal state is detected and the output unit 12 needs to be controlled to the off state, and outputs a control signal C0 with an L logic value when the output unit 12 needs to be controlled according to the first control signal C1. In this case, the front-end control unit 20 may have an even number of inverters 22 connected in series between the extraction control unit 54 and the back-end control unit 24. Furthermore, the back-end control unit 24 may have an even number of back-end inverters 26 connected in series between the front-end control unit 20 and the second connection switching unit 28.

[0085] Using this structure, the downstream control unit 24 can operate as a level shifting circuit based on the output potential OUT, and when the upstream control unit 20 outputs an H logic value, it controls the second connection switching unit 28 to be in the on state. Therefore, even when the low potential GND rises, the semiconductor device 100 and the like can be protected. In addition, when the second connection switching unit 28 is a PMOSFET, the downstream control unit 24 can also have one stage or an odd number of stages of downstream inverter 26.

[0086] Furthermore, when the front-end control unit 20 needs to control the second connection switching unit 28 to the on state, it can output an H logic value. When the low potential GND rises, the output of the front-end control unit 20 is fixed at the H logic value regardless of the logic value of the control signal C0. Therefore, in two situations—when an abnormal state such as overcurrent is detected in the semiconductor device 100, and when the low potential GND rises—the second connection switching unit 28 can be controlled to the on state, and the output unit 12 can be controlled to the off state. Thus, the semiconductor device 100, etc., can be protected.

[0087] Furthermore, the extraction control unit 54 can also output a control signal C0 with an L logic value when an abnormal state is detected and the output unit 12 needs to be controlled to the off state, and output a control signal C0 with an H logic value when the output unit 12 needs to be controlled according to the first control signal C1. In this case, it is preferable that the front-end control unit 20 does not have a fourth inverter 22-4.

[0088] Figures 7 to 10 This is an explanation Figure 6 The diagram shows an example of the operation of the pre-stage control unit 20 and the post-stage control unit 24. Figures 7 to 10 In this diagram, the frame lines and labels of the front-end control unit 20 and the back-end control unit 24 are omitted; only the inverters are shown. Furthermore, in... Figures 7 to 10 In the example, the extraction control unit 54 outputs the control signal C0 of the H logic value when it detects an abnormal state and wants to control the output unit 12 to the off state.

[0089] Figure 7 This describes an operation example where a low potential GND is applied to the low potential line 38 and the control unit 54 outputs an H logic value. In this case, the first inverter 22-1 selects the low potential GND (equivalent to an L logic value) of the low potential line 38 based on the input H logic value and outputs it. The second inverter 22-2 selects the high potential VCC (equivalent to an H logic value) of the high potential line 30 based on the input L logic value and outputs it. As a result, the first connection switching unit 27 is controlled to be in the on state.

[0090] The third inverter 22-3 selects the low potential GND of the low potential line 38 and outputs it according to the input H logic value. As a result, the cut-off section 29 is controlled to be in the on state. That is, the control line 32 and the low potential line 38 are connected, and the charge on the gate terminal G of the output section 12 is extracted.

[0091] The fourth inverter 22-4 selects the high potential VCC (equivalent to the H logic value) of the high potential line 30 based on the input L logic value and outputs it. The subsequent inverter 26-1 selects the output potential OUT (equivalent to the L logic value) of the output line 36 based on the input H logic value and outputs it. The subsequent inverter 26-2 selects the high potential VCC (equivalent to the H logic value) of the high potential line 30 based on the input L logic value and outputs it. As a result, the second connection switching unit 28 is controlled to be in the conducting state. That is, the control line 32 and the output line 36 are connected, and the charge at the gate terminal G of the output unit 12 is also extracted by the output line 36. As a result, the output unit 12 is forced to be in the disconnected state.

[0092] Figure 8 This describes an operation example where a low potential GND is applied to the low potential line 38 and the control unit 54 outputs an L logic value. In this case, the first inverter 22-1 selects the high potential VCC (equivalent to the H logic value) of the high potential line 30 based on the input L logic value and outputs it. The second inverter 22-2 selects the low potential GND (equivalent to the L logic value) of the low potential line 38 based on the input H logic value and outputs it. As a result, the first connection switching unit 27 is controlled to be in the off state.

[0093] The third inverter 22-3 selects the high potential VCC of the high potential line 30 and outputs it according to the input L logic value. As a result, the cut-off section 29 is controlled to be in the off state. That is, the control line 32 and the low potential line 38 are cut off.

[0094] The fourth inverter 22-4 selects the low potential GND (equivalent to the L logic value) of the low potential line 38 according to the input H logic value and outputs it. The subsequent inverter 26-1 selects the high potential VCC (equivalent to the H logic value) of the high potential line 30 according to the input L logic value and outputs it. The subsequent inverter 26-2 selects the output potential OUT (equivalent to the L logic value) of the output line 36 according to the input H logic value and outputs it. As a result, the second connection switching unit 28 is disconnected. That is, the control line 32 and the output line 36 are cut off. The output unit 12 operates according to the first control signal C1.

[0095] Figure 9This describes an operation example where an open-circuit potential Vop, equivalent to the H logic value, is applied to the low-potential line 38, and the control unit 54 outputs the H logic value. In this case, the outputs of the respective inverters 22 of the front-end control unit 20 are fixed at the open-circuit potential Vop of the low-potential line 38. Therefore, the first connection switching unit 27 is controlled to be in the on state, and the disconnection unit 29 is controlled to be in the off state. Thus, the control line 32 and the low-potential line 38 can be disconnected, and the rise of the potential of the control line 32 based on the open-circuit potential Vop of the low-potential line 38 can be suppressed.

[0096] The downstream inverter 26-1 selects the output potential OUT (equivalent to the L logic value) of the output line 36 based on the input H logic value and outputs the output. The downstream inverter 26-2 selects the high potential VCC (equivalent to the H logic value) of the high potential line 30 based on the input L logic value and outputs the output. As a result, the second connection switching unit 28 becomes active. With this structure, even if the potential of the low potential line 38 rises to the potential equivalent to the H logic value, the control line 32 and the output line 36 can be connected, and the control line 32 and the low potential line 38 can be disconnected, forcibly controlling the output unit 12 to be in an off state.

[0097] Figure 10 This describes an operation example where an open-circuit potential Vop, equivalent to the H logic value, is applied to the low-potential line 38, and the control unit 54 outputs the L logic value. In this case, it is also consistent with... Figure 9 Similarly, in this example, the outputs of the respective inverters 22 of the front-end control unit 20 are fixed at the H logic value. Therefore, the operations of the first connection switching unit 27, the second connection switching unit 28, and the disconnection unit 29 are the same as... Figure 9 The example is the same. Using this structure, even when the potential of the low potential line 38 rises to a potential equivalent to the H logic value, the control line 32 and the output line 36 can be connected, and the control line 32 and the low potential line 38 can be disconnected, forcibly controlling the output section 12 to the off state.

[0098] use Figures 7 to 10 The operation described herein allows the output unit 12 to be controlled to a disconnected state in two situations: when an abnormal state such as overcurrent is detected in the semiconductor device 100, and when the potential of the low-potential GND rises. Therefore, the semiconductor device 100 and the like can be protected.

[0099] Figure 11 This diagram illustrates other structural examples of the front-end control unit 20. In this example, the front-end control unit 20 includes a first inverter 22-1, a second inverter 22-2, and a third inverter 22-3. The first inverter 22-1 and... Figures 1 to 10 The first inverter 22-1 described herein is the same.

[0100] The second inverter 22-2 is positioned between the high-potential line 30 and the low-potential line 38. It selects the potential of either the high-potential line 30 or the low-potential line 38 based on the output of the first inverter 22-1 and outputs the corresponding voltage. The output of the second inverter 22-2 is input to both the subsequent inverter 26-1 in the subsequent control unit 24 and the MOSFET in the first connection switching unit 27.

[0101] The third inverter 22-3 is positioned between the high-potential line 30 and the low-potential line 38. Based on the output of the second inverter 22-2, it selects the potential of either the high-potential line 30 or the low-potential line 38 and inputs this potential to the cutoff unit 29. When the output of the third inverter 22-3 is higher than the first threshold potential, the cutoff unit 29 cuts off the control line 32 and the low-potential line 38.

[0102] Using this structure, the drive circuit 10 and Figures 7 to 10 The example described above operates in the same manner. Furthermore, the drive circuit 10 in this example does not have a fourth inverter 22-4, thus reducing the circuit size.

[0103] Figure 12 This is a cross-sectional view showing an example of the MOSFETs in the output section 12, the first connection switching section 27, and the cut-off section 29. In this example, the MOSFETs in the output section 12, the first connection switching section 27, and the cut-off section 29 are formed on the same semiconductor substrate 300. The semiconductor substrate 300 is, in an example, a silicon substrate, but is not limited thereto. In this example, the semiconductor substrate 300 has an n-type drift region 308. The upper surface 301 of the semiconductor substrate 300 is covered by an interlayer insulating film 302. A drain electrode 310 is provided on the entire surface of the lower surface 303 of the semiconductor substrate 300.

[0104] In this example, the output section 12 is a vertically oriented power MOSFET in which the main current flows between the upper surface 301 and the lower surface 303 of the semiconductor substrate 300. A p-type base region 312 and an n-type source region 311 are provided on the upper surface 301. The base region 312 is in contact with the upper surface 301. The source region 311 is selectively located within the base region 312 in the region in contact with the upper surface 301. Furthermore, an n+ type drift region 314 is provided between the lower surface 303 and the drift region 308. The drain region 314 is in contact with the drain electrode 310.

[0105] The source region 311 is connected to the source electrode 306 via a through-hole disposed in the interlayer insulating film 302. Furthermore, on the upper surface 301, a gate electrode 304 is disposed above the base region 312 sandwiched between the drift region 308 and the source region 311, separated by the interlayer insulating film 302. A predetermined gate voltage is applied to the gate electrode 304, thereby forming a channel on the surface of the base region 312, and the main current flows between the source region 311 and the drift region 308. The main current flows between the source electrode 306 and the drain electrode 310 through the source region 311, the channel, the drift region 308, and the drain region 314.

[0106] In this example, the first connection switching section 27 is an n-channel MOSFET. The cut-off section 29 is a p-channel MOSFET. The first connection switching section 27 is disposed between the control line 32 and the cut-off section 29. The cut-off section 29 is disposed between the first connection switching section 27 and the low-potential line 38.

[0107] The first connection switching unit 27 includes a drain electrode 320, a gate electrode 322, a wiring 324, a drain region 330, a source region 331, and a well region 332. The well region 332 is a p-type region that contacts the upper surface 301. The drain region 330 and the source region 331 are n-type regions that are contacted by the upper surface 301 inside the well region 332. The drain region 330 is connected to the drain electrode 320, and the source region 331 is connected to the wiring 324. In addition, the well region 332 is also connected to the wiring 324.

[0108] A well region 332 is disposed between the drain region 330 and the source region 331. A gate electrode 322 is disposed above the well region 332 between the drain region 330 and the source region 331, separated by an interlayer insulating film 302. A predetermined gate voltage is applied to the gate electrode 322, thereby forming a channel in the well region 332, connecting the drain region 330 and the source region 331.

[0109] The cut-off portion 29 has a drain electrode 328, a gate electrode 326, wiring 324, a drain region 335, and a source region 334. The drain region 335 and the source region 334 are p-type regions disposed inside the drift region 308 and in contact with the upper surface 301. The drain region 335 is connected to the drain electrode 328, and the source region 334 is connected to the wiring 324.

[0110] A drift region 308 is disposed between the drain region 335 and the source region 334. A gate electrode 326 is disposed above the drift region 308 between the drain region 335 and the source region 334, separated by an interlayer insulating film 302. A predetermined gate voltage is applied to the gate electrode 326, thereby forming a channel in the drift region 308, connecting the drain region 335 and the source region 334.

[0111] Using this structure, the output section 12, the first connection switching section 27, and the cut-off section 29 can be provided on the semiconductor substrate 300. In addition, in the area where the first connection switching section 27 and the cut-off section 29 are provided, leakage current flow between the upper surface 301 and the lower surface 303 of the semiconductor substrate 300 can be suppressed.

[0112] Figure 13 This is a cross-sectional view showing another example of the MOSFET, including the output section 12, the first connection switching section 27, and the cut-off section 29. In this example, the cut-off section 29 is located on the control line 32 side, and the first connection switching section 27 is located on the low-potential line 38 side. In this example, the well region 332 is connected to the low-potential line 38. Other structures are similar to... Figure 12 The example is the same. In this example, the source region 334 of the cut-off section 29 is connected to a control line 32 with a higher potential. Therefore, sometimes current flows between the control line 32 and the drain electrode 310 via the source region 334 and the drift region 308. In contrast, in Figure 12 In the example shown, the first connection switching part 27 is disposed on the high potential side. Therefore, in the area where the first connection switching part 27 and the cut-off part 29 are disposed, current flow between the upper surface 301 and the lower surface 303 of the semiconductor substrate 300 can be suppressed.

[0113] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. Those skilled in the art will understand that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements are also included within the technical scope of the present invention.

[0114] Label Explanation

[0115] 10. Drive circuit, 12. Output section, 20. Pre-stage control section, 22. Inverter, 24. Post-stage control section, 26. Post-stage inverter, 27. First connection switching section, 28. Second connection switching section, 29. Cut-off section, 30. High-potential line, 32. Control line, 36. Output line, 38. Low-potential line, 50. Logic circuit, 52. ··Output control unit, 54···Extraction control unit, 56···Load open circuit detection unit, 58···Overcurrent detection unit, 60···Overheat detection unit, 62···Status signal output unit, 64, 66, 68···Diode, 70···Internal power supply, 72···Low voltage detection unit, 100···Semiconductor device, 101···Input terminal, 102···Output terminal, 103···High voltage Bit terminal, 104...low potential terminal, 105...status terminal, 110...power supply, 130...pull-up power supply, 140...external resistor, 200...load, 300...semiconductor substrate, 301...top surface, 302...interlayer insulating film, 303...bottom surface, 304...gate electrode, 306...source electrode, 308...drift region, 310 ...Drain electrode, 311...Source region, 312...Base region, 314...Drain region, 320...Drain electrode, 322...Gate electrode, 324...Wiring, 326...Gate electrode, 328...Drain electrode, 330...Drain region, 331...Source region, 332...Trap region, 334...Source region, 335...Drain region.

Claims

1. A driving circuit that controls an output unit, the output unit switching whether to provide current to the output line based on the potential difference between an input first control signal and the voltage of the output line, characterized in that, The driving circuit includes: A control line that transmits the first control signal to the output unit; A low-potential line, to which a predetermined reference potential is applied; A high-potential line, which is applied with a high potential higher than the first threshold potential; A pre-stage control unit is disposed between the high potential line and the low potential line, and outputs the potential of one of the high potential line and the low potential line as a second control signal. A first connection switching unit, one end of which is connected to the control line, and switches between connecting the control line and the low-potential line according to the second control signal; and A cutting-off section, which is connected in series with the first connection switching section between the control line and the low-potential line, cuts off the control line and the low-potential line based on the potential of the low-potential line. The first connection switching unit has a MOSFET that becomes in the on state when the potential input from the front-end control unit is higher than the second threshold potential. The cutting part is connected to the other end of the first connection switching part so that the first connection switching part and the cutting part are electrically connected in series with the control line and the low potential line, and the connection between the control line and the low potential line is cut off based on the potential of the low potential line.

2. The driving circuit as described in claim 1, characterized in that, When the potential of the low potential line is higher than the first threshold potential, the cutting part cuts off the control line and the low potential line regardless of the value of the second control signal.

3. The driving circuit as described in claim 1, characterized in that, The front-end control unit has: The first inverter is located between the high potential line and the low potential line, and selects the potential of one of the high potential line and the low potential line according to the input signal and outputs it. and The second inverter, positioned between the high-potential line and the low-potential line, selects the potential of either the high-potential line or the low-potential line based on the output of the first inverter, and inputs this potential as the second control signal to the MOSFET of the first connection switching unit. The cutting-off section cuts off the control line and the low-potential line when the output of the first inverter is higher than the first threshold potential.

4. The driving circuit as described in claim 1, characterized in that, The front-end control unit has: The first inverter is located between the high potential line and the low potential line, and selects the potential of one of the high potential line and the low potential line according to the input signal and outputs it. The second inverter is disposed between the high potential line and the low potential line. Based on the output of the first inverter, it selects the potential of one of the high potential line and the low potential line, and inputs the potential of one of the high potential line and the low potential line as the second control signal to the MOSFET of the first connection switching unit. and A third inverter, positioned between the high-potential line and the low-potential line, selects the potential of one of the high-potential line and the low-potential line based on the output of the second inverter, and inputs the potential of the one of the high-potential line and the low-potential line to the cut-off section. The cutting-off section cuts off the control line and the low-potential line when the output of the third inverter is higher than the first threshold potential.

5. The driving circuit as described in claim 1, characterized in that, The front-end control unit has: The first inverter is located between the high potential line and the low potential line, and selects the potential of one of the high potential line and the low potential line according to the input signal and outputs it. The second inverter is disposed between the high potential line and the low potential line. Based on the output of the first inverter, it selects the potential of one of the high potential line and the low potential line, and inputs the potential of one of the high potential line and the low potential line as the second control signal to the MOSFET of the first connection switching unit. and A third inverter, disposed between the high-potential line and the low-potential line, selects the potential of one of the high-potential line and the low-potential line based on the input to the first inverter, and inputs the potential of the one of the high-potential line and the low-potential line to the cut-off section. The cutting-off section cuts off the control line and the low-potential line when the output of the third inverter is higher than the first threshold potential.

6. The driving circuit as described in claim 1, characterized in that, Also includes: The second connection switching unit switches whether the control line and the output line are connected; and The downstream control unit connects the control line and the output line when the upstream control unit outputs a voltage higher than a predetermined third threshold potential.

7. The driving circuit as described in claim 6, characterized in that, The post-stage control unit is located between the high-potential line and the output line. Based on the voltage output by the pre-stage control unit, it selects the potential of one of the high-potential line and the output line, and inputs the potential of one of the high-potential line and the output line to the second connection switching unit.

8. The driving circuit as described in claim 6 or 7, characterized in that, The front-end control unit has: The first inverter is located between the high potential line and the low potential line, and selects the potential of one of the high potential line and the low potential line according to the input signal and outputs it. The second inverter is disposed between the high potential line and the low potential line. Based on the output of the first inverter, it selects the potential of one of the high potential line and the low potential line, and inputs the potential of one of the high potential line and the low potential line as the second control signal to the MOSFET of the first connection switching unit. The third inverter is disposed between the high potential line and the low potential line. Based on the output of the second inverter, it selects the potential of one of the high potential line and the low potential line, and inputs the potential of one of the high potential line and the low potential line to the cut-off section. and The fourth inverter, located between the high-potential line and the low-potential line, selects the potential of either the high-potential line or the low-potential line based on the output of the first inverter, and inputs the potential of either the high-potential line or the low-potential line to the subsequent control unit. The cutting-off section cuts off the control line and the low-potential line when the output of the third inverter is higher than the first threshold potential.

9. The driving circuit as described in claim 6 or 7, characterized in that, The front-end control unit has: The first inverter is located between the high potential line and the low potential line, and selects the potential of one of the high potential line and the low potential line according to the input signal and outputs it. A second inverter, disposed between the high-potential line and the low-potential line, selects the potential of one of the high-potential line and the low-potential line based on the output of the first inverter, and inputs the potential of the high-potential line and the low-potential line to the MOSFET of the first connection switching unit and the subsequent control unit; and A third inverter, positioned between the high-potential line and the low-potential line, selects the potential of one of the high-potential line and the low-potential line based on the output of the second inverter, and inputs the potential of the one of the high-potential line and the low-potential line to the cut-off section. The cutting-off section cuts off the control line and the low-potential line when the output of the third inverter is higher than the first threshold potential.

10. The driving circuit according to any one of claims 1 to 7, characterized in that, The first connection switching unit has an n-channel MOSFET disposed between the control line and the low potential line. The cut-off portion has a p-channel MOSFET disposed between the n-channel MOSFET and the low-potential line.

11. A semiconductor device, characterized in that, include: Output line; The output unit switches whether to supply current to the output line based on the potential difference between the input first control signal and the voltage of the output line. and The driving circuit according to any one of claims 1 to 10.

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