Semiconductor device and semiconductor module

Abstract

The manufacturing cost of semiconductor devices is reduced. A semiconductor device is provided, which comprises: a semiconductor substrate; an active portion, which is provided on the semiconductor substrate; a first well region and a second well region, which are provided on the semiconductor substrate, and the first well region and the second well region are arranged to sandwich the active portion when viewed from above; an emitter electrode, which is arranged above the active portion; and a pad, which is arranged above the first well region and is separated from the emitter electrode, and the emitter electrode is arranged above the second well region. A peripheral well region is also provided, which is arranged to surround the active portion when viewed from above, and the first well region and the second well region can protrude toward the center of the active portion compared to the peripheral well region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a semiconductor module. Background Art

[0002] Conventionally, there are known semiconductor devices provided with sensors for detecting chip temperature, etc. (see, for example, Patent Document 1). Also, there are known semiconductor devices provided with protective films such as polyimide (see, for example, Patent Documents 2 to 4).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2007-329330

[0004] Patent Document 2: Japanese Patent Application Publication No. 2009-38140

[0005] Patent Document 3: Japanese Patent Application Publication No. 2015-177116

[0006] Patent Document 4: Japanese Patent Application Publication No. 2015-26683 Summary of the invention

[0007] Technical issues

[0008] It is preferred that the semiconductor device be easy to assemble.

[0009] Technical Solution

[0010] In order to solve the above-mentioned problems, in a first embodiment of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may have an active portion provided on the semiconductor substrate. The semiconductor device may have a first well region and a second well region provided on the semiconductor substrate and arranged to sandwich the active portion when viewed from above. The semiconductor device may have an emitter electrode arranged above the active portion. The semiconductor device may have a pad arranged above the first well region and separated from the emitter electrode. An emitter electrode may be arranged above the second well region.

[0011] The semiconductor device may include a peripheral well region arranged to surround the active portion in a plan view. The first well region and the second well region may protrude toward the center of the active portion relative to the peripheral well region.

[0012] The semiconductor substrate may have a first end side and a second end side facing each other in a plan view. The first well region may be arranged between the active portion and the first end side. The second well region may be arranged between the active portion and the second end side.

[0013] The semiconductor device may include: a transistor portion, which is arranged in the active portion; and a dummy element portion, which is arranged surrounded by the second well region when viewed from above. Both the transistor portion and the dummy element portion may include a gate groove portion provided on the upper surface of the semiconductor substrate. The transistor portion may include an emitter region of a first conductivity type, and the emitter region of the first conductivity type is provided on the upper surface of the semiconductor substrate in contact with the gate groove portion. A region of a second conductivity type may be provided in a region of the upper surface of the dummy element portion in contact with the gate groove portion.

[0014] In a plan view, the area of ​​the dummy element portion is smaller than the area of ​​the transistor portion.

[0015] The second conductivity type region of the dummy element portion is electrically connected to the emitter electrode.

[0016] The gate trench portion may have a long side on the upper surface of the semiconductor substrate in a predetermined trench long side direction. The second conductivity type region in the dummy element portion may have: a second conductivity type base region; and a second conductivity type contact region, which is alternately arranged with the base region along the trench long side direction and has a higher doping concentration than the base region.

[0017] The semiconductor device may include a split well region that divides the active portion when viewed from above. The split well region may have a long side in a predetermined well long side direction. The split well region may have a wide portion whose width in a direction perpendicular to the well long side direction when viewed from above is wider than the width of other portions. An emitter electrode may be arranged above the wide portion.

[0018] The emitting electrode may cover the entire wide portion.

[0019] The wide portion may be disposed between the first well region and the second well region in a plan view.

[0020] The split well region may be provided from the first well region to the second well region in a plan view.

[0021] A gate pad may be provided above the first well region. The semiconductor device may include a gate channel connected to the gate pad. The gate channel may have a portion provided along an edge of the second well region when viewed from above. The gate channel may have a portion provided along an edge of the wide portion when viewed from above.

[0022] The semiconductor device may include a protective layer disposed above the emitter electrode. The protective layer may divide the upper surface of the semiconductor substrate into a first region where the first well region is disposed, a second region where the second well region is disposed, and a third region between the first well region and the second well region.

[0023] In a plan view, an area of ​​the third region may be larger than an area of ​​any one of the first region and the second region.

[0024] The semiconductor device may include a connection portion connected to a region of the emitter electrode that is not covered by the protective layer. The connection portion may be connected to the third region.

[0025] The protective layer may include a first beam portion and a second beam portion, wherein the first beam portion has a first direction as a long side direction, and the second beam portion has a second direction as a long side direction, and the second direction is different from the first direction. When viewed from above, each beam portion may be sandwiched by an emitting electrode not covered by the protective layer in a short side direction orthogonal to the respective long side directions.

[0026] The third region of the emitter electrode may be surrounded by a protection layer including at least one first beam portion and at least one second beam portion.

[0027] In a second embodiment of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may include an active portion provided on the semiconductor substrate. The semiconductor device may include a transistor portion configured on the active portion. The semiconductor device may include a dummy element portion. The semiconductor device may include a well region separating the transistor portion from the dummy element portion. Both the transistor portion and the dummy element portion may include a gate groove portion provided on the upper surface of the semiconductor substrate. The transistor portion may include an emitter region of a first conductivity type, and the emitter region of the first conductivity type is provided on the upper surface of the semiconductor substrate in contact with the gate groove portion. A region of a second conductivity type may be provided in a region on the upper surface of the dummy element portion in contact with the gate groove portion.

[0028] In a third aspect of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may have an active portion provided on the semiconductor substrate. The semiconductor device may have an emitter electrode disposed above the active portion. The semiconductor device may have a split well region that divides the active portion when viewed from above. The split well region may have a long side in a predetermined well long side direction. The split well region may have a wide portion whose width in a direction perpendicular to the well long side direction when viewed from above is wider than the width of other portions. An emitter electrode may be disposed above the wide portion.

[0029] In a fourth aspect of the present invention, a semiconductor module including a first semiconductor device and a second semiconductor device is provided. The first semiconductor device may be the semiconductor device of the first aspect. The second semiconductor device may include a semiconductor substrate. The second semiconductor device may include an active portion provided on the semiconductor substrate. The second semiconductor device may include a first well region and a second well region provided on the semiconductor substrate and arranged to sandwich the active portion when viewed from above. The second semiconductor device may include an emitter electrode arranged above the active portion. The second semiconductor device may include a first pad arranged above the first well region and separated from the emitter electrode. The second semiconductor device may include a second pad arranged above the second well region and separated from the emitter electrode.

[0030] In a fifth aspect of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may have an emitter electrode disposed above the semiconductor substrate. The semiconductor device may have a protective layer disposed above the emitter electrode. The semiconductor device may have a connection portion connected to a region of the emitter electrode that is not covered by the protective layer. The protective layer may divide the upper surface of the emitter electrode into a plurality of regions. Among the plurality of regions of the emitter electrode, the area of ​​the connection region to which the connection portion is connected may be the largest.

[0031] The protective layer may include a first beam portion and a second beam portion, wherein the first beam portion has a first direction as a long side direction, and the second beam portion has a second direction as a long side direction, and the second direction is different from the first direction. When viewed from above, each beam portion is sandwiched by an emitting electrode not covered by the protective layer in a short side direction orthogonal to the respective long side directions.

[0032] The connection region of the emitter electrode is surrounded by a protection layer including at least one first beam portion and at least one second beam portion.

[0033] The semiconductor device may include a pad disposed separately from the emitter electrode above the semiconductor substrate. The protective layer may include an electrode separation portion disposed between the emitter electrode and the pad when viewed from above. The width of the first beam portion in the short side direction and the width of the second beam portion in the short side direction may be greater than the width of the electrode separation portion.

[0034] At least one of the first beam portion and the second beam portion may be arranged on the upper surface of the emitting electrode.

[0035] The semiconductor device may include a diode portion having a cathode region of a first conductivity type connected to the lower surface of the semiconductor substrate. The semiconductor device may include a transistor portion having a collector region of a second conductivity type connected to the lower surface of the semiconductor substrate. The diode portion may include a lifetime adjustment region for adjusting the lifetime of carriers on the upper surface side of the semiconductor substrate. The first beam portion may be provided at a position that does not overlap with the cathode region.

[0036] The transistor portion may have the first direction as a long side direction. The first beam portion may be provided above the transistor portion.

[0037] The protection layer may be disposed at a position not overlapping with the cathode region.

[0038] In a sixth aspect of the present invention, a semiconductor device having a semiconductor substrate is provided. The semiconductor device may include an emitter electrode disposed above the semiconductor substrate. The semiconductor device may include a protective layer disposed above the emitter electrode. The semiconductor device may include a diode portion having a cathode region of a first conductivity type in contact with the lower surface of the semiconductor substrate. The semiconductor device may include a transistor portion having a collector region of a second conductivity type in contact with the lower surface of the semiconductor substrate. The protective layer may be disposed at a position that does not overlap with the cathode region.

[0039] It should be noted that the above summary of the invention does not list all the necessary features of the present invention. In addition, sub-combinations of these feature groups can also constitute other inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0041] Figure 2 The figure shows the emitter electrode 52 and the pad 50 arranged above the semiconductor substrate 10 .

[0042] Figure 3 1 is a diagram showing an example of arrangement of the transistor portion 70 , the diode portion 80 , and the gate channel 48 on the upper surface of the semiconductor device 100 .

[0043] Figure 4 yes Figure 3 Magnified view of area A in FIG.

[0044] Figure 5 Yes means Figure 4 A diagram showing an example of the aa section in FIG.

[0045] Figure 6 Yes means Figure 4 A diagram showing an example of the bb cross section in FIG.

[0046] Figure 7 1 is a diagram showing an example of an XZ cross section of the dummy element portion 110 .

[0047] Figure 8 1 is a diagram showing an example of the upper surface of the mesa portion 60 of the dummy element portion 110 .

[0048] Fig. 9 Yes means Figure 3 A diagram showing an example of a dd cross section in FIG.

[0049] Fig.10 It is a plan view showing an example of arrangement of the protective layer 150 .

[0050] Fig.11It is a side view of the semiconductor substrate 10 in a state of being mounted on the mounting substrate 200 .

[0051] Fig.12 It is a plan view showing an example of a semiconductor module 300 according to an embodiment of the present invention.

[0052] Fig.13 It is a diagram showing an example of the upper surface of the first semiconductor device 100 - 1 .

[0053] Fig.14 Yes means Fig.13 A diagram showing an example of an ee cross section in .

[0054] Fig.15 1 is a plan view showing the mesa portion 60 in the dummy element portion 110 of the first semiconductor device 100 - 1 .

[0055] Fig.16 It is a diagram showing another example of arrangement of the protective layer 150 in a plan view.

[0056] Fig.17 1 is a diagram showing an example of arrangement of the transistor portion 70 , the diode portion 80 , and the protective layer 150 on the upper surface of the semiconductor device 100 .

[0057] Fig.18 This is an example of an XZ cross section of the semiconductor device 100 .

[0058] Fig.19 FIG. 1 shows a cross section of a semiconductor device 100 in which a protective layer 150 is provided on a diode portion 80 .

[0059] Fig. 20 It is a plan view showing another arrangement example of the protection layer 150 .

[0060] Explanation of symbols

[0061] 10…semiconductor substrate, 11…well region, 12…emitter region, 14…base region, 15…contact region, 16…accumulation region, 18…drift region, 20…buffer region, 21…upper surface, 22…collector region, 23…lower surface, 24…collector, 25…connection portion, 29…extension portion, 30…dummy trench portion, 31…front end portion, 32…dummy insulating film, 34…dummy conductive portion, 38…interlayer insulating film, 39…extension portion, 40…gate trench portion, 41…front end portion, 42…gate insulating film, 44…gate conductive portion, 48…gate flow channel, 50…pad, 52…emitter, 54…contact hole, 56…contact hole, 60…mesa portion, 70…transistor portion, 72…lifetime adjustment region, 73…lifetime killer, 80…diode portion, 81…extension region, 82…cathode region, 86…Main terminal, 88…Casing, 90…Intermediate region, 99…Control terminal, 100…Semiconductor device, 102…End edge, 110…Dummy element portion, 111…First well region, 112…Second well region, 113…Surrounding well region, 114…Divided well region, 115…Wide width portion, 120…Active portion, 150…Protective layer, 152-1…First region, 152-2…Second region, 152-3…Third region, 160…Connection portion, 161…Plated portion, 162…Connection portion, 163…Wiring, 172…Current detection pad, 174…Anode pad, 176…Cathode pad, 178…Current sensor, 180…Anode wiring, 182…Cathode wiring, 184…Anode, 186…Cathode, 190…Mask, 200…Mounting substrate, 300…Semiconductor module DETAILED DESCRIPTION

[0062] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments are not intended to limit the invention of the claims. In addition, all combinations of features described in the embodiments are not necessarily essential to the solution of the invention.

[0063] In this specification, one side in a direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as an upper surface, and the other surface is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when the semiconductor device is installed.

[0064] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The rectangular coordinate axes only determine the relative positions of the components and do not limit specific directions. For example, the Z-axis is not limited to the height direction relative to the ground. It should be noted that the +Z axis direction and the -Z axis direction are opposite directions to each other. In the case where the Z axis direction is recorded without recording the positive and negative, it refers to the direction parallel to the +Z axis and the -Z axis. In addition, in this specification, sometimes the situation of observing from the +Z axis direction is called a bird's-eye view.

[0065] In this specification, when it is said that they are "same" or "equal", it may include the case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0066] In this specification, the conductivity type of the doped region doped with impurities is described as P-type or N-type. However, the conductivity type of each doped region may also be opposite in polarity. In addition, in this specification, when it is described as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is described as P-type or N-type, it means that the doping concentration is lower than the doping concentration of P type or N type.

[0067] In this specification, doping concentration refers to the concentration of impurities activated as donors or acceptors. In this specification, the concentration difference between the donor and the acceptor is sometimes set to the concentration of the larger one of the donor or the acceptor. The concentration difference can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by the spreading resistance measurement method (SR) can be used as the concentration of the donor or the acceptor. In addition, in the case where the concentration distribution of the donor or the acceptor has a peak, the peak value can be used as the concentration of the donor or the acceptor in the region. In the case where the concentration of the donor or the acceptor in the region where the donor or the acceptor is present is roughly equal, the average value of the donor or the acceptor concentration in the region can be used as the donor or the acceptor concentration.

[0068] Figure 1 1 is a top view of an example of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 has an edge 102 when viewed from above. The semiconductor substrate 10 of this example has two sets of edge 102 facing each other when viewed from above. Figure 1 In FIG. 1 , a set of first end edges 102-1 and second end edges 102-2 facing each other are shown. Figure 1 In the figure, a direction parallel to the first end side 102-1 and the second end side 102-2 is set as a Y-axis direction, and a direction perpendicular to the first end side 102-1 and the second end side 102-2 is set as an X-axis direction.

[0069] The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the upper surface and the lower surface of the semiconductor substrate 10 when the semiconductor device 100 is controlled to be in an on state. Figure 1 The region inside the well region indicated by the diagonal lines in the figure is the active portion 120. The active portion 120 may include a transistor portion including a transistor element such as an IGBT (insulated gate bipolar transistor). The active portion 120 may also include a diode portion including a diode element such as a FWD (freewheeling diode). The active portion 120 may be a region where at least one of a transistor portion and a diode portion is provided.

[0070] A P-type well region is provided in the semiconductor substrate 10. The well region is a region having a higher doping concentration than the base region described later, formed in contact with the upper surface of the semiconductor substrate 10, and formed to a position deeper than the bottom of the base region. The depth is the depth with the upper surface of the semiconductor substrate 10 as the reference position. Figure 1 FIG. 2 shows an example of the arrangement of the well region on the upper surface of the semiconductor substrate 10. Figure 1 In FIG. 1 , the well region is marked with a hatched oblique line.

[0071] Since the well region is a P-type region with a relatively high concentration, it is difficult for the electron current to flow. Therefore, if the well region is configured in a biased manner, the region where the electron current is difficult to flow will be biased. The semiconductor device 100 of this example configures the region where the electron current is difficult to flow in a well-balanced manner by configuring the well region in a balanced manner when viewed from above. As a result, the bias of the electron current can be suppressed and the tolerance of the semiconductor device 100 can be improved.

[0072] The semiconductor device 100 includes a first well region 111 and a second well region 112. The first well region 111 and the second well region 112 are arranged to sandwich an active portion 120 in a plan view. The first well region 111 and the second well region 112 are arranged in a predetermined direction (in Figure 1 The two well regions sandwich the active portion 120, which means that any straight line connecting the two well regions passes through the active portion 120 in a plan view.

[0073] The first well region 111 may be disposed near the first end edge 102-1. That is, the distance between the first well region 111 and the first end edge 102-1 is smaller than the distance between the first well region 111 and the second end edge 102-2. The second well region 112 may be disposed near the second end edge 102-2. That is, the distance between the second well region 112 and the second end edge 102-2 is smaller than the distance between the second well region 112 and the first end edge 102-1.

[0074] The first well region 111 of this example is arranged between the active portion 120 and the first end side 102-1 in the X-axis direction. The active portion 120 is not provided between the first well region 111 and the first end side 102-1. That is, the first well region 111 is arranged between the end of the active portion 120 in the X-axis direction and the first end side 102-1.

[0075] The second well region 112 of this example is arranged between the active portion 120 and the second edge 102-2 in the X-axis direction. No active portion 120 is provided between the second well region 112 and the second edge 102-2. That is, the second well region 112 is arranged between the end of the active portion 120 in the X-axis direction and the second edge 102-2.

[0076] The first well region 111 and the second well region 112 may be disposed in a range including a center position Yc of the first end side 102-1 and the second end side 102-2 in the Y-axis direction. The first well region 111 may be sandwiched by the active portion 120 in the Y-axis direction. The second well region 112 may be sandwiched by the active portion 120 in the Y-axis direction. The second well region 112 may be disposed in a wider range in the Y-axis direction than the first well region 111.

[0077] The second well region 112 may surround a predetermined region in a plan view. The second well region 112 of this example surrounds the dummy element portion 110 provided in the semiconductor substrate 10. The dummy element portion 110 will be described later.

[0078] The semiconductor device 100 may include a peripheral well region 113 configured to surround the active portion 120 in a plan view. The peripheral well region 113 may be provided parallel to each end side of the semiconductor substrate 10. The peripheral well region 113 of this example is an annular region surrounding the active portion 120 in a plan view. The width of the peripheral well region 113 in a direction perpendicular to each end side may be a constant value.

[0079] The first well region 111 and the second well region 112 of this example protrude toward the center Ac side of the active portion 120 compared to the surrounding well region 113. The center Ac of the active portion 120 is the geometric center of gravity of the active portion 120 when viewed from above. In other examples, at least one of the first well region 111 and the second well region 112 may be disposed between the surrounding well region 113 and the edge 102 of the semiconductor substrate 10. In this case, the first well region 111 and the second well region 112 protrude from the surrounding well region 113 toward the edge 102 side.

[0080] The semiconductor device 100 may include a split well region 114 that divides the active portion 120 in a plan view. The active portion 120 may be divided into two or more regions by a well region including the split well region 114. The split well region 114 has a long side in a predetermined well long side direction. The split well region 114 extends in the well long side direction and crosses the active portion 120. Figure 1 The long side direction of the well is the X-axis direction.

[0081] The split well region 114 may be disposed between the first well region 111 and the second well region 112. One end of the split well region 114 in the long direction may be connected to the first well region 111, and the other end may be connected to the second well region 112. The split well region 114 may be disposed in a region overlapping with the center Ac of the active portion 120.

[0082] The split well region 114 may have a wide portion 115 whose width in a direction perpendicular to the well long side direction (in this example, the Y-axis direction) is wider than the width of other portions when viewed from above. The wide portion 115 is also provided between the first well region 111 and the second well region 112. The wide portion 115 may be provided in a region overlapping with the center Ac of the active portion 120. The wide portion 115 may be configured in a region including the center of the split well region 114 in the well long side direction.

[0083] Figure 2 FIG. 5 is a diagram showing an emitter electrode 52 and a pad 50 disposed above a semiconductor substrate 10. Figure 2 In the middle, the dotted line indicates Figure 1 The emitter electrode 52 and the pad 50 are indicated by solid lines. The emitter electrode 52 and the pad 50 are electrodes made of metal such as aluminum. An insulating film is provided between the emitter electrode 52 and the pad 50 and the semiconductor substrate 10. The emitter electrode 52 and the pad 50 are connected to the semiconductor substrate 10 via a contact hole provided in the insulating film. Figure 2 In the embodiment, the insulating film and the contact holes are omitted.

[0084] The emitter electrode 52 is arranged above the active portion 120. The emitter electrode 52 is connected to the active portion 120 via the contact hole described above. A wire or a lead frame is connected to the upper surface of the emitter electrode 52, and a predetermined emitter voltage is applied to the upper surface of the emitter electrode 52. The pad 50 is, for example, a gate pad. The emitter electrode 52 and the pad 50 are provided separately from each other in a plan view. A wire is connected to the upper surface of the pad 50, and a predetermined gate voltage is applied to the upper surface of the pad 50. The gate voltage applied to the pad 50 is supplied to the transistor portion of the active portion 120 through a gate flow path described later.

[0085] The pad 50 is arranged above the first well region 111. That is, at least a portion of the pad 50 overlaps with at least a portion of the first well region 111. More than half of the pad 50 in the present example overlaps with the first well region 111 when viewed from above. The pad 50 may also overlap with the first well region 111 as a whole. Each pad in the semiconductor device is preferably arranged above the well region.

[0086] An emitter electrode 52 is disposed above the second well region 112. The emitter electrode 52 above the second well region 112 is not separated from the emitter electrode 52 above the active portion 120 and is provided continuously. More than half of the second well region 112 may be covered by the emitter electrode 52, or the entire second well region 112 may be covered by the emitter electrode 52. In addition, an emitter electrode 52 may be disposed above the dummy element portion 110. The entire dummy element portion 110 may be covered by the emitter electrode 52.

[0087] The emitter electrode 52 may be disposed above the peripheral well region 113. That is, the emitter electrode 52 above the active portion 120 may be disposed extending above the peripheral well region 113. The peripheral well region 113 may have a region not covered by the emitter electrode 52.

[0088] The emitter electrode 52 may be disposed above the wide portion 115. The entire wide portion 115 may be covered by the emitter electrode 52. The entire divided well region 114 may be covered by the emitter electrode 52.

[0089] As a semiconductor device, there is known a structure having a current sensor for detecting the current flowing between the upper surface and the lower surface of the semiconductor substrate. For example, the current sensor is arranged in an area corresponding to the dummy element part 110 in the semiconductor device 100. The current sensor has the same structure as the transistor part of the semiconductor substrate, and simulates the operation of the transistor part. By detecting the current flowing through the current sensor, the current flowing through the transistor part can be estimated. In the semiconductor device, a pad for the current sensor is provided. The pad for the current sensor is sometimes arranged in an area corresponding to the second well region 112 in this example. In addition, pads such as a gate pad are arranged in an area corresponding to the first well region 111.

[0090] The well regions under each pad are arranged facing each other in a plan view. Since the well regions are areas where current is difficult to flow, by arranging the well regions facing each other, the areas where current is difficult to flow can be evenly arranged in the semiconductor substrate. Therefore, the tolerance of the semiconductor device can be improved.

[0091] The semiconductor device 100 of this example does not have a pad for the current sensor disposed above the second well region 112. As a result, although it is difficult to estimate the current flowing through the transistor portion of the semiconductor device 100, since wiring to the pad for the current sensor is not required, the semiconductor device 100 becomes easy to assemble. Therefore, the manufacturing cost can be reduced.

[0092] The emitter electrode 52 is disposed above the second well region 112. The dummy element portion 110 may be connected to the emitter electrode 52. The dummy element portion 110 is, for example, a region where a gate trench portion described later is provided but an emitter region is not provided. That is, the dummy element portion 110 is a region where a gate trench portion is provided but does not operate as a transistor.

[0093] In a semiconductor device that makes the dummy element portion 110 work as a current sensor, the pad for the current sensor is separated from the emitter electrode. Therefore, the current directly from the current sensor does not flow in the emitter electrode. In the semiconductor device 100 of this example, by not making the dummy element portion 110 work as a transistor portion, the current from the dummy element portion 110 is not directly supplied to the emitter electrode 52. Therefore, in the semiconductor device that makes the dummy element portion 110 work as a current sensor and the semiconductor device 100 of this example, the main current flowing in the emitter electrode 52 can be equal. Therefore, even when two semiconductor devices are used in combination, the non-uniformity of the main current can be suppressed. In addition, by providing a gate groove portion in the dummy element portion 110, the gate capacitance can be equal to that of the semiconductor device that makes the dummy element portion 110 work as a current sensor. Therefore, even when two semiconductor devices are used in combination, the non-uniformity of characteristics such as switching speed can be suppressed.

[0094] Figure 3 1 is a diagram showing an example of the arrangement of the transistor portion 70, the diode portion 80, and the gate channel 48 on the upper surface of the semiconductor device 100. Figure 3 In the figure, the region where the transistor portion 70 is arranged is marked with a symbol "I", and the region where the diode portion 80 is arranged is marked with a symbol "F". The transistor portion 70 and the diode portion 80 may be arranged alternately and in parallel in the X-axis direction. In the case where the active portion 120 is divided by the split well region 114, the transistor portion 70 and the diode portion 80 may be arranged alternately and in parallel in each region of the active portion 120 in the X-axis direction.

[0095] exist Figure 3 In FIG. 4 , a gate channel 48 is indicated by a dotted line. The gate channel 48 is a wiring formed of a conductive material such as polysilicon or metal to which impurities are added. The gate channel 48 supplies a gate voltage applied to the gate pad 50 to each transistor unit 70. The gate channel 48 may be arranged above the well region.

[0096] The semiconductor device 100 may include a gate runner 48 - 3 disposed so as to surround the active portion 120 in a plan view. The gate runner 48 - 3 may be disposed above the peripheral well region 113 .

[0097] The semiconductor device 100 may include a gate channel 48-1 surrounding at least a portion of the first well region 111 in a plan view. The gate channel 48-1 may be arranged along the edge of the first well region 111 in a plan view. The gate channel 48-1 may include a portion parallel to each edge of the first well region 111.

[0098] The semiconductor device 100 may include a gate channel 48-2 surrounding at least a portion of the second well region 112 in a plan view. The gate channel 48-2 may be arranged along the edge of the second well region 112 in a plan view. The gate channel 48-2 may include a portion parallel to each edge of the second well region 112.

[0099] The semiconductor device 100 may include a gate channel 48-4 disposed above the divided well region 114 in a plan view. The semiconductor device 100 may include a gate channel 48-5 surrounding at least a portion of the wide portion 115 in a plan view. The gate channel 48-5 may be disposed along the edge of the wide portion 115 in a plan view. The gate channel 48-5 may include a portion parallel to each edge of the wide portion 115. The gate channel 48-4 and the gate channel 48-5 may divide the active portion 120 in a plan view.

[0100] The semiconductor device 100 may include an edge termination structure between the peripheral well region 113 and the edge of the semiconductor substrate 10. The edge termination structure alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure includes, for example, a guard ring provided in an annular shape surrounding the active portion 120, a field plate, a surface electric field reduction structure, and a combination of these structures.

[0101] Figure 4 yes Figure 3 1 is an enlarged view of region A in FIG. Region A is a region including gate channel 48, transistor portion 70, and diode portion 80. Although the gate channel 48 in this example corresponds to gate channel 48-2 above second well region 112, the configuration of other gate channels 48, transistor portion 70, and diode portion 80 is the same.

[0102] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 provided inside the upper surface side of the semiconductor substrate 10. Although the well region 11 of this example corresponds to the second well region 112, the first well region 111, the peripheral well region 113, and the divided well region 114 also have the same structure as the well region 11.

[0103] exist Figure 4, the range where the emitter electrode 52 is provided is shown. Although the emitter electrode 52 of this example is provided in a range that does not overlap with the gate flow channel 48, it may overlap with the gate flow channel 48. In this case, an insulating film is provided between the emitter electrode 52 and the gate flow channel 48. Although an interlayer insulating film is provided between the emitter electrode 52 and the upper surface of the semiconductor substrate, Figure 4 In the interlayer insulating film of this example, the contact hole 56 and the contact hole 54 are provided through the interlayer insulating film.

[0104] The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate through the contact hole 54. In addition, the emitter electrode 52 is connected to the dummy conductive portion in the dummy groove portion 30 through the contact hole 56. Between the emitter electrode 52 and the dummy conductive portion, a connecting portion 25 formed of a conductive material such as polysilicon doped with impurities may be provided. The connecting portion 25 is provided on the upper surface of the semiconductor substrate. Between the connecting portion 25 and the semiconductor substrate, an insulating film such as a thermal oxide film is provided.

[0105] An insulating film such as a thermal oxide film is provided between the gate channel 48 and the semiconductor substrate. The gate channel 48 is connected to the gate conductive portion in the gate groove portion 40 on the upper surface of the semiconductor substrate. The gate channel 48 is not connected to the dummy conductive portion in the dummy groove portion 30. The gate channel 48 of this example is provided to overlap with the front end portion 41 of the gate groove portion 40. The front end portion 41 is the end of the gate groove portion 40 that is closest to the gate channel 48. In the front end portion 41 of the gate groove portion 40, the gate conductive portion is exposed to the upper surface of the semiconductor substrate and is in contact with the gate channel 48.

[0106] The emitter electrode 52 is formed of a material containing a metal. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy. The emitter electrode 52 may have a barrier metal formed of titanium and / or a titanium compound, etc., under the region formed of aluminum, etc. The emitter electrode 52 may further have a plug formed by filling tungsten, etc. in a contact hole in contact with the barrier metal and aluminum, etc.

[0107] One or more gate trench portions 40 and one or more dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction in the region of the transistor portion 70 . Figure 4 The arrangement direction in the X-axis direction. In the transistor portion 70, one or more gate trench portions 40 and one or more dummy trench portions 30 may be alternately provided along the arrangement direction.

[0108] The gate trench portion 40 of this example may include: two extension portions 39 (portions of a linear trench along the extension direction) extending in the extension direction perpendicular to the arrangement direction; and a front end portion 41 connecting the two extension portions 39 . Figure 4 The extension direction is the Y-axis direction. Preferably, at least a portion of the front end portion 41 is set to be curved. The front end portion 41 connects one end of the linear shape along the extension direction of the two extension portions 39 of the gate groove portion 40, that is, the end portion, to each other, thereby alleviating the electric field concentration at the end of the extension portion 39.

[0109] The dummy trench portions 30 of this example are provided between the extension portions 39 of the gate trench portions 40. These dummy trench portions 30 may have a linear shape extending along the extension direction.

[0110] In the transistor portion 70, an intermediate region 90 in which no emitter region is provided on the surface may be provided at the boundary adjacent to the diode portion 80. In addition, in the transistor portion 70, a plurality of dummy groove portions 30 may be continuously arranged at a portion adjacent to the intermediate region 90. The dummy groove portion 30 provided at the portion adjacent to the intermediate region 90 may also have an extension portion 29 and a front end portion 31. The front end portion 31 and the extension portion 29 have the same shape as the front end portion 41 and the extension portion 39. The length of the dummy groove portion 30 in the extension direction of the linear shape may be equal to the length of the dummy groove portion 30 having the front end portion 31.

[0111] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The well region 11 is disposed in a predetermined range apart from the contact hole 54. The diffusion depth of the well region 11 may be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the extension direction are disposed in the well region 11.

[0112] The mesa portion 60 sandwiched by the grooves is provided with a base region 14. The mesa portion is a region of the semiconductor substrate sandwiched by the grooves, which is located on the upper surface side relative to the deepest bottom of the grooves. The base region 14 is of the second conductivity type with a doping concentration lower than that of the well region 11. In this example, the base region 14 is of the P- type, and the well region 11 is of the P+ type.

[0113] A contact region 15 of a second conductivity type having a higher doping concentration than the base region 14 is provided on the upper surface of the base region 14 of the mesa portion 60. The contact region 15 of this example is of P+ type. The well region 11 can be provided in a direction away from the contact region 15 disposed at the end in the extending direction of the groove portion among the contact regions 15 in the direction of the gate flow channel 48. In addition, in the transistor portion 70, an emitter region 12 of a first conductivity type is selectively provided on a portion of the upper surface of the contact region 15, and the doping concentration of the emitter region 12 of the first conductivity type is higher than the doping concentration of the semiconductor substrate 10. The emitter region 12 of this example is of N+ type.

[0114] Each of the contact region 15 and the emitter region 12 is provided from one adjacent trench portion to the other trench portion. One or more contact regions 15 and one or more emitter regions 12 of the transistor portion 70 are provided so as to be alternately exposed on the upper surface of the mesa portion 60 along the extending direction of the trench portion.

[0115] In other examples, the contact region 15 and the emitter region 12 may be arranged in stripes along the extending direction in the mesa portion 60 in the transistor portion 70. For example, the emitter region 12 may be arranged in a region adjacent to the trench portion, and the contact region 15 may be arranged in a region sandwiched by the emitter region 12.

[0116] The emitter region 12 may not be provided in the mesa portion 60 of the diode portion 80 . In addition, the contact region 15 is provided in the mesa portion 60 of the intermediate region 90 in an area larger than that of the contact region 15 in the mesa portion 60 of the transistor portion 70 .

[0117] In transistor portion 70, contact hole 54 is provided above each region of contact region 15 and emitter region 12. Contact hole 54 is not provided in the region corresponding to base region 14 and well region 11. In diode portion 80, contact hole 54 is provided above contact region 15 and base region 14.

[0118] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate. Figure 4 In FIG. 1 , the region where the cathode region 82 is provided is indicated by a dotted line. In the region adjacent to the lower surface of the semiconductor substrate where the cathode region 82 is not provided, a P+ type collector region may be provided. Figure 4 Although one mesa portion 60 of the diode portion 80 is shown in FIG. 8 , the diode portion 80 may include a plurality of mesa portions 60 in the X-axis direction.

[0119] An N+ type storage region 16 is provided in at least a portion of the transistor portion 70. Figure 4In FIG. 6 , a region where the accumulation region 16 is provided is indicated by a dotted line. The accumulation region 16 may be provided below the emitter region 12 or the contact region 15 in each mesa portion 60 .

[0120] Figure 5 Yes means Figure 4 FIG. 1 is a diagram showing an example of the aa cross section in FIG. The aa cross section is an XZ plane passing through the emitter region 12. The semiconductor device 100 of this example includes a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section. The emitter electrode 52 is provided on the upper surface of the semiconductor substrate 10 and the interlayer insulating film 38.

[0121] The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are provided with a conductive material such as metal. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0122] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate such as gallium nitride. The semiconductor substrate 10 in this example is a silicon substrate. A P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in this cross section.

[0123] In this cross section, on the upper surface 21 side of the semiconductor substrate 10 in the transistor portion 70 , the N+ type emitter region 12 , the P− type base region 14 , and the N+ type accumulation region 16 are provided in order from the upper surface 21 side of the semiconductor substrate 10 .

[0124] In this cross section, a P-type base region 14 is provided on the upper surface 21 side of the semiconductor substrate 10 in the diode portion 80. In the diode portion 80 of this example, the accumulation region 16 is not provided. In other examples, the accumulation region 16 may be provided in the diode portion 80. In addition, a contact region 15 is provided on the upper surface 21 of the mesa portion 60 of the semiconductor substrate 10 adjacent to the transistor portion 70.

[0125] In transistor section 70, N-type drift region 18 is provided below accumulation region 16. Providing accumulation region 16 with a higher concentration than drift region 18 between drift region 18 and base region 14 can enhance carrier injection enhancement effect (IE effect) and reduce on-voltage.

[0126] The accumulation region 16 of this example is provided in each mesa portion 60 of the transistor portion 70. The accumulation region 16 can be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60. In the diode portion 80, the drift region 18 is provided on the lower surface of the base region 14. In both the transistor portion 70 and the diode portion 80, the N+ type buffer region 20 is provided under the drift region 18.

[0127] The buffer region 20 is provided at the lower side of the drift region 18. The doping concentration of the buffer region 20 is higher than that of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0128] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. It should be noted that in the active section 120, a projection region overlapping with the cathode region 82 in the Z-axis direction is set as the diode section 80. That is, a projection region when the cathode region 82 is projected on the upper surface 21 of the semiconductor substrate 10 in a direction perpendicular to the lower surface 23 of the semiconductor substrate 10 is set as the diode section 80. In addition, a region formed by extending the projection region in the Y-axis direction to the well region may be set as the diode section 80. In addition, in the active section 120, a region which is a projection region when the collector region 22 is projected on the upper surface 21 of the semiconductor substrate 10 in a direction perpendicular to the lower surface 23 of the semiconductor substrate 10 and is a region where a predetermined unit structure including the emitter region 12 and the contact region 15 is regularly arranged is set as the transistor section 70.

[0129] On the upper surface 21 side of the semiconductor substrate 10, one or more gate groove portions 40 and one or more dummy groove portions 30 are provided. Each groove portion is provided in a manner that penetrates the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reaches the drift region 18. In the region where at least one of the emitter region 12, the contact region 15 and the accumulation region 16 is provided, each groove portion also penetrates these regions and reaches the drift region 18. The groove portion penetrating the doped region is not limited to the structure obtained by forming the doped region first and then the groove portion. The structure obtained by forming the doped region between the groove portions after the groove portion is formed is also included in the structure in which the groove portion penetrates the doped region.

[0130] The gate groove portion 40 includes a gate insulating film 42 and a gate conductive portion 44 provided on the upper surface 21 side of the semiconductor substrate 10. The gate insulating film 42 is provided to cover the inner wall of the gate groove portion 40. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate groove portion 40. The gate conductive portion 44 is provided inside the gate groove portion 40 at a position closer to the inner side than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0131] The gate conductive portion 44 includes a region facing the base region 14 via a gate insulating film 42. The gate groove portion 40 in the cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface in the base region 14 that is in contact with the gate groove.

[0132] The dummy groove portion 30 may have the same structure as the gate groove portion 40 in this cross section. The dummy groove portion 30 includes a dummy groove provided on the upper surface 21 side of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is provided to cover the inner wall of the dummy groove. The dummy conductive portion 34 is provided inside the dummy groove and is provided at a position closer to the inner side than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44.

[0133] Figure 6 Yes means Figure 4 FIG. bb is a diagram of an example of a cross section in FIG. The cross section bb is a YZ plane passing through the front end portion 41 of the gate groove portion 40. The front end portion 41 is surrounded by the well region 11. The well region 11 is exposed to the upper surface 21 of the semiconductor substrate 10, and is a P-type region with a higher doping concentration than the base region 14, and is a region set to a deeper position than the base region 14. The doping concentration of the well region 11 can be more than 10 times the doping concentration of the base region 14. With the upper surface 21 as a reference, the well region 11 can be set to a position deeper than the accumulation region 16, and can also be set to a position deeper than the lower end of the front end portion 41. Figure 1 The well regions shown may have the same doping concentration and depth as the well region 11 .

[0134] Figure 7 1 is a diagram showing an example of an XZ cross section of the dummy element portion 110. The dummy element portion 110 is surrounded by the well region 11 ( Figure 1 The dummy element portion 110 of this example has one or more gate trench portions 40 and one or more mesa portions 60.

[0135] The structure of the gate groove portion 40 of the dummy element portion 110 may be the same as the structure of the gate groove portion 40 of the transistor portion 70. The gate groove portion 40 of the dummy element portion 110 is connected to the gate flow channel 48. Thus, the non-uniformity of the gate capacitance can be suppressed. The density per unit area of ​​the gate groove portion 40 in the dummy element portion 110 may be higher than the density per unit area of ​​the gate groove portion 40 in the transistor portion 70. In the dummy element portion 110, a plurality of gate groove portions 40 may be provided instead of providing a dummy groove portion 30.

[0136] The mesa portion 60 of the dummy element portion 110 may have a structure different from that of the mesa portion 60 of the transistor portion 70. In the mesa portion 60 of the dummy element portion 110, the emitter region 12 may not be provided. Thus, the dummy element portion 110 is prevented from operating as a transistor. In the mesa portion 60 of this example, the base region 14 and the contact region 15 are provided.

[0137] The mesa portion 60 of the dummy element portion 110 can be connected to the emitter electrode 52 through the contact hole 54. Thus, the base region 14 and the contact region 15 of the dummy element portion 110 can be electrically connected to the emitter electrode 52 and fixed to the emitter potential. Thus, it is possible to prevent the dummy element portion 110 from becoming an unexpected state. In addition, the holes accumulated in the drift region 18 of the dummy element portion 110 can be led out to the emitter electrode 52. Thus, it is possible to prevent excessive holes from accumulating in the dummy element portion 110.

[0138] The reservoir region 16 may not be provided in the mesa portion 60 of the dummy element portion 110 . This can promote extraction of holes in the dummy element portion 110 .

[0139] Figure 8 1 is a diagram showing an example of the upper surface of the mesa portion 60 of the dummy element portion 110. In this example, a P-type region is provided in the region of the upper surface of the dummy element portion 110 that is in contact with the gate trench portion 40. That is, the emitter region 12 is not provided in the region that is in contact with the gate trench portion 40. Figure 8 In the example, the contact regions 15 and the base regions 14 are alternately arranged on the upper surface of the mesa portion 60 of the dummy element portion 110 along the long side direction of the gate groove portion 40. It should be noted that the present invention is not limited to this example, and the contact regions 15 and the base regions 14 may be arranged on the upper surface of the mesa portion 60 of the dummy element portion 110 along the long side direction of the gate groove portion 40. The gate groove portion 40 has a long side in the long side direction of the groove. The long side direction of the groove in this example is the Y-axis direction.

[0140] As described above, the dummy element portion 110 is a region where a current sensor is formed in other semiconductor devices. When viewed from above, the area of ​​the dummy element portion 110 is smaller than the area of ​​the active portion 120. The area of ​​the dummy element portion 110 may be less than 1 / 100 of the area of ​​the active portion 120, or less than 1 / 1000 of the area of ​​the active portion 120, or less than 1 / 10000 of the area of ​​the active portion 120. The area of ​​the dummy element portion 110 may be the area of ​​the region surrounded by the second well region 112 when viewed from above. The area of ​​the active portion 120 may be the area of ​​the region surrounded by the surrounding well region 113 where no well region is provided.

[0141] Fig. 9 Yes means Figure 3dd section is a YZ plane passing through the wide portion 115 that divides the well region 114. Two gate channels 48-5 are arranged above the wide portion 115. The two gate channels 48-5 are arranged to be separated from each other in the Y-axis direction. When the wide portion 115 is divided into two parts in the Y-axis direction, one gate channel 48-5 is arranged in one divided area, and one gate channel 48-5 is arranged in the other divided area. An interlayer insulating film 38 such as a thermal oxide film is provided between the gate channel 48-5 and the semiconductor substrate 10.

[0142] An emitter electrode 52 is disposed above the gate flow channel 48-5. An interlayer insulating film 38 such as a BPSG film is provided between the emitter electrode 52, the gate flow channel 48-5, and the semiconductor substrate 10. The emitter electrode 52 of this example covers the entire wide portion 115. A protective layer 150 formed of polyimide or the like may be provided above the emitter electrode 52. The protective layer 150 covers a portion or the entire wide portion 115.

[0143] As a semiconductor device, there is known a structure in which a temperature sensor is provided above the semiconductor substrate 10. For example, the temperature sensor is arranged above a region corresponding to the wide portion 115 in this example. The temperature sensor is, for example, a PN junction diode formed of polycrystalline silicon.

[0144] The semiconductor device 100 of this example does not have a temperature sensor disposed above the wide portion 115. Thus, although it is difficult to detect the temperature of the semiconductor device 100, the semiconductor device 100 is easy to assemble, thereby reducing the manufacturing cost.

[0145] As described above, the emitter electrode 52 is arranged above the wide portion 115 in this example. Thus, a common emitter electrode 52 can be easily arranged for a plurality of active portions 120 divided by the divided well region 114. Therefore, even if the emitter electrode 52 is not connected between the plurality of active portions 120 by a wire or the like, the emitter potential variation on the upper surface of the semiconductor substrate 10 can be suppressed.

[0146] In addition, there is known a structure in which wiring connected to the temperature sensor is provided above the split well region 114. The wiring is formed of a conductive material such as metal. The semiconductor device 100 of this example does not configure wiring or electrodes other than the emitter electrode 52 above the split well region 114. As a result, the semiconductor device 100 becomes easy to assemble. Therefore, the manufacturing cost can be reduced. Figure 2 As shown, an emitter electrode 52 is arranged above the divided well region 114 in this example.

[0147] Fig.10 FIG. 1 is a top view showing an example of the configuration of the protective layer 150. Fig.10In FIG. 5 , the region where the protective layer 150 is disposed is indicated by hatching with oblique lines. The protective layer 150 may be disposed above the emitter electrode 52 and above the semiconductor substrate 10. The protective layer 150 may be in contact with the upper surface of the emitter electrode 52.

[0148] The semiconductor device 100 may include a protective layer 150 - 1 covering the first well region 111. The protective layer 150 - 1 may expose a portion of the upper surface of the pad 50. Thus, a wire or the like may be connected to the upper surface of the pad 50.

[0149] The semiconductor device 100 may include a protective layer 150-2 covering the second well region 112. The protective layer 150-2 may cover the entire second well region 112. The semiconductor device 100 may include a protective layer 150-3 covering the peripheral well region 113. The protective layer 150-3 may cover the entire peripheral well region 113. The semiconductor device 100 may include a protective layer 150-4 and a protective layer 150-7 covering the split well region 114. The protective layer 150-4 and the protective layer 150-7 may cover the entire split well region 114. In this example, the protective layer 150-4 covers the entire wide portion 115, and the protective layer 150-7 covers the entire split well region 114 except the wide portion 115.

[0150] The protective layer 150 exposes a portion of the upper surface of the emitter electrode 52 . This allows a wire or the like to be easily connected to the upper surface of the emitter electrode 52 .

[0151] The semiconductor device 100 may include a protective layer 150-5 and a protective layer 150-6, which divide the upper surface of the semiconductor substrate 10 into a first region 152-1, a second region 152-2, and a third region 152-3. The protective layer 150-5 and the protective layer 150-6 may be arranged across the upper surface of the semiconductor substrate 10 in the Y-axis direction. The first region 152-1 is a region where the first well region 111 is arranged, the second region 152-2 is a region where the second well region 112 is arranged, and the third region 152-3 is a region arranged between the first well region 111 and the second well region 112 in the X-axis direction. In the present embodiment, the third region 152-3 is divided into two parts in the Y-axis direction by the protective layer 150-7 and the protective layer 150-4.

[0152] In the third region 152-3 of this example, a protective layer 150-4 is provided. The area of ​​the third region 152-3 of this example is larger than the area of ​​either the first region 152-1 or the second region 152-2. The protective layer 150-5 can be connected to the protective layer 150-2. The protective layer 150-5 of this example is connected to the front end of the protective layer 150-2 in the X-axis direction. The protective layer 150-6 can be connected to the protective layer 150-1. The protective layer 150-6 of this example is connected to the front end of the protective layer 150-1 in the X-axis direction.

[0153] A connection material such as solder may be provided on the upper surface of the emitter electrode 52 exposed in the third region 152-3. Thus, wiring such as a wire or a lead frame can be connected to the upper surface of the emitter electrode 52. By increasing the area of ​​the third region 152-3, these wirings can be easily connected.

[0154] In addition, the third region 152-3 is separated from the first region 152-1 by the protective layer 150-6, thereby preventing the solder or the like in the third region 152-3 from flowing to the pad 50. In addition, by providing the second region 152-2 on the side opposite to the first region 152-1, the position of the solder or the like on the upper surface of the semiconductor substrate 10 can be prevented from being biased.

[0155] Fig.11 FIG. 1 is a side view of the semiconductor substrate 10 mounted on the mounting substrate 200. Fig.11 In the embodiment, the collector electrode 24, the interlayer insulating film 38, etc. are omitted. The semiconductor substrate 10 is fixed to the mounting substrate 200 by a connection portion 160 such as solder. In addition, a connection portion 162 such as solder is provided on the upper surface of the third region 152-3 of the emitter electrode 52. A plated portion 161 may be provided between the connection portion 162 and the emitter electrode 52.

[0156] The plated portion 161 may be a plated layer of a metal material different from that of the emitter electrode 52. The plated portion 161 may also be provided on the upper surface of the emitter electrode 52 where the connecting portion 162 is not provided. The connecting portion 162 connects the wiring 163 such as the lead frame to the emitter electrode 52. The wiring 163 may be formed across Fig.10 The two third regions 152-3 shown are provided. The wiring 163 may also be provided above the protective layer 150-7 and the protective layer 150-4. In this case, a connection portion 162 may also be provided between the protective layer 150-7 and the protective layer 150-4 and the wiring 163. The upper end of the connection portion 162 provided in the third region 152-3 may be arranged at a position higher than the upper end of the protective layer 150.

[0157] like Fig.11As shown, the protective layer 150-6 and the protective layer 150-5 can prevent the connection portion 162 from flowing to the first region 152-1 and the second region 152-2. As a result, the positional deviation of the connection portion 162 in the X-axis direction can be suppressed. If the position of the connection portion 162 is biased, the center of gravity of the semiconductor device 100 will deviate from the center in the X-axis direction. Therefore, in the process of mounting the semiconductor substrate 10 on the mounting substrate 200 through the connection portion 160, the semiconductor substrate 10 may sometimes tilt in the Y-axis direction. By providing the first region 152-1 and the second region 152-2, the positional deviation of the connection portion 162 can be suppressed, and the tilt of the semiconductor substrate 10 during mounting can be suppressed.

[0158] It is preferred that the widths of the first region 152-1 and the second region 152-2 in the X-axis direction are the same. The difference in the widths of the first region 152-1 and the second region 152-2 in the X-axis direction may be less than 5% of the length of the semiconductor substrate 10 in the X-axis direction. The width W1 of the protective layer 150-6 and the protective layer 150-5 may be greater than 100 μm, greater than 200 μm, or greater than 300 μm. The protective layer 150-7 may also have a width W1. The width of the protective layer 150 is the width of the protective layer 150 in the short side direction when viewed from above.

[0159] exist Fig.10 and Fig.11 The protective layer 150 described in the above can function as a beam portion for preventing the semiconductor device 100 from warping. Fig.10 As shown in the top view of FIG. 1 , the beam portion is a protective layer 150 sandwiched between the emitter electrodes 52 not covered by the protective layer 150 in the short side direction orthogonal to the long side direction of the beam portion. Both ends of the beam portion in the long side direction may be connected to the protective layer 150.

[0160] exist Fig.10 In the embodiment, the protective layer 150-5 and the protective layer 150-6 function as a first beam portion, and the first beam portion has a first direction (in this example, the Y-axis direction) as a long side direction. In the short side direction (in this example, the X-axis direction), the protective layer 150-5 is sandwiched between the emitting electrode 52 exposed in the second region 152-2 and the emitting electrode 52 exposed in the third region 152-3. The protective layer 150-6 is sandwiched between the emitting electrode 52 exposed in the first region 152-1 and the emitting electrode 52 exposed in the third region 152-3 in the short side direction (in this example, the X-axis direction).

[0161] exist Fig.10In the embodiment, the protective layer 150-4 and the protective layer 150-7 function as a second beam portion, and the second beam portion has a second direction (in this example, the X-axis direction) as a longitudinal direction. The second direction is a direction different from the first direction. Fig.10 In the example, the first direction is orthogonal to the second direction, but the angle between the first direction and the second direction is not limited to a right angle. The protective layer 150-4 and the protective layer 150-7 are sandwiched between the emitter electrodes 52 exposed in the two third regions 152-3 in the short side direction (in this example, the Y-axis direction).

[0162] At least one of the first beam and the second beam may be arranged so as not to cross the emitting electrode 52. At least one end of the beam may be connected to another protective layer 150 above the emitting electrode 52. Fig.10 In the example, one end of the second beam portion composed of the protection layer 150-7, the protection layer 150-4 and the protection layer 150-7 arranged on a straight line is connected to the protection layer 150-6 functioning as the first beam portion. The other end of the second beam portion is connected to the protection layer 150-2.

[0163] At least one of the first beam portion and the second beam portion may be connected to the protection layer 150 - 3 covering the surrounding well region 113 . Fig.10 In the example of FIG. 1 , the ends of the protective layer 150-5 and the protective layer 150-6 are connected to the protective layer 150-3. At least one of the first beam portion and the second beam portion may cross the emitter electrode 52 in a plan view. Fig.10 In the example of , the protective layer 150-6 crosses the emitter electrode 52. That is, one end of the protective layer 150-6 is connected to the protective layer 150-3, and the protective layer 150-6 crosses the emitter electrode 52, and the other end of the protective layer 150-6 is connected to the protective layer 150-3.

[0164] By providing at least a portion of the protective layer 150 as a beam portion that divides the upper surface of the emitter electrode 52, it is possible to suppress the warping of the semiconductor substrate 10 in the Z-axis direction. By providing a beam portion that crosses the upper surface of the emitter electrode 52 as in the protective layer 150-6, it is possible to further suppress the warping of the semiconductor substrate 10. In addition, by providing a beam portion that extends on the upper surface of the emitter electrode 52 and connects the protective layers 150 to each other as in the protective layer 150-7 and the protective layer 150-4, it is possible to further suppress the warping of the semiconductor substrate 10.

[0165] In addition, by not covering the entire upper surface of the emitting electrode 52 with the protective layer 150 but providing a beam portion, a beam portion is provided on the upper surface of the emitting electrode 52. Fig.11The connection portion 162 shown in the figure is easily formed. The connection portion 162 is connected to the connection region of the upper surface of the emitter electrode 52 that is not covered by the protective layer 150. As described above, the connection portion 162 can be connected to the emitter electrode 52 via the plated portion 161.

[0166] exist Fig.10 In the example of , the third region 152-3 functions as a connection region. As described above, the third region 152-3 is the region with the largest area among the regions 152 on the upper surface of the emitter electrode 52. The upper surface of the emitter electrode 52 may have a plurality of third regions 152-3. In this case, the connection portion 162 may be provided in each third region 152-3. In addition, wiring such as a lead frame may be connected to each third region 152-3.

[0167] The third region 152-3 may be surrounded by the protective layer 150 including at least one first beam portion and at least one second beam portion when viewed from above. For example, when the third region 152-3 is rectangular, the first beam portion may be disposed along at least one side of the third region 152-3, and the second beam portion may be disposed along at least one other side. In addition, the first beam portion and the second beam portion may also be disposed crosswise when viewed from above.

[0168] exist Fig.10 In the example of , the protective layer 150 surrounding the third region 152-3 includes the protective layer 150-5 and the protective layer 150-6 functioning as the first beam portion, and the protective layer 150-4 and the protective layer 150-7 functioning as the second beam portion. The protective layer 150 surrounding the third region 152-3 in this example includes the protective layer 150 other than the beam portion. In other examples, the protective layer 150 surrounding the third region 152-3 may include only the beam portion. By surrounding the third region 152-3 where the connection portion 162 is provided with the protective layer 150, the warping of the semiconductor substrate 10 caused by the stress generated in the third region 152-3 can be suppressed.

[0169] like Fig.11 As shown, here, the protective layer 150-5 and the protective layer 150-6 functioning as the first beam portion are arranged on the upper surface of the emitting electrode 52. That is, the protective layer 150-5 and the protective layer 150-6 are protective layers provided to function as the first beam portion, rather than protective layers provided to form insulation to separate the emitting electrode 52. Similarly, the protective layer 150-4 and the protective layer 150-7 functioning as the second beam portion may also be arranged on the upper surface of the emitting electrode 52.

[0170] In addition, the protective layers 150-1, 150-2, and 150-3 may be provided to form insulation to separate the emitter electrode 52. That is, the protective layers 150-1, 150-2, and 150-3 may be provided to cut off the emitter electrode 52. It should be noted that the protective layers 150-5 and 150-6 functioning as the first beam portion and the protective layers 150-4 and 150-7 functioning as the second beam portion may also be provided to cut off the emitter electrode 52.

[0171] As described above, by appropriately disposing the protective layer 150, it is possible to suppress the positional bias of the solder or the like on the upper surface of the semiconductor substrate 10, suppress the warping of the semiconductor substrate 10, and ensure the third region 152-3 to which the wiring 163 such as a wire or a lead frame can be connected. Thus, the semiconductor device 100 becomes easy to assemble.

[0172] Fig.12 1 is a plan view showing an example of a semiconductor module 300 according to an embodiment of the present invention. The semiconductor module 300 includes a first semiconductor device 100-1 and a second semiconductor device 100-2. The semiconductor module 300 may include a plurality of sets of the first semiconductor device 100-1 and the second semiconductor device 100-2.

[0173] The semiconductor module 300 of this example includes a housing 88. The housing 88 accommodates each semiconductor device 100. A refrigerant for cooling the semiconductor device 100 flows inside the housing 88. The second semiconductor device 100-2 is arranged upstream of the flow path of the refrigerant compared to the first semiconductor device 100-1. That is, the refrigerant that has passed through the vicinity of the second semiconductor device 100-2 passes through the vicinity of the first semiconductor device 100-1. Therefore, the cooling efficiency of the first semiconductor device 100-1 may sometimes be worse than the cooling efficiency of the second semiconductor device 100-2.

[0174] The second semiconductor device 100-2 is Figures 1 to 11 The first semiconductor device 100-1 has a Figures 1 to 11In addition to the configuration of the semiconductor device 100 described in the above, the semiconductor module 300 further includes at least one of a temperature sensor and a current sensor. The semiconductor module 300 controls both the first semiconductor device 100-1 and the second semiconductor device 100-2 based on the detection results of the temperature sensor and the current sensor of the first semiconductor device 100-1. For example, when overheating is detected in the first semiconductor device 100-1, the semiconductor module 300 suppresses the output current of the first semiconductor device 100-1 and the second semiconductor device 100-2. By using the detection results of the sensor of the first semiconductor device 100-1 with poor cooling efficiency, overheating in the first semiconductor device 100-1 can also be suppressed.

[0175] In this case, by using the semiconductor device 100 as the second semiconductor device 100-2, the manufacturing cost of the second semiconductor device 100-2 can be reduced. Figures 1 to 11 With the structure described in , the performance of the second semiconductor device 100 - 2 such as endurance can be maintained at the same level as that of the first semiconductor device 100 - 1 .

[0176] The housing 88 has a main terminal 86 and a control terminal 99. At least a portion of the main terminal 86 is electrically connected to the emitter electrode 52 of the semiconductor device 100. At least a portion of the control terminal 99 is electrically connected to the pad 50 of the semiconductor device 100. In addition, at least a portion of the control terminal 99 is electrically connected to the sensor of the first semiconductor device 100-1.

[0177] Fig.13 is a diagram showing an example of the upper surface of the first semiconductor device 100-1. Figures 1 to 11 In addition to the structure of the semiconductor device 100 described in the above, the semiconductor device 100 further includes a temperature sensor 178, an anode wiring 180, a cathode wiring 182, an anode pad 174, a cathode pad 176, and a current detection pad 172. In addition, the dummy element portion 110 functions as a current sensor. Fig.13 In the embodiment, the pad 50 is an example of a first pad, and the anode pad 174, the cathode pad 176, and the current detection pad 172 are examples of a second pad. In addition, the emitter electrode 52 is provided for each divided region of the active portion 120. Each pad is provided separately from the emitter electrode 52.

[0178] Anode pad 174, cathode pad 176, and current detection pad 172 are arranged above second well region 112. Current detection pad 172 is connected to mesa portion 60 of dummy element portion 110. Anode pad 174 is connected to an anode of temperature sensor 178 via anode wiring 180. Cathode pad 176 is connected to a cathode of temperature sensor 178 via cathode wiring 182.

[0179] Anode wiring 180 and cathode wiring 182 are disposed above divided well region 114. Anode wiring 180 and cathode wiring 182 may be metal wirings such as aluminum.

[0180] The temperature sensor 178 is disposed above the wide portion 115. The entire temperature sensor 178 may overlap with the wide portion 115. The temperature sensor 178 in this example is a PN junction diode formed of a semiconductor material such as polysilicon.

[0181] Fig.14 Yes means Fig.13 An example of an ee cross section in FIG. Fig. 9 The cross section shown is different in that a temperature sensor 178, an anode wiring 180, and a cathode wiring 182 are provided. In addition, the emitter electrode 52 is divided in the Y-axis direction by the temperature sensor 178, the anode wiring 180, and the cathode wiring 182.

[0182] The temperature sensor 178 has an anode 184 and a cathode 186. The anode 184 in this example is polysilicon doped with P-type impurities. The cathode 186 in this example is polysilicon doped with N-type impurities. The anode wiring 180 is connected to the anode 184, and the cathode wiring 182 is connected to the cathode 186. The temperature of the temperature sensor 178 can be estimated based on the voltage applied to the temperature sensor 178 and the current flowing through the temperature sensor 178.

[0183] Fig.15 1 is a top view showing the mesa portion 60 in the dummy element portion 110 of the first semiconductor device 100-1. The mesa portion 60 is provided with an emitter region 12 in contact with the gate trench portion 40. Thus, the dummy element portion 110 operates as a transistor. By detecting the current flowing through the dummy element portion 110, the current flowing through the active portion 120 can be estimated.

[0184] According to Figures 1 to 11 The semiconductor device 100 described in the specification can make the area of ​​the active portion 120 of the second semiconductor device 100-2 the same as the area of ​​the active portion 120 of the first semiconductor device 100-1. In addition, the gate capacitance of the second semiconductor device 100-2 can be made the same as the gate capacitance of the first semiconductor device 100-1. In addition, the tolerance of the second semiconductor device 100-2 equivalent to that of the first semiconductor device 100-1 can be achieved. In addition, the manufacturing process of the first semiconductor device 100-1 and the manufacturing process of the second semiconductor device 100-2 can be partially common. Thus, the manufacturing cost of the semiconductor device can be reduced. In addition, by making the manufacturing process of the semiconductor device partially common, the semiconductor device can be easily assembled.

[0185] Fig.16 1 is a diagram showing another example of the configuration of the protective layer 150 when viewed from above. The semiconductor device 100 is configured above the semiconductor substrate 10 and has a pad separated from the emitter electrode 52. The semiconductor device 100 of this example has the same Fig.13 That is, the semiconductor device 100 has a current detection pad 172 , an anode pad 174 , and a cathode pad 176 separated from the emitter electrode 52 .

[0186] In the case of having more than one pad, the protective layer 150 is provided with an opening to expose the upper surface of each pad. In this example, the protective layer 150-2 is provided with an opening for each pad, namely, the current detection pad 172, the anode pad 174, and the cathode pad 176. The protective layer 150 has an electrode separation portion provided between each pad and the emitter electrode 52 in a plan view. Fig.16 In the example of FIG. 1 , the protective layer 150 - 8 functions as an electrode separation portion.

[0187] The width of the protective layer 150 (protective layer 150-8 in this example) that functions as an electrode separation portion is set to W2. The width W2 refers to the smallest width among the widths of the electrode separation portion when viewed from above. In addition, the width of the protective layer 150 (protective layer 150-4, protective layer 150-5, protective layer 150-6, protective layer 150-7 in this example) that functions as a beam portion is set to W3. The width W3 refers to the smallest width among the widths of the beam portion when viewed from above. Fig.16 In the example, the width of the protective layer 150 - 7 is set to W3, but the width of the other protective layer 150 that functions as a beam portion may be W3.

[0188] In this example, the width W3 is larger than the width W1. By increasing the width of the beam portion, it is possible to easily suppress the warping of the semiconductor substrate 10. In addition, by reducing the width of the electrode separation portion, it is possible to ensure that the upper surface exposure area of ​​the pad is smaller than the exposure area of ​​the emitter electrode 52, and it is easy to connect wiring to each pad.

[0189] The width W3 may be greater than or equal to 100 μm, greater than or equal to 200 μm, or greater than or equal to 300 μm. The width W3 may be greater than or equal to the thickness of the semiconductor substrate 10 in the Z-axis direction.

[0190] Here, the protective layers 150-5 and 150-6 functioning as the first beam portion are arranged on the upper surface of the emitting electrode 52. On the other hand, the protective layers 150-4 and 150-7 functioning as the second beam portion are provided so as to cut off the emitting electrode 52. That is, the protective layers 150-4 and 150-7 are provided in order to perform both the function as the second beam portion and the function of insulation separation.

[0191] Fig.17 FIG. 1 is a diagram showing an example of the arrangement of the transistor unit 70, the diode unit 80, and the protective layer 150 on the upper surface of the semiconductor device 100. The arrangement of the transistor unit 70 and the diode unit 80 may be different from that of FIG. Figure 3 The transistor portion 70 includes a collector region 22 in contact with the lower surface 23 of the semiconductor substrate 10 . The diode portion 80 includes a cathode region 82 in contact with the lower surface 23 of the semiconductor substrate 10 .

[0192] exist Fig.17 The solid rectangle enclosing the symbol "F" in the figure indicates the region where the cathode region 82 is provided. The collector region 22 is provided in the region other than the cathode region 82 on the lower surface 23 of the semiconductor substrate 10. The diode portion 80 is the region where the cathode region 82 is provided in a plan view. Fig.17 In the embodiment, each cathode region 82 is extended in the Y-axis direction to the well region 11 (refer to Fig.10 The region obtained by the extension region 81 is defined as the extension region 81. In this specification, the region where the extension region 81 is provided is also included in the diode portion 80 in a plan view.

[0193] In this example, the first beam portion (in this example, the protective layer 150-5 and the protective layer 150-6) having a long side in the Y-axis direction is provided at a position not overlapping with the cathode region 82 in a plan view. The first beam portion may be provided at a position not overlapping with the diode portion 80. Fig.17 In the example of , the first beam portion is provided at a position overlapping with the transistor portion 70. The long side direction of the first beam portion may be the same as the long side direction (in this example, the Y-axis direction) of the transistor portion 70. In addition, it is preferred that no protective layer 150 is provided at a position overlapping with the cathode region 82.

[0194] Fig.18 is an example of an XZ cross section of the semiconductor device 100. The semiconductor device 100 of this example has Figures 1 to 17 In addition to the structure of the semiconductor device 100 described in the above, the semiconductor device 100 further includes a lifetime adjustment region 72. The other structures are the same as those described in the above. Figures 1 to 17 The configuration of the protective layer 150 is the same as that of Fig.17 The same as the example shown in .

[0195] The lifetime adjustment region 72 is provided on the upper surface 21 side of the semiconductor substrate 10. The upper surface 21 side refers to the region between the center of the semiconductor substrate 10 in the depth direction and the upper surface 21. The lifetime adjustment region 72 contains lifetime killers, which are vacancy defects etc. generated by injecting particles such as helium or hydrogen from the upper surface 21 side of the semiconductor substrate 10. Fig.18 In the figure, the injection depth position of the particle is indicated by a cross symbol. The distribution of the lifetime killer density in the depth direction has a peak at the injection position of the particle. Since vacancy defects and the like are also generated in the area through which the particle passes, the lifetime killer may also be distributed from the injection position of the particle to the upper surface 21. Regarding the change in the lifetime killer density, the distribution from the peak position toward the upper surface 21 may be more gentle than the distribution from the peak position toward the lower surface 23. In addition, the distribution of the particle concentration of helium and the like in the depth direction has a peak at the injection position of the particle.

[0196] In the process of injecting particles such as helium, a mask 190 is provided in the region where the particles are not to be injected. The mask 190 is made of a material capable of shielding the particles and is formed with a thickness capable of shielding the particles. The mask 190 may be formed of a resist, a metal, or other materials.

[0197] The lifetime adjustment region 72 is provided in the diode portion 80. Thus, during the reverse recovery of the diode portion 80, the lifetime of the carriers of the diode portion 80 can be shortened, and the reverse recovery characteristics can be improved. The lifetime adjustment region 72 can also be provided in the intermediate region 90. By providing the lifetime adjustment region 72 in the intermediate region 90, the flow of carriers from the transistor portion 70 to the diode portion 80 can be suppressed.

[0198] In this example, the protective layer 150 is not provided at a position overlapping with the cathode region 82, but is arranged above the transistor portion 70. Therefore, the implantation depth position of particles such as helium in the diode portion 80 is prevented from being changed by the protective layer 150.

[0199] Preferably, the protective layer 150 is disposed in a range that does not overlap with the lifetime adjustment region 72 . Thus, the depth position of the lifetime adjustment region 72 can be controlled with high precision. The protective layer 150 may also be covered by the mask 190 .

[0200] It should be noted that, in the case where there is a cathode region 82 that does not function as a part of the diode section 80, a protective layer 150 may be provided above the cathode region 82. The cathode region 82 that does not function as a part of the diode section 80 refers to, for example, a cathode region 82 where no emitter electrode 52 is arranged on the upper surface 21. That is, the cathode region 82 that does not overlap with the emitter electrode 52 when viewed from above may not function as a part of the diode section 80. As an example, the cathode region 82 provided in a region other than the active section 120 may be set as the cathode region 82 that does not function as a part of the diode section 80. For example, in the case where the cathode region 82 is provided in the edge termination structure portion between the peripheral well region 113 and the end side of the semiconductor substrate 10, the protective layer 150 may be provided in the edge termination structure portion.

[0201] Fig.19 FIG. 1 shows a cross section of a semiconductor device 100 in which a protective layer 150 is provided on a diode portion 80. If a protective layer 150 is provided on a diode portion 80, particles such as helium are decelerated by the protective layer 150. As a result, a lifetime killer 73 may be formed at a position different from the lifetime adjustment region 72. In this case, the characteristics of the diode portion 80 cannot be controlled with high accuracy. Fig.18 In the example shown, since the depth position of the lifetime killer can be controlled with high accuracy, the characteristics of the diode unit 80 can be controlled with high accuracy.

[0202] Fig. 20 FIG. 1 is a top view showing another configuration example of the protective layer 150. Fig. 20 In the embodiment, the protective layer 150 is omitted except for the protective layer 150-9 that functions as the first beam portion and the protective layer 150-10 that functions as the second beam portion. In addition, the structure other than the schematic active portion 120, the semiconductor substrate 10 and the protective layer 150 is also omitted. The structure other than the active portion 120, the semiconductor substrate 10 and the protective layer 150 is similar to the structure of FIG. Figures 1 to 19 The same as any of the methods described in .

[0203] The protective layer 150-9 and the protective layer 150-10 of this example may have long sides in a direction different from the long side direction of the transistor portion 70 (for example, the Y-axis direction). The protective layer 150-9 and the protective layer 150-10 may have long sides in a direction different from the extending direction of each groove portion. The protective layer 150-9 and the protective layer 150-10 may have long sides in a direction different from the end side 102 of the semiconductor substrate 10. The fourth region 152-4 of the upper surface of the emitter electrode 52 may be surrounded by two protective layers 150-9 and two protective layers 150-10. In the fourth region 152-4, a Fig.11The connection portion 162 shown in FIG.

[0204] Although the present invention is described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear that such changes or improvements can also be included in the technical scope of the present invention according to the description of the claims.

Claims

1. A semiconductor device, characterized in that: have: Semiconductor substrates; an active portion, which is disposed on the semiconductor substrate; A first well region and a second well region, which are provided in the semiconductor substrate, and the first well region and the second well region are arranged to sandwich the active portion in a plan view; an emitting electrode disposed above the active portion; as well as a pad, which is arranged above the first well region and is separated from the emitter electrode, The emitter electrode is disposed above the second well region. The semiconductor device further includes a divided well region, the divided well region dividing the active portion in a plan view, The split well region has a long side in a predetermined well long side direction, The divided well region has a wide portion whose width in a direction perpendicular to the long side direction of the well in a plan view is wider than that of other portions. The emitting electrode is arranged above the wide portion.

2. The semiconductor device according to claim 1, wherein: The semiconductor device further includes a peripheral well region, the peripheral well region being arranged to surround the active portion in the plan view. The first well region and the second well region protrude toward a center side of the active portion relative to the peripheral well region.

3. The semiconductor device according to claim 1, wherein: The semiconductor substrate has a first end side and a second end side facing each other in a plan view, The first well region is disposed between the active portion and the first end side, The second well region is disposed between the active portion and the second end side.

4. The semiconductor device according to claim 2, wherein: The semiconductor substrate has a first end side and a second end side facing each other in a plan view, The first well region is disposed between the active portion and the first end side, The second well region is disposed between the active portion and the second end side.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The semiconductor device includes: a transistor portion arranged in the active portion; and a dummy element portion arranged to be surrounded by the second well region in a plan view. The transistor portion and the dummy element portion both include a gate trench portion provided on the upper surface of the semiconductor substrate. The transistor portion has an emitter region of a first conductivity type, and the emitter region of the first conductivity type is provided on the upper surface of the semiconductor substrate in contact with the gate trench portion. A second conductivity type region is provided in a region of the upper surface of the dummy element portion that is in contact with the gate trench portion.

6. The semiconductor device according to claim 5, wherein: In a plan view, an area of ​​the dummy element portion is smaller than an area of ​​the transistor portion.

7. The semiconductor device according to claim 5, wherein: The second conductivity type region of the dummy element portion is electrically connected to the emitter electrode.

8. The semiconductor device according to claim 6, wherein: The second conductivity type region of the dummy element portion is electrically connected to the emitter electrode.

9. The semiconductor device according to claim 5, wherein: The gate trench portion has a long side on the upper surface of the semiconductor substrate in a predetermined trench long side direction. The second conductivity type region of the dummy element portion has: a base region of a second conductivity type; as well as The contact regions of the second conductivity type are arranged alternately with the base regions along the longitudinal direction of the trenches, and the doping concentration of the contact regions is higher than that of the base regions.

10. The semiconductor device according to claim 6, wherein: The gate trench portion has a long side on the upper surface of the semiconductor substrate in a predetermined trench long side direction. The second conductivity type region of the dummy element portion has: a base region of a second conductivity type; as well as The contact regions of the second conductivity type are arranged alternately with the base regions along the longitudinal direction of the trenches, and the doping concentration of the contact regions is higher than that of the base regions.

11. The semiconductor device according to claim 7, wherein: The gate trench portion has a long side on the upper surface of the semiconductor substrate in a predetermined trench long side direction. The second conductivity type region of the dummy element portion has: a base region of a second conductivity type; as well as The contact regions of the second conductivity type are arranged alternately with the base regions along the longitudinal direction of the trenches, and the doping concentration of the contact regions is higher than that of the base regions.

12. The semiconductor device according to claim 1, wherein: The emitting electrode covers the entire wide portion.

13. The semiconductor device according to claim 1 or 12, characterized in that: The wide portion is disposed between the first well region and the second well region in a plan view.

14. The semiconductor device according to claim 13, wherein: The divided well region is provided from the first well region to the second well region in a plan view.

15. The semiconductor device according to any one of claims 1 to 4, wherein: A gate pad is disposed above the first well region, The semiconductor device further includes a gate channel connected to the gate pad. The gate flow channel has a portion provided along an end side of the second well region in a plan view.

16. The semiconductor device according to claim 1, wherein: A gate pad is disposed above the first well region, The semiconductor device further includes a gate channel connected to the gate pad. The gate flow path has a portion provided along an end side of the wide portion in a plan view.

17. The semiconductor device according to any one of claims 1 to 4, characterized in that: The semiconductor device further comprises a protective layer, wherein the protective layer is provided above the emitter electrode. The protection layer divides the upper surface of the semiconductor substrate into a first region where the first well region is disposed, a second region where the second well region is disposed, and a third region between the first well region and the second well region.

18. The semiconductor device according to claim 17, wherein: In a plan view, an area of ​​the third region is larger than an area of ​​any one of the first region and the second region.

19. The semiconductor device according to claim 18, wherein: The semiconductor device further includes a connection portion connected to a region of the emitter electrode that is not covered by the protective layer. The connection portion is connected to the third region.

20. The semiconductor device according to claim 19, wherein: The protective layer includes a first beam portion and a second beam portion, the first beam portion has a first direction as a long side direction, the second beam portion has a second direction as a long side direction, and the second direction is different from the first direction. In a plan view, each beam portion is sandwiched by the emitting electrode not covered by the protective layer in a short-side direction perpendicular to the long-side direction.

21. The semiconductor device according to claim 20, wherein: The third region of the emitter electrode is surrounded by the protection layer including at least one first beam portion and at least one second beam portion.

22. A semiconductor device, characterized in that: have: Semiconductor substrates; an active portion, which is disposed on the semiconductor substrate; a transistor portion, which is disposed in the active portion; Dummy component department; as well as a well region separating the transistor portion from the dummy element portion, The dummy element portion is arranged to be surrounded by the well region in a plan view, The transistor portion and the dummy element portion both include a gate trench portion, and the gate trench portion is provided on the upper surface of the semiconductor substrate. The transistor portion has an emitter region of a first conductivity type, and the emitter region of the first conductivity type is provided on the upper surface of the semiconductor substrate in contact with the gate trench portion. A second conductivity type region is provided in a region of the upper surface of the dummy element portion that is in contact with the gate trench portion.

23. A semiconductor device, characterized in that: have: Semiconductor substrates; an active portion, which is disposed on the semiconductor substrate; an emitting electrode disposed above the active portion; and a split well region which divides the active portion in a plan view, The split well region has a long side in a predetermined well long side direction, The divided well region has a wide portion whose width in a direction perpendicular to the long side direction of the well in a plan view is wider than that of other portions. The emitting electrode is arranged above the wide portion.

24. A semiconductor module, characterized in that: The semiconductor module includes a first semiconductor device and a second semiconductor device. The first semiconductor device is the semiconductor device according to any one of claims 1 to 21, The second semiconductor device has: Semiconductor substrates; an active portion, which is disposed on the semiconductor substrate; A first well region and a second well region, which are provided in the semiconductor substrate, and the first well region and the second well region are arranged to sandwich the active portion in a plan view; an emitting electrode disposed above the active portion; a first pad, which is disposed above the first well region and is separated from the emitter electrode; as well as The second pad is disposed above the second well region and is separated from the emitter electrode.

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