Clock delay detection, compensation method, device, terminal and readable storage medium

Abstract

The embodiment of the present invention provides a clock delay detection and compensation method, device, terminal and readable storage medium. The clock delay detection method transmits a first synchronous clock to a clock module to be detected through a first physical link, receives a feedback clock adjusted according to the phase of the first synchronous clock transmitted by the clock module to be detected through a second physical link, and then determines the delay of the clock module to be detected through the feedback clock, the self-returned clock, and the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link. The present invention also provides a clock delay detection and compensation method, device, terminal and readable storage medium. By taking into account the delay of the main clock module itself and the delay caused by the physical characteristics of the first physical link and the second physical link, the error of the delay caused by the clock distribution of the detection switch device can be further reduced, thereby improving the accuracy of clock delay detection.

Description

Technical Field

[0001] The embodiments of the present invention relate to, but are not limited to, the field of communication technology, and specifically, relate to, but are not limited to, a clock delay detection and compensation method, device, terminal, and readable storage medium. Background Art

[0002] As network throughput continues to increase, the types of service cards and rack slots in large-capacity switches are increasing. The system architecture of the switch's entire clock is usually composed of a synchronous clock network distributed by a master clock. The slave clocks of each service card receive the synchronous clock sent by the master clock through the backplane and synchronize their frequency and phase. Since the length of the wiring from the master clock to the backplane and connectors in different slots is different, there is a different delay error when the synchronous clock reaches each service card, ranging from a few nanoseconds to hundreds of nanoseconds, resulting in a delay error between the phases of service cards in different slots and the reference phase of the master clock. This error makes the switch unusable in high-precision clock synchronization scenarios.

[0003] Existing communication equipment mainly adopts the traditional manual compensation method for the delay phase of the synchronous clock. The instrument with time and phase detection function is used to measure the delay time of the synchronous clock signal of the main clock module across the backplane, to the service card from the clock to the synchronized chip, and then compensated in the form of quantitative constants when the service is started. This compensation method still has errors above the nanosecond level, because the same routing transmission delay is different under different temperature conditions and different power supply voltages; even under the same temperature conditions and the same power supply voltage, due to the production process, on boards produced in different batches, due to problems such as inconsistent line width control and inconsistent impedance matching, it is difficult to determine the real delay by the manual compensation method, and the error range of tens to hundreds of nanoseconds can only be reduced to a few nanoseconds. The delay error detected is still large, which only meets the application scenario of high-precision clock synchronization. However, for the application scenario of ultra-high-precision clock synchronization, this delay detection and compensation method still has a large error on the equipment, and the delay error needs to be further reduced. Summary of the invention

[0004] The embodiments of the present invention provide a clock delay detection and compensation method, device, terminal and readable storage medium, which mainly solve the technical problem of how to further reduce the delay detection error caused by the clock distribution of the switch device, thereby improving the accuracy of clock delay detection.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides a clock delay detection method, comprising:

[0006] Transmitting the first synchronization clock to the clock module to be detected through the first physical link;

[0007] receiving a feedback clock transmitted by the clock module to be detected through a second physical link, wherein the feedback clock is a clock obtained by adjusting the current clock of the clock module to be detected to have the same phase as the first synchronization clock;

[0008] Determine the delay of the clock module to be detected, wherein the delay is determined according to the feedback clock, the self-returned clock and the delay parameter, and the delay parameter includes the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link.

[0009] The embodiment of the present invention further provides a clock delay compensation method, comprising:

[0010] Obtaining the delay described in any of the above embodiments;

[0011] The delay is compensated to the clock module to be detected corresponding to the delay.

[0012] The embodiment of the present invention further provides a clock delay detection device, the clock delay detection device comprising:

[0013] A master clock module, a first physical link, a second physical link and a clock module to be detected;

[0014] The master clock module includes a sending module, a receiving module and a calculating module, wherein:

[0015] The sending module is used to transmit the first synchronization clock to the clock module to be detected through the first physical link;

[0016] The receiving module is used to receive a feedback clock transmitted by the clock module to be detected through the second physical link, where the feedback clock is a clock obtained by adjusting the current clock of the clock module to be detected to have the same phase as the first synchronization clock;

[0017] The calculation module is used to determine the delay of the clock module to be detected, and the delay is determined according to the feedback clock, the self-returning clock and the delay parameter, and the delay parameter includes the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link.

[0018] An embodiment of the present invention further provides a clock delay compensation device, the device comprising:

[0019] The clock delay detection device and compensation module as described in any one of the above embodiments;

[0020] The compensation module is used to obtain the delay detected by the clock delay detection device, and compensate the delay to the clock module to be detected corresponding to the delay.

[0021] An embodiment of the present invention further provides a terminal, the terminal comprising: a first processor, a first memory and a first communication bus;

[0022] The first communication bus is used to realize the connection and communication between the first processor and the first memory;

[0023] The first processor is used to execute one or more first computer programs stored in the first memory to implement the steps of the clock delay detection method as described in any one of the above embodiments.

[0024] An embodiment of the present invention further provides a terminal, the terminal comprising: a second processor, a second memory and a second communication bus;

[0025] The second communication bus is used to realize the connection and communication between the second processor and the second memory;

[0026] The second processor is used to execute one or more second computer programs stored in the second memory to implement the steps of the clock delay compensation method as described in any one of the above embodiments.

[0027] An embodiment of the present invention further provides a readable storage medium, wherein the readable storage medium stores one or more first computer programs, and the one or more first computer programs can be executed by one or more first processors to implement the steps of the clock delay detection method as described in any one of the above items;

[0028] or,

[0029] The readable storage medium stores one or more second computer programs, and the one or more second computer programs can be executed by one or more second processors to implement the steps of the clock delay compensation method as described in any of the above embodiments.

[0030] The beneficial effects of the present invention are:

[0031] The embodiment of the present invention provides a clock delay detection and compensation method, device, terminal and readable storage medium, wherein the clock delay detection method transmits a first synchronous clock to a clock module to be detected through a first physical link, receives a feedback clock adjusted according to the phase of the first synchronous clock transmitted by the clock module to be detected through a second physical link, and then determines the delay of the clock module to be detected through the feedback clock, the self-returned clock, the delay parameter corresponding to the first physical link, and the delay parameter corresponding to the second physical link. By taking into account the delay existing in the main clock module itself and the delay caused by the physical characteristics of the first physical link and the second physical link, the error of the delay caused by the clock distribution of the detection switch device can be further reduced, thereby improving the accuracy of clock delay detection. Furthermore, the embodiment of the present invention also provides a clock delay compensation method, by compensating the delay obtained by the above-mentioned clock delay detection method to the clock module to be detected, it is possible to improve the accuracy of clock synchronization and reduce the error of clock synchronization.

[0032] Other features and corresponding beneficial effects of the present invention are described in the latter part of the specification, and it should be understood that at least part of the beneficial effects become obvious from the description in the specification of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a delay detection method provided in Embodiment 1 of the present invention;

[0034] Figure 2 A schematic diagram of a flow chart of a delay compensation method provided in Embodiment 2 of the present invention;

[0035] Figure 3 A topological diagram of a rack-mounted switch provided in Embodiment 3 of the present invention;

[0036] Figure 4 A topological diagram of clock delay detection and compensation provided in Embodiment 3 of the present invention;

[0037] Figure 5 A device diagram of a clock delay detection and compensation hardware architecture provided in Embodiment 3 of the present invention;

[0038] Figure 6 A flowchart of a specific clock delay detection and compensation method provided in Embodiment 3 of the present invention;

[0039] Figure 7 A topological diagram of another clock delay detection and compensation provided in Embodiment 3 of the present invention;

[0040] Figure 8 A device diagram of another clock delay detection and compensation hardware architecture provided in Embodiment 3 of the present invention;

[0041] Fig. 9 A flowchart of another specific clock delay detection and compensation method provided in Embodiment 3 of the present invention;

[0042] Fig.10 A topological diagram of another clock delay detection and compensation provided in Embodiment 3 of the present invention;

[0043] Fig.11 A device diagram of another clock delay detection and compensation hardware architecture provided in Embodiment 3 of the present invention;

[0044] Fig.12 A flowchart of another specific clock delay detection and compensation method provided in Embodiment 3 of the present invention;

[0045] Fig.13 A schematic diagram of the structure of a clock delay detection device provided in Embodiment 4 of the present invention;

[0046] Fig.14 A schematic diagram of the structure of a clock delay compensation device provided in Embodiment 5 of the present invention;

[0047] Fig.15 A schematic diagram of the structure of a terminal provided in Embodiment 6 of the present invention;

[0048] Fig.16 A schematic diagram of the structure of another terminal provided in Embodiment 7 of the present invention.

[0049] The marks in the accompanying drawings are: H1, master clock module; H2, slave clock module; H3, transmission link, with two channels, upstream and downstream, between the master clock and the slave clock; H4, storage module; H5, temperature sensor; H6, voltage sensor; C1, clock chip of the master clock module; C2, CPU chip; C3, FLASH; C4, clock chip of the slave clock module; C5, MAC switching chip; C6, temperature sensor; C7, voltage sensor; L1, L3 and L5, clock downstream channels; L2 and L4, clock upstream channels. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the following is a further detailed description of the embodiments of the present invention through specific implementation methods combined with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0051] Embodiment 1:

[0052] See also Figure 1 , a clock delay detection method provided in this embodiment includes:

[0053] S101: Transmitting a first synchronization clock to a clock module to be detected through a first physical link;

[0054] S102: Receive a feedback clock transmitted by the clock module to be detected through a second physical link;

[0055] S103: Determine the delay of the clock module to be detected.

[0056] In some embodiments, the clock delay detection method in the embodiments of the present invention is applied to a switch device, which includes but is not limited to: a master clock module, a transmission link, a clock module to be detected, and a storage module;

[0057] Among them, the master clock module is the core clock module in the switch device. Its function can be synchronized with clock devices and equipment such as time servers, GPS antennas, BITS clocks, 1588 modules, etc. It can also synchronize with internal devices and equipment such as syncE clocks, TOD phase, time and other information, and has clock processing, synchronization, distribution and other functions. In terms of hardware, it can be a dedicated clock chip, or a network processor or single-chip microcomputer with clock synchronization function, field programmable gate array processor, etc., the number can be one or more, the type can be one or a mixture of several, and it is a module that can process and distribute synchronous clocks.

[0058] The transmission link is a transmission medium that carries signals. Its hardware can be a circuit board, a connector, or a signal transmission medium such as an optical fiber or a network cable. In the embodiment of the present invention, the transmission link is divided into two physical links: a first physical link as a downlink transmission link and a second physical link as an uplink transmission link. The transmission link is transmitted from the master clock module to the clock module to be detected, and then synchronized by the clock module to be detected and transmitted back to the master clock module, forming a closed-loop feedback.

[0059] The clock module to be detected is a clock module distributed in the switch device, that is, a slave clock module. Its function is to accept the time signal from the master clock module and synchronize its frequency or phase so that the service card clock is synchronized with the master clock module. Its hardware dedicated clock chip can also be a network processor or a single-chip microcomputer, a field programmable gate array processor, etc. The number can be one or more, and the type can be one or a combination of several. Usually, in a switch, the number of clock modules to be detected can be one or more. Correspondingly, the transmission link can also be one or more groups.

[0060] The storage module may be a volatile or non-volatile memory, DDR, FIFO, array table, register, etc. with storage function. The number may be one or more, and the type may be one or a mixture of several.

[0061] In some embodiments, the feedback clock is a clock obtained by adjusting the current clock of the clock module to be detected to the same phase as the first synchronous clock. The specific implementation method can be that after the clock module to be detected receives the first synchronous clock sent by the master clock module, its own output clock is locked with the first synchronous clock, and the output clock and the first synchronous clock are corrected by a phase-locked loop with zero delay, so that the input and output clocks are in phase. At this time, the clock to be detected uses the corrected output clock as the feedback clock and feeds it back to the master clock module. Among them, the frequency of the output clock and the first synchronous clock may be different, but the frequency deviation is equal. It should be noted that in the embodiment of the present invention, the clock module to be detected uses the phase-locked loop zero delay function for phase correction, and of course, the phase-locked loop zero delay function may not be used for phase correction. This error can also be corrected by the algorithm later. For those skilled in the art, the error correction of the slave clock module can be completed in a variety of ways without creative labor.

[0062] It should be noted that the clock frequency of the feedback clock is not fixed to a specific frequency, and the frequency can be set to 1 Hz, or to several kilohertz, or several megahertz, or tens of megahertz, etc., and of course it can also be set to a multiple of the downlink synchronization clock frequency, and those skilled in the art can adjust it according to actual conditions. The second physical link can be one or more, and the embodiment of the present invention does not specifically refer to the number of second physical links used, and those skilled in the art can adjust it according to actual conditions.

[0063] In some embodiments, the delay is determined according to the feedback clock, the self-return clock and the delay parameter, and the delay parameter includes the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link. It should be noted that the self-return clock is the self-return clock of the main clock module. The self-return clock can be obtained by adding a feedback line of itself in the main clock module, or by using the internal feedback of the clock chip of the main clock module to obtain the self-return clock.

[0064] It should be noted that the clock frequency of the synchronization clock may not be fixed to a specific frequency, and the frequency may be set to 1 Hz, or may be set to several kilohertz, several megahertz, or tens of megahertz, etc., and those skilled in the art may adjust it according to actual conditions. The first physical link may be one or more, and the embodiment of the present invention does not specifically refer to the number of first physical links to be used, and those skilled in the art may adjust it according to actual conditions.

[0065] In some embodiments, the first physical link and the second physical link usually use the same type of board physical material, but the first physical link and the second physical link in the embodiment of the present invention may also use different types of board physical materials.

[0066] In some embodiments, determining the delay of the clock module to be detected includes: obtaining the phase relationship between the feedback clock and the self-returning clock; determining the corresponding delay value based on the phase relationship; obtaining the delay parameter, the delay parameter is determined based on the routing distance between the first physical link and the second physical link and the physical material parameters of the board; determining the delay based on the delay value and the delay parameter.

[0067] In some embodiments, obtaining the phase relationship between the feedback clock and the self-returned clock includes:

[0068] The clock data in the feedback clock is selected to perform phase detection with the self-returned clock to determine the phase relationship.

[0069] In some embodiments, the master clock chip in the master clock module performs phase detection on a clock data of the feedback clock and the self-returned clock through an internal phase detector to obtain a phase difference and complete a single delayed sampling.

[0070] In some embodiments, obtaining a phase relationship between the feedback clock and the self-returned clock, and determining a corresponding delay value according to the phase relationship includes:

[0071] At least two phase relationships between the feedback clock and the self-returned clock are obtained, and at least two corresponding delay values ​​are determined according to the at least two phase relationships.

[0072] In some embodiments, the master clock chip in the master clock module performs phase detection on at least two clock data of the feedback clock and the self-return clock through a phase detector inside it, obtains a phase difference, and completes delayed sampling. For example, if the phase detection is performed 4000 times in 1 second, 4000 samples can be collected, that is, 4000 phase relationships are obtained, and 4000 delay values ​​can be obtained based on these 4000 phase relationships. These 4000 delay values ​​may be completely different, or they may be partially the same and partially different, and there is a very low probability that all 4000 delay values ​​may be the same. It should be noted that the number of phase detectors can be one or more phase detectors to speed up the acquisition rate of the phase relationship. Those skilled in the art can make adjustments according to actual conditions.

[0073] In some embodiments, those skilled in the art may also use the internal feedback of the clock chip for phase detection instead of the external feedback phase detection method according to the special functions of the clock chip. There are many ways of phase detection, such as measuring the number of pulses accumulated by a high-power clock counter, or measuring using an XOR gate, etc. This embodiment does not limit a certain phase detection method. For those skilled in the art, the clock delay measurement process can be completed in a variety of ways without creative work. The frequency of phase detection is not limited to 4000 times per second, and of course it can be once every few seconds or tens of thousands of times per second. Those skilled in the art can adjust it according to actual conditions.

[0074] In some embodiments, determining the delay according to the delay value and the delay parameter includes:

[0075] Processing at least two delay values ​​according to a preset rule to obtain a processed delay value;

[0076] The delay is determined based on the processed delay value and the delay parameter.

[0077] In some embodiments, since multiple delay values ​​are obtained, multiple delay values ​​can be stored in the storage module first, and after all sampling data records are completed, that is, the phase relationship between all required feedback clocks and self-return clocks is obtained, the corresponding delay value is determined according to the phase relationship, and then the above delay values ​​are read, and a processed delay value is obtained after processing according to the preset rules. It should be noted that the preset rules can be sampling calculation methods, average value calculations, smoothing filter operations, proportional integral operations, etc. This embodiment does not limit which operation method or filtering method is used to complete the delay operation. For technicians in this field, without paying creative labor, the operation process of the delay value after clock processing can be completed in a variety of ways.

[0078] In some embodiments, when the physical board parameters of the first physical link and the second physical link are the same and they are in the same usage environment, their respective delay parameters are only related to their respective routing distances.

[0079] It should be noted that the physical board parameters of the board are not only related to the line width control and impedance matching caused by its production process, but also to the temperature and power supply voltage it uses.

[0080] In some embodiments, before determining the delay of the clock module to be detected, the method further includes:

[0081] Acquire at least one of the following data: working status of the clock module to be detected, temperature of the clock module to be detected, voltage of the clock module to be detected, and whether the clock module to be detected has been manually configured;

[0082] If at least one of the following conditions exists: the working state is interrupted, the temperature exceeds the preset temperature threshold, the voltage exceeds the preset voltage threshold, or there is manual configuration;

[0083] Then, determine the delay of the clock to be detected.

[0084] In some embodiments, the master clock module can sense the presence of a signal, power level, clock frequency and other information from the feedback clock and mark it. A master clock module can be connected to multiple clock modules to be detected. When there are multiple clock modules to be detected, the master clock module can read the comprehensive information of each clock module to be detected through the feedback clock fed back by each clock module to be detected, and make a judgment to obtain the working condition of the clock module to be detected, and then the working condition of the business card where the clock to be detected is located can also be obtained. In addition, the master clock module can also timely feedback the presence of the business card where each clock module to be detected is located, as well as the clock status, accuracy information, etc. to the operating system control layer management interface. It can be understood that the above information can also be read by the operating system control layer management interface.

[0085] By detecting whether at least one of the following conditions exists: the working status of the clock module to be detected, the temperature of the clock module to be detected, the voltage of the clock module to be detected, whether the clock module to be detected is manually configured, etc., it is not necessary to repeatedly measure the delay, but the measurement delay can be triggered when the above conditions exist, thereby achieving the purpose of reducing power consumption.

[0086] A clock delay detection method provided by an embodiment of the present invention transmits a first synchronous clock to a clock module to be detected through a first physical link, receives a feedback clock adjusted according to the phase of the first synchronous clock and transmitted by the clock module to be detected through a second physical link, and then determines the delay of the clock module to be detected through the feedback clock, the self-returned clock, and the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link. The clock delay detection method provided by an embodiment of the present invention can further reduce the error of the delay caused by the clock distribution of the detection switch device by calculating the delay existing in the main clock module itself and the delay caused by the physical characteristics of the first physical link and the second physical link, thereby improving the accuracy of clock delay detection.

[0087] Furthermore, when determining the delay parameters, the physical board parameters of the first physical link and the second physical link are taken into consideration, which can further reduce the error caused by the line width control and impedance matching of the first physical link and the second physical link being substantially inconsistent with the single preset standard delay due to slight differences in the manufacturing process. It can also reduce the error caused by the delay actually caused by the first physical link and the second physical link being substantially inconsistent with the preset standard delay under different temperature conditions and power supply voltage conditions.

[0088] Furthermore, before determining the delay of the clock module to be detected, it is also necessary to obtain the working state of the clock module to be detected, the temperature of the clock module to be detected, the voltage of the clock module to be detected, whether the clock module to be detected has manual configuration and other data, and further determine that when there are including but not limited to the following situations, the delay of the clock module to be detected is continued to be determined: the working state is interrupted, the temperature exceeds the temperature preset threshold, the voltage exceeds the voltage preset threshold, and there is manual configuration. The waste of resources caused by continuous delay measurement can be avoided. The detection efficiency is further improved. At the same time, when the switching device is in an environment with unstable temperature or a large power supply fluctuation, the method used in the present invention can timely discover the delay change, and automatically detect the delay, thereby improving the accuracy of delay detection.

[0089] Embodiment 2:

[0090] See also Figure 2 , a clock delay compensation method provided in this embodiment includes:

[0091] S201, obtaining the delay described in any one of the above embodiments;

[0092] S202: Compensate the delay to the clock module to be detected corresponding to the delay.

[0093] It should be noted that the delay compensation to the clock module to be detected corresponding to the delay may be performed in a manual compensation manner or in an automatic compensation manner.

[0094] In some embodiments, the delay is compensated to the clock module to be detected corresponding to the delay, and the compensation method includes but is not limited to the following methods:

[0095] The delay is compensated to the constant delay memory of the clock module to be detected through the management interface, and the clock module to be detected removes the delay in the subsequent clock synchronization calculation;

[0096] or,

[0097] Modify the phase of the second synchronous clock so that the second synchronous clock received by the clock module to be detected has compensated the delay, and the second synchronous clock is a clock obtained by adjusting the first synchronous clock according to the delay;

[0098] or,

[0099] The output phase of the local clock of the clock module to be detected is modified to compensate for the delay.

[0100] It can be understood that the above-mentioned several compensation methods are all automatic compensation methods. Specifically, the automatic compensation method can be:

[0101] The master clock module automatically compensates the delay to the constant delay memory of the clock module to be detected through management interfaces such as SGMII, MLVDS, IIC, SPI lines, etc. The clock module to be detected subsequently removes the constant delay during clock synchronization calculation;

[0102] Directly modify the phase of the first synchronous clock sent by the master clock module to any clock module to be detected;

[0103] Directly modify the local clock output phase of the clock module to be detected so that it is aligned with the first synchronous clock phase;

[0104] It should be noted that, for those skilled in the art, the clock delay automatic compensation process can be completed in a variety of ways without creative work.

[0105] A clock delay compensation method provided in an embodiment of the present invention obtains the delay provided in any of the above embodiments and compensates it to the clock to be detected. The clock to be detected can be compensated according to the delay with higher accuracy, so that the reliability of clock synchronization accuracy is guaranteed.

[0106] Furthermore, the embodiment of the present invention also provides an embodiment of automatic delay compensation, which can greatly reduce the uncontrollable delay error caused by manual compensation, improve the delay error accuracy, and greatly improve the clock synchronization accuracy of the switching device.

[0107] Third embodiment

[0108] The clock delay detection and compensation methods provided in the above embodiments are specifically described below by taking the application scenario in which the methods provided in the above embodiments are applied to a rack-mounted switch as an example.

[0109] It should be noted that the methods provided by the present invention are not limited to being applied to rack-mounted switches, and the following is only an exemplary description. Other switch devices that use physical links to transmit synchronous clocks are also applicable to the methods provided by the present invention.

[0110] See also Figure 3 , Figure 3This is a topology diagram of a rack-mounted switch. The switch consists of a main control card and multiple service cards.

[0111] See also Figure 4 , Figure 4 This is a topological diagram of clock delay detection and compensation. The device includes a master clock module, a clock module to be detected, a storage module, a first physical link and a second physical link. For the sake of convenience, the clock module to be detected is referred to as a slave clock module, the first physical link is referred to as a downlink, and the second physical link is referred to as a downlink. The detailed architecture of the hardware device is as follows: Figure 5 As shown, Figure 5 yes Figure 4 The detailed hardware architecture of the clock delay detection device provided in the document is a rack-type architecture consisting of a main control card and multiple service cards. The main control card is equipped with a clock card. The clock chip C1 and the CPU chip C2 of the main clock module of the clock card constitute the main clock module, where the CPU chip C2 is the chip for managing the clock, and C3 is FLASH; the service card is composed of the clock chip C4 and the MAC switching chip C5 of the slave clock module to form a slave clock module; L1, L2, L3, and L4 connect the main control card and multiple service cards via the backplane physical transmission link; for specific clock delay detection and compensation methods, see Figure 6 As shown, Figure 6 It is a specific clock delay detection and compensation method:

[0112] S601: The master clock module distributes a first synchronous clock;

[0113] In some embodiments, see Figure 4 and Figure 5 The master clock module distributes the first synchronous clock, which can be understood as the clock chip C1 of the master clock module on the main control card distributes the first synchronous clock to business card 1 to business card N through downlinks L1 and L3 respectively, and the clock chip C1 of the master clock module divides a downlink link L5, which is returned to the input end of the clock chip C1 of the master clock module.

[0114] It should be noted that L5 is an external feedback phase detection method. According to the special functions of the clock chip, technicians in this field can remove the L5 feedback line and use the internal feedback method of the clock chip for phase detection. This embodiment only marks this feedback line as a detailed explanation. Similarly, the clock frequency of the first synchronous clock is not fixed to a specific frequency. The frequency can be set to 1 Hz, of course, it can also be set to several thousand Hz or several megahertz, tens of megahertz, etc., and technicians in this field can adjust it according to actual conditions. In addition, the downlink can be one or more. This embodiment cites two downlinks to better illustrate the transmission situation when there are multiple business cards. It does not specifically refer to the number of downlinks used in the invention. Technicians in this field can adjust it according to actual conditions.

[0115] S602: The slave clock module locks the first synchronization clock for synchronization;

[0116] In some embodiments, see Figure 4 and Figure 5 After the service card 1 receives the first synchronization clock of the L1 downlink, the clock chip C4 of the slave clock module locks the clock outputted L2 with the first synchronization clock inputted L1, wherein the two clock frequencies may be different, but the frequency deviations are equal, and then the output clock and the input clock are corrected by the phase-locked loop zero delay, so that the input and output clocks are in phase, and the clock chip C4 of the slave clock module outputs a part of the clock synchronized with the first synchronization clock for use by the local MAC switching chip C5, and the other part is used as the feedback clock and transmitted to the master clock module. It should be noted that in this embodiment, the slave clock module uses the phase-locked loop zero delay function for phase correction, and of course, the phase-locked loop zero delay function may not be used for phase correction, and the error may be corrected by the algorithm later. For those skilled in the art, the error correction of the slave clock module can be completed in a variety of ways without creative labor. The clock frequency of the feedback clock is not fixed to a specific frequency, and the frequency can be set to 1 Hz, or to several kilohertz, or to several megahertz, or to tens of megahertz, etc., and of course, it can also be set to a multiple of the downlink synchronization clock frequency, and those skilled in the art can adjust it according to actual conditions.

[0117] S603: Upload the feedback clock from the clock module to the master clock module;

[0118] In some embodiments, see Figure 4 and Figure 5, the clock chip C4 of the slave clock module sends the feedback clock back to the clock chip C1 of the master clock module through the uplink transmission link L2. Similarly, the process of service card N is the same as that of service card 1, and the feedback clock of service card N is sent back to the clock chip C1 of the master clock module through the uplink transmission link L4. It should be noted here that the uplink can be one or more. The two uplinks in this embodiment are used to better illustrate the transmission situation when there are multiple service cards. The invention does not specify the number of uplinks to be used. Those skilled in the art can adjust according to actual conditions.

[0119] S604: The master clock module senses in rounds and reports to the operating system control layer management interface;

[0120] In some embodiments, the clock chip C1 of the master clock module receives feedback clocks uploaded by business card 1 and business card N from the uplink transmission links L2 and L4. The clock chip C1 of the master clock module can sense the signal presence, power size, clock frequency and other information through the clock fed back by the uplink feedback channel of each business card and mark it. The CPU chip C2 can read the comprehensive information of each clock link through the data link interface of the clock chip C1 of the master clock module, make judgments, detect the presence of the business card and the working status of the business card clock, and can timely feed the board presence status of each slot business card and the clock status and accuracy information to the operating system control layer management interface. Of course, this information can also be read by the operating system control layer management interface.

[0121] S605: sampling and phase detection of the feedback clock and the self-returning clock;

[0122] In some embodiments, the clock chip C1 of the master clock module performs phase detection on a feedback clock of a certain channel in the uplink L2 and L4 of the service card and the self-returned clock L5 through a phase detector inside it, obtains a phase difference, and completes a single delay sampling. Repeating this step, the uplink clock fed back by a certain service card can be repeatedly collected delay samples. If the phase detection is performed 4000 times in 1 second, 4000 samples can be collected. When the collection is completed, the phase detection input can be switched to the uplink clock fed back by the next service card for phase detection, and phase detection is performed with the self-returned clock L5 to obtain another phase difference. The number of phase detectors here is taken as an example. Of course, multiple phase detectors can also be used to make the downlink synchronous clock and the uplink clock fed back by multiple service cards perform phase detection at the same time, thereby accelerating the collection rate. Those skilled in the art can adjust it according to actual conditions. Using the self-returning clock L5 to phase-comparison with the uplink feedback clock of a certain route card is a method of external feedback phase-comparison. This embodiment only describes this function as a detailed description of the phase-comparison method. The technicians in this field can also remove the L5 feedback line according to the special functions of the clock chip and use the internal feedback of the clock chip for phase-comparison. There are many ways of phase-comparison, such as measuring the number of pulses accumulated by a high-multiple clock counter, or measuring using an XOR gate, etc. This embodiment does not limit a certain phase-comparison method. For the technicians in this field, the clock delay measurement process can be completed in a variety of ways without creative work. The frequency of phase-comparison is not limited to 4000 times per second. Of course, it can be once every few seconds or tens of thousands of times per second. The technicians in this field can adjust it according to the actual situation.

[0123] S606: Saving the sample to the storage module;

[0124] In some embodiments, the CPU chip C2 samples the delay values ​​of the service cards in each slot from the clock chip C1 of the main clock module, writes them into the storage module C3 in sequence for storage, and completes the recording of the sampled data of the service cards in all slots.

[0125] S607: The main clock module extracts the sample and calculates the delay;

[0126] In some embodiments, the CPU chip C2 reads the delay sampling samples recorded by the storage module C3, and samples and calculates in sequence according to the previously set distances of the uplink and downlink transmission links from the clock card to each service card, and obtains the delay of each service card slot. The sampling calculation method can be an average value calculation, a smoothing filter calculation, a proportional integral calculation, etc. This embodiment does not limit which calculation method or filtering method is used to complete the delay calculation. For those skilled in the art, the clock delay calculation process can be completed in a variety of ways without creative labor.

[0127] S608: The main clock module compensates for the delay of each service card.

[0128] In some embodiments, the CPU chip C2 automatically compensates the measured delay of each service card to each service card. In this embodiment, the phase control word of the clock chip C1 of the master clock module is directly modified to make the output phase of the clock chip C4 of any slot slave clock module the same as the phase returned by the master clock chip. It should be noted that there are many ways of automatic compensation, including but not limited to the following: 1. The master clock module automatically compensates the delay to the constant delay memory of the slave clock module of the service card through management interfaces such as SGMII, MLVDS, IIC, SPI lines, etc., and the subsequent service card removes the constant delay during clock synchronization calculation; 2. Directly modify the phase of the downlink synchronous clock from the master clock module to any slot; 3. Directly modify the local clock output phase of the slave clock module to align it with the synchronous clock phase. For technicians in this field, the clock delay automatic compensation process can be completed in a variety of ways without creative labor.

[0129] It should be noted that, according to the needs of those skilled in the art, a manual compensation method may also be used to compensate for the delay of the module to be detected (slave clock module).

[0130] It should be noted that, if necessary, the above steps S601 - S608 may be repeated multiple times to obtain more accurate clock delay compensation.

[0131] In some embodiments, the clock delay detection also takes into account the influence of temperature factors, such as Figure 7 The clock delay detection and compensation topology diagram is shown in the figure. It includes a master clock module, a slave clock module, a temperature sensor, a storage module, and an uplink and downlink transmission link. The device no longer needs to repeatedly measure the delay, but triggers the delay measurement as needed to achieve the purpose of reducing power consumption. The detailed architecture of its hardware device is shown in the attached figure. Figure 8 , the delay detection and compensation process is as follows Fig. 9 The specific implementation process is as follows:

[0132] S901: Record the ambient temperature and set the temperature preset threshold;

[0133] like Figure 8 As shown, the current temperature of the temperature sensor C6 is recorded by the CPU chip C2, and a temperature preset threshold is set.

[0134] It should be noted that the temperature preset threshold value may be set manually or automatically, and the threshold range may be adjusted by technicians in this field according to actual conditions.

[0135] S902: The master clock module distributes a first synchronous clock;

[0136] In some embodiments, see Figure 7 The master clock module distributes the first synchronous clock, which can be understood as the clock chip C1 of the master clock module on the main control card distributes the first synchronous clock to business card 1 to business card N through downlinks L1 and L3 respectively, and the clock chip C1 of the master clock module divides a downlink link L5, which is returned to the input end of the clock chip C1 of the master clock module.

[0137] It should be noted that L5 is an external feedback phase detection method. According to the special functions of the clock chip, technicians in this field can remove the L5 feedback line and use the internal feedback method of the clock chip for phase detection. This embodiment only marks this feedback line as a detailed explanation. Similarly, the clock frequency of the first synchronous clock is not fixed to a specific frequency. The frequency can be set to 1 Hz, of course, it can also be set to several thousand Hz or several megahertz, tens of megahertz, etc., and technicians in this field can adjust it according to actual conditions. In addition, the downlink can be one or more. This embodiment cites two downlinks to better illustrate the transmission situation when there are multiple business cards. It does not specifically refer to the number of downlinks used in the invention. Technicians in this field can adjust it according to actual conditions.

[0138] S903: The slave clock module locks the first synchronization clock for synchronization;

[0139] In some embodiments, see Figure 7 After the service card 1 receives the first synchronization clock of the L1 downlink, the clock chip C4 of the slave clock module locks the clock outputted L2 with the first synchronization clock inputted L1, wherein the two clock frequencies may be different, but the frequency deviations are equal, and then the output clock and the input clock are corrected by the phase-locked loop zero delay, so that the input and output clocks are in phase, and the clock chip C4 of the slave clock module outputs a part of the clock synchronized with the first synchronization clock for use by the local MAC switching chip C5, and the other part is used as the feedback clock and transmitted to the master clock module. It should be noted that in this embodiment, the slave clock module uses the phase-locked loop zero delay function for phase correction, and of course, the phase-locked loop zero delay function may not be used for phase correction, and the error may be corrected by the algorithm later. For those skilled in the art, the error correction of the slave clock module can be completed in a variety of ways without creative labor. The clock frequency of the feedback clock is not fixed to a specific frequency, and the frequency can be set to 1 Hz, or to several kilohertz, or to several megahertz, or to tens of megahertz, etc., and of course, it can also be set to a multiple of the downlink synchronization clock frequency, and those skilled in the art can adjust it according to actual conditions.

[0140] S904: Upload the feedback clock from the clock module to the master clock module;

[0141] In some embodiments, see Figure 7 , the clock chip C4 of the slave clock module sends the feedback clock back to the clock chip C1 of the master clock module through the uplink transmission link L2. Similarly, the process of service card N is the same as that of service card 1, and the feedback clock of service card N is sent back to the clock chip C1 of the master clock module through the uplink transmission link L4. It should be noted here that the uplink can be one or more. The two uplinks in this embodiment are used to better illustrate the transmission situation when there are multiple service cards. The invention does not specify the number of uplinks to be used. Those skilled in the art can adjust according to actual conditions.

[0142] S905: The master clock module senses in rounds and reports to the operating system control plane management interface;

[0143] In some embodiments, the clock chip C1 of the master clock module receives feedback clocks uploaded by business card 1 and business card N from the uplink transmission links L2 and L4. The clock chip C1 of the master clock module can sense the signal presence, power size, clock frequency and other information through the clock fed back by the uplink feedback channel of each business card and mark it. The CPU chip C2 can read the comprehensive information of each clock link through the data link interface of the clock chip C1 of the master clock module, make judgments, detect the presence of the business card and the working status of the business card clock, and can timely feed the board presence status of each slot business card and the clock status and accuracy information to the operating system control layer management interface. Of course, this information can also be read by the operating system control layer management interface.

[0144] S906: sampling and phase detection of the feedback clock and the self-returning clock;

[0145] In some embodiments, the clock chip C1 of the master clock module performs phase detection on a feedback clock of a certain channel in the uplink L2 and L4 of the service card and the self-returned clock L5 through a phase detector inside it, obtains a phase difference, and completes a single delay sampling. Repeating this step, the uplink clock fed back by a certain service card can be repeatedly collected delay samples. If the phase detection is performed 4000 times in 1 second, 4000 samples can be collected. When the collection is completed, the phase detection input can be switched to the uplink clock fed back by the next service card for phase detection, and phase detection is performed with the self-returned clock L5 to obtain another phase difference. The number of phase detectors here is taken as an example. Of course, multiple phase detectors can also be used to make the downlink synchronous clock and the uplink clock fed back by multiple service cards perform phase detection at the same time, thereby accelerating the collection rate. Those skilled in the art can adjust it according to actual conditions. Using the self-returning clock L5 to phase-comparison with the uplink feedback clock of a certain route card is a method of external feedback phase-comparison. This embodiment only describes this function as a detailed description of the phase-comparison method. The technicians in this field can also remove the L5 feedback line according to the special functions of the clock chip and use the internal feedback of the clock chip for phase-comparison. There are many ways of phase-comparison, such as measuring the number of pulses accumulated by a high-multiple clock counter, or measuring using an XOR gate, etc. This embodiment does not limit a certain phase-comparison method. For the technicians in this field, the clock delay measurement process can be completed in a variety of ways without creative work. The frequency of phase-comparison is not limited to 4000 times per second. Of course, it can be once every few seconds or tens of thousands of times per second. The technicians in this field can adjust it according to the actual situation.

[0146] S907: Save the sample to the storage module;

[0147] In some embodiments, the CPU chip C2 samples the delay values ​​of the service cards in each slot from the clock chip C1 of the main clock module, writes them into the storage module C3 in sequence for storage, and completes the recording of the sampled data of the service cards in all slots.

[0148] S908: The main clock module extracts the sample and calculates the delay;

[0149] In some embodiments, the CPU chip C2 reads the delay sampling samples recorded by the storage module C3, and samples and calculates in sequence according to the previously set distances of the uplink and downlink transmission links from the clock card to each service card, and obtains the delay of each service card slot. The sampling calculation method can be an average value calculation, a smoothing filter calculation, a proportional integral calculation, etc. This embodiment does not limit which calculation method or filtering method is used to complete the delay calculation. For those skilled in the art, the clock delay calculation process can be completed in a variety of ways without creative labor.

[0150] S909: The main clock module compensates for the delay of each service card.

[0151] In some embodiments, the CPU chip C2 automatically compensates the measured delay of each service card to each service card. In this embodiment, the phase control word of the clock chip C1 of the master clock module is directly modified to make the output phase of the clock chip C4 of any slot slave clock module the same as the phase returned by the master clock chip. It should be noted that there are many ways of automatic compensation, including but not limited to the following: 1. The master clock module automatically compensates the delay to the constant delay memory of the slave clock module of the service card through management interfaces such as SGMII, MLVDS, IIC, SPI lines, etc., and the subsequent service card removes the constant delay during clock synchronization calculation; 2. Directly modify the phase of the downlink synchronous clock from the master clock module to any slot; 3. Directly modify the local clock output phase of the slave clock module to align it with the synchronous clock phase. For technicians in this field, the clock delay automatic compensation process can be completed in a variety of ways without creative labor.

[0152] It should be noted that those skilled in the art may also use manual compensation to compensate the above delay to the slave clock module (clock module to be detected).

[0153] At this point, the master clock chip C1 has already compensated the calculated delay error to each line card.

[0154] S910: Detect whether at least one of the temperature exceeds a preset temperature, a service card is plugged in or out, and a manual configuration exists;

[0155] In some embodiments, when the temperature of the temperature sensor is detected to exceed the preset temperature threshold, the CPU chip C2 triggers an interrupt and returns to step S905; when the service card is inserted or removed, the CPU chip C2 triggers an interrupt and returns to step S905; when the management interface manually configures the delay detection, the CPU chip C2 triggers an interrupt and returns to step S905. The above three interrupt mechanisms are only examples of the present embodiment, and those skilled in the art can add and delete them according to actual needs without creative work.

[0156] In some embodiments, clock delay detection also takes into account the influence of voltage factors, and its detection and compensation methods are similar to the above-mentioned detection and compensation methods that are only affected by temperature. Technical personnel in this field can easily obtain the detection and compensation methods of voltage factors based on the above-mentioned temperature influence, which will not be elaborated here.

[0157] In some embodiments, in addition to considering the temperature effect, the clock delay detection and compensation method also considers the voltage effect. The clock delay detection device also provides a voltage sensor based on the temperature sensor, such as Fig.10 The clock delay detection and compensation topology diagram provided includes a master clock module, a slave clock module, a temperature sensor, a voltage sensor, a storage module, and an uplink and downlink transmission link. Instead of repeatedly measuring the delay, the delay measurement is triggered as needed to achieve the purpose of reducing power consumption. The detailed architecture of the hardware device is as follows Fig.11 , the delay detection and compensation process is as follows Fig.12 As shown, the specific embodiments are as follows:

[0158] S1201: Recording ambient temperature and voltage, and setting a preset temperature threshold and a preset voltage threshold;

[0159] like Fig.11 As shown, the current temperature of the temperature sensor C6 is recorded by the CPU chip C2, and a temperature preset threshold is set.

[0160] It should be noted that the temperature preset threshold value may be set manually or automatically, and the threshold range may be adjusted by technicians in this field according to actual conditions.

[0161] S1202: The master clock module distributes a first synchronous clock;

[0162] In some embodiments, see Fig. 9 The master clock module distributes the first synchronous clock, which can be understood as the clock chip C1 of the master clock module on the main control card distributes the first synchronous clock to business card 1 to business card N through downlinks L1 and L3 respectively, and the clock chip C1 of the master clock module divides a downlink link L5, which is returned to the input end of the clock chip C1 of the master clock module.

[0163] It should be noted that L5 is an external feedback phase detection method. According to the special functions of the clock chip, technicians in this field can remove the L5 feedback line and use the internal feedback method of the clock chip for phase detection. This embodiment only marks this feedback line as a detailed explanation. Similarly, the clock frequency of the first synchronous clock is not fixed to a specific frequency. The frequency can be set to 1 Hz, of course, it can also be set to several thousand Hz or several megahertz, tens of megahertz, etc., and technicians in this field can adjust it according to actual conditions. In addition, the downlink can be one or more. This embodiment cites two downlinks to better illustrate the transmission situation when there are multiple business cards. It does not specifically refer to the number of downlinks used in the invention. Technicians in this field can adjust it according to actual conditions.

[0164] S1203: The slave clock module locks the first synchronization clock for synchronization;

[0165] In some embodiments, see Fig. 9After the service card 1 receives the first synchronization clock of the L1 downlink, the clock chip C4 of the slave clock module locks the clock outputted L2 with the first synchronization clock inputted L1, wherein the two clock frequencies may be different, but the frequency deviations are equal, and then the output clock and the input clock are corrected by the phase-locked loop zero delay, so that the input and output clocks are in phase, and the clock chip C4 of the slave clock module outputs a part of the clock synchronized with the first synchronization clock for use by the local MAC switching chip C5, and the other part is used as the feedback clock and transmitted to the master clock module. It should be noted that in this embodiment, the slave clock module uses the phase-locked loop zero delay function for phase correction, and of course, the phase-locked loop zero delay function may not be used for phase correction, and the error may be corrected by the algorithm later. For those skilled in the art, the error correction of the slave clock module can be completed in a variety of ways without creative labor. The clock frequency of the feedback clock is not fixed to a specific frequency, and the frequency can be set to 1 Hz, or to several kilohertz, or to several megahertz, or to tens of megahertz, etc., and of course, it can also be set to a multiple of the downlink synchronization clock frequency, and those skilled in the art can adjust it according to actual conditions.

[0166] S1204: Upload the feedback clock from the clock module to the master clock module;

[0167] In some embodiments, see Fig. 9 , the clock chip C4 of the slave clock module sends the feedback clock back to the clock chip C1 of the master clock module through the uplink transmission link L2. Similarly, the process of service card N is the same as that of service card 1, and the feedback clock of service card N is sent back to the clock chip C1 of the master clock module through the uplink transmission link L4. It should be noted here that the uplink can be one or more. The two uplinks in this embodiment are used to better illustrate the transmission situation when there are multiple service cards. The invention does not specify the number of uplinks to be used. Those skilled in the art can adjust according to actual conditions.

[0168] S1205: The master clock module senses in rounds and reports to the operating system control layer management interface;

[0169] In some embodiments, the clock chip C1 of the master clock module receives feedback clocks uploaded by business card 1 and business card N from the uplink transmission links L2 and L4. The clock chip C1 of the master clock module can sense the signal presence, power size, clock frequency and other information through the clock fed back by the uplink feedback channel of each business card and mark it. The CPU chip C2 can read the comprehensive information of each clock link through the data link interface of the clock chip C1 of the master clock module, make judgments, detect the presence of the business card and the working status of the business card clock, and can timely feed the board presence status of each slot business card and the clock status and accuracy information to the operating system control layer management interface. Of course, this information can also be read by the operating system control layer management interface.

[0170] S1206: sampling and phase detection of the feedback clock and the self-returning clock;

[0171] In some embodiments, the clock chip C1 of the master clock module performs phase detection on a feedback clock of a certain channel in the uplink L2 and L4 of the service card and the self-returned clock L5 through a phase detector inside it, obtains a phase difference, and completes a single delay sampling. Repeating this step, the uplink clock fed back by a certain service card can be repeatedly collected delay samples. If the phase detection is performed 4000 times in 1 second, 4000 samples can be collected. When the collection is completed, the phase detection input can be switched to the uplink clock fed back by the next service card for phase detection, and phase detection is performed with the self-returned clock L5 to obtain another phase difference. The number of phase detectors here is taken as an example. Of course, multiple phase detectors can also be used to make the downlink synchronous clock and the uplink clock fed back by multiple service cards perform phase detection at the same time, thereby accelerating the collection rate. Those skilled in the art can adjust it according to actual conditions. Using the self-returning clock L5 to phase-comparison with the uplink feedback clock of a certain route card is a method of external feedback phase-comparison. This embodiment only describes this function as a detailed description of the phase-comparison method. The technicians in this field can also remove the L5 feedback line according to the special functions of the clock chip and use the internal feedback of the clock chip for phase-comparison. There are many ways of phase-comparison, such as measuring the number of pulses accumulated by a high-multiple clock counter, or measuring using an XOR gate, etc. This embodiment does not limit a certain phase-comparison method. For the technicians in this field, the clock delay measurement process can be completed in a variety of ways without creative work. The frequency of phase-comparison is not limited to 4000 times per second. Of course, it can be once every few seconds or tens of thousands of times per second. The technicians in this field can adjust it according to the actual situation.

[0172] S1207: Saving the sample to the storage module;

[0173] In some embodiments, the CPU chip C2 samples the delay values ​​of the service cards in each slot from the clock chip C1 of the main clock module, writes them into the storage module C3 in sequence for storage, and completes the recording of the sampled data of the service cards in all slots.

[0174] S1208: The main clock module extracts the sample and calculates the delay;

[0175] In some embodiments, the CPU chip C2 reads the delay sampling samples recorded by the storage module C3, and samples and calculates in sequence according to the previously set distances of the uplink and downlink transmission links from the clock card to each service card, and obtains the delay of each service card slot. The sampling calculation method can be an average value calculation, a smoothing filter calculation, a proportional integral calculation, etc. This embodiment does not limit which calculation method or filtering method is used to complete the delay calculation. For those skilled in the art, the clock delay calculation process can be completed in a variety of ways without creative labor.

[0176] S1209: The main clock module compensates for the delay of each service card.

[0177] In some embodiments, the CPU chip C2 automatically compensates the measured delay of each service card to each service card. In this embodiment, the phase control word of the clock chip C1 of the master clock module is directly modified to make the output phase of the clock chip C4 of any slot slave clock module the same as the phase returned by the master clock chip. It should be noted that there are many ways of automatic compensation, including but not limited to the following: 1. The master clock module automatically compensates the delay to the constant delay memory of the slave clock module of the service card through management interfaces such as SGMII, MLVDS, IIC, SPI lines, etc., and the subsequent service card removes the constant delay during clock synchronization calculation; 2. Directly modify the phase of the downlink synchronous clock from the master clock module to any slot; 3. Directly modify the local clock output phase of the slave clock module to align it with the synchronous clock phase. For technicians in this field, the clock delay automatic compensation process can be completed in a variety of ways without creative labor.

[0178] It should be noted that those skilled in the art may also compensate the delay to the slave clock module (clock module to be detected) by manual compensation.

[0179] At this point, the master clock chip C1 has already compensated the calculated delay error to each line card.

[0180] S1210: Detect whether at least one of the temperature exceeds a preset temperature, the voltage exceeds a preset threshold, the service card is plugged in or out, and manual configuration occurs;

[0181] In some embodiments, when the temperature of the temperature sensor is detected to exceed the threshold, the CPU chip C2 triggers an interrupt and returns to step S1205; when the voltage of the voltage sensor is detected to exceed the threshold, the CPU chip C2 triggers an interrupt and returns to step S1205; when the service card is inserted or removed, the CPU chip C2 triggers an interrupt and returns to step S1205; when the management interface manually configures the delay detection, the CPU chip C2 triggers an interrupt and returns to step S1205. The above four interrupt mechanisms are only examples of the present embodiment, and those skilled in the art can add and delete according to actual needs without creative work.

[0182] Fourth embodiment

[0183] See also Fig.13 , a clock delay detection device 1300 provided in this embodiment includes:

[0184] A master clock module 1301, a first physical link 1302, a second physical link 1303 and a clock module to be detected 1304;

[0185] The master clock module 1301 includes a sending module 1311, a receiving module 1312 and a calculating module 1313, wherein:

[0186] The sending module 1311 is used to transmit the first synchronization clock to the clock module to be detected 1304 through the first physical link 1302;

[0187] The receiving module 1312 is used to receive the feedback clock transmitted by the clock module to be detected 1304 through the second physical link 1303, where the feedback clock is a clock obtained by adjusting the current clock of the clock module to be detected 1304 to have the same phase as the first synchronization clock;

[0188] The calculation module 1313 is used to determine the delay of the clock module 1304 to be detected. The delay is determined according to the feedback clock, the self-returned clock and the delay parameters. The delay parameters include the delay parameters corresponding to the first physical link 1302 and the delay parameters corresponding to the second physical link 1303.

[0189] In some embodiments, the clock delay detection device in the embodiments of the present invention may be a switch device, which includes but is not limited to: a master clock module, a transmission link, a clock module to be detected, and a storage module;

[0190] Among them, the master clock module is the core clock module in the switch device. Its function can be synchronized with clock devices and equipment such as time servers, GPS antennas, BITS clocks, 1588 modules, etc. It can also synchronize with internal devices and equipment such as syncE clocks, TOD phase, time and other information, and has clock processing, synchronization, distribution and other functions. In terms of hardware, it can be a dedicated clock chip, or a network processor or single-chip microcomputer with clock synchronization function, field programmable gate array processor, etc., the number can be one or more, the type can be one or a mixture of several, and it is a module that can process and distribute synchronous clocks.

[0191] The transmission link is a transmission medium that carries signals. Its hardware can be a circuit board, a connector, or a signal transmission medium such as an optical fiber or a network cable. In the embodiment of the present invention, the transmission link is divided into two physical links: a first physical link as a downlink transmission link and a second physical link as an uplink transmission link. The transmission link is transmitted from the master clock module to the clock module to be detected, and then synchronized by the clock module to be detected and transmitted back to the master clock module, forming a closed-loop feedback.

[0192] The clock module to be detected is a clock module distributed in the switch device, that is, a slave clock module. Its function is to accept the time signal from the master clock module and synchronize its frequency or phase so that the service card clock is synchronized with the master clock module. Its hardware dedicated clock chip can also be a network processor or a single-chip microcomputer, a field programmable gate array processor, etc. The number can be one or more, and the type can be one or a combination of several. Usually, in a switch, the number of clock modules to be detected can be one or more. Correspondingly, the transmission link can also be one or more groups.

[0193] The storage module may be a volatile or non-volatile memory, DDR, FIFO, array table, register, etc. with storage function. The number may be one or more, and the type may be one or a mixture of several.

[0194] In some embodiments, the feedback clock is a clock obtained by adjusting the current clock of the clock module to be detected to the same phase as the first synchronous clock. The specific implementation method can be that after the clock module to be detected receives the first synchronous clock sent by the master clock module, its own output clock is locked with the first synchronous clock, and the output clock and the first synchronous clock are corrected by a phase-locked loop with zero delay, so that the input and output clocks are in phase. At this time, the clock to be detected uses the corrected output clock as the feedback clock and feeds it back to the master clock module. Among them, the frequency of the output clock and the first synchronous clock may be different, but the frequency deviation is equal. It should be noted that in the embodiment of the present invention, the clock module to be detected uses the phase-locked loop zero delay function for phase correction, and of course, the phase-locked loop zero delay function may not be used for phase correction. This error can also be corrected by the algorithm later. For those skilled in the art, the error correction of the slave clock module can be completed in a variety of ways without creative labor.

[0195] It should be noted that the clock frequency of the feedback clock is not fixed to a specific frequency, and the frequency can be set to 1 Hz, or to several kilohertz, or several megahertz, or tens of megahertz, etc., and of course it can also be set to a multiple of the downlink synchronization clock frequency, and those skilled in the art can adjust it according to actual conditions. The second physical link can be one or more, and the embodiment of the present invention does not specifically refer to the number of second physical links used, and those skilled in the art can adjust it according to actual conditions.

[0196] In some embodiments, the delay is determined according to the feedback clock, the self-return clock and the delay parameter, and the delay parameter includes the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link. It should be noted that the self-return clock is the self-return clock of the main clock module. The self-return clock can be obtained by adding a feedback line of itself in the main clock module, or by using the internal feedback of the clock chip of the main clock module to obtain the self-return clock.

[0197] It should be noted that the clock frequency of the synchronization clock may not be fixed to a specific frequency, and the frequency may be set to 1 Hz, or may be set to several kilohertz, several megahertz, or tens of megahertz, etc., and those skilled in the art may adjust it according to actual conditions. The first physical link may be one or more, and the embodiment of the present invention does not specifically refer to the number of first physical links to be used, and those skilled in the art may adjust it according to actual conditions.

[0198] In some embodiments, the first physical link and the second physical link usually use the same type of board physical material, but the first physical link and the second physical link in the embodiment of the present invention may also use different types of board physical materials.

[0199] In some embodiments, the computing module includes: a first computing submodule, a second computing submodule, a third computing submodule, and a fourth computing submodule, wherein

[0200] The first calculation submodule is used to obtain the phase relationship between the feedback clock and the self-returning clock;

[0201] The second calculation submodule is used to determine the corresponding delay value according to the phase relationship;

[0202] The third calculation submodule is used to obtain a delay parameter, where the delay parameter is determined according to a routing distance between the first physical link and the second physical link and a physical plate parameter of the board;

[0203] The fourth calculation submodule is used to determine the delay according to the delay value and the delay parameter.

[0204] In some embodiments, the first calculation submodule is used to obtain the phase relationship between the feedback clock and the self-returned clock, including:

[0205] The first calculation submodule selects the clock data in the feedback clock and the self-returned clock to perform phase detection to determine the phase relationship.

[0206] In some embodiments, the first calculation submodule is used to obtain at least two phase relationships between the feedback clock and the self-returning clock;

[0207] The second calculation submodule is used to determine at least two corresponding delay values ​​according to at least two phase relationships.

[0208] In some embodiments, the master clock chip in the master clock module performs phase detection on at least two clock data of the feedback clock and the self-return clock through a phase detector inside it, obtains a phase difference, and completes delayed sampling. For example, if the phase detection is performed 4000 times in 1 second, 4000 samples can be collected, that is, 4000 phase relationships are obtained, and 4000 delay values ​​can be obtained based on these 4000 phase relationships. These 4000 delay values ​​may be completely different, or they may be partially the same and partially different, and there is a very low probability that all 4000 delay values ​​may be the same. It should be noted that the number of phase detectors can be one or more phase detectors to speed up the acquisition rate of the phase relationship. Those skilled in the art can make adjustments according to actual conditions.

[0209] In some embodiments, those skilled in the art may also use the internal feedback of the clock chip for phase detection instead of the external feedback phase detection method according to the special functions of the clock chip. There are many ways of phase detection, such as measuring the number of pulses accumulated by a high-power clock counter, or measuring using an XOR gate, etc. This embodiment does not limit a certain phase detection method. For those skilled in the art, the clock delay measurement process can be completed in a variety of ways without creative work. The frequency of phase detection is not limited to 4000 times per second, and of course it can be once every few seconds or tens of thousands of times per second. Those skilled in the art can adjust it according to actual conditions.

[0210] In some embodiments, the fourth calculation submodule is used to obtain a processed delay value after processing at least two delay values ​​according to a preset rule; and determine the delay according to the processed delay value and the delay parameter.

[0211] In some embodiments, since multiple delay values ​​are obtained, multiple delay values ​​can be stored in the storage module first, and after all sampling data records are completed, that is, the phase relationship between all required feedback clocks and self-return clocks is obtained, the corresponding delay value is determined according to the phase relationship, and then the above delay values ​​are read, and a processed delay value is obtained after processing according to the preset rules. It should be noted that the preset rules can be sampling calculation methods, average value calculations, smoothing filter operations, proportional integral operations, etc. This embodiment does not limit which operation method or filtering method is used to complete the delay operation. For technicians in this field, without paying creative labor, the operation process of the delay value after clock processing can be completed in a variety of ways.

[0212] In some embodiments, when the physical board parameters of the first physical link and the second physical link are the same and they are in the same usage environment, their respective delay parameters are only related to their respective routing distances.

[0213] It should be noted that the physical board parameters of the board are not only related to the line width control and impedance matching caused by its production process, but also to the temperature and power supply voltage it uses.

[0214] In some embodiments, the clock delay detection device further includes: a judgment module,

[0215] The judgment module is used to: before the calculation module determines the delay of the clock module to be detected:

[0216] Acquire at least one of the following data: working status of the clock module to be detected, working status of the clock module to be detected, temperature of the clock module to be detected, voltage of the clock module to be detected, and whether the clock module to be detected has manual configuration;

[0217] If at least one of the following conditions exists: the working state is interrupted, the temperature exceeds the preset temperature threshold, the voltage exceeds the preset voltage threshold, or there is manual configuration;

[0218] Then, the calculation module determines the delay of the clock to be detected.

[0219] In some embodiments, the master clock module can sense the presence of a signal, power level, clock frequency and other information from the feedback clock and mark it. A master clock module can be connected to multiple clock modules to be detected. When there are multiple clock modules to be detected, the master clock module can read the comprehensive information of each clock module to be detected through the feedback clock fed back by each clock module to be detected, and make a judgment to obtain the working condition of the clock module to be detected, and then the working condition of the business card where the clock to be detected is located can also be obtained. In addition, the master clock module can also timely feedback the presence of the business card where each clock module to be detected is located, as well as the clock status, accuracy information, etc. to the operating system control layer management interface. It can be understood that the above information can also be read by the operating system control layer management interface.

[0220] By detecting whether at least one of the following conditions exists: the working status of the clock module to be detected, the temperature of the clock module to be detected, the voltage of the clock module to be detected, whether the clock module to be detected is manually configured, etc., it is not necessary to repeatedly measure the delay, but the measurement delay can be triggered when the above conditions exist, thereby achieving the purpose of reducing power consumption.

[0221] The clock delay detection device provided by the embodiment of the present invention comprises a sending module that transmits a first synchronous clock to a clock module to be detected through a first physical link, a receiving module that receives a feedback clock that is adjusted according to the phase of the first synchronous clock and transmitted by the clock module to be detected through a second physical link, and then a calculation module that determines the delay of the clock module to be detected through the feedback clock, the self-returned clock, and the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link. The clock delay detection device provided by the embodiment of the present invention can further reduce the error of the delay caused by the clock distribution of the detection switch device by calculating the delay existing in the main clock module itself and the delay caused by the physical characteristics of the first physical link and the second physical link, thereby improving the accuracy of clock delay detection.

[0222] Furthermore, when determining the delay parameters, the physical board parameters of the first physical link and the second physical link are taken into consideration, which can further reduce the error caused by the line width control and impedance matching of the first physical link and the second physical link being substantially inconsistent with the single preset standard delay due to slight differences in the manufacturing process. It can also reduce the error caused by the delay actually caused by the first physical link and the second physical link being substantially inconsistent with the preset standard delay under different temperature conditions and power supply voltage conditions.

[0223] Further, before determining the delay of the clock module to be detected, the working state of the clock module to be detected, the temperature of the clock module to be detected, the voltage of the clock module to be detected, whether the clock module to be detected has manual configuration and other data are obtained through the judgment module, and it is further judged that when there are including but not limited to the following situations, the delay of the clock module to be detected is continued to be determined: the working state is interrupted, the temperature exceeds the temperature preset threshold, the voltage exceeds the voltage preset threshold, and there is manual configuration. The waste of resources caused by continuous delay measurement can be avoided. The detection efficiency is further improved. At the same time, when the switching device is in an environment with unstable temperature or a large power supply fluctuation, the method used in the present invention can timely discover the delay change, automatically detect the delay, and improve the accuracy of delay detection.

[0224] Fifth embodiment

[0225] See also Fig.14 , a clock delay compensation device 1400 provided in this embodiment includes: a clock delay detection device 1300 and a compensation module 1401 as described in any one of the above items;

[0226] The compensation module 1401 is used to obtain the delay detected by the clock delay detection device 1300 and compensate the delay to the clock module to be detected 1304 corresponding to the delay.

[0227] It should be noted that the delay compensation to the clock module to be detected corresponding to the delay may be performed in a manual compensation manner or in an automatic compensation manner.

[0228] In some embodiments, the compensation module further comprises:

[0229] A first compensation module, used for compensating the delay into the constant delay memory of the clock module to be detected through the management interface, so that the clock module to be detected removes the delay in subsequent clock synchronization calculation;

[0230] or

[0231] A second compensation module is used to modify the phase of the second synchronous clock so that the second synchronous clock received by the clock module to be detected has compensated the delay, and the second synchronous clock is a clock obtained by adjusting the first synchronous clock according to the delay;

[0232] or,

[0233] The third compensation module is used to modify the output phase of the local clock of the clock module to be detected according to the delay.

[0234] It can be understood that the above-mentioned several compensation methods are all automatic compensation methods. Specifically, the automatic compensation method can be:

[0235] The master clock module automatically compensates the delay to the constant delay memory of the clock module to be detected through management interfaces such as SGMII, MLVDS, IIC, SPI lines, etc. The clock module to be detected subsequently removes the constant delay during clock synchronization calculation;

[0236] Directly modify the phase of the first synchronous clock sent by the master clock module to any clock module to be detected;

[0237] Directly modify the local clock output phase of the clock module to be detected so that it is aligned with the first synchronous clock phase;

[0238] It should be noted that, for those skilled in the art, the clock delay automatic compensation process can be completed in a variety of ways without creative work.

[0239] A clock delay compensation device provided in an embodiment of the present invention obtains the delay provided in any of the above embodiments and compensates it to the clock to be detected. It can compensate the clock to be detected based on the delay with higher accuracy, so that the reliability of clock synchronization accuracy is guaranteed.

[0240] Furthermore, the embodiment of the present invention also provides an embodiment of automatic delay compensation, which can greatly reduce the uncontrollable delay error caused by manual compensation, improve the delay error accuracy, and greatly improve the clock synchronization accuracy of the switching device.

[0241] Sixth embodiment

[0242] This embodiment also provides a terminal. Fig.15 As shown, it includes a first processor 1501, a first memory 1503 and a first communication bus 1502, wherein:

[0243] The first communication bus 1502 is used to realize the connection and communication between the first processor 1501 and the first memory 1503;

[0244] The first processor 1501 is configured to execute one or more first computer programs stored in the first memory 1503 to implement at least one step in the clock delay detection method in the above embodiments.

[0245] Seventh embodiment:

[0246] This embodiment also provides a terminal. Fig.16 As shown, it includes a second processor 1601, a second memory 1603 and a second communication bus 1602, wherein:

[0247] The second communication bus 1602 is used to realize the connection and communication between the second processor 1601 and the second memory 1603;

[0248] The second processor 1601 is used to execute one or more second computer programs stored in the second memory 1603 to implement at least one step in the clock delay compensation method in the above embodiments.

[0249] The present embodiment also provides a computer-readable storage medium, which includes volatile or non-volatile, removable or non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, computer program modules or other data). Computer-readable storage media include, but are not limited to, RAM (Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable read only memory), flash memory or other memory technology, CD-ROM (Compact Disc Read-Only Memory), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer.

[0250] The computer-readable storage medium in this embodiment may be used to store one or more first computer programs, and the one or more first computer programs stored therein may be executed by the first processor to implement at least one step of the clock delay detection method in each of the above embodiments;

[0251] or,

[0252] The computer-readable storage medium stores one or more second computer programs, and the one or more second computer programs stored therein can be executed by one or more second processors to implement the steps of the clock delay compensation method in the above-mentioned embodiments.

[0253] This embodiment also provides a computer program (or computer software), which can be distributed on a computer-readable medium and executed by a computing device to implement at least one step of the clock delay detection method / clock delay compensation method in the above embodiments; and in some cases, at least one step shown or described can be executed in an order different from that described in the above embodiments.

[0254] It should be understood that, in some cases, at least one step shown or described may be performed in an order different from that described in the above embodiments.

[0255] This embodiment further provides a computer program product, including a computer readable device, on which the computer program as shown above is stored. In this embodiment, the computer readable device may include the computer readable storage medium as shown above.

[0256] It can be seen that those skilled in the art should understand that all or some of the steps, systems, and functional modules / units in the above disclosed methods can be implemented as software (which can be implemented with computer program code executable by a computing device), firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit.

[0257] In addition, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, computer program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery media. Therefore, the present invention is not limited to any specific hardware and software combination.

[0258] The above contents are further detailed descriptions of the embodiments of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A clock delay detection method, characterized in that: The clock delay detection method comprises: Transmitting the first synchronization clock to the clock module to be detected through the first physical link; receiving a feedback clock transmitted by the clock module to be detected through a second physical link, wherein the feedback clock is a clock obtained by adjusting the current clock of the clock module to be detected to have the same phase as the first synchronization clock; Determine the delay of the clock module to be detected, wherein the delay is determined according to the feedback clock, the self-returned clock and the delay parameter, and the delay parameter includes the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link; Wherein, determining the delay of the clock module to be detected includes: Acquiring a phase relationship between the feedback clock and the self-returning clock; Determine a corresponding delay value according to the phase relationship; Acquire the delay parameter, where the delay parameter is determined according to the routing distance between the first physical link and the second physical link and the physical plate parameter of the board; The delay is determined according to the delay value and the delay parameter.

2. The clock delay detection method according to claim 1, characterized in that: The acquiring of the phase relationship between the feedback clock and the self-returned clock comprises: The clock data in the feedback clock is selected to perform phase detection with the self-returned clock to determine the phase relationship.

3. The clock delay detection method according to claim 1, characterized in that: The acquiring the phase relationship between the feedback clock and the self-returned clock, and determining the corresponding delay value according to the phase relationship comprises: At least two phase relationships between the feedback clock and the self-returning clock are obtained, and at least two corresponding delay values ​​are determined according to the at least two phase relationships.

4. The clock delay detection method according to claim 3, characterized in that: Determining the delay according to the delay value and the delay parameter comprises: Processing the at least two delay values ​​according to a preset rule to obtain a processed delay value; The delay is determined according to the processed delay value and the delay parameter.

5. The clock delay detection method according to any one of claims 1 to 4, characterized in that: Before determining the delay of the clock module to be detected, the method further includes: Acquire at least one of the following data: the working state of the clock module to be detected, the temperature of the clock module to be detected, the voltage of the clock module to be detected, and whether the clock module to be detected has been manually configured; If at least one of the following conditions exists: the working state is interrupted, the temperature exceeds the preset temperature threshold, the voltage exceeds the preset voltage threshold, and manual configuration exists; Then, determine the delay of the clock to be detected.

6. A clock delay compensation method, characterized in that: include: Obtaining the delay as described in any one of claims 1 to 5; The delay is compensated to the clock module to be detected corresponding to the delay.

7. The clock delay compensation method according to claim 6, characterized in that: The clock module to be detected that compensates the delay to the delay includes: Compensating the delay into the constant delay memory of the clock module to be detected through the management interface, and the clock module to be detected removes the delay in subsequent clock synchronization calculation; or, Modify the phase of the second synchronous clock so that the second synchronous clock received by the clock module to be detected has compensated for the delay, and the second synchronous clock is a clock obtained by adjusting the first synchronous clock according to the delay; or, According to the delay, the output phase of the local clock of the clock module to be detected is modified.

8. A clock delay detection device, characterized in that: The clock delay detection device comprises: A master clock module, a first physical link, a second physical link and a clock module to be detected; The master clock module includes a sending module, a receiving module and a calculating module, wherein: The sending module is used to transmit the first synchronization clock to the clock module to be detected through the first physical link; The receiving module is used to receive a feedback clock transmitted by the clock module to be detected through the second physical link, where the feedback clock is a clock obtained by adjusting the current clock of the clock module to be detected to have the same phase as the first synchronization clock; The calculation module is used to determine the delay of the clock module to be detected, wherein the delay is determined according to the feedback clock, the self-returning clock and the delay parameter, and the delay parameter includes the delay parameter corresponding to the first physical link and the delay parameter corresponding to the second physical link; The calculation module includes: a first calculation submodule, a second calculation submodule, a third calculation submodule and a fourth calculation submodule, wherein The first calculation submodule is used to obtain the phase relationship between the feedback clock and the self-returning clock; The second calculation submodule is used to determine the corresponding delay value according to the phase relationship; The third calculation submodule is used to obtain the delay parameter, and the delay parameter is determined according to the routing distance between the first physical link and the second physical link and the physical plate material parameter of the board; The fourth calculation submodule is used to determine the delay according to the delay value and the delay parameter.

9. The clock delay detection device according to claim 8, characterized in that: The first calculation submodule is used to obtain the phase relationship between the feedback clock and the self-returning clock, including: The first calculation submodule selects clock data in the feedback clock and performs phase detection with the self-returned clock to determine the phase relationship.

10. The clock delay detection device according to claim 8, characterized in that: The first calculation submodule is used to obtain at least two phase relationships between the feedback clock and the self-returning clock; The second calculation submodule is used to determine at least two corresponding delay values ​​according to the at least two phase relationships.

11. The clock delay detection device according to claim 10, characterized in that: The fourth calculation submodule is used to process the at least two delay values ​​according to a preset rule to obtain a processed delay value; The delay is determined according to the processed delay value and the delay parameter.

12. The clock delay detection device according to any one of claims 8 to 11, characterized in that: The clock delay detection device shown also includes: a judgment module, The judging module is used for, before the calculating module determines the delay of the clock module to be detected: Acquire at least one of the following data: the working state of the clock module to be detected, the working state of the clock module to be detected, the temperature of the clock module to be detected, the voltage of the clock module to be detected, and whether the clock module to be detected has been manually configured; If at least one of the following conditions exists: the working state is interrupted, the temperature exceeds the preset temperature threshold, the voltage exceeds the preset voltage threshold, and manual configuration exists; Then, the calculation module determines the delay of the clock to be detected.

13. A clock delay compensation device, characterized in that: The clock delay compensation device comprises a clock delay detection device and a compensation module as described in any one of claims 8 to 12; The compensation module is used to obtain the delay detected by the clock delay detection device, and compensate the delay to the clock module to be detected corresponding to the delay.

14. The clock delay compensation device according to claim 13, characterized in that: The compensation module also includes: A first compensation module, used for compensating the delay into the constant delay memory of the clock module to be detected through a management interface, and the clock module to be detected removes the delay in subsequent clock synchronization calculation; or, A second compensation module is used to modify the phase of a second synchronous clock so that the second synchronous clock received by the clock module to be detected has compensated for the delay, and the second synchronous clock is a clock obtained by adjusting the first synchronous clock according to the delay; or, The third compensation module is used to modify the output phase of the local clock of the clock module to be detected according to the delay.

15. A terminal, characterized in that: The terminal comprises: a first processor, a first memory and a first communication bus; The first communication bus is used to realize the connection and communication between the first processor and the first memory; The first processor is used to execute one or more first computer programs stored in the first memory to implement the steps of the clock delay detection method according to any one of claims 1 to 5.

16. A terminal, characterized in that: The terminal comprises: a second processor, a second memory and a second communication bus; The second communication bus is used to realize the connection and communication between the second processor and the second memory; The second processor is used to execute one or more second computer programs stored in the second memory to implement the steps of the clock delay compensation method as described in any one of claims 6 or 7.

17. A readable storage medium, characterized in that: The readable storage medium stores one or more first computer programs, and the one or more first computer programs can be executed by one or more first processors to implement the steps of the clock delay detection method according to any one of claims 1 to 5; or, The readable storage medium stores one or more second computer programs, and the one or more second computer programs can be executed by one or more second processors to implement the steps of the clock delay compensation method as described in any one of claims 6 or 7.

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