An input offset voltage automatic correction circuit

Abstract

The present invention relates to an input offset voltage automatic correction circuit, the correction circuit includes a comparator circuit, a comparator circuit output drive tube, a switch control tube, and a logic control module; wherein the comparator circuit includes a first-level input and a second-level input, the correction circuit also includes a first-level input load and a second-level input load, the first-level input is connected to the first-level input load, the second-level input is connected to the second-level load, and the switch control tube controls the comparison circuit; the technical solution has a simple structure, and automatic correction can be achieved by adding conventional components. The circuit of the present invention will re-correct the input offset voltage every time it is powered on, eliminating the influence of the external environment on the input offset voltage, and the technical solution automatically reduces the input offset voltage of the comparator to a very low level.

Description

Technical Field

[0001] The invention relates to a correction circuit, in particular to an input offset voltage automatic correction circuit, and belongs to the technical field of analog integrated circuit design. Background Art

[0002] In the process of analog integrated circuit design, high-precision comparators are often used. High-precision comparators have very high requirements for input offset voltage, usually requiring the input offset voltage to be less than 1mV or even 0.1mV. Ideally, when the positive input and inverting input of the comparator are connected to the same input voltage, the output of the comparator is the middle value of the power supply voltage. When the voltage at the positive input of the comparator is higher than the inverting input, the output of the comparator is high, and when the voltage at the positive input of the comparator is lower than the inverting input, the output of the comparator is low. In the actual process, due to the influence of the circuit, layout and manufacturing process, the comparator has an input offset voltage △V. Only when the voltage at the positive input of the comparator is higher than the voltage at the inverting input by △V, the output of the comparator is high, and when the voltage at the positive input of the comparator minus △V is lower than the voltage at the inverting input, the output of the comparator is low.

[0003] Input offset voltage has a great impact on the use of high-precision comparators. Due to factors such as circuits, layouts, and manufacturing processes, we cannot completely eliminate the input offset voltage, but we can use some technical means to reduce the value of the input offset voltage as much as possible and minimize its adverse effects. Summary of the invention

[0004] The present invention aims at the problems existing in the prior art and provides an input offset voltage automatic correction circuit. The technical solution has a simple structure and can realize automatic correction by adding conventional components. The circuit of the present invention will re-correct the input offset voltage every time it is powered on, eliminating the influence of the external environment on the input offset voltage. The technical solution automatically reduces the input offset voltage of the comparator to a very low level.

[0005] In order to achieve the above-mentioned purpose, the technical solution of the present invention is as follows: an input offset voltage automatic correction circuit, the correction circuit includes a comparator circuit, a comparator circuit output driver tube, a switch control tube, and a logic control module; wherein the comparator circuit includes a first-level input and a second-level input, the correction circuit also includes a first-level input load and a second-level input load, the first-level input is connected to the first-level input load, the second-level input is connected to the second-level load, and the switch control tube controls the comparison circuit.

[0006] As an improvement of the present invention, the comparator circuit includes PMOS tubes P1, P2, P3 and P4, wherein the PMOS tubes P1 and P2 are used as an input pair of tubes for the first-stage input of the comparator circuit; the PMOS tubes P3 and P4 are used as an input pair of tubes for the second-stage input of the comparator circuit; the resistors R1 to R10 are used as loads for the first-stage input of the comparator; the NMOS tubes N1 and N2 are used as loads for the second-stage input; and the NMOS tube N3 is used as an output drive tube of the comparator circuit.

[0007] As an improvement of the present invention, the NMOS tubes N4~N13 and the PMOS tubes P5 and P6 are used as switch control tubes, LOGIC is the logic control module of the circuit of the present invention, the output signal OUT of the comparator is used as the input signal of the LOGIC module, and Trim and K1~K8 are the output signals of the LOGIC module.

[0008] As an improvement of the present invention, the internal circuit of the logic control module LOGIC includes a clock generating circuit CLK, a clock dividing circuit DFF, a comparator circuit COMP and an RS trigger RS, wherein one end of the clock dividing circuit DFF is connected to the clock generating circuit CLK, and the other end is connected to the comparator circuit COMP, and the comparator circuit COMP is connected to two triggers RS at the same time.

[0009] Compared with the prior art, the present invention has the following advantages: 1) the technical solution can automatically correct the input offset voltage without manual testing and burning. The circuit structure of the present invention is simple, and automatic correction can be achieved by adding conventional components; 2) the circuit of the present invention will re-correct the input offset voltage every time it is powered on, eliminating the influence of the external environment on the input offset voltage. The comparator circuit of the present invention can control the accuracy of the input offset voltage within 0.1mV, which is far better than most comparator circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of the overall structure of the present invention;

[0011] Figure 2 It is a schematic diagram of the internal circuit of the logic control module LOGIC;

[0012] Figure 3 It is a schematic diagram of the signal waveforms of D1~D4 and Trim in the LOGIC circuit;

[0013] Figure 4 This is a schematic diagram of the working principle of LOGIC. DETAILED DESCRIPTION

[0014] In order to deepen the understanding of the present invention, the present embodiment is described in detail below with reference to the accompanying drawings.

[0015] Example 1: See Figure 1 , an input offset voltage automatic correction circuit, the correction circuit includes a comparator circuit, a comparator circuit output driver, a switch control tube, and a logic control module; wherein the comparator circuit includes a first-level input and a second-level input, the correction circuit also includes a first-level input load and a second-level input load, the first-level input is connected to the first-level input load, the second-level input is connected to the second-level load, and the switch control tube controls the comparison circuit. The comparator circuit includes PMOS tubes P1, P2, P3 and P4, wherein PMOS tubes P1 and P2 are used as input pairs of tubes for the first-level input of the comparator circuit; PMOS tubes P3 and P4 are used as input pairs of tubes for the second-level input of the comparator circuit; resistors R1 to R10 are used as loads of the first-level input of the comparator; NMOS tubes N1 and N2 are used as loads of the second-level input; and NMOS tube N3 is used as an output driver of the comparator circuit. , the NMOS tubes N4~N13 and the PMOS tubes P5 and P6 are used as switch control tubes, LOGIC is the logic control module of the circuit of the present invention, the output signal OUT of the comparator is used as the input signal of the LOGIC module, Trim and K1~K8 are the output signals of the LOGIC module, the internal circuit of the logic control module LOGIC, the internal circuit of the logic control module LOGIC includes a clock generating circuit CLK, a clock frequency dividing circuit DFF, a comparator circuit COMP and an RS trigger RS, wherein one end of the clock frequency dividing circuit DFF is connected to the clock generating circuit CLK, and the other end is connected to the comparator circuit COMP, and the comparator circuit COMP is connected to two triggers RS at the same time.

[0016] Working principle: See Figure 1 — Figure 4 , an input offset voltage automatic correction circuit, the working principle is as follows:

[0017] When designing a comparator, the input offset voltage of the comparator can be easily designed to be within the range of -4mV to 4mV through optimization of circuits, layout and process. That is, the input offset voltage is:

[0018] -4mV<△V<4mV;

[0019] Resistors R1 to R8 will cause the offset voltage of the comparator to change, but the amount of change is different. R7 will produce an offset voltage change of +0.25±0.05mV mV, R8 will produce an offset voltage change of -0.25mV±0.05mV, R5 will produce an offset voltage change of +0.5mV±0.05mV, R6 will produce an offset voltage change of -0.5mV±0.05mV, R3 will produce an offset voltage change of +1mV±0.05mV, R4 will produce an offset voltage change of -1mV±0.05mV, R1 will produce an offset voltage change of +2mV±0.05mV, and R2 will produce an offset voltage change of about -2mV±0.05mV.

[0020] 1. Initial power-on judgment

[0021] After the circuit is started, the Trim signal is set to a high level, the positive and negative input terminals INP and INN of the comparator are short-circuited to ground, the switch signals K1 to K8 are set to high levels, and the resistors R1 to R8 are short-circuited.

[0022] 1.1 If the output OUT of the comparator is high, it means that the input offset voltage of the comparator is a negative voltage value. Since -4mV<△V<4mV, then:

[0023] -4mV<△V<0mV---------------Formula 1;

[0024] 1.2 If the output OUT of the comparator is low, it means that the input offset voltage of the comparator is a positive voltage value. Since -4mV<△V<4mV, then:

[0025] 0mV<△V<4mV---------------Formula 2;

[0026] Combining Formula 1 and Formula 2, we know:

[0027] |△V|<4mV;

[0028] That is, the initial accuracy of the comparator's input offset voltage is 4mV.

[0029] 2. First revision

[0030] 2.1 If OUT is high, it means that the input offset voltage of the comparator is a negative voltage value, that is, -4mV<△V<0mV. When the D1 signal is high, the switch signal K1 is set to a low level, and the resistor R1 starts to work, causing the comparator to produce an input offset voltage change of +2mV±0.05mV, so the input offset voltage of the comparator is corrected to:

[0031] △V1=△V+2mV±0.05mV;

[0032] Since -4mV<△V<0mV, so:

[0033] -2.05mV<△V1<2.05mV-----------------Formula 3;

[0034] 2.2 If OUT is low, it means that the input offset voltage of the comparator is a positive voltage value, that is, 0mV<△V<4mV. When the D1 signal is high, the switch signal K2 is set to a low level, and the resistor R2 starts to work, causing the comparator to produce an input offset voltage change of -2mV±0.05mV, so the input offset voltage of the comparator is corrected to:

[0035] △V1=△V-2mV±0.05mV

[0036] Since 0mV<△V<4mV, so:

[0037] -2.05mV<△V1<2.05mV-----------------Formula 4;

[0038] Combining Formula 3 and Formula 4, we know:

[0039] |△V1|<2.05mV

[0040] That is, the input offset voltage accuracy of the comparator is optimized to 2.05mV after the first correction.

[0041] 3. Second Amendment

[0042] 3.1 If OUT is high, it means that the input offset voltage of the comparator is a negative voltage value, that is, -2.05mV<△V1<0mV. When the D2 signal is high, the switch signal K3 is set to a low level, and the resistor R3 starts to work, causing the comparator to produce an input offset voltage change of +1mV±0.05mV, so the input offset voltage of the comparator is corrected to:

[0043] △V2=△V1+1mV±0.05mV

[0044] Since -2.05mV<△V1<0mV, so:

[0045] -1.1mV<△V2<1.05mV-----------------Formula 5;

[0046] 3.2 If OUT is low, it means that the input offset voltage of the comparator is a positive voltage value, that is, 0mV<△V1<2.05mV. When the D2 signal is high, the switch signal K4 is set to a low level, and the resistor R4 starts to work, causing the comparator to produce an input offset voltage change of -1mV±0.05mV, so the input offset voltage of the comparator is corrected to:

[0047] △V2=△V1-1mV±0.05mV

[0048] Since 0mV<△V1<2.05mV, so:

[0049] -1.05mV<△V2<1.1mV-----------------Formula 6;

[0050] Combining Formula 5 and Formula 6, we know:

[0051] |△V2|<1.1mV;

[0052] That is, the input offset voltage accuracy of the comparator is optimized to 1.1mV after the second correction.

[0053] 4. Third Amendment;

[0054] 4.1 If OUT is high, it means that the input offset voltage of the comparator is a negative voltage value, that is, -1.1mV<△V2<0mV. When the D3 signal is high, the switch signal K5 is set to a low level, and the resistor R5 starts to work, causing the comparator to produce an input offset voltage change of +0.5mV±0.05mV, so the input offset voltage of the comparator is corrected to:

[0055] △V3=△V2+0.5mV±0.05mV

[0056] Since -1.1mV<△V2<0mV, so:

[0057] -0.65mV<△V3<0.55mV-----------------Formula 7;

[0058] 4.2 If OUT is low, it means that the input offset voltage of the comparator is a positive voltage value, that is, 0mV<△V2<1.1mV. When the D3 signal is high, the switch signal K6 is set to a low level, and the resistor R6 starts to work, causing the comparator to produce an input offset voltage change of -0.5mV±0.05mV, so the input offset voltage of the comparator is corrected to:

[0059] △V3=△V2-0.5mV±0.05mV

[0060] Since 0mV<△V2<1.1mV, so:

[0061] -0.55mV<△V3<0.65mV-----------------Formula 8;

[0062] Combining Formula 7 and Formula 8, we know that:

[0063] |△V3|<0.65mV

[0064] That is, the input offset voltage accuracy of the comparator is optimized to 0.65mV after the third correction.

[0065] 5. Fourth Amendment

[0066] 5.1 If OUT is high, it means that the input offset voltage of the comparator is a negative voltage value, that is, -0.65mV<△V3<0mV. When the D4 signal is high, the switch signal K7 is set to a low level, and the resistor R7 starts to work, causing the comparator to produce an input offset voltage change of +0.25mV±0.05mV, so the input offset voltage of the comparator is corrected to:

[0067] △V4=△V3+0.25mV±0.05mV

[0068] Since -0.65mV<△V3<0mV, so:

[0069] -0.45mV<△V4<0.3mV-----------------Formula 9

[0070] 5.2 If OUT is low, it means that the input offset voltage of the comparator is a positive voltage value, that is, 0mV<△V3<0.65mV. When the D4 signal is high, the switch signal K8 is set to a low level, and the resistor R8 starts to work, causing the comparator to produce an input offset voltage change of -0.25mV±0.05mV, so the input offset voltage of the comparator is corrected to:

[0071] △V4=△V3-0.25mV±0.05mV

[0072] Since 0mV<△V3<0.65mV, so:

[0073] -0.3mV<△V4<0.45mV-----------------Formula 10

[0074] Combining Formula 9 and Formula 10, we know:

[0075] |△V4|<0.45mV

[0076] That is, the input offset voltage accuracy of the comparator is optimized to 0.45mV after the fourth correction.

[0077] After the fourth input offset voltage correction is completed, the Trim signal is set to a low level, the entire input offset voltage correction process is completed, and the positive and negative input terminals of the comparator are connected to the external input signal (InputSignal). After that, the input offset voltage accuracy of the comparator is determined to be 0.45mV.

[0078] The patented circuit of the present invention only takes a 4-bit offset correction circuit as an example, and its input offset voltage accuracy is less than 0.45mV. As long as the number of offset correction bits is increased and the correction resistors are matched well, the patented circuit of the present invention can optimize the input offset voltage accuracy of the comparator to within 0.1mV.

[0079] It should be noted that the above embodiments are not intended to limit the protection scope of the present invention, and equivalent changes or substitutions made on the basis of the above technical solutions all fall within the protection scope of the claims of the present invention.

Claims

1. An input offset voltage automatic correction circuit, characterized in that: The correction circuit includes a comparator circuit, a comparator circuit output drive tube, a switch control tube, and a logic control module; wherein the comparator circuit includes a first-level input and a second-level input, the correction circuit also includes a first-level input load and a second-level input load, the first-level input is connected to the first-level input load, the second-level input is connected to the second-level load, and the switch control tube controls the comparison circuit; The comparator circuit includes PMOS tubes P1, P2, P3 and P4, wherein PMOS tubes P1 and P2 are used as input pairs of tubes for the first-stage input of the comparator circuit; PMOS tubes P3 and P4 are used as input pairs of tubes for the second-stage input of the comparator circuit; resistors R1 to R10 are used as loads for the first-stage input of the comparator; NMOS tubes N1 and N2 are used as loads for the second-stage input; and NMOS tube N3 is used as an output drive tube of the comparator circuit; The NMOS tubes N4~N13 and the PMOS tubes P5 and P6 are used as switch control tubes. Among them, N4 is connected to the drain and drain of P5, and is also connected to the INN signal; the gate is connected to the gate, and is also connected to the Trim signal; the source of N4 is grounded, and the source of P5 is connected to one end of the input signal. When the Trim signal is high, the INN signal is grounded through N4, and when the Trim signal is low, the INN signal is connected to one end of the input signal through P5. N5 is connected to the drain and drain of P6, and is also connected to the INP signal; the gate is connected to the gate, and is also connected to the Trim signal; the source of N5 is grounded, and the source of P6 is connected to the other end of the input signal. When the Trim signal is high, the INP signal is grounded through N5, and when the Trim signal is low, the INP signal is connected to the other end of the input signal through P6. The NMOS tubes N6 to N13 are used as switch tubes, and their source and drain ends are respectively connected in parallel with the resistors R1 to R8. When the gate control signal is at a high level, the switch tube can short-circuit the resistors connected in parallel with it. in, Both ends of N6 source and drain are connected in parallel with resistor R1, and the gate control signal is connected to K1; Both ends of N7 source and drain are connected in parallel with resistor R2, and the gate control signal is connected to K2; Both ends of N8 source and drain are connected in parallel with resistor R3, and the gate control signal is connected to K3; Both ends of N9 source and drain are connected in parallel with resistor R4, and the gate control signal is connected to K4; The source and drain ends of N10 are connected in parallel with resistor R5, and the gate control signal is connected to K5; Both ends of N11 source and drain are connected in parallel with resistor R6, and the gate control signal is connected to K6; Both ends of N12 source and drain are connected in parallel with resistor R7, and the gate control signal is connected to K7; Both ends of N13 source and drain are connected in parallel with resistor R8, and the gate control signal is connected to K8; LOGIC is the logic control module, the output signal OUT of the comparator is used as the input signal of the logic control module, and Trim and K1~K8 are the output signals of the logic control module; The internal circuit of the logic control module LOGIC includes a clock generating circuit CLK, a clock frequency dividing circuit DFF, a comparator circuit COMP and an RS trigger RS, wherein one end of the clock frequency dividing circuit DFF is connected to the clock generating circuit CLK, and the other end is connected to the comparator circuit COMP, and the comparator circuit COMP is simultaneously connected to two triggers RS.

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