Semiconductor device, display device, display module, and electronic device

Abstract

The present invention is entitled a semiconductor device, a display device, a display module, and an electronic device. One embodiment of the present invention provides a semiconductor device, which includes an interleaved transistor and a capacitor using an oxide semiconductor. One embodiment of the present invention is a semiconductor device including a transistor and a capacitor, wherein the transistor includes: an oxide semiconductor film; a gate insulating film on the oxide semiconductor film; a gate electrode on the gate insulating film; a second insulating film on the gate electrode; a third insulating film on the second insulating film; and a source electrode and a drain electrode on the third insulating film, the source electrode and the drain electrode being electrically connected to the oxide semiconductor film, and the capacitor includes: a first conductive film; a second conductive film; and the second insulating film, the first conductive film and the gate electrode are arranged on the same surface, the second conductive film and the source electrode and the drain electrode are arranged on the same surface, and the second insulating film is arranged between the first conductive film and the second conductive film.

Description

[0001] This application is a divisional application of the following invention patent application:

[0002] Invention name: semiconductor device, display device, display module and electronic device; Application date: February 5, 2015; Application number: 201510060315.X. Technical Field

[0003] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor film and a display device using the semiconductor device.

[0004] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc. relates to an object, method or manufacturing method. In addition, the present invention relates to a process, machine, product or composition of matter. One embodiment of the present invention particularly relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof or a manufacturing method thereof.

[0005] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are all forms of semiconductor devices. Camera devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells or organic thin-film solar cells, etc.), and electronic devices sometimes include semiconductor devices. Background Art

[0006] The technology of forming a transistor (also called a field effect transistor (FET) or a thin film transistor (TFT)) by using a semiconductor film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). As semiconductor films that can be applied to transistors, semiconductor materials represented by silicon are well known. In addition, as other materials, oxide semiconductors have attracted attention.

[0007] For example, a technology is disclosed in which a transistor is manufactured using an amorphous oxide containing In, Zn, Ga, Sn, etc. as an oxide semiconductor (see Patent Document 1). In addition, a technology is also disclosed in which a transistor having a self-aligned top gate structure is manufactured using an oxide thin film (see Patent Document 2).

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2006-165529

[0009] [Patent Document 2] Japanese Patent Application Publication No. 2009-278115

[0010] As transistors using oxide semiconductor films, for example, inverted staggered (also called bottom gate structure) transistors or staggered (also called top gate structure) transistors can be cited. When a transistor using an oxide semiconductor film is used in a display device, the inverted staggered type is used more often than the staggered type transistor, because the manufacturing process of the inverted staggered type is relatively simple and its manufacturing cost can be suppressed. However, there is the following problem: with the increasing size or high definition of the screen in the display device (for example, a high-definition display device represented by 4k×2k (the number of pixels in the horizontal direction is 3840 and the number of pixels in the vertical direction is 2160) or 8k×4k (the number of pixels in the horizontal direction is 7680 and the number of pixels in the vertical direction is 4320)), the inverted staggered transistor has a parasitic capacitance between the gate electrode and the source electrode and a parasitic capacitance between the gate electrode and the drain electrode, and the signal delay is increased due to the parasitic capacitance, which will lead to a decrease in the display quality of the display device. There is also the problem that the area occupied by the transistor is larger when using the inversely staggered transistor than when using the staggered transistor. Therefore, the staggered transistor using the oxide thin film is required to have stable semiconductor characteristics and a highly reliable structure and can be manufactured by a simple manufacturing process.

[0011] In addition, as the screen size or high definition in the display device is increasingly advanced, the structure of the transistor formed in the pixel of the display device and the capacitor connected to the transistor is important. The capacitor is used as a storage capacitor to store the data written into the pixel. Depending on the structure of the capacitor, there is a problem that the display quality of the display device is degraded due to the inability to maintain the data written into the pixel. Summary of the invention

[0012] In view of the above problems, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device including a transistor using an oxide semiconductor. In particular, one of the purposes of one embodiment of the present invention is to provide a semiconductor device including a staggered transistor using an oxide semiconductor. One of the other purposes of one embodiment of the present invention is to provide a semiconductor device including a staggered transistor using an oxide semiconductor and a capacitor connected to the transistor. One of the other purposes of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having a large on-state current. One of the other purposes of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having a small off-state current. One of the other purposes of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and occupying a small area. One of the other purposes of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having stable electrical characteristics. One of the other purposes of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having high reliability. One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. One of the purposes of one embodiment of the present invention is to provide a novel display device.

[0013] Note that the description of the above-mentioned purpose does not prevent the existence of other purposes. In addition, one mode of the present invention does not need to achieve all of the above-mentioned purposes. The purposes other than the above-mentioned purpose are obvious from the description of the specification, etc., and the purposes other than the above-mentioned purpose can be extracted from the description of the specification, etc.

[0014] One embodiment of the present invention is a semiconductor device including a transistor and a capacitor, wherein the transistor includes: an oxide semiconductor film; a gate insulating film on the oxide semiconductor film; a gate electrode on the gate insulating film; a second insulating film on the gate electrode; a third insulating film on the second insulating film; a source electrode on the third insulating film; and a drain electrode on the third insulating film, the source electrode is electrically connected to the oxide semiconductor film, and the drain electrode is electrically connected to the oxide semiconductor film, and the capacitor includes: a first conductive film; a second conductive film; and a second insulating film, the first conductive film and the gate electrode are arranged on the same surface, the second conductive film and the source electrode and the drain electrode are arranged on the same surface, and the second insulating film is arranged between the first conductive film and the second conductive film. For details, refer to the following.

[0015] One embodiment of the present invention is a semiconductor device including a transistor and a capacitor, wherein the transistor includes: an oxide semiconductor film on a first insulating film; a gate insulating film on the oxide semiconductor film; a gate electrode on the gate insulating film; a second insulating film on the gate electrode; a third insulating film on the second insulating film; a source electrode on the third insulating film; and a drain electrode on the third insulating film, the first insulating film has oxygen, the second insulating film has nitrogen, the source electrode is electrically connected to the oxide semiconductor film, and the drain electrode is electrically connected to the oxide semiconductor film, and the capacitor includes: a first conductive film; a second conductive film; and a second insulating film, the first conductive film and the gate electrode are arranged on the same surface, the second conductive film and the source electrode and the drain electrode are arranged on the same surface, and the second insulating film is arranged between the first conductive film and the second conductive film.

[0016] In addition, another embodiment of the present invention is a semiconductor device including a transistor and a capacitor, wherein the transistor includes: a first gate electrode on a first insulating film; a first gate insulating film on the first gate electrode; an oxide semiconductor film on the first gate insulating film; a second gate insulating film on the oxide semiconductor film; a second gate insulating film on the second gate insulating film; a second insulating film on the second gate electrode; a third insulating film on the second insulating film; a source electrode on the third insulating film; and a drain electrode on the third insulating film, the first gate insulating film has oxygen, the second insulating film has nitrogen, the source electrode is electrically connected to the oxide semiconductor film, and the drain electrode is electrically connected to the oxide semiconductor film, and the capacitor includes: a first conductive film; a second conductive film; and a second insulating film, the first conductive film and the second gate electrode are arranged on the same surface, the second conductive film and the source electrode and the drain electrode are arranged on the same surface, and the second insulating film is arranged between the first conductive film and the second conductive film.

[0017] In addition, in the above-mentioned embodiment, it is preferred that the oxide semiconductor film includes a first region and a second region, the first region has a region overlapping with the gate electrode, the second region has a region not overlapping with the gate electrode, the first region has a portion having an impurity element concentration of a first concentration, the second region has a portion having an impurity element concentration of a second concentration, and the first concentration is different from the second concentration. In addition, in the above-mentioned embodiment, it is preferred that the oxide semiconductor film includes a first region and a second region, the first region has a region overlapping with the second gate electrode, the second region has a region not overlapping with the second gate electrode, the first region has a portion having an impurity element concentration of a first concentration, the second region has a portion having an impurity element concentration of a second concentration, and the first concentration is different from the second concentration.

[0018] In the above embodiment, the impurity element preferably includes one or more of hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine and a rare gas element. In the above embodiment, the impurity element preferably includes argon and hydrogen.

[0019] In the above embodiment, the second region preferably has a region in contact with the second insulating film. In the above embodiment, the second region preferably has a region having a higher impurity element concentration than the first region. In the above embodiment, the first region preferably has a region having a higher crystallinity than the second region.

[0020] In addition, in the above-mentioned embodiment, the oxide semiconductor film preferably contains oxygen, In, Zn and M (M is Ti, Ga, Y, Zr, La, Ce, Nd or Hf). In addition, in the above-mentioned embodiment, the oxide semiconductor film preferably includes a crystalline portion, and the crystalline portion preferably has a c-axis orientation and a portion in which the c-axis is parallel to the normal vector of the formed surface of the oxide semiconductor film.

[0021] In addition, another embodiment of the present invention is a display device including the semiconductor device described in any of the above embodiments and a display element. In addition, another embodiment of the present invention is a display module including the display device and a touch sensor. In addition, another embodiment of the present invention is an electronic device, which includes: the semiconductor device described in any of the above embodiments, the display device or the display module; and an operation key or a battery.

[0022] Through one embodiment of the present invention, a novel semiconductor device including a transistor using an oxide semiconductor can be provided. In particular, through one embodiment of the present invention, a semiconductor device including an interleaved transistor using an oxide semiconductor can be provided. In addition, a semiconductor device can be provided, which includes an interleaved transistor using an oxide semiconductor and a capacitor connected to the transistor. In addition, a semiconductor device can be provided, which includes a transistor using an oxide semiconductor and having a large on-state current. In addition, a semiconductor device can be provided, which includes a transistor using an oxide semiconductor and having a small off-state current. In addition, a semiconductor device can be provided, which includes a transistor using an oxide semiconductor and occupying a small area. One of the other purposes of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having stable electrical characteristics. In addition, a semiconductor device can be provided, which includes a transistor using an oxide semiconductor and having high reliability. In addition, a novel semiconductor device can be provided. In addition, a novel display device can be provided.

[0023] Note that the description of these effects does not prevent the existence of other effects. In addition, one mode of the present invention does not need to have all of the above effects. In addition, effects other than these effects are obvious from the description of the specification, drawings, claims, etc., so that effects other than these effects can be extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figures 1A to 1D A top view and a cross-sectional view showing one embodiment of a semiconductor device;

[0025] Figure 2 is a cross-sectional view showing one embodiment of a semiconductor device;

[0026] Figures 3A to 3D is a cross-sectional view showing one embodiment of a semiconductor device;

[0027] Figure 4A and 4B is a cross-sectional view showing one embodiment of a semiconductor device;

[0028] Figures 5A to 5D A top view and a cross-sectional view showing one embodiment of a semiconductor device;

[0029] Figure 6 is a cross-sectional view showing one embodiment of a semiconductor device;

[0030] Figures 7A to 7D is a cross-sectional view showing one embodiment of a semiconductor device;

[0031] Figures 8A to 8D is a cross-sectional view showing one embodiment of a semiconductor device;

[0032] Figures 9A to 9D is a cross-sectional view showing one embodiment of a semiconductor device;

[0033] Fig.10 is a cross-sectional view showing one embodiment of a semiconductor device;

[0034] Figures 11A to 11C A cross-sectional view showing one embodiment of a semiconductor device and a diagram showing one embodiment of an energy band structure;

[0035] Figures 12A to 12H is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0036] Figures 13A to 13F is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0037] Figures 14A to 14F is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0038] Figures 15A to 15F is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0039] Figures 16A to 16F is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0040] 17A to 17C are cross-sectional TEM images and local Fourier transform images of an oxide semiconductor;

[0041] Figures 18A to 18D is a diagram showing a nanobeam electron diffraction pattern of an oxide semiconductor film and a diagram showing an example of a transmission electron diffraction measurement apparatus;

[0042] Figures 19A to 19C is a diagram showing an example of structural analysis using transmission electron diffraction measurement and a planar TEM image;

[0043] Fig. 20 is a diagram illustrating the computational model;

[0044] Fig.21A and 21B is a diagram illustrating the initial state and the final state;

[0045] Fig. 22 is a graph illustrating activation energy;

[0046] Fig.23A and 23B is a diagram illustrating the initial state and the final state;

[0047] Fig.24 is a graph illustrating activation energy;

[0048] Fig.25 It means V O Diagram of the migration energy levels of H;

[0049] Fig.26 is a top view showing one aspect of a display device;

[0050] Fig. 27 is a cross-sectional view showing one embodiment of a display device;

[0051] Fig.28 is a cross-sectional view showing one embodiment of a display device;

[0052] Fig.29A and 29B is a diagram illustrating the structure of a pixel portion of a light-emitting device;

[0053] Figures 30A to 30D is a cross-sectional view of a semiconductor device;

[0054] Figures 31A to 31C is a top view and a circuit diagram of the display device;

[0055] Fig.32A and 32B It is a circuit diagram and timing diagram of the display device;

[0056] Fig.33A and 33BIt is a circuit diagram and timing diagram of the display device;

[0057] Fig.34A and 34B It is a circuit diagram and timing diagram of the display device;

[0058] Fig.35A and 35B It is a circuit diagram and timing diagram of the display device;

[0059] Fig.36 is a diagram illustrating a display module;

[0060] Figures 37A to 37H is a diagram illustrating an electronic device;

[0061] Fig.38A and 38B is a cross-sectional TEM image in the embodiment;

[0062] Fig.39 is a graph illustrating the temperature dependence of resistivity;

[0063] Figures 40A to 40C is a schematic diagram illustrating a film formation model of CAAC-OS, and a cross-sectional view of particles and CAAC-OS;

[0064] Fig.41 is a schematic diagram illustrating a film formation model of nc-OS, wherein particles are shown;

[0065] Fig.42 is a diagram illustrating particles;

[0066] Fig.43 is a diagram illustrating the forces applied to particles on the formed surface;

[0067] Fig.44A and 44B It is a diagram illustrating the behavior of particles on the formed surface;

[0068] Fig.45A and 45B InGaZnO 4 The crystal diagram of

[0069] 46A and 46B show InGaZnO before atomic collision. 4 diagram of the structure, etc.

[0070] 47A and 47B are diagrams showing InGaZnO after atomic collision. 4 diagram of the structure, etc.

[0071] 48A and 48B are diagrams showing the trajectories of atoms after atomic collisions;

[0072] Fig.49A and49B It is a cross-sectional HAADF-STEM image of the CAAC-OS film and the target. DETAILED DESCRIPTION

[0073] The following describes the embodiments with reference to the accompanying drawings. However, a person skilled in the art can easily understand that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the following embodiments.

[0074] In the accompanying drawings, for the sake of clarity, the size, thickness of the layer or the region are sometimes exaggerated. Therefore, the present invention is not necessarily limited to the above-mentioned dimensions. In addition, in the accompanying drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the accompanying drawings.

[0075] The ordinal numbers such as “first”, “second” and “third” used in the present specification are added to avoid confusion among constituent elements, and are not intended to limit the number.

[0076] In this specification, for convenience, words and phrases such as "upper" and "lower" are used to indicate the positional relationship of the components with reference to the drawings. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, the words and phrases described in this specification are not limited and can be appropriately replaced according to the situation.

[0077] In this specification, etc., a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain terminal, drain region, or drain electrode) and a source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, etc., a channel region refers to a region through which current mainly flows.

[0078] The functions of "source" and "drain" may be interchanged when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" may be interchanged.

[0079] In addition, in this specification, "electrical connection" includes connection through "an element having some kind of electrical function". Here, "an element having some kind of electrical function" is not particularly limited as long as it can transmit and receive electrical signals between the connected objects. For example, "an element having some kind of electrical function" includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0080] Implementation Method 1

[0081] In this embodiment, refer to Figures 1A to 16F An example of a semiconductor device in which a transistor and a capacitor are provided over the same substrate and a method for manufacturing the semiconductor device will be described.

[0082] <Structure of semiconductor device 1>

[0083] Figures 1A to 1D An example of a semiconductor device in which a transistor and a capacitor are provided over the same substrate is shown. Note that this transistor has a top-gate structure.

[0084] Figure 1A is a top view of a transistor 100 included in a semiconductor device. Figure 1B is a top view of a capacitor 150 included in the semiconductor device. Figure 1C It is along Figure 1A The cross-sectional view along the dot-dash line X1-X2, Figure 1D It is along Figure 1B Note that for convenience, Figure 1A and 1B The substrate 102, the insulating film 104, the insulating film 108, the insulating film 118, the insulating film 120, and the like are omitted. Note that in the top view of the transistor and the capacitor element below, Figure 1A and 1B In the same manner, some of the components are omitted. In addition, the direction of the dashed line X1 - X2 is sometimes referred to as the channel length direction, and the direction of the dashed line Y1 - Y2 is sometimes referred to as the channel width direction.

[0085] Figure 1A and 1C The transistor 100 shown includes: an insulating film 108 formed on a substrate 102; an oxide semiconductor film 110 on the insulating film 108; an insulating film 112 on the oxide semiconductor film 110; a conductive film 114 overlapping the oxide semiconductor film 110 via the insulating film 112; an insulating film 118 covering the oxide semiconductor film 110, the insulating film 112, and the conductive film 114; an insulating film 120 on the insulating film 118; a conductive film 122 connected to the oxide semiconductor film 110 via an opening 140a provided in the insulating film 118 and the insulating film 120; and a conductive film 124 connected to the oxide semiconductor film 110 via an opening 140b provided in the insulating film 118 and the insulating film 120. In addition, an insulating film 128 covering the insulating film 120, the conductive film 122, and the conductive film 124 may be provided on the transistor 100.

[0086] exist Figure 1C, the insulating film 108 has a stacked structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. The conductive film 114 has a stacked structure of a conductive film 114a and a conductive film 114b on the conductive film 114a. The conductive film 122 has a stacked structure of a conductive film 122a and a conductive film 122b on the conductive film 122a. The conductive film 124 has a stacked structure of a conductive film 124a and a conductive film 124b on the conductive film 124a.

[0087] In the transistor 100, the conductive film 114 functions as a gate electrode (also referred to as a top gate electrode), the conductive film 122 functions as one of a source electrode and a drain electrode, and the conductive film 124 functions as the other of the source electrode and the drain electrode. In addition, in the transistor 100, the insulating film 108 functions as a base film of the oxide semiconductor film 110, and the insulating film 112 functions as a gate insulating film.

[0088] also, Figure 1B and 1D The capacitor element 150 shown includes: an insulating film 108 formed on a substrate 102; an insulating film 112 on the insulating film 108; a conductive film 116 on the insulating film 112; an insulating film 118 covering the insulating film 108, the insulating film 112, and the conductive film 116; an insulating film 120 on the insulating film 118; and a conductive film 126 overlapping the conductive film 116 via the insulating film 118 in an opening 140c provided in the insulating film 120. In addition, an insulating film 128 covering the insulating film 120 and the conductive film 126 may be provided on the capacitor element 150.

[0089] exist Figure 1D In the embodiment, the insulating film 108 has a stacked structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. The conductive film 116 has a stacked structure of a conductive film 116a and a conductive film 116b on the conductive film 116a. The conductive film 126 has a stacked structure of a conductive film 126a and a conductive film 126b on the conductive film 126a.

[0090] The capacitor 150 has a structure in which a dielectric is sandwiched between a pair of electrodes. More specifically, one of the pair of electrodes is a conductive film 116, the other of the pair of electrodes is a conductive film 126, and an insulating film 118 between the conductive films 116 and 126 serves as a dielectric.

[0091] The conductive film 114 used as the gate electrode of the transistor 100 and the conductive film 116 used as one of the pair of electrodes of the capacitor 150 are formed by the same process, and at least a portion of them are formed on the same surface. The conductive film 122 and the conductive film 124 used as the source electrode and the drain electrode of the transistor 100 and the conductive film 126 used as the other of the pair of electrodes of the capacitor 150 are formed by the same process, and at least a portion of the conductive films 122, 124, and 126 are formed on the same surface.

[0092] In this way, by forming the conductive films serving as the electrodes of the transistor 100 and the capacitor 150 in the same process, manufacturing costs can be reduced.

[0093] In addition, in the capacitor 150, the insulating film 120 has the opening 140c. Thus, only the insulating film 118 can be used as a dielectric in the insulating film stacked with the insulating film 118 and the insulating film 120. By adopting the above structure, the capacitance value of the capacitor 150 can be increased. Thus, the capacitance value of the display device can be increased.

[0094] then, Figure 2 Shown along Figure 1A A cross-sectional view of the transistor 100 taken along the dashed line Y1 - Y2 (in the channel width direction) is shown.

[0095] like Figure 2 As shown in FIG. 1 , the end of the conductive film 114a is located outside the end of the conductive film 114b in the channel width direction. The end of the insulating film 112 is located outside the end of the conductive film 114a. The insulating film 108b has a recessed portion in a region that does not overlap with the insulating film 112. By adopting the above structure, the coverage of the insulating film 118, the insulating film 120, and the insulating film 128 can be improved.

[0096] Next, the oxide semiconductor film 110 included in the transistor 100 is described in detail below.

[0097] In the oxide semiconductor film 110 of the transistor 100, a region that does not overlap with the conductive film 114 contains an element that forms an oxygen vacancy. Hereinafter, the element that forms the oxygen vacancy will be referred to as an impurity element for explanation. Typical examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, and rare gas elements. Typical examples of the rare gas element include helium, neon, argon, krypton, and xenon.

[0098] When an impurity element is added to an oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is cut to form an oxygen vacancy. Alternatively, when an impurity element is added to the oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film is bonded to the impurity element, and oxygen is separated from the metal element, thereby forming an oxygen vacancy. As a result, the carrier density of the oxide semiconductor film becomes higher, thereby increasing the conductivity.

[0099] When hydrogen is added to an oxide semiconductor to which an impurity element is added to form an oxygen vacancy, hydrogen enters the oxygen vacancy and forms a donor level near the conduction band. As a result, the conductivity of the oxide semiconductor increases and becomes a conductor. An oxide semiconductor that can become a conductor is called an oxide conductor. Generally speaking, since oxide semiconductors have a large energy gap, they are transparent to visible light. On the other hand, an oxide conductor is an oxide semiconductor with a donor level near the conduction band. Therefore, the influence caused by the absorption of the donor level is small, and it has the same degree of transparency to visible light as an oxide semiconductor.

[0100] Here, regarding a film formed using an oxide conductor (hereinafter referred to as an oxide conductor film), refer to Fig.39 Explain the temperature dependence of its resistivity.

[0101] Here, a sample having an oxide conductor film is manufactured. As the oxide conductor film, the following oxide conductor film is manufactured: an oxide conductor film (OC_SiN x ); an oxide conductor film formed by adding argon to an oxide semiconductor film in contact with a silicon nitride film in a doping device (OC_Ar dope+SiN x ); an oxide conductor film formed by exposing an oxide semiconductor film to argon plasma in a plasma processing apparatus and contacting the oxide semiconductor film with a silicon nitride film (OC_Ar plasma+SiN x ). In addition, the silicon nitride film contains hydrogen.

[0102] The following describes the oxide conductor film (OC_SiN x). After a 400nm thick silicon oxynitride film is formed on a glass substrate by a plasma CVD method, the silicon oxynitride film is exposed to oxygen plasma, and then oxygen ions are added to the silicon oxynitride film to form an oxynitride silicon film that releases oxygen due to heating. Next, a 100nm thick In-Ga-Zn oxide film is formed on the silicon oxynitride film that releases oxygen due to heating by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2, and the oxide film is heat-treated in a nitrogen atmosphere at 450°C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. Then, a 100nm thick silicon nitride film is formed by a plasma CVD method. Then, heat treatment is performed in a mixed gas atmosphere of nitrogen and oxygen at 350°C.

[0103] The following describes the oxide conductor film (OC_Ar dope + SiN x ). After a 400nm thick silicon oxynitride film is formed on a glass substrate by a plasma CVD method, the silicon oxynitride film is exposed to oxygen plasma, and then oxygen ions are added to the silicon oxynitride film to form an oxynitride film that releases oxygen due to heating. Next, a 100nm thick In-Ga-Zn oxide film is formed on the silicon oxynitride film that releases oxygen due to heating by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2, and the oxide film is heat-treated in a nitrogen atmosphere at 450°C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. Next, a doping device is used to add 5·10 14 ions / cm 2 Argon was added to form oxygen vacancies in the In-Ga-Zn oxide film. Then, a 100 nm thick silicon nitride film was formed by plasma CVD. Then, heat treatment was performed at 350° C. in a mixed gas atmosphere of nitrogen and oxygen.

[0104] The following describes the oxide conductor film (OC_Ar plasma + SiN x). After a 400nm thick silicon oxynitride film is formed on a glass substrate by a plasma CVD method, the silicon oxynitride film is exposed to oxygen plasma to form an oxynitride silicon film that releases oxygen due to heating. Next, a 100nm thick In-Ga-Zn oxide film is formed on the silicon oxynitride film that releases oxygen due to heating by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2, and the oxide film is heat-treated in a nitrogen atmosphere at 450°C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. Next, argon plasma is generated in a plasma processing device, and accelerated argon ions are caused to collide with the In-Ga-Zn oxide film to form oxygen vacancies. Then, a 100nm thick silicon nitride film is formed by a plasma CVD method. Then, heat treatment is performed in a mixed gas atmosphere of nitrogen and oxygen at 350°C.

[0105] Fig.39 The results of measuring the resistivity of each sample are shown. Here, the resistivity was measured using the four-terminal van der Pauw method. Fig.39 In the figure, the horizontal axis represents the measurement temperature, and the vertical axis represents the resistivity. In addition, the square represents the oxide conductor film (OC_SiN x ) measurement results, the circle shows the oxide conductor film (OC_Ar dope + SiN x ), the triangle shows the measurement results of the oxide semiconductor film (OC_Ar plasma +SiN x )’s measurement results.

[0106] Note that although not shown in the drawings, the resistivity of the oxide semiconductor film that is not in contact with the silicon nitride film is high and it is difficult to measure its resistivity. This shows that the resistivity of the oxide conductor film is lower than that of the oxide semiconductor film.

[0107] from Fig.39 It can be seen that when the oxide conductor film (OC_Ar dope + SiN x ) and oxide conductor film (OC_Arplasma+SiN x) contains oxygen vacancies and hydrogen, the change in resistivity is small. Typically, in the range of 80K or more and 290K or less, the change in resistivity is less than ±20%. Alternatively, in the range of 150K or more and 250K or less, the change in resistivity is less than ±10%. In other words, the oxide conductor is a degenerate semiconductor, and it can be inferred that its conduction band edge is consistent or roughly consistent with the Fermi level. Thus, by using the oxide conductor film as the source region and drain region of the transistor, the oxide conductor film can be in ohmic contact with the conductive film used as the source electrode and drain electrode of the transistor, thereby reducing the contact resistance between the oxide conductor film and the conductive film used as the source electrode and drain electrode of the transistor. In addition, since the resistivity of the oxide conductor is not very dependent on temperature, the change in contact resistance between the oxide conductor film and the conductive film used as the source electrode and drain electrode of the transistor is small, thereby manufacturing a transistor with high reliability.

[0108] Here, Figures 3A to 3D as well as Figure 4A and 4B FIG. 1 is an enlarged view of the vicinity of the oxide semiconductor film 110. Note that for simplicity, Figures 3A to 3D as well as Figure 4A and 4B A part of the components is omitted.

[0109] In the cross-sectional shape of the oxide semiconductor film 110 in the channel length direction, a region (hereinafter referred to as a low resistance region) is formed in which the conductivity is improved due to the increase in the carrier density of the oxide semiconductor film. Figures 3A to 3D as well as Figure 4A and 4B As shown in FIG. 1 , the low resistance region formed in the oxide semiconductor film 110 has a plurality of components. Figures 3A to 3D as well as Figure 4A and 4B In FIG, the channel length L is the length of a region sandwiched between a pair of low resistance regions.

[0110] like Figure 3A As shown, the oxide semiconductor film 110 includes: a channel region 110a formed in a region overlapping with the conductive film 114; and regions sandwiching the channel region 110a and containing impurity elements, namely, low resistance regions 110b and 110c. Figure 3AAs shown, in the cross-sectional shape in the channel length direction, the boundary between the channel region 110a and the low resistance region 110b and the boundary between the channel region 110a and the low resistance region 110c coincide with or substantially coincide with the lower end of the conductive film 114a via the insulating film 112. That is, in the top view, the boundary between the channel region 110a and the low resistance region 110b and the boundary between the channel region 110a and the low resistance region 110c coincide with or substantially coincide with the lower end of the conductive film 114a.

[0111] like Figure 3A As shown, in the cross-sectional shape in the channel length direction, the end of the conductive film 114a may be located outside the end of the conductive film 114b and the conductive film 114b may have a tapered shape. That is, the angle θ1 formed by the surface where the conductive film 114a and the conductive film 114b are in contact with each other and the side surface of the conductive film 114b may be less than 90°, 10° or more and 85° or less, 15° or more and 85° or less, 30° or more and 85° or less, 45° or more and 85° or less, or 60° or more and 85° or less. By setting the angle θ1 to be less than 90°, 10° or more and 85° or less, 15° or more and 85° or less, 30° or more and 85° or less, 45° or more and 85° or less, the coverage of the insulating film 118 on the side surface of the conductive film 114b can be improved.

[0112] like Figure 3A As shown, in the cross-sectional shape in the channel length direction, the end of the insulating film 112 may be located outside the end of the conductive film 114a and the conductive film 114b. In addition, a portion of the end of the insulating film 112 may also have an arc shape. In addition, the insulating film 112 may also have a tapered shape. That is, the angle θ2 formed by the surface where the oxide semiconductor film 110 and the insulating film 112 contact with the side of the insulating film 112 may also be less than 90°, preferably greater than 30° and less than 90°.

[0113] like Figure 3B As shown, in the cross-sectional shape in the channel length direction, the low resistance regions 110b and 110c have a region overlapping with the conductive film 114 via the insulating film 112. This region is used as the overlapping region. The length of the overlapping region in the channel length direction is represented by L ov .L ov It is less than 20%, less than 10%, less than 5% or less than 2% of the channel length L.

[0114] like Figure 3C As shown, in the cross-sectional shape in the channel length direction, the channel region 110a has a region that does not overlap with the lower end of the conductive film 114a. This region is used as a bias region. The length of the bias region in the channel length direction is represented by L offNote that in the case of multiple bias regions, the length of one bias region is referred to as L. off .L off Included in the channel length L. L off It is less than 20%, less than 10%, less than 5% or less than 2% of the channel length L.

[0115] like Figure 3D As shown, in the cross-sectional shape in the channel length direction, the oxide semiconductor film 110 has a low resistance region 110d between the channel region 110a and the low resistance region 110b, and has a low resistance region 110e between the channel region 110a and the low resistance region 110c. The impurity element concentration of the low resistance regions 110d and 110e is lower than that of the low resistance regions 110b and 110c, and the resistivity of the low resistance regions 110d and 110e is higher than that of the low resistance regions 110b and 110c. Here, although the low resistance regions 110d and 110e overlap with the insulating film 112, they may overlap with the insulating film 112 and the conductive film 114.

[0116] like Figure 4A As shown, in the cross-sectional shape in the channel length direction, the oxide semiconductor film 110 has regions 110f and 110g in the region overlapping with the conductive films 122 and 124. Impurity elements may not be added to the regions 110f and 110g. In this case, the oxide semiconductor film 110 includes regions having impurity elements between the regions 110f and 110g in contact with the conductive films 122 and 124 and the channel region 110a, i.e., low resistance regions 110b and 110c. When a voltage is applied to the conductive films 122 and 124, the regions 110f and 110g have conductivity, and thus the regions 110f and 110g are used as source regions and drain electrodes.

[0117] In addition, after the conductive films 122 and 124 are formed, an impurity element is added to the oxide semiconductor film 110 through the insulating film 120 and the insulating film 118 using the conductive films 114, 122, and 124 as masks to form an insulating film 114. Figure 4A The structure shown.

[0118] like Figure 4B As shown, in the cross-sectional shape in the channel length direction, low resistance regions 110b, 110c, 110d, 110e, 110h and 110i may be provided sandwiching the channel region 110a.

[0119] Specifically, Figure 4BThe oxide semiconductor film 110 shown includes: a channel region 110a; low resistance regions 110h and 110i sandwiching the channel region 110a; low resistance regions 110d and 110e sandwiching the low resistance regions 110h and 110i; and low resistance regions 110b and 110c sandwiching the low resistance regions 110d and 110e. The low resistance regions 110h and 110i are formed by adding impurity elements through the conductive film 114a and the insulating film 112 in the region not overlapping with the conductive film 114b. The low resistance regions 110d and 110e are formed by adding impurity elements through the insulating film 112 in the region not overlapping with the conductive film 114a and the conductive film 114b. The low resistance regions 110d and 110e are formed by directly adding impurity elements. Thus, the impurity element concentration of the low resistance regions 110h and 110i is lower than that of the low resistance regions 110d and 110e and the low resistance regions 110b and 110c, and the resistivity of the low resistance regions 110h and 110i is higher than that of the low resistance regions 110d and 110e and the low resistance regions 110b and 110c. In addition, the impurity element concentration of the low resistance regions 110d and 110e is lower than that of the low resistance regions 110b and 110c, and the resistivity of the low resistance regions 110d and 110e is higher than that of the low resistance regions 110b and 110c.

[0120] exist Figure 4B , the channel region 110a overlaps with the conductive film 114b. The low resistance regions 110h and 110i overlap with the conductive film 114a protruding outward from the conductive film 114b. The low resistance regions 110d and 110e overlap with the insulating film 112 protruding outward from the conductive film 114a. The low resistance regions 110b and 110c protrude outward from the insulating film 112 and overlap with the insulating film 118.

[0121] like Figure 3D and Figure 4B As shown, the oxide semiconductor film 110 includes low resistance regions 110d, 110e, 110h, and 110i having a lower impurity element concentration than the low resistance regions 110b and 110c and a higher resistivity than the low resistance regions 110b and 110c, so that the electric field in the drain region can be relaxed. Thus, the change in the threshold voltage caused by the electric field in the drain region can be reduced in the transistor.

[0122] Figures 3A to 3D as well as Figure 4A and 4B The oxide semiconductor film 110 shown includes a region where the film thickness of the region not overlapping with the insulating film 112 and the conductive film 114 is thinner than that of the region overlapping with the insulating film 112 and the conductive film 114. The film thickness of the thin region is thinner than that of the oxide semiconductor film in the region overlapping with the insulating film 112 and the conductive film 114, and the thickness of the thin region is greater than or equal to 0.1 nm and less than or equal to 5 nm.

[0123] The low-resistance regions 110b and 110c in the oxide semiconductor film 110 are used as a source region and a drain region. In addition, the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i contain an impurity element.

[0124] When the impurity element is a rare gas element and the oxide semiconductor film 110 is formed by sputtering, the channel region 110a and the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i all contain the rare gas element. In addition, the rare gas element concentration of the low resistance regions 110b and 110c is higher than that of the channel region 110a. The rare gas element concentration of the low resistance regions 110b and 110c is higher than that of the low resistance regions 110d and 110e. The rare gas element concentration of the low resistance regions 110d and 110e is higher than that of the low resistance regions 110h and 110i.

[0125] This is because of the following two reasons: when the oxide semiconductor film 110 is formed by sputtering, a rare gas is used as a sputtering gas, thereby containing a rare gas in the oxide semiconductor film 110; and, a rare gas is intentionally added to the low resistance regions 110b and 110c to form oxygen vacancies in the oxide semiconductor film 110. In the low resistance regions 110d, 110e, 110h, and 110i, the concentration of the rare gas added to form oxygen vacancies is different in the above-mentioned low resistance regions according to the film structure and film thickness formed on the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i. In addition, a rare gas element different from that of the channel region 110a may be added to the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i.

[0126] When the impurity element is boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, or chlorine, the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i contain the impurity element. Thus, the impurity element concentration of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i is higher than that of the channel region 110a. In addition, the impurity element concentration of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i obtained by secondary ion mass spectrometry (SIMS) can be 5×10 18 atoms / cm 3 Above and 1×10 22 atoms / cm 3 Below, 1×10 19 atoms / cm3 Above and 1×10 21 atoms / cm 3 Below, or 5×10 19 atoms / cm 3 Above and 5×10 20 atoms / cm 3 the following.

[0127] When the impurity element is hydrogen, the hydrogen concentration of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i is higher than that of the channel region 110a. In addition, the hydrogen concentration of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i obtained by secondary ion mass spectrometry can be 8×10 19 atoms / cm 3 Above, 1×10 20 atoms / cm 3 Above, or 5×10 20 atoms / cm 3 above.

[0128] Since the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i contain the impurity element, oxygen vacancies increase and carrier density increases, thereby improving the conductivity of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i.

[0129] The impurity element may be a combination of one or more of hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, and chlorine with a rare gas. In this case, in the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i, oxygen vacancies formed by the rare gas and one or more of the added hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, and chlorine interact with each other, so that the conductivity of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i may be higher.

[0130] When hydrogen is added to an oxide semiconductor with oxygen vacancies formed by adding impurity elements, hydrogen enters the oxygen vacancies and forms a donor level near the conduction band. As a result, an oxide conductor can be formed. Therefore, the oxide conductor has light transparency. Note that the oxide semiconductor that will become a conductor is referred to as an oxide conductor here.

[0131] Oxide conductors are degenerate semiconductors, and it can be inferred that their conduction band edges coincide with or approximately coincide with the Fermi level. As a result, the oxide conductor film is in ohmic contact with the conductive film used as the source electrode and drain electrode of the transistor, thereby reducing the contact resistance between the oxide conductor film and the conductive film used as the source electrode and drain electrode of the transistor.

[0132] The transistor 100 shown in this embodiment has a structure in which the channel region 110a is sandwiched between the low resistance region 110b and the low resistance region 110c used as the source region and the drain region. Therefore, the on-state current of the transistor 100 is large and its electric field effect mobility is high. In addition, in the transistor 100, the impurity element is added to the oxide semiconductor film 110 using the conductive film 114 as a mask. That is, the low resistance region can be formed in a self-aligned manner.

[0133] The transistor 100 has a structure in which a conductive film 114 that does not function as a gate electrode overlaps with conductive films 122 and 124 that function as a source electrode and a drain electrode. Thus, parasitic capacitance between the conductive film 114 and the conductive films 122 and 124 can be reduced. As a result, when a large-area substrate is used as the substrate 102, signal delay between the conductive film 114 and the conductive films 122 and 124 can be reduced.

[0134] Next, we will explain in detail Figures 1A to 1D Other structures of the semiconductor device shown.

[0135] As the substrate 102, various substrates can be used without being limited to a specific substrate. Examples of the substrate include semiconductor substrates (e.g., single crystal substrates or silicon substrates), SOI (Silicon on Insulator) substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates, substrates containing stainless steel foils, tungsten substrates, substrates containing tungsten foils, flexible substrates, laminated films, paper containing fibrous materials, or substrate films. As an example of a glass substrate, barium borosilicate glass, aluminum borosilicate glass, or soda-lime glass can be cited. Examples of flexible substrates, laminated films, and substrate films can include: plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyether sulfone (PES); synthetic resins such as acrylic resins; polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride; polyamide, polyimide, aramid, epoxy, inorganic vapor-deposited films or paper, etc. In particular, by using semiconductor substrates, single crystal substrates or SOI substrates to manufacture transistors and capacitors, transistors and capacitors with small deviations in characteristics, size or shape, high current capacity and small size can be manufactured. When circuits are constructed using the above transistors and capacitors, low power consumption or high integration of circuits can be achieved.

[0136] In addition, as the substrate 102, a flexible substrate may be used, and transistors and capacitors may be directly formed on the flexible substrate. Alternatively, a stripping layer may be provided between the substrate 102 and the transistors and capacitors. The stripping layer may be used in the following situations, i.e., a part or all of a semiconductor element is manufactured thereon, and then a part or all of the semiconductor device is separated from the substrate 102 and transferred to another substrate. In this case, the transistors and capacitors may also be transferred to a substrate with low heat resistance or a flexible substrate. In addition, as the above-mentioned stripping layer, for example, a laminated structure of an inorganic film of a tungsten film and a silicon oxide film or a structure having an organic resin film such as polyimide formed on a substrate may be used.

[0137] As examples of substrates for transposed transistors and capacitors, in addition to the above-mentioned substrates on which transistors and capacitors can be provided, there can also be paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or regenerated fibers (acetate, cuprammonium, rayon, regenerated polyester), etc.), leather substrates, rubber substrates, etc. By using the above-mentioned substrates, transistors with good characteristics or transistors with low power consumption can be formed, devices that are not prone to failure and have heat resistance can be manufactured, or lightweight or thinning can be achieved.

[0138] The insulating film 108 can be formed by appropriately using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like. In addition, the insulating film 108 can be formed using, for example, an oxide insulating film or a nitride insulating film in a single layer or a stacked layer. In addition, in order to improve the interface characteristics between the insulating film 108 and the oxide semiconductor film 110, it is preferable to form at least a region of the insulating film 108 in contact with the oxide semiconductor film 110 using an oxide insulating film. In addition, by using an oxide insulating film that releases oxygen by heating as the insulating film 108, oxygen contained in the insulating film 108 can be moved to the oxide semiconductor film 110 by heat treatment.

[0139] The thickness of the insulating film 108 may be greater than 50 nm, greater than 100 nm and less than 3000 nm, or greater than 200 nm and less than 1000 nm. By increasing the thickness of the insulating film 108, the amount of oxygen released from the insulating film 108 may be increased, and the interface energy level density at the interface between the insulating film 108 and the oxide semiconductor film 110 and the oxygen vacancies contained in the channel region 110a of the oxide semiconductor film 110 may be reduced.

[0140] The insulating film 108 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and can be provided in a stacked layer or a single layer. In this embodiment, a silicon nitride film is used as the insulating film 108 a , and a silicon oxynitride film is used as the insulating film 108 b .

[0141] The oxide semiconductor film 110 is typically formed using a metal oxide such as In-Ga oxide, In-Zn oxide, In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). The oxide semiconductor film 110 has light-transmitting properties.

[0142] In addition, when the oxide semiconductor film 110 is In-M-Zn oxide, when the sum of In and M is 100 atomic%, the atomic percentages of In and M are as follows: In is greater than 25 atomic% and M is less than 75 atomic% or In is greater than 34 atomic% and M is less than 66 atomic%.

[0143] The energy gap of the oxide semiconductor film 110 is greater than or equal to 2 eV, greater than or equal to 2.5 eV, or greater than or equal to 3 eV.

[0144] The thickness of the oxide semiconductor film 110 is greater than or equal to 3 nm and less than or equal to 200 nm, greater than or equal to 3 nm and less than or equal to 100 nm, or greater than or equal to 3 nm and less than or equal to 60 nm.

[0145] When the oxide semiconductor film 110 is an In-M-Zn oxide, the atomic number ratio of the metal element of the sputtering target used to form the In-M-Zn oxide film preferably satisfies In≥M and Zn≥M. The atomic number ratio of the metal element of such a sputtering target is preferably In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:1.5, In:M:Zn=2:1:2.3, In:M:Zn=2:1:3, In:M:Zn=3:1:2, etc. In addition, the atomic number ratio of the formed oxide semiconductor film 110 includes a variation of ±40% of the atomic number ratio of the metal element of the above-mentioned sputtering target as an error.

[0146] When the oxide semiconductor film 110 contains silicon or carbon, which is one of the Group 14 elements, oxygen vacancies in the oxide semiconductor film 110 increase, so that the oxide semiconductor film 110 is converted into an n-type. Therefore, in the oxide semiconductor film 110, especially in the channel region 110a, the concentration of silicon or carbon (concentration measured by secondary ion mass spectrometry) can be set to 2×10 18 atoms / cm 3 Below, or 2×10 17 atoms / cm 3As a result, the transistor has an electrical characteristic in which the threshold voltage becomes positive (also called a normally-off characteristic).

[0147] In addition, in the oxide semiconductor film 110, especially in the channel region 110a, the concentration of the alkali metal or alkaline earth metal measured by secondary ion mass spectrometry can be set to 1×10 18 atoms / cm 3 Below, or 2×10 16 atoms / cm 3 Below. Sometimes, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, carriers are generated and the off-state current of the transistor increases. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the channel region 110a. As a result, the transistor has an electrical characteristic in which the threshold voltage becomes positive (also called a normally-off characteristic).

[0148] When nitrogen is contained in the oxide semiconductor film 110, especially in the channel region 110a, electrons as carriers are sometimes generated, and the carrier density increases, so that the channel region 110a is converted to n-type. As a result, a transistor using an oxide semiconductor film containing nitrogen tends to have a normally-on characteristic. Therefore, in the oxide semiconductor film, especially in the channel region 110a, it is preferable to reduce nitrogen as much as possible. For example, the nitrogen concentration measured by secondary ion mass spectrometry can be set to 5×10 18 atoms / cm 3 the following.

[0149] By reducing the amount of impurity elements in the oxide semiconductor film 110, especially in the channel region 110a, the carrier density of the oxide semiconductor film can be reduced. In the oxide semiconductor film 110, especially in the channel region 110a, the carrier density can be set to 1×10 17 Pieces / cm 3 Below, 1×10 15 Pieces / cm 3 Below, 1×10 13 Pieces / cm 3 Below, 1×10 11 Pieces / cm 3 Below, or 1×10 -9 Pieces / cm 3 Above and 1×10 10 Pieces / cm 3 the following.

[0150] By using an oxide semiconductor film with a low impurity concentration and a low defect state density as the oxide semiconductor film 110, a transistor with better electrical characteristics can be manufactured. Here, the state of low impurity concentration and low defect state density (few oxygen vacancies) is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Because the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has fewer carrier generation sources, it is possible to reduce the carrier density. Therefore, a transistor having a channel region formed in the oxide semiconductor film can easily achieve an electrical characteristic of a positive threshold voltage (also called a normally-off characteristic). Because the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it is possible to have a lower trap state density. The off-state current of the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is significantly low. When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, the off-state current can also be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 -13 A or less. Therefore, a transistor having a channel region formed in the oxide semiconductor film has less variation in electrical characteristics, and the transistor may become a highly reliable transistor.

[0151] The oxide semiconductor film 110 may be, for example, a non-single-crystal structure. The non-single-crystal structure may include, for example, the following CAAC-OS (CAxis Aligned Crystalline Oxide Semiconductor: c-axis oriented crystalline oxide semiconductor), a polycrystalline structure, the following microcrystalline structure, or an amorphous structure. Among the non-single-crystal structures, the amorphous structure has the highest defect state density, while the CAAC-OS has the lowest defect state density.

[0152] In addition, the oxide semiconductor film 110 may be a mixed film having two or more regions among an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. A mixed film sometimes has a single-layer structure having two or more regions among an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. In addition, a mixed film sometimes has a stacked structure having two or more regions among an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region.

[0153] In the oxide semiconductor film 110, the crystallinity of the channel region 110a is sometimes different from that of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i. Specifically, in the oxide semiconductor film 110, the crystallinity of the channel region 110a is higher than that of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i. This is because when an impurity element is added to the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i, the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i are damaged, thereby reducing the crystallinity.

[0154] The insulating film 112 may be formed using an oxide insulating film or a nitride insulating film in a single layer or in a stacked layer. In order to improve the interface characteristics between the insulating film 112 and the oxide semiconductor film 110, it is preferable to form at least a region of the insulating film 112 in contact with the oxide semiconductor film 110 using an oxide insulating film. The insulating film 112 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and may be provided in a stacked layer or in a single layer.

[0155] Furthermore, by providing an insulating film having an effect of blocking oxygen, hydrogen, water, and the like as the insulating film 112, oxygen can be prevented from diffusing from the oxide semiconductor film 110 to the outside, and hydrogen, water, and the like can be prevented from intruding from the outside into the oxide semiconductor film 110. Examples of the insulating film having an effect of blocking oxygen, hydrogen, water, and the like include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film.

[0156] In addition, by using hafnium silicate (HfSiO x ), nitrogen-doped hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), hafnium oxide, yttrium oxide and other high-k materials can reduce the gate leakage current of transistors.

[0157] In addition, by using an oxide insulating film that releases oxygen by heating as the insulating film 112 , oxygen included in the insulating film 112 can be moved to the oxide semiconductor film 110 by heat treatment.

[0158] The thickness of the insulating film 112 can be, for example, greater than or equal to 5 nm and less than or equal to 400 nm, greater than or equal to 5 nm and less than or equal to 300 nm, or greater than or equal to 10 nm and less than or equal to 250 nm.

[0159] The conductive film 114, the conductive film 116, the conductive film 122, the conductive film 124, and the conductive film 126 can be formed by using a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. The conductive film 114, the conductive film 116, the conductive film 122, the conductive film 124, and the conductive film 126 can be formed using, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. In addition, one or more metal elements selected from manganese and zirconium can also be used. The conductive film 114, the conductive film 116, the conductive film 122, the conductive film 124, and the conductive film 126 can have a single-layer structure or a stacked-layer structure of two or more layers. For example, there can be mentioned a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure of a titanium film stacked on an aluminum film, a two-layer structure of a titanium film stacked on a titanium nitride film, a two-layer structure of a tungsten film stacked on a titanium nitride film, a two-layer structure of a tungsten film stacked on a tantalum nitride film or a tungsten nitride film, a two-layer structure of a copper film stacked on a copper film containing manganese, a three-layer structure of a titanium film, an aluminum film, and a titanium film stacked in sequence, and a three-layer structure of a copper film containing manganese, a copper film, and a copper film containing manganese stacked in sequence, etc. In addition, an alloy film or a nitride film formed by combining aluminum with one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can also be used.

[0160] The conductive films 114 and 116 are formed at the same time and thus have the same material and the same stacked structure. The conductive films 122, 124, and 126 are formed at the same time and thus have the same material and the same stacked structure.

[0161] The conductive films 114, 116, 122, 124, and 126 may also be made of a light-transmitting conductive material such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide containing silicon oxide. In addition, a stacked structure of the above-mentioned light-transmitting conductive materials and the above-mentioned metal elements may be used.

[0162] The thickness of the conductive films 114 , 116 , 122 , 124 , and 126 can be, for example, greater than or equal to 30 nm and less than or equal to 500 nm or greater than or equal to 100 nm and less than or equal to 400 nm.

[0163] A nitride insulating film is used as the insulating film 118. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. The hydrogen concentration of the insulating film 118 is preferably 1×10 22 atoms / cm 3The insulating film 118 is in contact with the low resistance region of the oxide semiconductor film 110 . Thus, hydrogen contained in the insulating film 118 diffuses into the low resistance region of the oxide semiconductor film 110 , so that the hydrogen concentration in the low resistance region is higher than that in the channel region of the oxide semiconductor film 110 .

[0164] The insulating film 120 can be formed using an oxide insulating film or a nitride insulating film in a single layer or a stacked layer. For example, the insulating film 120 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and can be provided in a single layer or a stacked layer.

[0165] The insulating film 128 preferably has a function of blocking hydrogen, water, etc. from the outside. The insulating film 128 can be made of, for example, silicon nitride, silicon nitride oxide, aluminum oxide, or the like, and can be provided in a single layer or in a stacked layer.

[0166] The thickness of the insulating film 118 , the insulating film 120 , and the insulating film 128 can each be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

[0167] <Structure of semiconductor device 2>

[0168] Next, refer to Figures 5A to 5D and Figure 6 Explain in detail Figures 1A to 1D Other structures of the semiconductor device shown.

[0169] Figure 5A is a top view of a transistor 100A included in a semiconductor device. Figure 5B is a top view of a capacitor element 150A included in the semiconductor device. Figure 5C It is along Figure 5A The cross-sectional view along the dot-dash line X1-X2, Figure 5D It is along Figure 5B A cross-sectional view along the dotted line X3-X4.

[0170] Figure 5A and 5CThe transistor 100A shown includes: an insulating film 104 formed on a substrate 102: a conductive film 106 on the insulating film 104; an insulating film 108 on the insulating film 104 and the conductive film 106; an oxide semiconductor film 110 overlapping the conductive film 106 via the insulating film 108; an insulating film 112 on the oxide semiconductor film 110; a conductive film 114 overlapping the oxide semiconductor film 110 via the insulating film 112; an insulating film 118 covering the oxide semiconductor film 110, the insulating film 112, and the conductive film 114; an insulating film 120 on the insulating film 118; a conductive film 122 connected to the oxide semiconductor film 110 via an opening 140a provided in the insulating film 118 and the insulating film 120; and a conductive film 124 connected to the oxide semiconductor film 110 via an opening 140b provided in the insulating film 118 and the insulating film 120. Furthermore, an insulating film 128 that covers the insulating film 120 , the conductive film 122 , and the conductive film 124 may be provided over the transistor 100A.

[0171] exist Figure 5C , the conductive film 106 has a stacked structure of a conductive film 106a and a conductive film 106b on the conductive film 106a. The insulating film 108 has a stacked structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. The conductive film 114 has a stacked structure of a conductive film 114a and a conductive film 114b on the conductive film 114a. The conductive film 122 has a stacked structure of a conductive film 122a and a conductive film 122b on the conductive film 122a. The conductive film 124 has a stacked structure of a conductive film 124a and a conductive film 124b on the conductive film 124a.

[0172] In the transistor 100A, the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), the conductive film 114 functions as a second gate electrode (also referred to as a top gate electrode), the conductive film 122 functions as one of a source electrode and a drain electrode, and the conductive film 124 functions as the other of the source electrode and the drain electrode. In addition, in the transistor 100A, the insulating film 108 functions as a first gate insulating film, and the insulating film 112 functions as a second gate insulating film.

[0173] exist Figure 5A and 5C The transistor 100A shown has a structure having conductive films serving as gate electrodes above and below the oxide semiconductor film 110, which is different from the transistor 100 described above. As shown in the transistor 100A, the semiconductor device of one embodiment of the present invention may have two or more gate electrodes.

[0174] also, Figure 5B and 5DThe capacitor element 150A shown includes: an insulating film 104 formed on a substrate 102; an insulating film 108 on the insulating film 104; an insulating film 112 on the insulating film 108; a conductive film 116 on the insulating film 112; an insulating film 118 covering the insulating film 108, the insulating film 112, and the conductive film 116; an insulating film 120 on the insulating film 118; and a conductive film 126 overlapping the conductive film 116 via the insulating film 118 in an opening 140c provided in the insulating film 120. In addition, an insulating film 128 covering the insulating film 120 and the conductive film 126 may be provided on the capacitor element 150A.

[0175] exist Figure 5D In the embodiment, the insulating film 108 has a stacked structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. The conductive film 116 has a stacked structure of a conductive film 116a and a conductive film 116b on the conductive film 116a. The conductive film 126 has a stacked structure of a conductive film 126a and a conductive film 126b on the conductive film 126a.

[0176] The capacitor 150A has a structure in which a dielectric is sandwiched between a pair of electrodes. More specifically, one of the pair of electrodes is a conductive film 116, the other of the pair of electrodes is a conductive film 126, and an insulating film 118 between the conductive films 116 and 126 serves as a dielectric.

[0177] The conductive film 114 used as the second gate electrode of the transistor 100A and the conductive film 116 used as one of the pair of electrodes of the capacitor 150A are formed by the same process, and at least a portion of them are formed on the same surface. The conductive film 122 and the conductive film 124 used as the source electrode and the drain electrode of the transistor 100A and the conductive film 126 used as the other of the pair of electrodes of the capacitor 150A are formed by the same process, and at least a portion of them are formed on the same surface.

[0178] In this way, by forming the conductive films serving as the electrodes of the transistor 100A and the capacitor 150A in the same process, the manufacturing cost can be reduced.

[0179] In addition, in the capacitor element 150A, the insulating film 120 has the opening 140c. Thus, only the insulating film 118 can be used as a dielectric in the insulating film stacked with the insulating film 118 and the insulating film 120. By adopting the above structure, the capacitance value of the capacitor element 150A can be increased. Thus, the capacitance value of the display device can be increased.

[0180] then, Figure 6 Shown along Figure 5A A cross-sectional view of the transistor 100A taken along the dashed line Y3 - Y4 (in the channel width direction) is shown.

[0181] like Figure 6 As shown in FIG. 1 , the conductive film 114 serving as the second gate electrode is connected to the conductive film 106 serving as the first gate electrode in the opening 139 provided in the insulating film 108 and the insulating film 112. Thus, the conductive film 114 and the conductive film 106 are supplied with the same potential. Alternatively, a structure may be employed in which the conductive film 114 and the conductive film 106 are not connected without providing the opening 139. When the conductive film 114 and the conductive film 106 are not connected, different potentials may be supplied to the conductive film 114 and the conductive film 106.

[0182] like Figure 6 As shown, the oxide semiconductor film 110 is disposed opposite to the conductive film 106 used as the first gate electrode and the conductive film 114 used as the second gate electrode, and is sandwiched between the two conductive films used as gate electrodes. The length of the conductive film 114 used as the second gate electrode in the channel width direction is longer than that of the oxide semiconductor film 110 in the channel width direction, and the entire oxide semiconductor film 110 in the channel width direction is covered by the conductive film 114 via the insulating film 112. The conductive film 114 used as the second gate electrode and the conductive film 106 used as the first gate electrode are connected to each other in the openings 139 in the insulating film 108 and the insulating film 112, so that one of the side surfaces of the oxide semiconductor film 110 in the channel width direction is opposite to the conductive film 114 used as the second gate electrode via the insulating film 112.

[0183] In other words, in the channel width direction of the transistor 100A, while the conductive film 106 used as the first gate electrode and the conductive film 114 used as the second gate electrode are connected to each other in the opening portions in the insulating film 108 used as the first gate insulating film and the insulating film 112 used as the second gate insulating film, the oxide semiconductor film 110 is surrounded by the insulating film 108 used as the first gate insulating film and the insulating film 112 used as the second gate insulating film.

[0184] By adopting the above structure, the oxide semiconductor film 110 included in the transistor 100A can be electrically surrounded by the electric field of the conductive film 106 used as the first gate electrode and the conductive film 114 used as the second gate electrode. As shown in the transistor 100A, the device structure of the above transistor can be called a surrounded channel structure (s-channel structure), and the s-channel structure is as follows: the oxide semiconductor film having a channel region is electrically surrounded by the electric field of the first gate electrode and the second gate electrode.

[0185] The transistor 100A has an s-channel structure. Therefore, the conductive film 106 used as the first gate electrode or the conductive film 114 used as the second gate electrode can efficiently apply an electric field for moving electrons to the oxide semiconductor film 110, thereby improving the current driving capability of the transistor 100A, thereby obtaining a high on-state current characteristic. In addition, since the on-state current can be increased, the transistor 100A can be miniaturized. In addition, the transistor 100A adopts a structure in which the oxide semiconductor film 110 is surrounded by the conductive film 106 used as the first gate electrode and the conductive film 114 used as the second gate electrode, thereby improving the mechanical strength of the transistor 100A.

[0186] In the channel width direction of the transistor 100A, an opening different from the opening 139 may be formed in the side surface of the oxide semiconductor film 110 where the opening 139 is not formed.

[0187] As the insulating film 104 included in the transistor 100A and the capacitor 150A, the same material as that of the insulating film 108 can be used. Here, as the insulating film 104, a silicon nitride film is formed to a thickness of 100 nm using a PECVD apparatus.

[0188] The conductive film 106 included in the transistor 100A can use the same material as that of the conductive films 114, 122, and 124. Here, a 10-nm-thick tantalum nitride film is formed as the conductive film 106a by a sputtering device, and a 300-nm-thick copper film is formed as the conductive film 106b by a sputtering device.

[0189] Next, refer to 7A to 11A Explain in detail Figures 1A to 1D as well as Figures 5A to 5D Other structures of the semiconductor device shown. Note that 7A to 11A The semiconductor device shown is Figures 5A to 5D A modified example of the semiconductor device shown.

[0190] Fig. 7A 1 is a cross-sectional view showing a transistor 100B included in the semiconductor device. Figure 7B FIG. 1 is a cross-sectional view of a capacitor 150B included in a semiconductor device. Note that the top view of the transistor 100B and the capacitor 150B are respectively Figure 5A and 5B The top view shown is the same and is omitted here. Figure 7C The transistor 100C shown, Fig.7D The capacitor element 150C shown, Fig. 8A The transistor 100D shown, Figure 8B The capacitor element 150D shown, Figure 8C The transistor 100E shown, Fig.8D The capacitive element 150E shown, Fig.9A The transistor 100F shown, Fig. 9B The capacitor element 150F shown, Fig. 9C The transistor 100G shown, Fig.9D The top view of the capacitor element 150G shown is also respectively Figure 5A and 5B The top views shown are the same and are omitted here.

[0191] In addition, 7A to 11A In the illustrated structures, when having the same functions as those described above, the same hatching is sometimes used without particularly adding a reference numeral.

[0192] <Structure of semiconductor device 3>

[0193] Fig. 7A The transistor 100B shown is Figure 5C The transistor 100A shown is different in the shape of the conductive film 114. Specifically, the conductive film 114 of the transistor 100B is a stacked structure of a conductive film 114a and a conductive film 114b on the conductive film 114a, wherein the lower end of the conductive film 114a is consistent with or substantially consistent with the upper end of the insulating film 112, and the lower end of the conductive film 114b is located inside the upper end of the conductive film 114a. A portion of the end of the conductive film 114b has an arc shape.

[0194] Figure 7B The capacitor element 150B is shown with Figure 5D The difference of the capacitor element 150A shown is the shape of the conductive film 116. Specifically, the conductive film 116 of the capacitor element 150B is a stacked structure of a conductive film 116a and a conductive film 116b on the conductive film 116a, wherein the lower end of the conductive film 116a is consistent or approximately consistent with the upper end of the insulating film 112, and the lower end of the conductive film 116b is located inside the upper end of the conductive film 116a.

[0195] By adopting Fig. 7A , 7B The shapes of the insulating film 112 and / or the conductive films 114 and 116 shown can improve the coverage of the insulating film 118 .

[0196] <Structure of semiconductor device 4>

[0197] Figure 7C The transistor 100C shown is Figure 5CThe difference between the transistor 100A shown in the figure lies in the shape of the insulating film 112. Specifically, in the insulating film 112 included in the transistor 100C, the lower end and the upper end of the insulating film 112 are located outside the lower end of the conductive film 114. That is, the transistor 100C has the insulating film 112 extending outside the conductive film 114. By adopting Figure 7C The shape of the insulating film 112 shown can separate the channel region of the oxide semiconductor film 110 from the insulating film 118 , thereby preventing nitrogen, hydrogen, and the like contained in the insulating film 118 from entering the channel region of the oxide semiconductor film 110 .

[0198] Fig.7D The capacitor element 150C is shown with Figure 5D The capacitor 150A shown is different in the shape of the insulating film 112. Specifically, in the insulating film 112 included in the capacitor 150C, the lower end and the upper end of the insulating film 112 are located outside the lower end of the conductive film 116.

[0199] By adopting Figure 7C , 7D The shape of the insulating film 112 shown can improve the coverage of the insulating film 118.

[0200] <Structure of semiconductor device 5>

[0201] Fig. 8A The transistor 100D shown is Figure 5C The difference of the transistor 100A shown is the structure of the insulating film 108 and the insulating film 112. Specifically, Fig. 8A The insulating film 108 of the transistor 100D shown in the figure has a stacked structure of insulating films 108a, 108b, and 108c. Fig. 8A The insulating film 112 included in the transistor 100D shown has a stacked-layer structure of an insulating film 112 a and an insulating film 112 b .

[0202] Figure 8B The capacitor element 150D is shown with Figure 5D The difference between the capacitor element 150A shown is the structure of the insulating film 108 and the insulating film 112. Specifically, Figure 8B The insulating film 108 of the capacitor 150D shown in the figure has a stacked structure of insulating films 108a, 108b, and 108c. Figure 8B The insulating film 112 included in the capacitor 150D shown has a stacked-layer structure of an insulating film 112 a and an insulating film 112 b .

[0203] Fig. 8A and 8BThe insulating film 108c and the insulating film 112a shown in the figure can be formed using an oxide insulating film having a low energy level density of nitride oxide. Note that the energy level density of the nitride oxide may sometimes be formed at the energy level at the top of the valence band (E v _ os ) and the energy of the conduction band bottom (E c _ os ). As the energy at the top of the valence band (E v _ os ) and the energy of the conduction band bottom (E c _ os ) can be used as an oxide insulating film with a low energy level density of nitride oxide between the insulating films 108c and 112a, and a silicon oxynitride film with a small amount of nitride oxide released or an aluminum oxynitride film with a small amount of nitride oxide released can be used. In addition, the average film thickness of the insulating film 108c and the insulating film 112a is greater than 0.1nm and less than 50nm or greater than 0.5nm and less than 10nm.

[0204] In addition, in thermal desorption spectroscopy (TDS), the silicon oxynitride film with a small amount of nitrogen oxide release is a film that releases more ammonia than nitrogen oxide. Typically, the amount of ammonia released is 1×10 18 Pieces / cm 3 Above and 5×10 19 Pieces / cm 3 Note that the amount of ammonia released is the amount released when the film surface temperature is heated to a temperature of 50° C. to 650° C., preferably 50° C. to 550° C.

[0205] The insulating film 108b and the insulating film 112b can be formed using an oxide insulating film that releases oxygen by heating. The insulating film 108b and the insulating film 112b have an average film thickness of 5 nm to 1000 nm or 10 nm to 500 nm.

[0206] Typical examples of the oxide insulating film that releases oxygen by heating include a silicon oxynitride film, an aluminum oxynitride film, and the like.

[0207] Nitrogen oxides (NO x , x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO 2or NO, forming an energy level in the insulating film 108 and the insulating film 112. This energy level is located in the energy gap of the oxide semiconductor film 110. Therefore, when the nitrogen oxide diffuses in the interface between the insulating film 108 and the oxide semiconductor film 110, the interface between the insulating film 112 and the oxide semiconductor film 110, and the interface between the insulating film 108 and the insulating film 112, sometimes this energy level captures electrons on one side of the insulating films 108 and 112. As a result, the captured electrons remain near the interface of the insulating film 108, the insulating film 112, and the oxide semiconductor film 110, thereby causing the threshold voltage of the transistor to drift in the positive direction.

[0208] In addition, when heat treatment is performed, nitrogen oxide reacts with ammonia and oxygen. When heat treatment is performed, nitrogen oxide contained in the insulating films 108b and 112b reacts with ammonia contained in the insulating films 108c and 112a, thereby reducing nitrogen oxide contained in the insulating films 108b and 112b. Therefore, electrons are not easily captured at the interface between the insulating film 108 and the oxide semiconductor film 110, the interface between the insulating film 112 and the oxide semiconductor film 110, and the interface between the insulating film 108 and the insulating film 112.

[0209] By using the energy at the top of the valence band (E v _ os ) and the energy of the conduction band bottom (E c _ os ) using an oxide insulating film with low energy level density of the nitride oxide between as the insulating films 108c and 112a can reduce the drift of the threshold voltage of the transistor, thereby reducing the variation of the electrical characteristics of the transistor.

[0210] By performing a heat treatment in the manufacturing process of the transistor, typically a heat treatment at a temperature of 300°C or higher and below the substrate strain point, the insulating films 108 and 112 are observed in the ESR spectrum measured at an ESR of 100K or lower: a first signal having a g value of 2.037 or higher and 2.039 or lower; a second signal having a g value of 2.001 or higher and 2.003 or lower; and a third signal having a g value of 1.964 or higher and 1.966 or lower. In the ESR measurement of the X-band, the split width between the first signal and the second signal and the split width between the second signal and the third signal are approximately 5 mT. In addition, the sum of the spin densities of the first signal having a g value of 2.037 or higher and 2.039 or lower, the second signal having a g value of 2.001 or higher and 2.003 or lower, and the third signal having a g value of 1.964 or higher and 1.966 or lower is less than 1×10 18 spins / cm 3 , typically 1×10 17 spins / cm 3 Above and below 1×10 18 spins / cm3 .

[0211] In the ESR spectrum below 100K, the first signal with a g value of 2.037 to 2.039, the second signal with a g value of 2.001 to 2.003, and the third signal with a g value of 1.964 to 1.966 correspond to signals caused by nitrogen oxides (NOx, x is 0 to 2, preferably 1 to 2). Typical examples of nitrogen oxides include nitrogen monoxide and nitrogen dioxide. That is, the smaller the total number of spin densities of the first signal with a g value of 2.037 to 2.039, the second signal with a g value of 2.001 to 2.003, and the third signal with a g value of 1.964 to 1.966, the less the nitrogen oxide content in the oxide insulating film.

[0212] In addition, the oxide insulating film containing nitrogen and having a small amount of defects has a nitrogen concentration of 6×10 20 atoms / cm 3 The following membrane.

[0213] By forming an oxide insulating film containing nitrogen and having a small amount of defects by a PECVD method using silane and nitrous oxide at a substrate temperature of 220° C. or higher, 280° C. or higher, or 350° C. or higher, a dense film with high hardness can be formed.

[0214] <Structure of semiconductor device 6>

[0215] Figure 8C The transistor 100E shown is Figure 5C The transistor 100A shown is different in the shapes of the insulating film 112 and the conductive film 114. Specifically, the insulating film 112 of the transistor 100E has a portion of an arc-shaped end. In addition, the lower end and the upper end of the conductive film 114a are located inside the upper end of the insulating film 112. The lower end of the conductive film 114b is located inside the upper end of the conductive film 114a. The ends of the conductive films 114a and 114b have a portion of an arc-shaped end.

[0216] Fig.8D The capacitor element 150E is shown with Figure 5D The difference of the capacitor element 150A shown is the shape of the insulating film 112 and the conductive film 116. Specifically, a portion of the end of the insulating film 112 of the capacitor element 150E has an arc shape. In addition, the lower end and the upper end of the conductive film 116a are located inside the upper end of the insulating film 112. The lower end of the conductive film 116b is located inside the upper end of the conductive film 116a. Parts of the ends of the conductive films 116a and 116b have an arc shape.

[0217] <Structure of semiconductor device 7>

[0218] Fig.9A The transistor 100F shown with Figure 5C The transistor 100A shown is different in the shapes of the insulating film 112 and the conductive film 114 . Specifically, the insulating film 112 and the conductive film 114 included in the transistor 100F have a rectangular cross-section. In addition, the transistor 100F includes an insulating film 117 between the oxide semiconductor film 110 and the insulating film 118 .

[0219] Fig. 9B The capacitor element 150F is shown with Figure 5D The capacitor 150A shown is different in the shapes of the insulating film 112 and the conductive film 116. Specifically, the insulating film 112 and the conductive film 116 of the capacitor 150F also have a rectangular cross-section. In addition, the capacitor 150F has an insulating film 117 between the conductive film 116 and the insulating film 118.

[0220] Fig.9A and 9B The insulating film 117 shown may be used Fig. 8A and 8B The oxide insulating film described in the transistor 100D and the capacitor 150D shown in the figure is formed. This oxide insulating film can be used for the insulating films 108c and 112a, contains nitrogen, and has a small amount of defects.

[0221] When the transistor 100F has Fig.9A When the shape shown in FIG. 1 is changed to the shape shown in FIG. 1 , the shape of the low resistance region formed in the oxide semiconductor film 110 may be changed to Fig.10 The structure shown.

[0222] Fig.10 yes Fig.9A FIG. 1 is an enlarged view of the vicinity of the oxide semiconductor film 110 of the transistor 100F. Fig.10 As shown in FIG. 1 , in the cross-sectional shape of the oxide semiconductor film 110 in the channel length direction, a region (low resistance region) is formed in which the conductivity is improved due to the increase in the carrier density of the oxide semiconductor film. Fig.10 In FIG, the channel length L is the length of a region sandwiched between a pair of low resistance regions.

[0223] In the cross-sectional shape along the channel length direction, Fig.10The oxide semiconductor film 110 shown has a low resistance region 110d between the channel region 110a and the low resistance region 110b, and has a low resistance region 110e between the channel region 110a and the low resistance region 110c. The impurity element concentration of the low resistance regions 110d and 110e is lower than that of the low resistance regions 110b and 110c, and the resistivity of the low resistance regions 110d and 110e is higher than that of the low resistance regions 110b and 110c. Note that the low resistance regions 110d and 110e overlap with the insulating film 117 in contact with the side surfaces of the insulating film 112 and the conductive film 114. Here, the low resistance regions 110d and 110e may also overlap with the insulating film 112 and the conductive film 114.

[0224] The oxide semiconductor film 110 includes the low resistance regions 110d and 110e having lower impurity element concentration and higher resistivity than the low resistance regions 110b and 110c, so that the electric field in the drain region can be relaxed. Thus, the threshold voltage variation caused by the electric field in the drain region can be reduced in the transistor.

[0225] <Structure of semiconductor device 8>

[0226] Fig. 9C The transistor 100G shown with Figure 5C The transistor 100A shown is different in the shapes of the insulating film 112 and the oxide semiconductor film 110. Specifically, the insulating film 112 included in the transistor 100G has two film thicknesses, one of which is the film thickness of the region overlapping with the conductive film 114, and the other is the film thickness of the region not overlapping with the conductive film 114. The film thickness of the region not overlapping with the conductive film 114 is thinner than the region overlapping with the conductive film 114. In addition, the insulating film 112 covers the oxide semiconductor film 110, so that the film thickness is substantially uniform in the entire portion of the oxide semiconductor film 110.

[0227] Fig.9D The capacitor element 150G is shown with Figure 5D The capacitor 150A shown is different in the shape of the insulating film 112. Specifically, the insulating film 112 included in the capacitor 150G has two film thicknesses, one of which is the film thickness of the region overlapping with the conductive film 116, and the other is the film thickness of the region not overlapping with the conductive film 116. The film thickness of the region not overlapping with the conductive film 116 is thinner than that of the region overlapping with the conductive film 116.

[0228] As a formation Fig. 9C and 9DAs a method for forming the insulating film 112 shown, for example, a method is exemplified in which, after processing the conductive film 114 , the insulating film 112 is removed so as to leave the insulating film 112 in a region that does not overlap with the conductive film 114 .

[0229] exist Fig. 9C In the transistor 100G shown, the insulating film 112 is in contact with the channel region 110a and the low resistance regions 110b and 110c of the oxide semiconductor film 110. In addition, in the insulating film 112, the film thickness of the region in contact with the low resistance regions 110b and 110c is thinner than the region in contact with the channel region 110a. Typically, the average film thickness of the insulating film 112 is greater than 0.1nm and less than 50nm or greater than 0.5nm and less than 10nm. As a result, while the impurity element is added to the oxide semiconductor film 110 through the insulating film 112, the hydrogen contained in the insulating film 118 can be moved to the oxide semiconductor film 110 through the insulating film 112. Therefore, the low resistance regions 110b and 110c can be formed.

[0230] By using an oxide insulating film containing nitrogen and having a small amount of defects as the insulating film 112, nitrogen oxides are less likely to be generated in the insulating film 112, thereby reducing carrier traps at the interface between the insulating film 112 and the oxide semiconductor film 110. As a result, the drift of the threshold voltage of the transistor can be reduced, thereby reducing the variation of the electrical characteristics of the transistor.

[0231] Furthermore, the insulating film 108 has a multilayer structure of an insulating film 108a, an insulating film 108b, and an insulating film 108c. For example, the insulating film 108a is formed using a nitride insulating film, the insulating film 108b is formed using an oxynitride silicon film that releases oxygen due to heating, and the insulating film 108c is formed using an oxide insulating film containing nitrogen and having a small amount of defects. Furthermore, the insulating film 112 is formed using an oxide insulating film containing nitrogen and having a small amount of defects. That is, the oxide semiconductor film 110 can be covered with an oxide insulating film containing nitrogen and having a small amount of defects. As a result, while the oxygen contained in the insulating film 108b is moved to the oxide semiconductor film 110 by heat treatment to reduce the oxygen vacancies contained in the channel region 110a of the oxide semiconductor film 110, the carrier traps in the interface between the insulating films 108c and 112 and the oxide semiconductor film 110 can be reduced. As a result, the drift of the threshold voltage of the transistor can be reduced, and thus the variation of the electrical characteristics of the transistor can be reduced.

[0232] <Structure of semiconductor device 9>

[0233] Fig.11A The transistor 100H is shown with Figure 5CThe transistor 100A shown is different in the structure of the oxide semiconductor film 110. Specifically, the oxide semiconductor film 110 included in the transistor 100H includes an oxide semiconductor film 110_1 and an oxide semiconductor film 110_2 in contact with the oxide semiconductor film 110_1. That is, the oxide semiconductor film 110 has a multilayer structure.

[0234] Fig.11A The oxide semiconductor film 110 of the transistor 100H shown has the low resistance region described above. Specifically, the oxide semiconductor film 110 of the transistor 100H includes a channel region 110a_1, a channel region 110a_2, a low resistance region 110b_1, a low resistance region 110b_2, a low resistance region 110c_1, and a low resistance region 110c_2.

[0235] Energy Band Diagram

[0236] Here, Fig. 11B The energy band diagram of the AB cross section including the channel region of the transistor 100H is shown. In addition, the energy gap of the oxide semiconductor film 110_2 is larger than that of the oxide semiconductor film 110_1. The energy gaps of the insulating films 108a, 108b, and 112 are larger than those of the oxide semiconductor film 110_1 and the oxide semiconductor film 110_2. In addition, the Fermi levels (expressed as Ef) of the oxide semiconductor film 110_1, the oxide semiconductor film 110_2, the insulating films 108a, 108b, and the insulating film 112 are located at the positions of the intrinsic Fermi levels (expressed as Ei). The work functions of the conductive films 106 and 114 are the same as the Fermi level.

[0237] When the gate voltage is set to be equal to or higher than the threshold voltage of the transistor, electrons flow preferentially to the oxide semiconductor film 110_1 due to the energy difference at the bottom of the conduction band between the oxide semiconductor film 110_1 and the oxide semiconductor film 110_2. That is, it can be estimated that the electrons are buried in the oxide semiconductor film 110_1. Note that the energy at the bottom of the conduction band is represented as Ec, and the energy at the top of the valence band is represented as Ev.

[0238] Thus, in the transistor according to one embodiment of the present invention, the influence of interface scattering can be reduced by burying electrons. Therefore, the channel resistance of the transistor according to one embodiment of the present invention is small.

[0239] then, Fig. 11CThe energy band diagram on the CD cross section including the source region or the drain region of the transistor is shown. Note that the low resistance region 110c_1 and the low resistance region 110c_2 are in a degenerate state. In addition, in the low resistance region 110c_1, the Fermi level of the oxide semiconductor film 110_1 is equal to the energy of the bottom of the conduction band. In the low resistance region 110c_2, the Fermi level of the oxide semiconductor film 110_2 is equal to the energy of the bottom of the conduction band.

[0240] At this time, the potential barrier between the conductive film 124 having the function of the source electrode or the drain electrode and the low resistance region 110c_2 is sufficiently small, so the conductive film 124 and the low resistance region 110c_2 are in ohmic contact. The low resistance region 110c_2 and the low resistance region 110c_1 are in ohmic contact. It can be seen from this that the transfer of electrons between the conductive film 124 and the oxide semiconductor film 110_1 and the oxide semiconductor film 110_2 is very smooth.

[0241] In the region where the conductive film 122 having one of the functions of the source electrode and the drain electrode is in contact with the low resistance region 110b_1 of the oxide semiconductor film 110 and the low resistance region 110b_2 of the oxide semiconductor film 110, the conductive film 122 may be connected to the low resistance region 110b_2 of the oxide semiconductor film 110. Fig. 11C The same description as described.

[0242] As described above, the transistor according to one embodiment of the present invention is a transistor in which electron transfer between the source electrode and the drain electrode and the channel region is smooth and the channel resistance is small. In other words, it is known that the transistor has excellent switching characteristics.

[0243] <Connection and intersection of conductive film in semiconductor device>

[0244] Next, refer to Figures 30A to 30D illustrate Figures 5A to 5D The semiconductor device according to one embodiment of the present invention has structures of connection portions and intersection portions of respective conductive films. Figures 30A to 30C A cross-sectional view showing the structure of the connection portion of each conductive film, Fig.30D A cross-sectional view showing the structure of an intersection of two conductive films.

[0245] Fig. 30AThe connecting portion shown includes: an insulating film 104 on a substrate 102; a conductive film 306 on the insulating film 104; an insulating film 108 covering the conductive film 306; an insulating film 112 on the insulating film 108; a conductive film 314 disposed on the insulating film 112 and connected to the conductive film 306 in an opening 352 disposed in the insulating film 112 and the insulating film 108; an insulating film 118 covering the insulating films 108, 112 and the conductive film 314; an insulating film 120 on the insulating film 118; a conductive film 318 disposed on the insulating film 120 and connected to the conductive film 314 in an opening 353 disposed in the insulating film 118 and the insulating film 120; and an insulating film 128 covering the insulating film 120 and the conductive film 318.

[0246] Fig. 30B The connecting portion shown includes: an insulating film 104 on a substrate 102; an insulating film 108 on the insulating film 104; an insulating film 112 on the insulating film 108; a conductive film 324 on the insulating film 112; an insulating film 118 covering the insulating films 108, 112 and the conductive film 324; an insulating film 120 on the insulating film 118; a conductive film 328 disposed on the insulating film 120 and connected to the conductive film 324 in an opening 354 placed in the insulating film 118 and the insulating film 120; and an insulating film 128 covering the insulating film 120 and the conductive film 328.

[0247] Fig. 30C The connecting portion shown includes: an insulating film 104 on a substrate 102; a conductive film 316 on the insulating film 104; an insulating film 108 covering the conductive film 316; an insulating film 112 on the insulating film 108; a conductive film 334 disposed on the insulating film 112 and connected to the conductive film 316 in an opening 355 disposed in the insulating film 112 and the insulating film 108; an insulating film 118 covering the insulating film 108 and the conductive film 334; an insulating film 120 on the insulating film 118; and an insulating film 128 on the insulating film 120.

[0248] Fig.30D The intersection shown includes: insulating film 104 on substrate 102; conductive film 326 on insulating film 104; insulating film 108 covering conductive film 326; insulating film 118 on insulating film 108; insulating film 120 on insulating film 118; conductive film 338 on insulating film 120; and insulating film 128 on conductive film 338.

[0249] exist Figures 30A to 30D In the embodiment, the insulating film 108 has a stacked structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. Fig. 30AIn the embodiment, the conductive film 306 has a stacked structure of a conductive film 306a and a conductive film 306b on the conductive film 306a, the conductive film 314 has a stacked structure of a conductive film 314a and a conductive film 314b on the conductive film 314a, and the conductive film 318 has a stacked structure of a conductive film 318a and a conductive film 318b on the conductive film 318a. Fig. 30B In FIG. 1 , the conductive film 324 has a stacked structure of a conductive film 324a and a conductive film 324b on the conductive film 324a, and the conductive film 328 has a stacked structure of a conductive film 328a and a conductive film 328b on the conductive film 328a. Fig. 30C In FIG. 1 , the conductive film 316 has a stacked structure of a conductive film 316a and a conductive film 316b on the conductive film 316a, and the conductive film 334 has a stacked structure of a conductive film 334a and a conductive film 334b ​​on the conductive film 334a. Fig.30D In the figure, the conductive film 326 has a stacked-layer structure of a conductive film 326a and a conductive film 326b on the conductive film 326a, and the conductive film 338 has a stacked-layer structure of a conductive film 338a and a conductive film 338b on the conductive film 338a.

[0250] The conductive films 306, 316, and 326 are formed by the same process as the conductive film 106 of the transistor 100A. That is, at least a portion of the conductive films 106, 306, 316, and 326 are formed on the same surface. In addition, the conductive films 314, 324, and 334 are formed by the same process as the conductive film 114 of the transistor 100A and the conductive film 116 of the capacitor 150A. That is, at least a portion of the conductive films 114, 116, 314, 324, and 334 are formed on the same surface. In addition, the conductive films 318, 328, and 338 are formed by the same process as the conductive films 122 and 124 of the transistor 100A and the conductive film 126 of the capacitor 150A. That is, at least a portion of the conductive films 124, 126, 318, 328, and 338 are formed on the same surface.

[0251] like Fig.30D As shown in FIG. 1 , insulating films 108, 118, and 120 are provided between the conductive film 326 and the conductive film 338. That is, a plurality of insulating films are stacked between the conductive film 326 and the conductive film 338. Fig.30D The structure of the intersection of the conductive films shown above can reduce parasitic capacitance in the intersection of the conductive films, thereby reducing signal delay caused by parasitic capacitance.

[0252] <Method for manufacturing semiconductor device 1>

[0253] Next, refer to FIG. 12A to FIG. 16F illustrate Figures 1A to 1DAn example of a method for manufacturing the transistor 100 and the capacitor 150 is shown.

[0254] The film (insulating film, oxide semiconductor film, conductive film, etc.) constituting the transistor 100 and the capacitor 150 can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD). Alternatively, it can be formed by coating or printing. As typical film forming methods, there are sputtering and plasma chemical vapor deposition (PECVD), but thermal CVD can also be used. As an example of thermal CVD, MOCVD (metal organic chemical vapor deposition) or ALD (atomic layer deposition) can be used.

[0255] Deposition by the thermal CVD method can be performed as follows: by setting the pressure in the processing chamber to atmospheric pressure or reduced pressure, the source gas and the oxidant are simultaneously supplied into the processing chamber, and are allowed to react with each other near or on the substrate to be deposited on the substrate. In this way, since the thermal CVD method does not generate plasma to form a film, it has the advantage of not generating defects caused by plasma damage.

[0256] In addition, deposition by the ALD method can be performed as follows: the pressure in the processing chamber is set to atmospheric pressure or reduced pressure, the source gas for the reaction is introduced into the processing chamber in sequence, and then the gas is repeatedly introduced in this order. For example, two or more source gases are sequentially supplied into the processing chamber by switching respective switch valves (also called high-speed valves). In this case, an inert gas (argon or nitrogen, etc.) is introduced at the same time or after the first source gas is introduced in a manner that prevents the mixing of multiple source gases, and then the second source gas is introduced. Note that in the case where the first source gas and the inert gas are introduced at the same time, the inert gas is used as a carrier gas, and the inert gas can also be introduced at the same time as the second source gas is introduced. In addition, the first source gas can be discharged by vacuum pumping without introducing an inert gas, and then the second source gas can be introduced. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer; then the second source gas is introduced to react with the first monoatomic layer; as a result, the second monoatomic layer is stacked on the first monoatomic layer to form a thin film.

[0257] By repeatedly introducing the gases in this order until the desired thickness is obtained, a thin film with good step coverage can be formed. The thickness of the thin film can be adjusted by the number of times the gases are repeatedly introduced in this order, so the ALD method can accurately adjust the thickness and is therefore suitable for manufacturing micro transistors.

[0258] also, Fig. 12A , 12C , 12E, 12G, Fig.13A , 13C 、13E、 Fig.14A , 14C 、14E、 Fig.15A , 15C , 15E and Fig.16A , 16C 16E is a cross-sectional view illustrating a method for manufacturing the transistor 100. Fig. 12B , 12D 、12F、12H、 Fig. 13B , 13D , 13F, Fig. 14B , 14D , 14F, Fig. 15B , 15D , 15F and Fig. 16B , 16D 16F is a cross-sectional view for explaining a method for manufacturing the capacitor element 150 .

[0259] First, an insulating film 108 (insulating films 108a and 108b) is formed on the substrate 102 (see Fig. 12A and 12B ).

[0260] The insulating film 108 can be formed by appropriately using a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like. In this embodiment, a 100 nm thick silicon nitride film is formed as the insulating film 108a using a PECVD device. A 400 nm thick silicon oxynitride film is formed as the insulating film 108b using a PECVD device.

[0261] In addition, oxygen may be added to the insulating film 108b after the insulating film 108b is formed. As the oxygen species added to the insulating film 108b, there are oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc. In addition, as the adding method, there are ion doping method, ion implantation method, plasma treatment, etc. In addition, after a film for suppressing the separation of oxygen is formed on the insulating film, oxygen may be added to the insulating film 108b through the film.

[0262] The insulating film 108b is formed by using a silicon oxide film or a silicon oxynitride film that can release oxygen by heat treatment under the following conditions: the substrate is maintained in a vacuum processing chamber of a plasma PECVD device at a temperature of 180° C. to 280° C. or 200° C. to 240° C., a source gas is introduced into the processing chamber, the pressure in the processing chamber is set to 100 Pa to 250 Pa or 100 Pa to 200 Pa, and 0.17 W / cm2 is supplied to an electrode in the processing chamber. 2 Above 0.5W / cm 2 Below or 0.25W / cm 2 Above and 0.35W / cm2 The following high frequency power.

[0263] Here, a method is described in which a film that suppresses oxygen desorption is formed on the insulating film 108 b and oxygen is added to the insulating film 108 b through the film.

[0264] A film 141 for suppressing oxygen desorption is formed on the insulating film 108b (see Fig. 12C and 12D ).

[0265] Next, oxygen 142 is added to the insulating film 108b through the film 141 (see Fig.12E and 12F ).

[0266] A film 141 for inhibiting oxygen detachment is formed using a conductive material such as a metal element selected from aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, an alloy containing the above metal elements, an alloy combining the above metal elements, a metal nitride having the above elements, a metal oxide having the above elements, or a metal nitride oxide having the above elements.

[0267] The thickness of the film 141 for suppressing oxygen desorption can be set to be greater than or equal to 1 nm and less than or equal to 2 nm and less than or equal to 10 nm.

[0268] As a method of adding oxygen 142 to the insulating film 108b through the film 141, there are ion doping, ion implantation, plasma treatment, etc. By providing the film 141 on the insulating film 108b to add oxygen, the film 141 is used as a protective film to suppress the separation of oxygen from the insulating film 108b. Thus, more oxygen can be added to the insulating film 108b.

[0269] When oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 108 b can be increased by exciting oxygen with microwaves to generate high-density oxygen plasma.

[0270] Then, the film 141 is removed (see Figure 12G and 12H ).

[0271] In addition, when the insulating film 108b can be formed with sufficient oxygen added after film formation, it is not necessary to perform the Fig. 12C and 12D as well as Fig.12E and 12F Treatment with added oxygen is shown.

[0272] Next, an oxide semiconductor film is formed on the insulating film 108 b and processed into a desired shape to form the oxide semiconductor film 110. Then, an insulating film 112 is formed on the insulating film 108 b and the oxide semiconductor film 110 (see Fig.13A and 13B ).

[0273] The following describes a method for forming the oxide semiconductor film 110. The oxide semiconductor film is formed on the insulating film 108b by sputtering, coating, pulse laser evaporation, laser ablation, thermal CVD, or the like. Next, a mask is formed on the oxide semiconductor film by a photolithography process, and a portion of the oxide semiconductor film is etched using the mask, thereby forming a thin film. Fig.13A As shown in FIG. 1 , the oxide semiconductor film 110 can be formed. Then, the mask is removed. Alternatively, heat treatment may be performed after the oxide semiconductor film 110 is formed.

[0274] In addition, by forming the oxide semiconductor film 110 by a printing method, the oxide semiconductor film 110 for element isolation can be directly formed.

[0275] In the case of forming an oxide semiconductor film by a sputtering method, an RF power supply device, an AC power supply device, a DC power supply device, or the like can be appropriately used as a power supply device for generating plasma. By using an AC power supply device or a DC power supply device, a CAAC-OS film can be formed. Compared with the case of forming an oxide semiconductor film by a sputtering method using an RF power supply device, the case of using a sputtering method using an AC power supply device or a DC power supply device can form an oxide semiconductor film with uniform film thickness distribution, film composition distribution, or crystallinity distribution, so it is preferred.

[0276] As a sputtering gas when forming an oxide semiconductor film, a rare gas (typically argon), an oxygen gas, or a mixed gas of a rare gas and an oxygen gas is appropriately used. When a mixed gas of a rare gas and an oxygen gas is used, it is preferable to increase the ratio of the oxygen gas to the rare gas.

[0277] In addition, a sputtering target when forming an oxide semiconductor film may be appropriately selected according to the composition of the oxide semiconductor film to be formed.

[0278] In addition, when the oxide semiconductor film is formed by, for example, a sputtering method, the CAAC-OS film can be formed by setting the substrate temperature to 150° C. to 750° C., 150° C. to 450° C., or 200° C. to 350° C. In addition, a microcrystalline oxide semiconductor film can be formed by setting the substrate temperature to 25° C. to less than 150° C.

[0279] In order to form the CAAC-OS film described below, the following conditions are preferably applied.

[0280] By suppressing the mixing of impurities during film formation, the damage to the crystalline state caused by impurities can be suppressed. For example, the concentration of impurities (hydrogen, water, carbon dioxide, nitrogen, etc.) present in the film forming chamber can be reduced. In addition, the concentration of impurities in the film forming gas can be reduced. Specifically, a film forming gas with a dew point below -80°C or below -100°C is used.

[0281] In addition, it is preferable to increase the oxygen ratio in the film forming gas and optimize the power to reduce plasma damage during film forming. The oxygen ratio in the film forming gas is set to 30 vol.% or more, preferably 100 vol.%.

[0282] Alternatively, the oxide semiconductor film may be dehydrogenated or dehydrated by performing a heat treatment after the oxide semiconductor film is formed. The heat treatment temperature is typically 150° C. or higher and lower than the strain point of the substrate, 250° C. or higher and 450° C. or higher and 300° C. or lower.

[0283] The heat treatment is performed in an inert gas atmosphere containing a rare gas such as helium, neon, argon, xenon, krypton, or nitrogen. Alternatively, the heat treatment may be performed in an inert gas atmosphere and then in an oxygen atmosphere. In addition, the inert gas atmosphere and the oxygen atmosphere preferably do not contain hydrogen, water, etc. The treatment time is more than 3 minutes and less than 24 hours.

[0284] The heat treatment can be performed using an electric furnace, an RTA device, etc. By using an RTA device, the heat treatment can be performed at a temperature above the strain point of the substrate within a limited time. Thus, the heat treatment time can be shortened.

[0285] The oxide semiconductor film is formed while being heated, or the oxide semiconductor film is heat-treated after being formed, and thus the hydrogen concentration in the oxide semiconductor film measured by secondary ion mass spectrometry can be 5×10 19 atoms / cm 3 Below, 1×10 19 atoms / cm 3 Below, 5×10 18 atoms / cm 3 Below, 1×10 18 atoms / cm 3 Below, 5×10 17 atoms / cm 3 Below or 1×10 16 atoms / cm 3 the following.

[0286] For example, when an oxide semiconductor film such as InGaZnO is formed using a film forming apparatus using ALDX (X>0) film, In(CH 3 ) 3 Gas and O 3 Gas formation InO 2 layer, while introducing Ga(CH 3 ) 3 Gas and O 3 gas to form a GaO layer, and then simultaneously introduce Zn(CH 3 ) 2 Gas and O 3 The gases form a ZnO layer. Note that the order of these layers is not limited to the above example. In addition, these gases can also be mixed to form a mixed compound layer such as InGaO 2 Layer, InZnO 2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. Note that H bubbling with an inert gas such as Ar may also be used. 2 O gas to replace O 3 gas, but preferably O containing no H 3 Gas. You can also use In (C 2 H 5 ) 3 Gas replaces In (CH 3 ) 3 Gas. Ga(C 2 H 5 ) 3 Gas replaces Ga(CH 3 ) 3 Gas. Alternatively, Zn(CH 3 ) 2 gas.

[0287] In this embodiment, the oxide semiconductor film 110 is formed by the following steps: a 50 nm thick oxide semiconductor film is formed using a sputtering target of In-Ga-Zn metal oxide (In:Ga:Zn=1:1:1.2 [atomic ratio]) using a sputtering device, and then heat treatment is performed to transfer oxygen contained in the insulating film 108b to the oxide semiconductor film. Finally, a mask is formed on the oxide semiconductor film and the oxide semiconductor film is selectively etched.

[0288] In addition, by performing heat treatment at a temperature higher than 350°C and lower than 650°C or higher than 450°C and lower than 600°C, an oxide semiconductor film having a CAAC rate of 60% or higher and lower than 100%, 80% or higher and lower than 100%, 90% or higher and lower than 100%, or 95% or higher and lower than 98% can be obtained. In addition, an oxide semiconductor film having a reduced content of hydrogen, water, etc. can be obtained. That is, an oxide semiconductor film having a low impurity concentration and a low defect state density can be formed.

[0289] The insulating film 112 can appropriately utilize the method for forming the insulating film 108b. As the insulating film 112, a silicon oxide film or a silicon oxynitride film can be formed by a PECVD method. At this time, as source gases, it is preferable to use a deposition gas containing silicon and an oxidizing gas. Typical examples of deposition gases containing silicon include silane, disilane, trisilane, and fluorinated silane. As oxidizing gases, there are oxygen, ozone, nitrous oxide, nitrogen dioxide, and the like.

[0290] A silicon oxynitride film with few defects can be formed as an insulating film 112 using the PECVD method under the following conditions: the ratio of the oxidizing gas to the deposition gas is greater than 20 times and less than 100 times or greater than 40 times and less than 80 times; and the pressure in the processing chamber is less than 100 Pa or less than 50 Pa.

[0291] A dense silicon oxide film or silicon oxynitride film can be formed as the insulating film 112 under the following conditions: the substrate is maintained in a vacuum processing chamber of a PECVD device at a temperature of not less than 280°C and not more than 400°C, the source gas is introduced into the processing chamber, the pressure in the processing chamber is set to not less than 20Pa and not more than 250Pa, preferably not less than 100Pa and not more than 250Pa, and high-frequency power is supplied to an electrode arranged in the processing chamber.

[0292] The insulating film 112 can be formed by using a plasma CVD method using microwaves. Microwaves refer to a frequency range of 300 MHz to 300 GHz. Microwaves have low electron temperature and low electron energy. In addition, a small proportion of the supplied power is used for electron acceleration, so the remaining proportion of power can be used for the dissociation and ionization of more molecules, thereby exciting a high-density plasma (high-density plasma). Therefore, an insulating film 112 with less plasma damage to the film-forming surface and the deposit and fewer defects can be formed.

[0293] The insulating film 112 can be formed by a CVD method using an organic silane gas. As the organic silane gas, tetraethyl orthosilicate (TEOS: a chemical formula of Si(OC 2 H 5 ) 4), tetramethylsilane (TMS: chemical formula is Si(CH 3 ) 4 ), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC 2 H 5 ) 3 ), tris(dimethylamino)silane (SiH(N(CH 3 ) 2 ) 3 ) or the like. By utilizing a CVD method using an organic silane gas, the insulating film 112 having improved coverage can be formed.

[0294] When a gallium oxide film is formed as the insulating film 112 , it can be formed by using a MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0295] When forming a hafnium oxide film as the insulating film 112 by a thermal CVD method such as an MOCVD method or an ALD method, two gases are used, namely, ozone (O 3 ) and a source gas obtained by vaporizing a liquid (hafnium alkoxide solution, typically tetrakis dimethylamide hafnium (TDMAH)) containing a solvent and a hafnium precursor compound. Note that the chemical formula of tetrakis dimethylamide hafnium is Hf[N(CH 3 ) 2 ] 4 In addition, other material liquids include tetrakis(ethylmethylamide)hafnium and the like.

[0296] For example, when an aluminum oxide film is formed as the insulating film 112 by a thermal CVD method such as an MOCVD method or an ALD method, two gases are used, namely, H as an oxidizing agent and 2 O and a source gas obtained by gasifying a liquid containing a solvent and an aluminum precursor compound (trimethylaluminum (TMA) or the like). Note that the chemical formula of trimethylaluminum is Al(CH 3 ) 3 Other material liquids include tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione), and the like. In addition, by using the ALD method, the insulating film 112 can be formed with a high coverage and a thin film thickness.

[0297] For example, when a silicon oxide film is formed as the insulating film 112 by a thermal CVD method such as an MOCVD method or an ALD method, hexachlorodisilane is adsorbed on the film-forming surface, chlorine contained in the adsorbate is removed, and an oxidizing gas (O 2or nitrous oxide) to react with the adsorbate.

[0298] Here, as the insulating film 112, a silicon oxynitride film is formed to a thickness of 100 nm using a PECVD apparatus.

[0299] Next, the conductive film 113 (the conductive film 113 a and the conductive film 113 b ) is formed on the insulating film 112 (see Fig. 13C and 13D ).

[0300] The conductive film 113 can be formed by using a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. In this embodiment, a 10 nm thick tantalum nitride film is formed as the conductive film 113a using a sputtering device. In addition, a 300 nm thick copper film is formed as the conductive film 113b using a sputtering device. In addition, when the conductive film 113a and the conductive film 113b are formed continuously in a vacuum, impurities can be suppressed from entering the interface between the conductive film 113a and the conductive film 113b, which is preferable.

[0301] Alternatively, a tungsten film may be formed as the conductive film 113b by using a film forming apparatus using an ALD method. In this case, WF is introduced repeatedly in sequence. 6 Gas and B 2 H 6 The gas forms the initial tungsten film and then simultaneously introduces WF 6 Gas and H 2 Gas to form a tungsten film. Note that SiH 4 Gas Replacement B 2 H 6 gas.

[0302] Next, a mask 145 is formed on the conductive film 113b by a photolithography process, and then the conductive film 113b, the conductive film 113a, and a portion of the insulating film 112 are etched (see Fig.13E and 13F ).

[0303] As a method of etching the conductive film 113 and the insulating film 112 , a wet etching method and / or a dry etching method can be used as appropriate.

[0304] Next, the conductive film 113 and the insulating film 112 are processed while shrinking the mask 145 to form conductive films 114a, 114b, 116a, and 116b (see Fig.14A and 14B ).

[0305] In addition, a portion of the oxide semiconductor film 110 is exposed in the transistor 100 through the etching process of the conductive film 113 and the insulating film 112. In addition, since the conductive film 114 and the insulating film 112 are etched, the thickness of the exposed region of the oxide semiconductor film 110 may be thinner than the region of the oxide semiconductor film 110 overlapping with the conductive film 114. In addition, in the transistor 100, a portion of the region where the insulating film 108b serving as a base film is not covered by the oxide semiconductor film 110 is removed through the etching process of the conductive film 113 and the insulating film 112, and the thickness of the region may be thinner than the region overlapping with the oxide semiconductor film 110. In addition, in the capacitor 150, a portion of the region where the insulating film 108b serving as a base film is not covered by the insulating film 112 is removed through the etching process of the conductive film 113 and the insulating film 112, and the thickness of the region may be thinner than the region overlapping with the insulating film 112.

[0306] Next, an impurity element 143 is added to the insulating film 108 b, the insulating film 112 , the oxide semiconductor film 110 , the conductive film 114 , and the mask 145 (see Fig. 14C and 14D ).

[0307] Through the step of adding the impurity element 143, the impurity element 143 is added to the oxide semiconductor film 110 that is not covered by the conductive film 114, the insulating film 112, and the mask 145. At this time, oxygen vacancies are formed in the oxide semiconductor film 110 due to the addition of the impurity element 143.

[0308] In addition, as a method of adding the impurity element 143, there are ion doping, ion implantation, plasma treatment, etc. When plasma treatment is used, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing plasma treatment. As an apparatus for generating plasma, a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high-density plasma CVD apparatus, etc. can be used.

[0309] As the source gas of the impurity element 143, B 2 H 6 , PH 3 , CH 4 、N 2 NH 3 , AlH 3 、AlCl 3 、SiH 4 、Si 2 H 6 、F 2 , HF, H 2Alternatively, B diluted with a rare gas may be used. 2 H 6 , PH 3 、N 2 NH 3 , AlH 3 、AlCl 3 、F 2 , HF and H 2 By using B diluted with a rare gas 2 H 6 , PH 3 、N 2 NH 3 , AlH 3 、AlCl 3 、F 2 , HF and H 2 The impurity element 143 may be added to the oxide semiconductor film 110 at one or more of the following: a rare gas and one or more of hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, and chlorine may be added to the oxide semiconductor film 110 at the same time.

[0310] Alternatively, after adding the rare gas to the oxide semiconductor film 110, B 2 H 6 , PH 3 , CH 4 、N 2 NH 3 , AlH 3 、AlCl 3 、SiH 4 、Si 2 H 6 、F 2 , HF and H 2 One or more of the above are added to the oxide semiconductor film 110 .

[0311] Alternatively, you can also add B 2 H 6 , PH 3 , CH 4 、N 2 NH 3 , AlH 3 、AlCl 3 、SiH 4 、Si 2 H 6 、F 2 , HF and H 2 After one or more of the above are added to the oxide semiconductor film 110 , a rare gas is added to the oxide semiconductor film 110 .

[0312] The addition of the impurity element 143 can be controlled by appropriately setting the implantation conditions such as the acceleration voltage and the dose. For example, when argon is added by ion implantation, the acceleration voltage can be set to 10 kV and the dose can be set to 1×10 13 ions / cm 2 Above and 1×10 16 ions / cm 2 For example, the dose can be set to 1×10 14 ions / cm 2 When phosphorus ions are added by ion implantation, the acceleration voltage can be set to 30 kV and the dose can be set to 1×10 13 ions / cm 2 Above and 5×10 16 ions / cm 2 For example, the dose can be set to 1×10 15 ions / cm 2 .

[0313] When argon is added as the impurity element 143 by using a dry etching device, the substrate can be placed on the cathode side of the parallel plate and RF power can be supplied to apply a bias voltage to the substrate side. As for the RF power, the power density can be set to 0.1 W / cm 2 Above and 2W / cm 2 the following.

[0314] Furthermore, as described in this embodiment, the impurity element 143 is preferably added while leaving the mask 145. By adding the impurity element 143 while leaving the mask 145, adhesion of constituent elements of the conductive film 114 to the side wall of the insulating film 112 can be suppressed. Note that the method of adding the impurity element 143 is not limited to the above method, and for example, the impurity element 143 may be added using the conductive film 114 and the insulating film 112 as masks after removing the mask 145.

[0315] Thereafter, heat treatment may be performed to further improve the conductivity of the region to which the impurity element 143 is added. The temperature for the heat treatment is typically 150° C. or higher and lower than the strain point of the substrate, 250° C. or higher and 450° C. or higher and 300° C. or lower.

[0316] Next, the mask 145 is removed (see Fig.14E and 14F ).

[0317] Next, an insulating film 118 is formed over the insulating film 108 b, the oxide semiconductor film 110 , and the conductive films 114 and 116 , and an insulating film 120 is formed over the insulating film 118 (see Fig.15A and 15B).

[0318] The insulating film 118 and the insulating film 120 can utilize the formation method of the insulating film 108 a and the insulating film 108 b as appropriate.

[0319] In this embodiment, a 100 nm thick silicon nitride film is formed by a PECVD device as the insulating film 118. A 300 nm thick silicon oxynitride film is formed by a PECVD device as the insulating film 120.

[0320] When a silicon nitride film is used as the insulating film 118 , hydrogen in the silicon nitride film can be introduced into the oxide semiconductor film 110 , so that the carrier concentration of the oxide semiconductor film 110 in contact with the insulating film 118 can be further increased.

[0321] Next, a mask is formed on the insulating film 120 by a photolithography process, and then a portion of the insulating film 120 is etched to form an opening 140c reaching the insulating film 118 (see Fig. 15C and 15D ).

[0322] As a method of etching the insulating film 120 , a wet etching method and / or a dry etching method can be used as appropriate.

[0323] Next, a mask is formed on the insulating film 120 by a photolithography process, and then a portion of the insulating films 118 and 120 is etched to form openings 140a and 140b reaching the oxide semiconductor film 110 (see Fig.15E and 15F ).

[0324] In addition, in this embodiment, the method of forming the opening 140c and the openings 140a and 140b by different processes is exemplified, but the present invention is not limited thereto. For example, the opening 140c and the openings 140a and 140b may be formed simultaneously using a halftone mask or a gray tone mask. By using a halftone mask or a gray tone mask, one photolithography process can be reduced, thereby reducing manufacturing costs.

[0325] Next, the conductive film 121 (the conductive film 121a and the conductive film 121b) is formed on the insulating film 120 so as to cover the openings 140a, 140b, and 140c (see Fig.16A and 16B ).

[0326] The conductive film 121 can be formed by using the method for forming the conductive film 113 as appropriate. Here, as the conductive film 121a, a 50-nm-thick tungsten film is formed by a sputtering device, and as the conductive film 121b, a 200-nm-thick copper film is formed by a sputtering device.

[0327] Next, a mask is formed over the conductive film 121b by a photolithography step, and then portions of the conductive film 121a and the conductive film 121b are etched to form the conductive films 122, 124, and 126 (see FIG. 1 ). Fig. 16C and 16D ).

[0328] The conductive film 122 has a stacked structure of a conductive film 122a and a conductive film 122b on the conductive film 122a. The conductive film 124 has a stacked structure of a conductive film 124a and a conductive film 124b on the conductive film 124a. The conductive film 126 has a stacked structure of a conductive film 126a and a conductive film 126b on the conductive film 126a.

[0329] Next, an insulating film 128 is formed on the insulating film 120, the conductive film 122, the conductive film 124, and the conductive film 126 (see Fig.16E and 16F ).

[0330] The insulating film 128 can utilize the formation method of the insulating film 108a as appropriate. Here, as the insulating film 128, a 200 nm thick silicon nitride film is formed by using a PECVD apparatus.

[0331] Through the above steps, the transistor 100 and the capacitor 150 can be manufactured over the same substrate.

[0332] <Method for manufacturing semiconductor device 2>

[0333] Next, the following explains Figures 5A to 5D An example of a method for manufacturing the transistor 100A and the capacitor 150A is shown.

[0334] An insulating film 104 is formed on the substrate 102. Next, a conductive film is formed on the insulating film 104 and processed into a desired shape to form a conductive film 106. Figures 12A to 12H as well as Fig.13A and 13B Then, after a mask is formed on the insulating film 112 by a photolithography process, a portion of the insulating film 112 is etched to form an opening 139 that reaches the conductive film 106. Then, by performing the same process as in Fig. 13C The same process as the process shown in the following figures can be manufactured on the same substrate Figures 5A to 5D Transistor 100A and capacitor element 150A are shown.

[0335] The structure and method described in this embodiment can be used in combination with the structure and method described in other embodiment as appropriate.

[0336] Implementation Method 2

[0337] In this embodiment, a structure of an oxide semiconductor film included in a semiconductor device which is one embodiment of the present invention is described in detail below.

[0338] First, a possible structure of the oxide semiconductor film is described.

[0339] Oxide semiconductor films are generally classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Non-single-crystal oxide semiconductor films include CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) films, polycrystalline oxide semiconductor films, microcrystalline oxide semiconductor films, and amorphous oxide semiconductor films.

[0340] First, the CAAC-OS film is described.

[0341] The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal portions aligned in the c-axis.

[0342] In a transmission electron microscope (TEM) image of the CAAC-OS film, a clear boundary between crystal parts, namely, a grain boundary, is not observed. Therefore, in the CAAC-OS film, a decrease in electron mobility due to the grain boundary is unlikely to occur.

[0343] According to the TEM image (cross-sectional TEM image) of the CAAC-OS film observed from a direction roughly parallel to the sample surface, metal atoms are arranged in layers in the crystal part. Each metal atom layer has a shape reflecting the convex and concave shape of the surface forming the CAAC-OS film (also called the formed surface) or the top surface of the CAAC-OS film, and is arranged in parallel to the formed surface or the top surface of the CAAC-OS film.

[0344] On the other hand, according to the TEM image of the CAAC-OS film observed from a direction approximately perpendicular to the sample surface (planar TEM image), metal atoms are arranged in a triangular or hexagonal shape in the crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0345] FIG17A is a cross-sectional TEM image of a CAAC-OS film. Fig. 17B This is an enlarged cross-sectional TEM image of FIG. 17A , in which the atomic arrangement is emphasized for easier understanding.

[0346] Fig. 17C It is a local Fourier transform image of the area surrounded by a circle (about 4 nm in diameter) between AO-A' in FIG17A. Fig. 17C The c-axis orientation can be confirmed in each region shown. In addition, the c-axis direction between AO is different from the c-axis direction between O-A', from which it can be seen that the grains between AO are different from the grains between O-A'. In addition, the angle of the c-axis between AO changes gradually and continuously, such as 14.3°, 16.6°, and 30.9°. Similarly, the angle of the c-axis between O-A' also changes gradually and continuously, such as -18.3°, -17.6°, and -11.3°.

[0347] In addition, in the electron diffraction pattern of the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, in the electron diffraction pattern of the top surface of the CAAC-OS film obtained using an electron beam having a wavelength of 1 nm or more and 30 nm or less (also referred to as a nanobeam electron diffraction pattern), spots are observed (see Fig.18A ).

[0348] It was found from cross-sectional TEM observation and planar TEM observation that the crystal parts of the CAAC-OS film have orientation.

[0349] Note that the crystalline parts included in the CAAC-OS film are almost all of a size that can be contained in a cube with a side length of less than 100nm. Therefore, sometimes the size of the crystalline parts included in the CAAC-OS film is a size that can be contained in a cube with a side length shorter than 10nm, shorter than 5nm, or shorter than 3nm. However, sometimes multiple crystalline parts included in the CAAC-OS film are connected to form a large crystalline region. For example, a 2500nm crystalline region is sometimes observed in a planar TEM image. 2 Above, 5mm 2 Above or 1000mm 2 above the crystalline region.

[0350] The structure of the CAAC-OS film is analyzed using an X-ray diffraction (XRD) device. For example, when the out-of-plane method is used to analyze the structure of the InGaZnO 4 In the case of a crystallized CAAC-OS film, a peak appears when the diffraction angle (2θ) is around 31°. This peak originates from InGaZnO 4 The (009) plane of the crystal indicates that the crystal in the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the top surface of the CAAC-OS film.

[0351] On the other hand, when the CAAC-OS film is analyzed using the in-plane method, in which X-rays are incident on the sample from a direction approximately perpendicular to the c-axis, a peak appears near 2θ of 56°. This peak originates from the InGaZnO4 The crystal (110) plane is fixed at 2θ around 56° and the sample is rotated about the normal vector of the sample plane (φ axis) for analysis (φ scanning). 4 When the sample is a single crystal oxide semiconductor film, six peaks appear. The six peaks originate from the crystal planes equivalent to the (110) plane. On the other hand, when the sample is a CAAC-OS film, no clear peaks can be observed even when φ scanning is performed with 2θ fixed at around 56°.

[0352] From the above results, it can be seen that in the CAAC-OS film with c-axis orientation, although the directions of the a-axis and the b-axis are different between the crystal parts, the c-axis is oriented in the direction parallel to the normal vector of the formed surface or the top surface. Therefore, the layered metal atomic layers observed in the above cross-sectional TEM image correspond to the plane parallel to the ab plane of the crystal.

[0353] Note that the crystal part is formed when the CAAC-OS film is formed or a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or top surface of the CAAC-OS film. Thus, for example, when the shape of the CAAC-OS film is changed by etching, etc., the c-axis of the crystal is not necessarily parallel to the normal vector of the formed surface or top surface of the CAAC-OS film.

[0354] In addition, in the CAAC-OS film, the distribution of the c-axis oriented crystal part is not necessarily uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth near the top surface of the CAAC-OS film, sometimes the proportion of the c-axis oriented crystal part near the top surface is higher than the proportion of the c-axis oriented crystal part near the formed surface. In addition, when impurities are added to the CAAC-OS film, the region to which the impurities are added is deteriorated and sometimes the proportion of the c-axis oriented crystal part in the CAAC-OS film varies depending on the region.

[0355] Note that when using the out-of-plane method to analyze the InGaZnO 4 In the case of a crystallized CAAC-OS film, in addition to a peak at 2θ of 31°, a peak at 2θ of 36° is sometimes observed. A peak at 2θ of 36° means that a portion of the CAAC-OS film contains crystals that do not have c-axis orientation. Preferably, in the CAAC-OS film, a peak appears at 2θ of 31° and no peak appears at 2θ of 36°.

[0356] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities refer to elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger bonding force with oxygen than the metal elements that constitute the oxide semiconductor film, will disrupt the atomic arrangement of the oxide semiconductor film because they will take oxygen from the oxide semiconductor film, resulting in a decrease in crystallinity. In addition, since heavy metals such as iron or nickel, argon, carbon dioxide, etc. have large atomic radii (or molecular radii), if they are contained in the oxide semiconductor film, they will also disrupt the atomic arrangement of the oxide semiconductor film, resulting in a decrease in crystallinity. Note that impurities contained in the oxide semiconductor film sometimes become carrier traps or carrier generation sources.

[0357] In addition, the CAAC-OS film is an oxide semiconductor film with a low defect state density. For example, an oxygen defect in the oxide semiconductor film may become a carrier trap or a carrier generation source by capturing hydrogen.

[0358] Next, a microcrystalline oxide semiconductor film is described.

[0359] Sometimes, no clear crystal part can be observed in the TEM image of a microcrystalline oxide semiconductor film. The size of the crystal part contained in the microcrystalline oxide semiconductor film is mostly greater than 1 nm and less than 100 nm, or greater than 1 nm and less than 10 nm. In particular, an oxide semiconductor film having nanocrystalline (nc: nanocrystal) microcrystals with a size of greater than 1 nm and less than 10 nm or greater than 1 nm and less than 3 nm is called an nc-OS (nanocrystalline Oxide Semiconductor: nanocrystalline oxide semiconductor) film. In addition, for example, in the TEM image of an nc-OS film, sometimes no clear grain boundary can be observed.

[0360] The atomic arrangement of the nc-OS film is periodic in a tiny area (for example, an area above 1 nm and below 10 nm, especially an area above 1 nm and below 3 nm). In addition, the regularity of the crystal orientation is not observed between different crystalline parts of the nc-OS film. Therefore, no orientation is observed in the film as a whole. Therefore, sometimes the nc-OS film is no different from the amorphous oxide semiconductor film in some analysis methods. For example, when the nc-OS film is structurally analyzed by an XRD device using an X-ray whose beam diameter is larger than the crystalline part by the out-of-plane method, no peak representing the crystalline plane is detected. In addition, when the nc-OS film is subjected to nanobeam electron diffraction (selected area electron diffraction) using electron beams whose beam diameter is larger than the crystalline part (for example, more than 50 nm), a diffraction pattern similar to a halo pattern is observed. On the other hand, when the nc-OS film is subjected to electron diffraction using electron beams whose beam diameter is close to or smaller than the crystalline part, spots are observed. In addition, in the nanobeam electron diffraction pattern of the nc-OS film, a high brightness region such as a circle (ring-shaped) is sometimes observed. In addition, in the nanobeam electron diffraction pattern of the nc-OS film, multiple spots are sometimes observed in the ring-shaped region (refer to Fig.18B ).

[0361] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Therefore, the defect state density of the nc-OS film is lower than that of the amorphous oxide semiconductor film. However, the regularity of the crystal orientation is not observed between different crystal parts of the nc-OS film. Therefore, the defect state density of the nc-OS film is higher than that of the CAAC-OS film.

[0362] Note that the oxide semiconductor film may be a stacked-layer film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

[0363] When the oxide semiconductor film has multiple structures, the structure can sometimes be analyzed by using nanobeam electron diffraction.

[0364] Fig. 18C A transmission electron diffraction measurement device is shown, which includes: an electron gun chamber 210; an optical system 212 under the electron gun chamber 210; a sample chamber 214 under the optical system 212; an optical system 216 under the sample chamber 214; an observation chamber 220 under the optical system 216; a camera 218 disposed in the observation chamber 220; and a film chamber 222 under the observation chamber 220. The camera 218 is disposed so as to face the inside of the observation chamber 220. In addition, the transmission electron diffraction measurement device may not include the film chamber 222.

[0365] also, Fig.18D Show Fig. 18C The structure of the transmission electron diffraction measurement device shown in FIG. In the transmission electron diffraction measurement device, electrons emitted from an electron gun disposed in an electron gun chamber 210 are irradiated to a substance 228 disposed in a sample chamber 214 via an optical system 212. The electrons that have passed through the substance 228 are incident on a fluorescent plate 232 disposed in an observation chamber 220 via an optical system 216. A pattern corresponding to the intensity of the incident electrons appears on the fluorescent plate 232, so that a transmission electron diffraction pattern can be measured.

[0366] Since the camera 218 is disposed toward the fluorescent plate 232, the pattern appearing on the fluorescent plate 232 can be photographed. The angle formed by the straight line passing through the center of the lens of the camera 218 and the center of the fluorescent plate 232 and the fluorescent plate 232 is, for example, 15° or more and 80° or more, 30° or more and 75° or more, or 45° or more and 70° or less. The smaller the angle, the greater the deformation of the transmission electron diffraction pattern photographed by the camera 218. However, if the angle is known in advance, the deformation of the obtained transmission electron diffraction pattern can be corrected. In addition, the camera 218 can sometimes be disposed in the film chamber 222. For example, the camera 218 can also be disposed in the film chamber 222 in a manner opposite to the incident direction of the electron 224. In this case, a transmission electron diffraction pattern with less deformation can be photographed from the back of the fluorescent plate 232.

[0367] The sample chamber 214 is provided with a support for fixing a substance 228 as a sample. The support allows electrons passing through the substance 228 to pass through. For example, the support may also have a function of moving the substance 228 in the direction of the X-axis, the Y-axis, the Z-axis, etc. The support may have, for example, an accuracy of moving the substance within a range of 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, 100 nm to 1 μm, etc. As for these ranges, the most suitable range may be set according to the structure of the substance 228.

[0368] Next, a method for measuring a transmission electron diffraction pattern of a substance using the above-mentioned transmission electron diffraction measurement apparatus will be described.

[0369] For example, Fig.18D As shown in FIG. 1 , by changing the position of the electron 224 as a nanobeam irradiated to the material (scanning), it can be confirmed that the structure of the material gradually changes. At this time, if the material 228 is a CAAC-OS film, it can be observed that Fig.18A If the substance 228 is a nc-OS film, then it can be observed that Fig.18B The diffraction pattern is shown.

[0370] Even if substance 228 is a CAAC-OS film, sometimes the same diffraction pattern as that of an nc-OS film is partially observed. Therefore, the quality of the CAAC-OS film can sometimes be represented by the proportion of the area in which the diffraction pattern of the CAAC-OS film is observed in a certain area (also called the CAACization rate). For example, the CAACization rate of an excellent CAAC-OS film is greater than 60%, preferably greater than 80%, more preferably greater than 90%, and further preferably greater than 95%. In addition, the proportion of the area where a diffraction pattern different from that of the CAAC-OS film is observed is expressed as the non-CAACization rate.

[0371] As an example, the top surface of a sample having a CAAC-OS film just after film formation (expressed as-sputtered) and the top surface of a sample having a CAAC-OS film after heat treatment at 450°C in an atmosphere containing oxygen are scanned to obtain a transmission electron diffraction pattern. Here, the diffraction pattern is observed by scanning at a speed of 5nm / second for 60 seconds, and the observed diffraction pattern is converted into a static image every 0.5 seconds, thereby calculating the CAAC rate. Note that a nanobeam with a beam diameter of 1nm is used as the electron beam. In addition, the same measurement is performed on six samples. Moreover, the CAAC rate is calculated by using the average value of the six samples.

[0372] Fig.19A The CAAC rate of each sample is shown. The CAAC rate of the CAAC-OS film just after film formation is 75.7% (the non-CAAC rate is 24.3%). In addition, the CAAC rate of the CAAC-OS film after a heat treatment at 450°C is 85.3% (the non-CAAC rate is 14.7%). It can be seen that the CAAC rate after a heat treatment at 450°C is higher than that just after film formation. In other words, it can be seen that a heat treatment at a high temperature (for example, above 400°C) reduces the non-CAAC rate (increases the CAAC rate). In addition, it can be seen that a CAAC-OS film with a high CAAC rate can be obtained when a heat treatment below 500°C is performed.

[0373] Here, most of the diffraction patterns different from the CAAC-OS film are the same diffraction patterns as the nc-OS film. In addition, no amorphous oxide semiconductor film is observed in the measurement area. It can be seen that by heat treatment, the area having the same structure as the nc-OS film is affected by the structure of the adjacent area and rearranged, so that the area is CAACized.

[0374] Fig.19B and Fig.19C This is a planar TEM image of the CAAC-OS film immediately after film formation and after a heat treatment at 450°C. Fig.19B and Fig.19C By comparison, it can be seen that the film quality of the CAAC-OS film after the heat treatment at 450° C. is more uniform. In other words, it can be seen that the film quality of the CAAC-OS film is improved by the high-temperature heat treatment.

[0375] By adopting this measurement method, it is sometimes possible to perform structural analysis on oxide semiconductor films having various structures.

[0376] By using an oxide semiconductor film having any of the above structures, a semiconductor device according to one embodiment of the present invention can be formed.

[0377] <Film Formation Model>

[0378] Next, the film formation models of CAAC-OS and nc-OS are described.

[0379] Fig.40A FIG. 1 is a schematic diagram in a film forming chamber showing a case where CAAC-OS is formed by a sputtering method.

[0380] The target 1130 is bonded to the backing plate. A plurality of magnets are arranged under the target 1130 and the backing plate. The plurality of magnets generate a magnetic field on the target 1130. The sputtering method that uses the magnetic field of the magnet to increase the film formation speed is called magnetron sputtering.

[0381] The target material 1130 has a polycrystalline structure, wherein at least one crystal grain includes a cleavage plane. The cleavage plane will be described in detail later.

[0382] The substrate 1120 is arranged opposite to the target 1130, and the distance d therebetween (also called the target-substrate distance (TS distance)) is greater than 0.01m and less than 1m, preferably greater than 0.02m and less than 0.5m. Most of the film forming chamber is filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 50 vol.% or more), and the pressure in the film forming chamber is controlled to be greater than 0.01Pa and less than 100Pa, preferably greater than 0.1Pa and less than 10Pa. Here, when a voltage greater than a certain value is applied to the target 1130, discharge begins and plasma is confirmed. In addition, a high-density plasma region is formed by the magnetic field on the target 1130. In the high-density plasma region, ions 1101 are generated due to the ionization of the film forming gas. The ions 1101 are, for example, cations of oxygen (O + ) or argon cation (Ar + )wait.

[0383] The ions 1101 are accelerated toward the target 1130 due to the electric field and then collide with the target 1130. At this time, the flat or granular sputtered particles 1100a and 1100b are peeled off from the cleavage plane and then knocked out. In addition, the impact of the ions 1101 when they collide sometimes causes strain in the structure of the particles 1100a and 1100b.

[0384] Particle 1100a is a flat or granular sputtered particle having a triangular plane, such as an equilateral triangle. In addition, particle 1100b is a flat or granular sputtered particle having a hexagonal plane, such as an equilateral hexagon. Note that the flat or granular sputtered particles such as particles 1100a and particles 1100b are collectively referred to as particles 1100. The planar shape of particle 1100 is not limited to a triangle or a hexagon. For example, it sometimes becomes a shape formed by combining two or more and six or less triangles. For example, it sometimes becomes a quadrangle (rhombus) formed by combining two triangles (equilateral triangles).

[0385] The thickness of the particle 1100 depends on the type of film-forming gas, etc. The thickness of the particle 1100 is preferably uniform, and the reason will be described later. In addition, regarding the shape of the sputtered particles, a particle shape with a small thickness is preferably used rather than a dice shape with a large thickness.

[0386] When the particle 1100 passes through the plasma, it sometimes receives an electric charge and its side is negatively or positively charged. The side of the particle 1100 has oxygen atoms, and the oxygen atoms may be negatively charged. For example, Fig.42 An example is shown in which the side of particle 1100a has negatively charged oxygen atoms. As such, when the side surfaces are charged with the same polarity, the charges repel each other, thereby maintaining a flat plate shape. In addition, when CAAC-OS is an In-Ga-Zn oxide, the oxygen atoms bonded to the indium atoms may be negatively charged. Alternatively, the oxygen atoms bonded to the indium atoms, gallium atoms, and zinc atoms may be negatively charged.

[0387] like Fig.40A As shown, for example, a particle 1100 flies like a kite in the plasma onto a substrate 1120. Since the particle 1100 is charged, a repulsive force is generated when it approaches an area where other particles 1100 have been deposited. Here, a magnetic field parallel to the top surface of the substrate 1120 is generated on the top surface of the substrate 1120. In addition, since there is a potential difference between the substrate 1120 and the target 1130, a current flows from the substrate 1120 to the target 1130. Therefore, the particle 1100 is subjected to a force (Lorentz force) caused by the magnetic field and the current on the top surface of the substrate 1120 (see Fig.43). This can be understood using Fleming's left-hand rule. In order to increase the force applied to the particle 1100, it is preferred to set a region on the top surface of the substrate 1120 where the magnetic field parallel to the top surface of the substrate 1120 is 10G or more, preferably 20G or more, more preferably 30G or more, and further preferably 50G or more. Alternatively, it is preferred to set a region on the top surface of the substrate 1120 where the magnetic field parallel to the top surface of the substrate 1120 is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more, and further preferably 5 times or more of the magnetic field perpendicular to the top surface of the substrate 1120.

[0388] In addition, since the substrate 1120 is heated, the resistance such as friction between the particles 1100 and the substrate 1120 is small. As a result, Fig.44A As shown in FIG. 1 , the particle 1100 slides down the top surface of the substrate 1120. The particle 1100 moves with the flat surface facing the substrate 1120. Then, as shown in FIG. Fig.44B As shown in FIG. 1 , when the particle 1100 reaches the side of another already deposited particle 1100, their side surfaces are bonded to each other. At this time, the oxygen atoms on the side of the particle 1100 are detached. Since the detached oxygen atoms sometimes fill the oxygen defects in the CAAC-OS, a CAAC-OS with a low defect state density is formed.

[0389] In addition, by heating the particles 1100 on the substrate 1120, the atoms are rearranged, and the strain of the structure caused by the collision of the ions 1101 is relieved. The particles 1100 whose strain is relieved are substantially single crystals. When the particles 1100 are substantially single crystals, even if the particles 1100 are heated after being bonded to each other, the particles 1100 themselves hardly expand or contract. Therefore, the gaps between the particles 1100 are not enlarged, resulting in the formation of defects such as grain boundaries and becoming cracks (crevasse). In addition, it can be considered that metal atoms with elasticity are spread in the gaps, and they connect the side surfaces of the particles 1100 that are deviated in direction like a highway.

[0390] It can be considered that according to the above model particles 1100 are deposited on the substrate 1120. Therefore, it can be known that: unlike epitaxial growth, CAAC-OS can be formed when the formed surface has no crystalline structure. For example, even if the structure of the top surface (formed surface) of the substrate 1120 is an amorphous structure, CAAC-OS can be formed.

[0391] In addition, it can be known that when CAAC-OS is formed, not only when the top surface of the substrate 1120 to be formed is a flat surface, but also when the top surface is concave-convex, the particles 1100 are arranged according to their shapes. For example, if the top surface of the substrate 1120 is flat at the atomic level, a layer with uniform thickness, flatness and high crystallinity is formed because the particles 1100 are arranged with the flat surface parallel to the ab plane facing downward. Moreover, by stacking n (n is a natural number) layers, CAAC-OS can be obtained (refer to Fig.40B ).

[0392] On the other hand, even if the top surface of the substrate 1120 is concavo-convex, CAAC-OS has a structure in which n (n is a natural number) particles 1100 are stacked in layers arranged in parallel along the convex surface. Since the substrate 1120 is concavo-convex, gaps between the particles 1100 are sometimes easily generated in CAAC-OS. However, since intermolecular forces are generated between the particles 1100, the particles are arranged in such a way that the gaps between the particles are as small as possible even on the concavo-convex surface. As a result, a CAAC-OS with high crystallinity can be formed even if the film-forming surface is concavo-convex (see Fig.40C ).

[0393] Therefore, CAAC-OS does not require laser crystallization and can be uniformly formed on a large-area glass substrate or the like.

[0394] Since CAAC-OS is formed according to this model, the sputtered particles are preferably in a granular form with a small thickness. In addition, if the sputtered particles are in a thick granular form, the surface facing the substrate 1120 is not fixed, so that a uniform thickness or crystal orientation may not be obtained.

[0395] According to the above film formation model, a CAAC-OS having high crystallinity can be formed even on a surface having an amorphous structure.

[0396] In addition, CAAC-OS can also be described using a film formation model having zinc oxide particles in addition to the particles 1100 .

[0397] The mass of the zinc oxide particles is smaller than that of the particles 1100, so they reach the substrate 1120 earlier than the particles 1100. On the top surface of the substrate 1120, the zinc oxide particles preferentially grow crystals in the horizontal direction to form a thin zinc oxide layer. The zinc oxide layer has a c-axis orientation. The c-axis of the crystal of the zinc oxide layer is oriented in a direction parallel to the normal vector of the substrate 1120. The zinc oxide layer has the function of a seed layer for the growth of CAAC-OS, and therefore has the function of improving the crystallinity of CAAC-OS. In addition, the thickness of the zinc oxide layer is greater than 0.1 nm and less than 5 nm, and is mostly greater than 1 nm and less than 3 nm. The thickness of the zinc oxide layer is thin enough, so that almost no grain boundaries are observed.

[0398] Therefore, in order to form a CAAC-OS having high crystallinity, it is preferable to use a target containing zinc at a higher ratio than the stoichiometric composition.

[0399] Likewise, nc-OS can utilize Fig.41 The film formation model shown is understood. Note that Fig.41 and Fig.40A The only difference is whether the substrate 1120 is heated.

[0400] Therefore, the substrate 1120 is not heated, and thus resistance such as friction between the particle 1100 and the substrate 1120 is large. As a result, the particle 1100 cannot slide down on the top surface of the substrate 1120, and thus falls irregularly on the top surface of the substrate 1120 to form nc-OS.

[0401] <Cleavage plane>

[0402] Next, the cleavage plane of the target material described in the film formation model of CAAC-OS will be described.

[0403] First, refer to Fig.45A and 45B The cleavage plane of the target material is described. Fig.45A and 45B InGaZnO 4 In addition, Fig.45A The c-axis is oriented upward and InGaZnO is observed from a direction parallel to the b-axis. 4 In addition, Fig.45B InGaZnO is observed from the direction parallel to the c-axis 4 The structure of the crystallization.

[0404] InGaZnO was calculated by first principle calculation 4The energy required for cleavage of each crystal plane of the crystal. Note that for the calculation, a density functional program (CASTEP) using pseudopotential and plane wave basis was used. Note that an ultrasoft pseudopotential was used as a pseudopotential. In addition, GGA / PBE was used as a functional. In addition, the cutoff energy was set to 400 eV.

[0405] After optimizing the structure including the cell size, the energy of the structure in the initial state is derived. In addition, optimizing the structure of the atomic arrangement with the cell size fixed is performed, and then the energy of the structure after cleavage on each surface is derived.

[0406] according to Fig.45A and 45B InGaZnO shown 4 The first surface is a crystal plane between the Ga-Zn-O layer and the In-O layer, and is a crystal plane parallel to the (001) plane (or ab plane) (refer to Fig.45A The second plane is the crystal plane between the Ga-Zn-O layer and the Ga-Zn-O layer, and is parallel to the (001) plane (or ab plane) (refer to Fig.45A The third plane is a crystal plane parallel to the (110) plane (refer to Fig.45B The fourth plane is a crystal plane parallel to the (100) plane (or bc plane) (refer to Fig.45B ).

[0407] The energy of the structure after cleavage on each surface is calculated under the above conditions. Next, the cleavage energy, which is an index of the ease of cleavage of each surface, is calculated by dividing the difference between the energy of the structure after cleavage and the energy of the structure in the initial state by the area of ​​the cleavage surface. Note that the energy of the structure is calculated based on the atoms and electrons included in the structure, that is, in the calculation, the kinetic energy of the electrons and the interactions between atoms, between atoms and electrons, and between electrons are taken into account.

[0408] From the calculation results, we can see that the cleavage energy of the first surface is 2.60J / m 2 The cleavage energy of the second surface is 0.68 J / m 2 , the cleavage energy of the third surface is 2.18 J / m 2 , the cleavage energy of the fourth surface is 2.12 J / m 2 (See Table 1).

[0409] [Table 1]

[0410] <![CDATA[Cleavage energy [J / m 2 > First side 2.60 Side 2 0.68 Third side 2.18 Side 4 2.12

[0411] From the above calculations, we can see that Fig.45Aand 45B InGaZnO shown 4 The cleavage energy of the second surface is the lowest in the crystal structure. In other words, it can be seen that the surface between the Ga-Zn-O layer and the Ga-Zn-O layer is the easiest to cleave (cleavage surface). Therefore, in this specification, the cleavage surface refers to the second surface that is easiest to cleave.

[0412] Because the second surface between the Ga-Zn-O layer and the Ga-Zn-O layer is a cleavage surface, Fig.45A InGaZnO shown 4 The crystal can be separated on two planes equal to the second plane. Therefore, it can be considered that when ions etc. collide with the target, the wafer-shaped unit (called a particle) cleaved on the plane with the lowest cleavage energy will fly out as the smallest unit. In this case, InGaZnO 4 The particle includes three layers of a Ga—Zn—O layer, an In—O layer and a Ga—Zn—O layer.

[0413] In addition, since the cleavage energy of the third plane (the crystal plane parallel to the (110) plane) and the fourth plane (the crystal plane parallel to the (100) plane (or bc plane)) is lower than the cleavage energy of the first plane (the crystal plane between the Ga-Zn-O layer and the In-O layer parallel to the (001) plane (or ab plane)), it can be seen that in many cases the planar shape of the particles is triangular or hexagonal.

[0414] Next, using classical molecular dynamics calculations, we assumed that InGaZnO with a homologous structure was used as the target. 4 Figure 46A shows the crystallization of InGaZnO used for calculation and the cleavage surface when the target is sputtered using argon (Ar) or oxygen (O). 4 The cross-sectional structure of the crystal (2688 atoms) Fig.46B The top view structure is shown. In addition, the fixed layer shown in FIG46A is a layer in which the atomic arrangement is fixed so that the position does not change. In addition, the temperature control layer shown in FIG46A is a layer that always maintains a constant temperature (300K).

[0415] Classical molecular dynamics calculations were performed using Materials Explorer 5.0 manufactured by Fujitsu Limited. In addition, the initial temperature was set to 300 K, the cell size was set to a constant, the time step was set to 0.01 femtoseconds, and the number of steps was set to 10 million times. In the calculation, an energy of 300 eV was applied to the atoms according to this condition, and the atoms were moved from a vertical direction to the InGaZnO 4 The direction of the ab plane of the crystal is incident on the unit.

[0416] FIG. 47A shows argon incident on the InGaZnO having the structure shown in FIGS. 46A and 46B. 4 The atomic arrangement of the crystal unit cell after 99.9 picoseconds (psec). Fig.47B The atomic arrangement after oxygen is injected into the cell for 99.9 picoseconds is shown. In addition, in FIGS. 47A and 47B , a part of the pinned layer shown in FIG. 46A is omitted and shown.

[0417] As shown in FIG. 47A, from the time when argon is incident into the cell to 99.9 picoseconds, the time corresponding to Fig.45A The cleavage plane of the second surface shown in the figure has cracks. Therefore, it can be known that when argon collides with InGaZnO 4 During crystallization, the topmost surface is the second surface (0th second surface), and large cracks are generated in the second surface (2nd second surface).

[0418] On the other hand, by Fig.47B It can be seen that from the time when oxygen is incident into the cell to 99.9 picoseconds, the time corresponding to Fig.45A The cleavage plane of the second surface shown has cracks. Note that it can be seen that when oxygen impinges on the cell, the InGaZnO 4 A large crack is generated in the second surface (first second surface) of the crystal.

[0419] It can be seen that in the case of atoms (ions) from InGaZnO with homologous structures 4 When the top surface of the crystallized target collides with the InGaZnO 4 The crystals are cleaved along the second surface and the flat particles (grains) are peeled off. In addition, it can be known that the particle size when oxygen is collided with the unit is smaller than the particle size when argon is collided with the unit.

[0420] In addition, it is known from the above calculation that the peeled grain includes a damaged region. The damaged region included in the grain can sometimes be repaired by reacting defects generated by the damage with oxygen.

[0421] Therefore, the fact that the particle size differs depending on the type of colliding atoms was investigated.

[0422] FIG. 48A shows a graph of a flow from argon incident on an InGaZnO electrode having a shape shown in FIGS. 46A and 46B. 4 The trajectory of each atom in the unit cell of the crystal from 0 picoseconds to 0.3 picoseconds. Therefore, Figure 48A corresponds to the period from Figures 46A and 46B to Figure 47A.

[0423] As can be seen from FIG. 48A, when argon collides with gallium (Ga) in the first layer (Ga-Zn-O layer), the gallium collides with zinc (Zn) in the third layer (Ga-Zn-O layer), and then the zinc reaches the vicinity of the sixth layer (Ga-Zn-O layer). In addition, oxygen colliding with gallium is ejected to the outside. Therefore, it can be considered that when argon collides with the InGaZnO 4 When the target material is a crystallized material, cracks are generated on the second surface (2nd second surface) in Figure 46A.

[0424] Fig.48B 46A and 46B show the incident oxygen into the InGaZnO 4 The trajectory of each atom in a crystal unit cell ranges from 0 picoseconds to 0.3 picoseconds. Fig.48B Corresponding to the period from Figures 46A and 46B to Figure 47A.

[0425] On the other hand, by Fig.48B It can be seen that when oxygen collides with gallium (Ga) in the first layer (Ga-Zn-O layer), zinc (Zn) does not reach the fifth layer (In-O layer) after the gallium collides with zinc (Zn) in the third layer (Ga-Zn-O layer). In addition, the oxygen colliding with gallium is ejected to the outside. Therefore, it can be considered that when oxygen collides with the InGaZnO 4 When the target material is a crystallized material, cracks are generated on the second surface (1st second surface) in Figure 46A.

[0426] This calculation also shows that when atoms (ions) collide, InGaZnO 4 The crystals peel off from the cleavage plane.

[0427] In addition, the depth of the crack is discussed from the perspective of conservation laws. The energy conservation law and momentum conservation law can be expressed by equations (1) and (2). Here, E is the energy of argon or oxygen before the collision (300 eV), m A is the mass of argon or oxygen, v A is the velocity of argon or oxygen before the collision, v′ A is the velocity of the argon or oxygen after the collision, m Ga is the mass of gallium, v Ga is the velocity of gallium before the collision, v′ Ga is the velocity of gallium after the collision.

[0428]

[0429]

[0430] When the collision of argon or oxygen is assumed to be an elastic collision, v can be expressed by formula (3): A , v′ A 、v Gaand v′ Ga relationship.

[0431]

[0432] According to formula (1), formula (2) and formula (3), in v Ga When it is 0, the velocity v′ of gallium after collision with argon or oxygen can be expressed by formula (4): Ga .

[0433]

[0434] In formula (4), substitute the mass of argon or oxygen into m A The speed of gallium after each atomic collision is compared. When the energy before the collision of argon and oxygen is the same, the speed of gallium during the collision of argon is 1.24 times that of gallium during the collision of oxygen. Therefore, the energy of gallium during the collision of argon is also higher than that of gallium during the collision of oxygen by the square of the speed of gallium.

[0435] It is known that the speed (energy) of gallium after collision when argon collides is higher than that when oxygen collides. Therefore, it is considered that cracks are generated at a deeper position when argon collides than when oxygen collides.

[0436] From the above calculation, it can be seen that by sputtering InGaZnO with a homologous structure 4 The target material of the crystallization is peeled off from the cleavage plane to form particles. On the other hand, even if the target material without cleavage plane is sputtered, no particles are formed, but sputtered particles with atomic size finer than the particles are formed. Since the sputtered particles are smaller than the particles, it is considered that they are discharged by the vacuum pump connected to the sputtering device. Therefore, in the case of sputtering including InGaZnO having a homologous structure 4 When using a target material for crystallization, it is difficult to consider the model in which particles of various sizes or shapes fly to the substrate and deposit to form a film. Fig.40A The model shown in the above makes more sense.

[0437] The density of the CAAC-OS formed by the above steps is approximately the same as that of the single-crystalline OS. 4 The density of the homologous single crystal OS is 6.36 g / cm 3 , while the density of CAAC-OS with approximately the same atomic ratio is 6.3 g / cm 3 about.

[0438] Fig.49A and 49B In-Ga-Zn oxide of CAAC-OS formed by sputtering is shown (refer to Fig.49A ) and its target (refer to Fig.49B ) cross-section. The atomic arrangement was observed using High-Angle Annular Dark Field Scanning Transmission Electron Microscopy (HAADF-STEM). Note that in HAADF-STEM, the intensity of the image of each atom is proportional to the square of the atomic number. Therefore, Zn (atomic number 30) and Ga (atomic number 31) with similar atomic numbers are almost indistinguishable. For HAADF-STEM, a Hitachi scanning transmission electron microscope HD-2700 was used.

[0439] In the right Fig.49A and 49B When compared, it can be seen that both CAAC-OS and the target have homologous structures, and the configuration of atoms in CAAC-OS corresponds to that of the target. Fig.40A As shown in the film formation model of FIG. 1 , the crystal structure of the target is transferred to form CAAC-OS.

[0440] The structure and method described in this embodiment can be used in combination with the structure and method described in other embodiment as appropriate.

[0441] Implementation 3

[0442] In this embodiment, oxygen vacancies in an oxide semiconductor film are described in detail below.

[0443] 〈(1) V O H formation and stability

[0444] When the oxide semiconductor film (hereinafter referred to as IGZO) is a complete crystal, H diffuses preferentially along the ab plane at room temperature. When the film is heated at 450°C, H diffuses in the ab plane and in the c-axis direction. This indicates that when there is an oxygen vacancy V in IGZO, O Is it easy for H to enter the oxygen-deficient V O Here, the oxygen deficiency V O The state in which H exists is called V O H.

[0445] In the calculation, use Fig. 20 InGaZnO shown 4 Here, the Nudged Elastic Band (NEB) method is used to analyze the crystallization model of V O The H in H is from V O The activation energy of the reaction path for releasing the oxygen bond (E a) is calculated. Table 2 shows the calculation conditions.

[0446] [Table 2]

[0447] software VASP Calculation method NEB method Functional GGA-PBE Pseudopotential PAW Cut-off energy 500eV K-point 2×2×3

[0448] InGaZnO 4 In the crystallization model, Fig. 20 As shown, there are oxygen positions 1 to 4 with different numbers of metal elements bonded to oxygen. O The oxygen position 1 and oxygen position 2 are calculated.

[0449] First, as V is prone to form oxygen deficiency O The oxygen position 1 of is calculated for the oxygen position bonded to three In atoms and one Zn atom.

[0450] Fig.21A The model shows the initial state, Fig. 21B A model showing the final state. In addition, Fig. 22 The activation energy (E) of the initial state and the final state is shown. a ). Note that the “initial state” here refers to the state in which the oxygen deficiency V O The state where H exists (V O H), and the "final state" refers to the following structure: with oxygen deficiency V O And the state in which oxygen bonded to one Ga atom and two Zn atoms is bonded to H (HO).

[0451] From the calculation results, we can see that when the oxygen deficiency V O When the H in the oxygen atom bonds with other O atoms, it requires an energy of about 1.52 eV. O An energy of about 0.46 eV is required.

[0452] Here, according to the activation energy (E a ) and equation 5 to calculate the response frequency (Γ). In equation 5, k B represents the Boltzmann constant, and T represents the absolute temperature.

[0453] [Formula 5]

[0454]

[0455] Assume frequency factor v=10 13 [1 / sec], calculate the reaction frequency at 350℃. Fig.21A The position in the model shown is moved to Fig. 21B The frequency of the position in the model shown is 5.52×10 0[1 / sec]. In addition, H Fig. 21B The position in the model shown is moved to Fig.21A The frequency of the positions in the model shown is 1.82×10 9 [1 / sec]. It can be seen from this that the H diffused in IGZO has oxygen vacancies V near it. O V O H, once V is formed O H is not easy to be damaged by oxygen deficiency O Release H.

[0456] Next, as a V that is easy to form oxygen vacancies O The oxygen positions 2 of are calculated for the oxygen positions bonded to one Ga atom and two Zn atoms.

[0457] Fig.23A The model shows the initial state, Fig. 23B A model showing the final state. In addition, Fig.24 The activation energy (E) of the initial state and the final state is shown. a ). Note that the “initial state” here refers to the state in which the oxygen deficiency V O The state where H exists (V O H), and the "final state" refers to the following structure: with oxygen deficiency V O And the state in which oxygen bonded to one Ga atom and two Zn atoms is bonded to H (HO).

[0458] From the calculation results, we can see that when the oxygen deficiency V O When the H in the oxygen atom bonds with other O atoms, it requires an energy of about 1.75 eV. O An energy of about 0.35 eV is required.

[0459] According to the activation energy (E a ) and the above formula 5 to calculate the response frequency (Γ).

[0460] Assume frequency factor v=10 13 [1 / sec], calculate the reaction frequency at 350℃. Fig.23A The position in the model shown is moved to Fig. 23B The local frequency in the model shown is 7.53×10 -2 [1 / sec]. In addition, H Fig. 23B The position in the model shown is moved to Fig.23A The frequency of the positions in the model shown is 1.44×10 10 [1 / sec]. It can be seen that once V is formed O H is not easy to be damaged by oxygen deficiency O Release H.

[0461] From the above results, it can be seen that when annealing is performed, H in IGZO is easy to diffuse. O When H easily enters the oxygen deficiency V O And become V O H.

[0462] 〈(2) V O H migration level

[0463] When there is an oxygen deficiency in IGZO, V O When H, according to 〈(1)V O The calculation using the NEB method shown in the figure shows that the oxygen deficiency V O It is easy to form V with H O H, and V O H is stable. So, in order to investigate V O Is H related to carrier traps? Calculate V O The migration level of H.

[0464] In the calculation, InGaZnO 4 Here, the crystal model of Fig. 20 V at oxygen position 1 and oxygen position 2 shown O The migration energy level was calculated based on the model of H. Table 3 shows the calculation conditions.

[0465] [Table 3]

[0466] software VASP Model <![CDATA[InGaZnO 4 Crystalline model of (112 atoms)]]> Functional HSE06 Mixing ratio of exchange terms 0.25 Pseudopotential GGA-PBE Cut-off energy 800eV K-point 1×1×1

[0467] The mixing ratio of the exchange term is adjusted in such a way that an energy gap close to the experimental value is formed, and defect-free InGaZnO 4 The energy gap of the crystalline model becomes 3.08 eV, which is close to the experimental value of 3.15 eV.

[0468] The transition energy level (ε(q / q')) of the model with defect D is calculated according to the following formula 6. In addition, ΔE(D q ) is the formation energy of the charge q of defect D, and this energy is calculated according to the following formula 7.

[0469] [Formula 6]

[0470]

[0471] [Formula 7]

[0472]

[0473] In equations 6 and 7, E tot (Dq ) represents the total energy of the charge q of the model containing the defect D, E tot (bulk) represents the total energy of the model without defects (complete crystallization), Δn i represents the increase or decrease of the number of atoms i caused by defects, μ i represents the chemical potential of atom i, ε VBM represents the energy of the valence band top in the model without defects, ΔV q represents the correction term related to the electrostatic potential, E f represents the Fermi energy.

[0474] Fig.25 The V calculated according to the above formula is shown O The migration level of H. Fig.25 The value in represents the depth from the bottom of the conduction band. Fig.25 It can be seen that V at oxygen position 1 O The H migration level exists at 0.05 eV below the conduction band. O The migration energy level of H exists at 0.11 eV below the conduction band. O H is related to electron traps. That is, it is known that V O H is used as a donor. It can also be seen that V O H-IGZO has electrical conductivity.

[0475] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0476] Implementation 4

[0477] In this embodiment, using Figure 26 to Figure 28 An example of a display device using the transistor and the capacitor described as examples in the above embodiments will be described.

[0478] Fig.26 is a plan view showing an example of a display device. Fig.26 The display device 700 shown includes: a pixel portion 702 arranged on a first substrate 701; a source driver circuit portion 704 and a gate driver circuit portion 706 arranged on the first substrate 701; a sealant 712 arranged in a manner surrounding the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706; and a second substrate 705 arranged in a manner opposite to the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealant 712. In other words, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Note that although in Fig.26Although not shown in the figure, a display element is provided between the first substrate 701 and the second substrate 705.

[0479] In addition, in the display device 700, an FPC (Flexible printed circuit) terminal portion 708 electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 is provided in a region on the first substrate 701 that is not surrounded by the sealant 712. In addition, the FPC terminal portion 708 is connected to the FPC 716, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. In addition, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 are each connected to a signal line 710. Various signals supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.

[0480] In addition, a plurality of gate drive circuit units 706 may be provided in the display device 700. In addition, as the display device 700, although an example is shown in which the source drive circuit unit 704 and the gate drive circuit unit 706 are formed on the same first substrate 701 as the pixel unit 702, it is not limited to this structure. For example, only the gate drive circuit unit 706 may be formed on the first substrate 701, or only the source drive circuit unit 704 may be formed on the first substrate 701. In this case, a structure in which a substrate having a source drive circuit or a gate drive circuit formed thereon (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted on the first substrate 701 may also be adopted. In addition, there is no particular limitation on the connection method of the separately formed drive circuit substrate, and a COG (Chip On Glass) method, a wire bonding method, or the like may be adopted.

[0481] In addition, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors, and the transistors of the semiconductor device of one embodiment of the present invention can be applied as the transistors. In addition, in the pixel portion 702, the transistors and capacitors of the semiconductor device of one embodiment of the present invention can be applied.

[0482] In addition, the display device 700 may include various elements. The element includes, for example, at least one of a liquid crystal element, an EL (electroluminescent) element (EL element including organic and inorganic materials, an organic EL element or an inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc.), a transistor (a transistor that emits light according to current), an electron emission element, an electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display (PDP), a display element using a micro-electromechanical system (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), a MIRASOL (registered trademark), an IMOD (interference measurement adjustment) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, or a display element of a carbon nanotube. In addition, it may also have a display medium that changes by changing contrast, brightness, reflectivity, transmittance, etc. through electrical or magnetic action. As an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron emission element, there are field emission displays (FED) or SED flat-panel displays (SED: Surface-conduction Electron-emitter Display: surface conduction electron emission display), etc. As an example of a display device using a liquid crystal element, there are liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), etc. As an example of a display device using electronic ink or electrophoretic elements, there are electronic paper, etc. Note that when a semi-transmissive liquid crystal display or a reflective liquid crystal display is implemented, part or all of the pixel electrode can have the function of a reflective electrode. For example, part or all of the pixel electrode can contain aluminum, silver, etc. In addition, at this time, a storage circuit such as SRAM can also be set under the reflective electrode. In this way, power consumption can be further reduced.

[0483] As a display mode of the display device 700, a progressive scanning mode or an interlaced scanning mode can be adopted. In addition, the color element controlled in the pixel when performing color display is not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it can be composed of four pixels of R pixel, G pixel, B pixel and W (white) pixel. Alternatively, as in the PenTile arrangement, a color element can be composed of two colors in RGB, and two different colors can be selected according to the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. can be added to RGB. In addition, the size of the display area of ​​the point of each color element can be different. However, the disclosed invention is not limited to a display device for color display, but can also be applied to a display device for black and white display.

[0484] In addition, in order to use white light (W) for a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) to enable the display device to display in full color, a coloring layer (also called a filter) can also be used. As a coloring layer, for example, red (R), green (G), blue (B), yellow (Y), etc. can be used in appropriate combinations. By using a coloring layer, the color reproducibility can be further improved compared to the case where a coloring layer is not used. At this time, it is also possible to directly use white light in an area that does not include a coloring layer by setting an area that includes a coloring layer and an area that does not include a coloring layer for display. By partially setting an area that does not include a coloring layer, when displaying a bright image, the brightness reduction caused by the coloring layer can sometimes be reduced and the power consumption can be reduced by about 20% to 30%. However, when using self-luminous elements such as organic EL elements or inorganic EL elements for full-color display, R, G, B, Y, and W can also be emitted from elements having each luminous color. By using a self-luminous element, power consumption can sometimes be further reduced compared to the case where a coloring layer is used.

[0485] In this embodiment, using Fig. 27 and Fig.28 A structure using a liquid crystal element and an EL element as a display element will be described. Fig. 27 It is along Fig.26 The cross-sectional view along the dot-dash line QR shown in FIG. 1 is a structure in which a liquid crystal element is used as a display element. Fig.28 It is along Fig.26 The cross-sectional view taken along the dashed line QR shown in the figure has a structure in which an EL element is used as a display element.

[0486] Below, first explain Fig. 27 and Fig.28 The common parts are shown, and then the different parts are described.

[0487] 〈Description of Common Parts of Display Devices〉

[0488] Fig. 27 and Fig.28 The display device 700 shown includes: a routing wiring section 711; a pixel section 702; a source driver circuit section 704; and an FPC terminal section 708. In addition, the routing wiring section 711 includes a signal line 710. In addition, the pixel section 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit section 704 includes a transistor 752.

[0489] The transistor 750 and the transistor 752 have the same structure as the transistor 100A described above. The transistor 750 and the transistor 752 may also have a structure using other transistors described in the previous embodiment.

[0490] The transistor used in this embodiment includes a highly purified oxide semiconductor film in which the formation of oxygen defects is suppressed. The transistor can reduce the current value in the off state (off-state current value). Therefore, the retention time of electrical signals such as image signals can be extended, and the writing interval can also be extended in the state where the power is turned on. Therefore, the frequency of refresh operation can be reduced, thereby achieving the effect of suppressing power consumption.

[0491] In addition, the transistor used in this embodiment can obtain a higher field effect mobility and can therefore be driven at high speed. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor in a pixel portion and a driving transistor for a driving circuit portion can be formed on the same substrate. In other words, since a semiconductor device formed of a silicon wafer or the like does not need to be used separately as a driving circuit, the number of components of the semiconductor device can be reduced. In addition, a high-quality image can also be provided in the pixel portion by using a transistor capable of high-speed driving.

[0492] Capacitor element 790 has the same structure as that of capacitor element 150A described above.

[0493] In addition, Fig. 27 and Fig.28 In the embodiment, an insulating film 766 and a planarizing insulating film 770 are provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0494] The insulating film 766 can be formed using the same material and manufacturing method as the insulating film 128 described in the previous embodiment. In addition, as the planarization insulating film 770, a heat-resistant organic material such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, epoxy resin, etc. can be used. The planarization insulating film 770 can also be formed by stacking a plurality of insulating films formed of these materials. In addition, a structure without the planarization insulating film 770 can also be used.

[0495] The signal line 710 is formed in the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. The signal line 710 may also use a conductive film used as the gate electrode of the transistors 750 and 752, such as a conductive film used as the first gate electrode or a conductive film used as the second gate electrode. For example, when a material containing copper is used as the signal line 710, signal delay due to wiring resistance is reduced, and a large screen display can be achieved.

[0496] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed in the same process as the conductive film used as the source electrode and the drain electrode of the transistors 750 and 752. The connection electrode 760 and the terminal included in the FPC 716 are electrically connected through the anisotropic conductive film 780.

[0497] Note that, for example, a glass substrate can be used as the first substrate 701 and the second substrate 705. Note that a flexible substrate can be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.

[0498] In addition, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer obtained by selectively etching an insulating film and is used to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Alternatively, a spherical spacer may be used as the structure 778.

[0499] In addition, on the second substrate 705 side, a light-shielding film 738 serving as a black matrix, a coloring film 736 serving as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the coloring film 736 are provided.

[0500] <Structural Example of Display Device Using Liquid Crystal Element as Display Element>

[0501] Fig. 27 The display device 700 shown includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and has a function of a counter electrode. Fig. 27 The display device 700 shown can change the alignment state of the liquid crystal layer 776 by applying a voltage to the conductive film 772 and the conductive film 774, thereby controlling the transmission and non-transmission of light to display an image.

[0502] The conductive film 772 is connected to a conductive film serving as a source electrode and a drain electrode included in the transistor 750. The conductive film 772 serves as a pixel electrode, that is, one electrode of a display element, formed over the planarizing insulating film 770. The conductive film 772 also functions as a reflective electrode. Fig. 27 The display device 700 shown is a so-called reflective color liquid crystal display device that reflects external light from the conductive film 772 and transmits it through the color film 736 to perform display.

[0503] As the conductive film 772, a conductive film that is translucent to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is translucent to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. As the conductive film that is reflective to visible light, for example, a material containing aluminum or silver is preferably used. In this embodiment, a conductive film that is reflective to visible light is used as the conductive film 772.

[0504] In addition, Fig. 27 In the display device 700 shown, a portion of the planarization insulating film 770 of the pixel portion 702 is provided with concavoconvexity. The concavoconvexity can be formed, for example, by forming the planarization insulating film 770 using an organic resin film or the like and providing a concave portion or a convex portion on the surface of the organic resin film. In addition, a conductive film 772 serving as a reflective electrode is formed along the above-mentioned concavoconvexity. Therefore, when external light is incident on the conductive film 772, the light can be diffusely reflected on the surface of the conductive film 772, and visibility can be improved.

[0505] Note that although as Fig. 27 The display device 700 shown in the figure exemplifies a reflective color liquid crystal display device, but is not limited thereto. For example, a conductive film having light-transmitting properties for visible light may be used for the conductive film 772 to manufacture a transmissive color liquid crystal display device. When the display device is a transmissive color liquid crystal display device, a structure in which the concavoconvexity in the planarization insulating film 770 is not provided may be adopted.

[0506] Note that although Fig. 27 Although not shown in the figure, an alignment film may be provided on the side of each of the conductive films 772 and 774 that contacts the liquid crystal layer 776. Fig. 27 Although not shown in the figure, optical components (optical substrates) such as polarization components, phase difference components, and anti-reflection components may be appropriately provided. For example, circular polarization using a polarization substrate and a phase difference substrate may also be used. In addition, backlight, side light, etc. may also be used as a light source.

[0507] When a liquid crystal element is used as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc. depending on the conditions.

[0508] In addition, when the lateral electric field method is adopted, a liquid crystal presenting a blue phase that does not require an alignment film can also be used. The blue phase is a type of liquid crystal phase, and when the temperature of the cholesteric liquid crystal is raised, it appears just before the transition from the cholesteric phase to the isotropic phase. Since the blue phase only appears in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of more than a few wt.% is used in the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing a liquid crystal presenting a blue phase and a chiral agent has a fast response speed. In addition, the liquid crystal presenting a blue phase and the liquid crystal composition of the chiral agent have optical isotropy, so no alignment treatment is required and the viewing angle dependence is small. In addition, since there is no need to set an alignment film and no friction treatment is required, electrostatic damage caused by the friction treatment can be prevented, thereby reducing the defects and damage of the liquid crystal display device in the manufacturing process.

[0509] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, or the like can be used.

[0510] In addition, a normally black liquid crystal display device may also be used, such as a transmissive liquid crystal display device using a vertical alignment (VA) mode. As vertical alignment modes, several examples may be cited, such as an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, and the like.

[0511] <Display device using a light-emitting element as a display element>

[0512] Fig.28 The display device 700 shown includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. Fig.28 In the display device 700 shown in the figure, an image can be displayed by causing the EL layer 786 included in the light-emitting element 782 to emit light.

[0513] In addition, the conductive film 784 is connected to a conductive film used as a source electrode and a drain electrode included in the transistor 750. The conductive film 784 is used as a pixel electrode formed on the planarization insulating film 770, that is, an electrode of the display element. As the conductive film 784, a conductive film that is transmissive to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is transmissive to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. As the conductive film that is reflective to visible light, for example, a material containing aluminum or silver is preferably used.

[0514] in addition, Fig.28 The display device 700 shown in the figure is provided with a planarization insulating film 770 and an insulating film 730 on the conductive film 784. The insulating film 730 covers a portion of the conductive film 784. Note that the light emitting element 782 has a top emission structure. Therefore, the conductive film 788 has light-transmitting properties and transmits light emitted by the EL layer 786. Note that although a top emission structure is illustrated in this embodiment mode, it is not limited to this. For example, a bottom emission structure that emits light to one side of the conductive film 784 or a double-sided emission structure that emits light to both the conductive film 784 and the conductive film 788 may also be applied.

[0515] In addition, a coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. The coloring film 736 and the light shielding film 738 are covered by the insulating film 734. The sealing film 732 is filled between the light emitting element 782 and the insulating film 734. Note that although Fig.28 The display device 700 shown in the figure illustrates a structure in which the coloring film 736 is provided, but the present invention is not limited to this. For example, when the EL layer 786 is formed by separate coating, a structure in which the coloring film 736 is not provided may be adopted.

[0516] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0517] Implementation method 5

[0518] In this embodiment, one embodiment of a light-emitting device using a semiconductor device of one embodiment of the present invention is described. Note that in this embodiment, Fig.29A and 29B The structure of a pixel portion of a light-emitting device will be described.

[0519] exist Fig.29A In the embodiment, a plurality of FETs 500 are formed on a first substrate 502, and each FET 500 is electrically connected to each light-emitting element (504R, 504G, 504B, 504W). Specifically, each FET 500 is electrically connected to a first conductive film 506 included in the light-emitting element. Note that each light-emitting element (504R, 504G, 504B, 504W) is composed of a first conductive film 506, a second conductive film 507, an EL layer 510, and a third conductive film 512.

[0520] In addition, coloring layers (514R, 514G, 514B, 514W) are provided at positions opposite to the light-emitting elements (504R, 504G, 504B, 504W). Note that the coloring layers (514R, 514G, 514B, 514W) are provided in contact with the second substrate 516. In addition, a sealing film 518 is provided between the first substrate 502 and the second substrate 516. As the sealing film 518, for example, a glass material such as glass frit or a curable resin such as a two-liquid mixed resin that cures at room temperature, a light-curable resin, a thermosetting resin, or other resin material can be used.

[0521] In addition, a partition wall 508 is provided in a manner covering the ends of the adjacent first conductive film 506 and the second conductive film 507. In addition, a structure 509 is formed on the partition wall 508. Note that the first conductive film 506 has the function of a reflective electrode and the function of an anode of a light-emitting element. In addition, the second conductive film 507 has the function of adjusting the optical path length of each light-emitting element. In addition, an EL layer 510 is formed on the second conductive film 507, and a third conductive film 512 is formed on the EL layer 510. In addition, the third conductive film 512 has the function of a semi-transmissive and semi-reflective electrode and the function of a cathode of a light-emitting element. In addition, the structure 509 is provided between the light-emitting element and the coloring layer and has the function of a spacer.

[0522] In addition, the EL layer 510 can be used in common by each light-emitting element (504R, 504G, 504B, 504W). Note that each light-emitting element (504R, 504G, 504B, 504W) has a so-called optical micro-resonant cavity (also called a micro-cavity) structure in which the light emitted from the EL layer 510 is resonated by the first conductive film 506 and the third conductive film 512, and even if the same EL layer 510 is used, the spectrum of different wavelengths can be extracted by narrowing the line width. Specifically, in each light-emitting element (504R, 504G, 504B, 504W), the thickness of the second conductive film 507 provided under the EL layer 510 is adjusted so that the spectrum obtained from the EL layer 510 becomes the desired emission spectrum, thereby obtaining light emission with high color purity. Therefore, by adopting Fig.29A The structure shown does not require a separate coating step of the EL layer, and thus can achieve high definition.

[0523] In addition, Fig.29A The light-emitting device shown includes a coloring layer (color filter). Therefore, by combining the microcavity structure and the color filter, light with higher color purity can be obtained. Specifically, the optical path length of the light-emitting element 504R is adjusted so that red light can be obtained, and the red light is emitted in the direction of the arrow via the coloring layer 514R. The optical path length of the light-emitting element 504G is adjusted so that green light can be obtained, and the green light is emitted in the direction of the arrow via the coloring layer 514G. The optical path length of the light-emitting element 504B is adjusted so that blue light can be obtained, and the blue light is emitted in the direction of the arrow via the coloring layer 514B. The optical path length of the light-emitting element 504W is adjusted so that white light can be obtained, and the white light is emitted in the direction of the arrow via the coloring layer 514W.

[0524] Note that the method of adjusting the optical path length of each light-emitting element is not limited to this. For example, the optical path length may be adjusted by adjusting the thickness of the EL layer 510 in each light-emitting element.

[0525] In addition, the coloring layer (514R, 514G, 514B) only needs to have a function of transmitting light in a specific wavelength range, and for example, a red (R) filter that transmits light in a red wavelength range, a green (G) filter that transmits light in a green wavelength range, and a blue (B) filter that transmits light in a blue wavelength range can be used. In addition, as the coloring layer 514W, for example, an acrylic resin material that does not contain a pigment can be used. As the coloring layer (514R, 514G, 514B, 514W), various materials can be used and formed by printing, inkjet, etching using photolithography, etc.

[0526] For example, a metal film having high reflectivity (a reflectivity of visible light of 40% to 100%, preferably 70% to 100%) can be used as the first conductive film 506. The first conductive film 506 can be formed using a single layer or a stack of aluminum, silver, or an alloy containing these metal materials (for example, an alloy of indium, palladium, and copper).

[0527] In addition, as the second conductive film 507, for example, a conductive metal oxide can be used. As the conductive metal oxide, indium oxide, tin oxide, zinc oxide, indium tin oxide, indium zinc oxide (Indium Zinc Oxide) or a material containing silicon oxide or tungsten oxide in these metal oxide materials can be used. By providing the second conductive film 507, it is possible to suppress the formation of an insulating film between the EL layer 510 formed later and the first conductive film 506, so it is preferred. In addition, a conductive metal oxide used as the second conductive film 507 can also be formed below the first conductive film 506.

[0528] In addition, the third conductive film 512 is formed using a reflective conductive material and a light-transmitting conductive material, and the reflectivity of visible light is preferably 20% to 80%, more preferably 40% to 70%. As the third conductive film 512, for example, silver, magnesium, or an alloy containing these metal materials is formed thin (for example, 10 nm or less), and then a conductive metal oxide that can be used for the second conductive film 507 is formed.

[0529] In the structure described above, a structure in which light is extracted from the second substrate 516 side (top emission structure) is adopted, but a structure in which light is extracted from the first substrate 501 side on which the FET 500 is formed (bottom emission structure) or a structure in which light is extracted from both the first substrate 501 side and the second substrate 516 side (double-side emission structure) may be adopted. In the case of adopting the bottom emission structure, for example, a colored layer (514R, 514G, 514B, 514W) may be formed below the first conductive film 506. Note that a light-transmitting substrate may be used as a substrate on the side on which light is emitted, and a light-transmitting substrate or a light-shielding substrate may be used as a substrate on the side on which light is not emitted.

[0530] In addition, although Fig.29A The example in the figure shows a structure in which the light emitting elements are of four colors (red (R), green (G), blue (B), and white (W)), but the present invention is not limited thereto. For example, a structure in which the light emitting elements are of three colors (red (R), green (G), and blue (B)) may also be adopted.

[0531] Here, use Fig.29B The connection relationship between each light emitting element and each FET is described in detail. Fig.29Byes Fig.29A An example of a structure of a region 520 surrounded by a dashed line is shown.

[0532] exist Fig.29B In the embodiment, an insulating film 522 serving as a planarization film is formed on the FET 500. An opening 524 is formed in the insulating film 522 to reach a conductive film serving as a source electrode or a drain electrode of the FET 500. A first conductive film 506 connected to the conductive film serving as a source electrode or a drain electrode of the FET 500 is formed on the insulating film 522. A second conductive film 507 is formed on the first conductive film 506.

[0533] The FET 500 has the same structure as the transistor 100A described in the previous embodiment, and thus the description of the FET 500 is omitted here.

[0534] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0535] Implementation 6

[0536] In this embodiment, a structural example of a display device according to one embodiment of the present invention is described.

[0537] <Configuration example of display device>

[0538] Fig.31A A top view of a display device according to one embodiment of the present invention is shown. Fig.31B A pixel circuit is shown when a liquid crystal element is used for a pixel of a display device according to one embodiment of the present invention. Fig.31C A pixel circuit is shown in which an organic EL element is used for a pixel of a display device according to one embodiment of the present invention.

[0539] The transistor used for the pixel can use the above transistor. Here, an example of using an n-channel transistor is shown. Note that a transistor manufactured by the same process as the transistor used for the pixel can also be used as a drive circuit. In addition, the above capacitor element can be used as a capacitor element for the pixel. In this way, by using the above transistor and capacitor element for a pixel or a drive circuit, a display device with high display quality and / or reliability can be manufactured.

[0540] Fig.31AAn example of a top view of an active matrix display device is shown. A pixel portion 5001, a first scan line driving circuit 5002, a second scan line driving circuit 5003, and a signal line driving circuit 5004 are provided on a substrate 5000 of the display device. The pixel portion 5001 is electrically connected to the signal line driving circuit 5004 through a plurality of signal lines and is electrically connected to the first scan line driving circuit 5002 and the second scan line driving circuit 5003 through a plurality of scan lines. In addition, pixels including display elements are respectively provided in the regions divided by the scan lines and the signal lines. In addition, the substrate 5000 of the display device is electrically connected to a timing control circuit (also referred to as a controller, control IC) through a connection portion such as an FPC (flexible printed circuit).

[0541] The first scan line driver circuit 5002, the second scan line driver circuit 5003, and the signal line driver circuit 5004 are formed on the substrate 5000 in the same manner as the pixel portion 5001. Therefore, the cost of manufacturing the display device can be reduced compared to the case where the driver circuit is manufactured separately. In addition, when the driver circuit is manufactured separately, the number of connections between the wirings increases. Therefore, by providing the driver circuit on the same substrate 5000, the number of connections between the wirings can be reduced, thereby improving reliability and / or yield.

[0542] <(1) Liquid crystal display device>

[0543] also, Fig.31B An example of a circuit structure of a pixel is shown. Here, a pixel circuit that can be applied to a pixel of a VA type liquid crystal display device and the like is shown.

[0544] This pixel circuit can be applied to a structure in which one pixel includes multiple pixel electrodes. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. Thus, the signal applied to each pixel electrode of a multi-domain designed pixel can be independently controlled.

[0545] The gate wiring 5012 of the transistor 5016 and the gate wiring 5013 of the transistor 5017 are separated to supply different gate signals to them. On the other hand, the transistor 5016 and the transistor 5017 share a source electrode or a drain electrode 5014 used as a data line. The transistor 5016 and the transistor 5017 use the above-mentioned transistors appropriately. In addition, the above-mentioned capacitor element can be appropriately used as the capacitor elements 5023a and 5023b. Thus, a liquid crystal display device with high display quality and / or reliability can be provided.

[0546] The transistor 5016 is electrically connected to the first pixel electrode, and the transistor 5017 is electrically connected to the second pixel electrode. The first pixel electrode and the second pixel electrode are separated from each other. The shapes of the first pixel electrode and the second pixel electrode are not limited thereto, and may be, for example, V-shaped.

[0547] A gate electrode of the transistor 5016 is electrically connected to the gate wiring 5012, and a gate electrode of the transistor 5017 is electrically connected to the gate wiring 5013. Different gate signals are supplied to the gate wiring 5012 and the gate wiring 5013 to adjust the operation timing of the transistor 5016 and the transistor 5017, thereby controlling the alignment of liquid crystal.

[0548] Alternatively, a capacitor element may be formed using the capacitor wiring 5010, an insulating film serving as a dielectric, and a conductive film electrically connected to the first pixel electrode or the second pixel electrode.

[0549] In the multi-domain structure, one pixel includes a first liquid crystal element 5018 and a second liquid crystal element 5019. The first liquid crystal element 5018 is composed of a first pixel electrode, an opposing electrode, and a liquid crystal layer therebetween, while the second liquid crystal element 5019 is composed of a second pixel electrode, an opposing electrode, and a liquid crystal layer therebetween.

[0550] In addition, the display device according to one embodiment of the present invention is not limited to Fig.31B For example, the pixel circuit shown in FIG. Fig.31B The pixel circuit shown further provides switches, resistor elements, capacitor elements, transistors, sensors or logic circuits, etc.

[0551] <(2) Light-emitting device>

[0552] Fig.31C Another example of a circuit structure of a pixel is shown. Here, a pixel structure of a display device (also referred to as a light-emitting device) using a light-emitting element, typically an organic EL element, is shown.

[0553] In an organic EL element, by applying a voltage to a light-emitting element, electrons from one of a pair of electrodes included in the organic EL element and holes from the other of the pair of electrodes are injected into a layer containing a light-emitting organic compound, so that current flows. Moreover, by causing the electrons and holes to recombine, the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. According to this mechanism, this light-emitting element is called a current-excitation type light-emitting element.

[0554] Fig.31Cis a diagram showing an example of a pixel circuit. Here, an example of using two n-channel transistors and a capacitor element for one pixel is shown. In addition, the above transistor can be used as an n-channel transistor. And, the above capacitor element can be used as a capacitor element. In addition, the pixel circuit can be driven by digital time grayscale.

[0555] The structure of an applicable pixel circuit and the operation of a pixel when digital time grayscale driving is applied are described.

[0556] The pixel 5020 includes a switching transistor 5021, a driving transistor 5022, a light emitting element 5024, and a capacitor 5023. In the switching transistor 5021, the gate electrode is connected to the scanning line 5026, the first electrode (one of the source electrode and the drain electrode) is connected to the signal line 5025, and the second electrode (the other of the source electrode and the drain electrode) is connected to the gate electrode of the driving transistor 5022. In the driving transistor 5022, the gate electrode is connected to the power line 5027 through the capacitor 5023, the first electrode is connected to the power line 5027, and the second electrode is connected to the first electrode (pixel electrode) of the light emitting element 5024. The second electrode of the light emitting element 5024 is equivalent to the common electrode 5028. The common electrode 5028 is electrically connected to a common potential line formed on the same substrate.

[0557] The above-described transistors can be used as the switching transistor 5021 and the driving transistor 5022. Furthermore, the above-described capacitor can be used as the capacitor 5023. Thus, an organic EL display device having high display quality and / or reliability can be realized.

[0558] The potential of the second electrode (common electrode 5028) of the light-emitting element 5024 is set to a low power supply potential. Note that the low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 5027, and for example, GND, 0 V, or the like can be set as the low power supply potential. By setting the high power supply potential and the low power supply potential to be equal to or higher than the forward threshold voltage of the light-emitting element 5024 and applying the potential difference therebetween to the light-emitting element 5024, a current flows through the light-emitting element 5024, and the light-emitting element 5024 emits light. Note that the forward voltage of the light-emitting element 5024 refers to a voltage at which a desired brightness is obtained, and includes at least the forward threshold voltage.

[0559] In addition, the capacitor 5023 may be omitted by using the gate capacitor of the driving transistor 5022 instead. The gate capacitor of the driving transistor 5022 may be formed between the channel formation region and the gate electrode.

[0560] Next, the signal input to the driving transistor 5022 is described. When the voltage input voltage driving method is adopted, a video signal that turns the driving transistor 5022 into two states, namely, on or off, is input to the driving transistor 5022. In addition, in order to operate the driving transistor 5022 in the linear region, a voltage higher than the voltage of the power supply line 5027 is applied to the gate electrode of the driving transistor 5022. In addition, a voltage equal to or higher than the power supply line voltage plus the threshold voltage Vth of the driving transistor 5022 is applied to the signal line 5025.

[0561] When analog grayscale driving is performed, a voltage equal to or higher than the forward voltage of the light-emitting element 5024 plus the threshold voltage Vth of the driving transistor 5022 is applied to the gate electrode of the driving transistor 5022. In addition, a video signal is input so that the driving transistor 5022 operates in a saturation region, and a current flows through the light-emitting element 5024. In addition, in order to operate the driving transistor 5022 in a saturation region, the potential of the power supply line 5027 is made higher than the gate potential of the driving transistor 5022. By using an analog video signal, a current corresponding to the video signal can flow through the light-emitting element 5024, and analog grayscale driving can be performed.

[0562] In addition, the display device according to one embodiment of the present invention is not limited to Fig.31C For example, it is also possible to Fig.31C The pixel circuit shown may be supplemented with switches, resistors, capacitors, sensors, transistors, logic circuits, etc.

[0563] For example, Fig.32A An example of a pixel circuit is shown in FIG. Here, an example in which one pixel is formed using three n-channel transistors and one capacitor is shown.

[0564] Fig.32A An example of a circuit diagram of a pixel 5111 is shown. The pixel 5111 includes a transistor 5155, a transistor 5156, a transistor 5157, a capacitor 5158, and a light-emitting element 5154.

[0565] The potential of the pixel electrode of the light emitting element 5154 is controlled according to the pixel signal Sig input to the pixel 5111. The luminance of the light emitting element 5154 is determined by the potential difference between the pixel electrode and the common electrode.

[0566] The transistor 5156 has a function of controlling the conduction state between the wiring SL and the gate electrode of the transistor 5155. One of the source electrode and the drain electrode of the transistor 5155 is electrically connected to the anode of the light-emitting element 5154, and the other of the source electrode and the drain electrode of the transistor 5155 is electrically connected to the wiring VL. The transistor 5157 has a function of controlling the conduction state between the wiring ML and one of the source electrode and the drain electrode of the transistor 5155. One of a pair of electrodes of the capacitor 5158 is electrically connected to the gate electrode of the transistor 5155, and the other of a pair of electrodes of the capacitor 5158 is electrically connected to the anode of the light-emitting element 5154.

[0567] The transistor 5156 performs a switching operation according to the potential of the wiring GL electrically connected to the gate electrode of the transistor 5156. The transistor 5157 performs a switching operation according to the potential of the wiring GL electrically connected to the gate electrode of the transistor 5157.

[0568] In addition, the above-mentioned transistor can be used as at least one of the transistor 5155, the transistor 5156, and the transistor 5157. Furthermore, the above-mentioned capacitor can be used as the capacitor 5158.

[0569] For example, when the source (or first terminal, etc.) of the transistor is electrically connected to X through Z1 (or not through Z1) and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through Z2 (or not through Z2), or when the source (or first terminal, etc.) of the transistor is directly connected to a part of Z1 and the other part of Z1 is directly connected to X and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2 and the other part of Z2 is directly connected to Y, it can be expressed as follows.

[0570] For example, it can be expressed as “X, Y, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y”. Alternatively, it can be expressed as “the source (or first terminal, etc.) of the transistor is electrically connected to X, the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y”. Alternatively, it can be expressed as “X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and are connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y”. By specifying the connection order in the circuit structure using the same expression method as these examples, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished to determine the technical scope. Note that the above expression method is only an example and is not limited to the above expression method. Here, X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0571] Below, the description Fig.32A An example of the operation of pixel 5111 is shown.

[0572] Fig.32B Examples with Fig.32A The potential of the wiring GL electrically connected to the pixel 5111 shown in FIG. 1 and the potential of the pixel signal Sig supplied to the wiring SL are shown in FIG. Fig.32B The timing diagram shown shows an example of the Fig.32A The transistors of the pixel 5111 shown are all n-channel transistors.

[0573] First, in period t1 , a high-level potential is supplied to the wiring GL, thereby turning on the transistors 5156 and 5157 . In addition, a potential Vdata of the pixel signal Sig is supplied to the wiring SL, and the potential Vdata is supplied to the gate electrode of the transistor 5155 via the transistor 5156 .

[0574] In addition, the wiring VL is supplied with a potential Vano, and the wiring CL is supplied with a potential Vcat. The potential Vano is preferably higher than the potential Vcat plus the threshold voltage Vthe of the light emitting element 5154 and the threshold voltage Vth of the transistor 5155. By providing the above-mentioned potential difference between the wiring VL and the wiring CL, the value of the drain current of the transistor 5155 is determined according to the potential Vdata. And, by supplying the drain current to the light emitting element 5154, the brightness of the light emitting element 5154 is determined.

[0575] When the transistor 5155 is an n-channel transistor, in the period t1, the potential of the wiring ML is preferably lower than a potential obtained by adding the threshold voltage Vthe of the light emitting element 5154 to the potential of the wiring CL, and the potential of the wiring VL is preferably higher than a potential obtained by adding the threshold voltage Vth of the transistor 5155 to the potential of the wiring ML. With the above structure, even when the transistor 5157 is in the on state, the drain current of the transistor 5155 can flow preferentially through the wiring ML instead of through the light emitting element 5154.

[0576] Next, in period t2, a low-level potential is supplied to wiring GL. As a result, transistors 5156 and 5157 are turned off. By turning off transistor 5156, the potential Vdata can be held in the gate electrode of transistor 5155. In addition, the potential Vano is supplied to wiring VL, and the potential Vcat is supplied to wiring CL. As a result, light-emitting element 5154 emits light according to the brightness specified in period t1.

[0577] Next, during period t3, a high-level potential is supplied to wiring GL. As a result, transistors 5156 and 5157 are turned on. In addition, a potential whose gate voltage of transistor 5155 is greater than threshold voltage Vth is supplied to wiring SL. A potential Vcat is supplied to wiring CL. The potential of wiring ML is lower than the potential obtained by adding threshold voltage Vthe of light-emitting element 5154 to the potential of wiring CL, and the potential of wiring VL is higher than the potential obtained by adding threshold voltage Vth of transistor 5155 to the potential of wiring ML. By adopting the above structure, the drain current of transistor 5155 can flow preferentially through wiring ML instead of through light-emitting element 5154.

[0578] The drain current of the transistor 5155 is supplied to the monitor circuit via the wiring ML. The monitor circuit generates a signal including the value of the drain current as information using the drain current flowing through the wiring ML. In addition, in the light-emitting device according to one embodiment of the present invention, the value of the potential Vdata of the pixel signal Sig supplied to the pixel 5111 can be corrected using the above signal.

[0579] In having Fig.32A In the light-emitting device of the pixel 5111 shown, the operation during the period t3 may not be performed after the operation during the period t2. For example, the operation during the period t1 to the period t2 may be repeatedly performed in the pixel 5111, and then the operation during the period t3 may be performed. In addition, the operation during the period t3 may be performed in the pixels 5111 of a row, and then the pixel signal corresponding to the minimum grayscale value 0 may be written to the pixels 5111 of the row that performed the operation, so that the operation during the period t3 may be performed in the pixels 5111 of the next row after the light-emitting element 5154 is placed in a non-luminous state.

[0580] In addition, you can also use Fig.33A The structure of the pixel circuit shown. Fig.33A An example of a pixel circuit is shown in FIG. Here, an example in which one pixel is formed using four n-channel transistors and one capacitor is shown.

[0581] Fig.33A The pixel 5211 shown includes a transistor 5215 , a transistor 5216 , a transistor 5217 , a capacitor 5218 , a light-emitting element 5214 , and a transistor 5219 .

[0582] The potential of the pixel electrode of the light emitting element 5214 is controlled according to the pixel signal Sig input to the pixel 5211. The luminance of the light emitting element 5214 is determined by the potential difference between the pixel electrode and the common electrode.

[0583] The transistor 5219 has a function of controlling the conduction state between the wiring SL and the gate electrode of the transistor 5215. One of the source electrode and the drain electrode of the transistor 5215 is electrically connected to the anode of the light-emitting element 5214. The transistor 5216 has a function of controlling the conduction state between the wiring VL and the other of the source and the drain of the transistor 5215. The transistor 5217 has a function of controlling the conduction state between the wiring ML and the other of the source and the drain of the transistor 5215. One of a pair of electrodes of the capacitor 5218 is electrically connected to the gate electrode of the transistor 5215, and the other of the pair of electrodes is electrically connected to the anode of the light-emitting element 5214.

[0584] The switching operation of the transistor 5219 is performed according to the potential of the wiring GLa electrically connected to the gate electrode of the transistor 5219. The switching operation of the transistor 5216 is performed according to the potential of the wiring GLb electrically connected to the gate electrode of the transistor 5216. The switching operation of the transistor 5217 is performed according to the potential of the wiring GLc electrically connected to the gate electrode of the transistor 5217.

[0585] Furthermore, the above-mentioned transistor can be used as at least one of the transistor 5215, the transistor 5216, the transistor 5217, and the transistor 5219. Furthermore, the above-mentioned capacitor can be used as the capacitor 5218.

[0586] Below, the description Fig.33A A working example of external correction for pixel 5211 is shown.

[0587] Fig.33B Examples with Fig.33A The potentials of the wirings GLa, GLb, and GLc electrically connected to the pixel 5211 shown in FIG. 1 and the potential of the pixel signal Sig supplied to the wiring SL are shown in FIG. Fig.33B The timing diagram shown shows an example of the Fig.33A The transistors of the pixel 5211 shown are all n-channel transistors.

[0588] First, in period t1, a high level potential is supplied to wiring GLa, a high level potential is supplied to wiring GLb, and a low level potential is supplied to wiring GLc. As a result, transistors 5219 and 5216 are turned on, and transistor 5217 is turned off. The potential Vdata of the pixel signal Sig is supplied to wiring SL, and the potential Vdata is supplied to the gate electrode of transistor 5215 through transistor 5219.

[0589] In addition, the wiring VL is supplied with a potential Vano, and the wiring CL is supplied with a potential Vcat. The potential Vano is preferably a potential higher than the potential Vcat plus the threshold voltage Vthe of the light emitting element 5214. The potential Vano of the wiring VL is supplied to the other of the source and the drain of the transistor 5215 through the transistor 5216. Thus, the value of the drain current of the transistor 5215 is determined by the potential Vdata. And, the drain current is supplied to the light emitting element 5214, and the brightness of the light emitting element 5214 is determined.

[0590] Next, in period t2, a low level potential is supplied to wiring GLa, a high level potential is supplied to wiring GLb, and a low level potential is supplied to wiring GLc. As a result, transistor 5216 is turned on, and transistors 5219 and 5217 are turned off. By turning off transistor 5219, the potential Vdata can be maintained in the gate electrode of transistor 5215. In addition, potential Vano is supplied to wiring VL, and potential Vcat is supplied to wiring CL. As a result, light emitting element 5214 maintains the brightness specified in period t1.

[0591] Next, in period t3, a low level potential is supplied to wiring GLa, a low level potential is supplied to wiring GLb, and a high level potential is supplied to wiring GLc. As a result, transistor 5217 is turned on, and transistors 5219 and 5216 are turned off. Potential Vcat is supplied to wiring CL. Potential Vano is supplied to wiring ML, and wiring ML is connected to the monitor circuit.

[0592] By performing the above operation, the drain current of the transistor 5215 is supplied to the light-emitting element 5214 through the transistor 5217. In addition, the drain current is also supplied to the monitor circuit through the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to generate a signal including the value of the drain current as information. In addition, in the light-emitting device according to one embodiment of the present invention, the value of the potential Vdata of the pixel signal Sig supplied to the pixel 5211 can be corrected using the above signal.

[0593] In having Fig.33A In the light-emitting device of the pixel 5211 shown, the operation during the period t3 may not be performed after the operation during the period t2. For example, the operation from the period t1 to the period t2 may be repeatedly performed in the light-emitting device, and then the operation during the period t3 may be performed. In addition, the operation during the period t3 may be performed in pixels 5211 of a row, and then a pixel signal corresponding to the minimum grayscale value 0 may be written to the pixels 5211 of the row that performed the operation, so that the operation during the period t3 may be performed in pixels 5211 of the next row after the light-emitting element 5214 is placed in a non-luminous state.

[0594] In addition, you can also use Fig.34A The structure of the pixel circuit shown. Fig.34A 2 is a diagram showing an example of a pixel circuit, in which five n-channel transistors and one capacitor are used for one pixel.

[0595] Fig.34A The pixel 5311 shown includes a transistor 5315 , a transistor 5316 , a transistor 5317 , a capacitor 5318 , a light-emitting element 5314 , a transistor 5319 , and a transistor 5320 .

[0596] The transistor 5320 has a function of controlling the conduction state between the wiring RL and the anode of the light-emitting element 5314. The transistor 5319 has a function of controlling the conduction state between the wiring SL and the gate electrode of the transistor 5315. One of the source and the drain of the transistor 5315 is electrically connected to the anode of the light-emitting element 5314. The transistor 5316 has a function of controlling the conduction state between the wiring VL and the other of the source and the drain of the transistor 5315. The transistor 5317 has a function of controlling the conduction state between the wiring ML and the other of the source and the drain of the transistor 5315. One of the pair of electrodes of the capacitor 5318 is electrically connected to the gate electrode of the transistor 5315, and the other of the pair of electrodes is electrically connected to the anode of the light-emitting element 5314.

[0597] The switching operation of the transistor 5319 is performed according to the potential of the wiring GLa connected to the gate electrode of the transistor 5319. The switching operation of the transistor 5316 is performed according to the potential of the wiring GLb electrically connected to the gate electrode of the transistor 5316. The switching operation of the transistor 5317 is performed according to the potential of the wiring GLc electrically connected to the gate electrode of the transistor 5317. The switching operation of the transistor 5320 is performed according to the potential of the wiring GLd electrically connected to the gate electrode of the transistor 5320.

[0598] Furthermore, the above transistor can be used as at least one of the transistor 5315, the transistor 5316, the transistor 5317, the transistor 5319, and the transistor 5320. Furthermore, the above capacitor can be used as the capacitor 5318.

[0599] Below, the description Fig.34A A working example of external correction for pixel 5311 is shown.

[0600] Fig.34B Examples with Fig.34A The potentials of the wirings GLa, GLb, GLc, and GLd electrically connected to the pixel 5311 shown in FIG. 1 and the potential of the pixel signal Sig supplied to the wiring SL are shown in FIG. Fig.34B The timing diagram shown shows an example of the Fig.34A The transistors of the pixel 5311 shown are all n-channel transistors.

[0601] First, during period t1, a high-level potential is supplied to wiring GLa, a high-level potential is supplied to wiring GLb, a low-level potential is supplied to wiring GLc, and a high-level potential is supplied to wiring GLd. As a result, transistors 5319, 5316, and 5320 are turned on, and transistor 5317 is turned off. Furthermore, a potential Vdata of pixel signal Sig is supplied to wiring SL, and the potential Vdata is supplied to the gate electrode of transistor 5315 through transistor 5319. Thus, the value of the drain current of transistor 5315 is determined by the potential Vdata. A potential Vdata of pixel signal Sig is supplied to wiring SL, and the potential Vdata is supplied to the gate electrode of transistor 5315 through transistor 5319. Furthermore, a potential Vano is supplied to wiring VL, and a potential V1 is supplied to wiring RL, and the drain current flows between wiring VL and wiring RL through transistor 5316 and transistor 5320.

[0602] The potential Vano is preferably a potential higher than the potential Vcat plus the threshold voltage Vthe of the light emitting element 5314. The potential Vano of the wiring VL is supplied to the other of the source and the drain of the transistor 5315 through the transistor 5316. The potential V1 supplied to the wiring RL is supplied to one of the source and the drain of the transistor 5315 through the transistor 5320. The potential Vcat is supplied to the wiring CL.

[0603] The potential V1 is preferably sufficiently lower than the potential V0 minus the threshold voltage Vth of the transistor 5315. In the period t1, the potential V1 can be sufficiently lower than the potential Vcat minus the threshold voltage Vthe of the light-emitting element 5314, so that the light-emitting element 5314 does not emit light.

[0604] Next, in period t2, a low level potential is supplied to wiring GLa, a high level potential is supplied to wiring GLb, a low level potential is supplied to wiring GLc, and a low level potential is supplied to wiring GLd. As a result, transistor 5316 is turned on, and transistors 5319, 5317, and 5320 are turned off. By turning off transistor 5319, the potential Vdata can be maintained at the gate electrode of transistor 5315.

[0605] Furthermore, the wiring VL is supplied with a potential Vano, and the wiring CL is supplied with a potential Vcat. As a result, the transistor 5320 is turned off, and the drain current of the transistor 5315 whose value is specified in the period t1 is supplied to the light emitting element 5314. Then, the luminance of the light emitting element 5314 is specified by supplying the drain current to the light emitting element 5314, and the luminance is maintained in the period t2.

[0606] Next, in period t3, a low level potential is supplied to wiring GLa, a low level potential is supplied to wiring GLb, a high level potential is supplied to wiring GLc, and a low level potential is supplied to wiring GLd. As a result, transistor 5317 is turned on, and transistors 5319, 5316, and 5320 are turned off. Potential Vcat is supplied to wiring CL. Potential Vano is supplied to wiring ML, and wiring ML is electrically connected to the monitor circuit.

[0607] By performing the above operation, the drain current of the transistor 5315 is supplied to the light-emitting element 5314 through the transistor 5317. In addition, the drain current is also supplied to the monitor circuit through the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to generate a signal including the value of the drain current as information. In addition, in the light-emitting device according to one embodiment of the present invention, the value of the potential Vdata of the pixel signal Sig supplied to the pixel 5311 can be corrected using the above signal.

[0608] In having Fig.34A In the light-emitting device of the pixel 5311 shown, the operation during the period t3 may not be performed after the operation during the period t2. For example, the operation during the period t1 to the period t2 may be repeatedly performed in the light-emitting device, and then the operation during the period t3 may be performed. In addition, the operation during the period t3 may be performed in pixels 5311 of a row, and then a pixel signal corresponding to the minimum grayscale value 0 may be written to the pixels 5311 of the row in which the operation is performed, so that the operation during the period t3 may be performed in pixels 5311 of the next row after the light-emitting element 5314 is placed in a non-luminous state.

[0609] In addition, Fig.34AIn the pixel 5311 shown, even if the resistance values ​​of the anode and cathode of the light emitting element 5314 in each pixel are different due to degradation of the light emitting element 5314 or the like, the source potential of the transistor 5315 can be set to a predetermined potential V1 when the potential Vdata is supplied to the gate electrode of the transistor 5315. Thus, the luminance of the light emitting element 5314 in each pixel can be prevented from being different.

[0610] In addition, you can also use Fig.35A The structure of the pixel circuit shown. Fig.35A 2 is a diagram showing an example of a pixel circuit, in which six n-channel transistors and one capacitor are used for one pixel.

[0611] Fig.35A The pixel 5411 shown includes a transistor 5415 , a transistor 5416 , a transistor 5417 , a capacitor 5418 , a light-emitting element 5414 , a transistor 5440 , a transistor 5441 , and a transistor 5442 .

[0612] The potential of the pixel electrode of the light emitting element 5414 is controlled according to the pixel signal Sig input to the pixel 5411. The luminance of the light emitting element 5414 is determined by the potential difference between the pixel electrode and the common electrode.

[0613] The transistor 5440 has a function of controlling the conduction state between the wiring SL and one of the pair of electrodes of the capacitor 5418. The other of the pair of electrodes of the capacitor 5418 is electrically connected to one of the source and drain of the transistor 5415. The transistor 5416 has a function of controlling the conduction state between the wiring VL1 and the gate electrode of the transistor 5415. The transistor 5441 has a function of controlling the conduction state between one of the pair of electrodes of the capacitor 5418 and the gate electrode of the transistor 5415. The transistor 5442 has a function of controlling the conduction state between one of the source and drain of the transistor 5415 and the anode of the light emitting element 5414. The transistor 5417 has a function of controlling the conduction state between one of the source and drain of the transistor 5415 and the wiring ML.

[0614] Furthermore, in Fig.35A In the embodiment, the other of the source and the drain of the transistor 5415 is electrically connected to the wiring VL.

[0615] The switching operation of the transistor 5440 is performed according to the potential of the wiring GLa connected to the gate electrode of the transistor 5440. The on-off operation of the transistor 5416 is performed according to the potential of the wiring GLa electrically connected to the gate electrode of the transistor 5416. The switching operation of the transistor 5441 is performed according to the potential of the wiring GLb electrically connected to the gate electrode of the transistor 5441. The switching operation of the transistor 5442 is performed according to the potential of the wiring GLb electrically connected to the gate electrode of the transistor 5442. The switching operation of the transistor 5417 is performed according to the potential of the wiring GLc electrically connected to the gate electrode of the transistor 5417.

[0616] Fig.35B exemplify Fig.35A 5411 and the potential of the wiring GLa, wiring GLb, and wiring GLc electrically connected to the pixel 5411 and the potential of the pixel signal Sig supplied to the wiring SL. Fig.35B The timing diagram shown shows an example of the Fig.35A The transistors of the pixel 5411 shown are all n-channel transistors.

[0617] First, in period t1, a low level potential is supplied to wiring GLa, a high level potential is supplied to wiring GLb, and a high level potential is supplied to wiring GLc. As a result, transistors 5441, 5442, and 5417 are turned on, and transistors 5440 and 5416 are turned off. Since transistors 5442 and 5417 are turned on, one of the source and drain of transistor 5415 and the other of the pair of electrodes of capacitor 5418 (indicated as node A in the drawing) are supplied with the potential V0 of wiring ML.

[0618] In addition, the wiring VL is supplied with a potential Vano, and the wiring CL is supplied with a potential Vcat. The potential Vano is preferably higher than the potential V0 plus the threshold voltage Vthe of the light emitting element 5414. The potential V0 is preferably lower than the potential Vcat plus the threshold voltage Vthe of the light emitting element 5414. By setting the potential V0 to the above value, current can be prevented from flowing through the light emitting element 5414 during the period t1.

[0619] By supplying a low potential to the wiring GLb, the transistor 5441 and the transistor 5442 are turned off, and the node A is maintained at the potential V0.

[0620] Next, in period t2, a high potential is supplied to wiring GLa, a low potential is supplied to wiring GLb, and a low potential is supplied to wiring GLc. As a result, transistors 5440 and 5416 are turned on, and transistors 5441, 5442, and 5417 are turned off.

[0621] In addition, preferably, when the period t1 is transferred to the period t2, the potential supplied to the wiring GLa is switched from the low potential to the high potential, and then the potential supplied to the wiring GLc is switched from the high potential to the low potential. By performing the above steps, the potential of the node A can be prevented from changing due to the switching of the potential supplied to the wiring GLa.

[0622] The wiring VL is supplied with a potential Vano, and the wiring CL is supplied with a potential Vcat. The wiring SL is supplied with a potential Vdata of the pixel signal Sig, and the wiring VL1 is supplied with a potential V1. The potential V1 is preferably a potential higher than the threshold voltage Vth of the transistor 5415 added to the potential Vcat and lower than the threshold voltage Vth of the transistor 5415 added to the potential Vano.

[0623] exist Fig.35A In the pixel structure shown, even if the potential V1 is higher than the potential obtained by adding the threshold voltage Vthe of the light-emitting element 5414 to the potential Vcat, as long as the transistor 5442 is in the off state, the light-emitting element 5414 does not emit light. As a result, the range of values ​​that can set the potential V0 can be expanded, thereby expanding the range of values ​​that can be V1-V0. Therefore, since the degree of freedom of the value of V1-V0 is improved, even in the case of shortening the time required to obtain the threshold voltage Vth of the transistor 5415, or in the case of a limit on the time to obtain the threshold voltage Vth, the threshold voltage Vth of the transistor 5415 can be accurately obtained.

[0624] After the above operation, a potential V1 higher than the potential of node A plus the threshold voltage Vth is input to the gate electrode of transistor 5415 (indicated as node B in the figure), whereby transistor 5415 becomes conductive. As a result, the charge of capacitor 5418 is released through transistor 5415, and the potential of node A with potential V0 begins to rise. Finally, the potential of node A converges to V1-Vth, and the gate voltage of transistor 5415 converges to the threshold voltage Vth, so that transistor 5415 becomes off.

[0625] A potential Vdata of the pixel signal Sig supplied to the wiring SL is provided to one of a pair of electrodes of the capacitor 5418 (indicated as a node C in the drawing) through the transistor 5440 .

[0626] Next, in period t3, a low level potential is supplied to wiring GLa, a high level potential is supplied to wiring GLb, and a low level potential is supplied to wiring GLc. As a result, transistors 5441 and 5442 are turned on, and transistors 5440, 5416, and 5417 are turned off.

[0627] In addition, when the period t2 is shifted to the period t3, it is preferred that the potential supplied to the wiring GLa is switched from a high potential to a low potential, and then the potential supplied to the wiring GLb is switched from a low potential to a high potential. By adopting the above structure, the potential of the node A can be prevented from changing due to the switching of the potential supplied to the wiring GLa.

[0628] Furthermore, the potential Vano is supplied to the wiring VL, and the potential Vcat is supplied to the wiring CL.

[0629] By performing the above operation, the potential Vdata is applied to the node B, and thus the gate voltage of the transistor 5415 becomes Vdata-V1+Vth. Therefore, the gate voltage of the transistor 5415 can be set to a value obtained by adding the threshold voltage Vth to its potential. In addition, the above structure can suppress the deviation of the threshold voltage Vth of the transistor 5415. Thus, the deviation of the current value supplied to the light-emitting element 5414 can be suppressed, thereby reducing the uneven brightness of the light-emitting device.

[0630] Here, by increasing the amount of change in the potential applied to the wiring GLb, it is possible to prevent the deviation in the threshold voltage of the transistor 5442 from affecting the current value supplied to the light-emitting element 5414. In other words, by setting the high-level potential supplied to the wiring GLb to be sufficiently higher than the threshold voltage of the transistor 5442 and setting the low-level potential supplied to the wiring GLb to be sufficiently lower than the threshold voltage of the transistor 5442, the switching operation of the transistor 5442 is ensured, thereby preventing the deviation in the threshold voltage of the transistor 5442 from affecting the current value of the light-emitting element 5414.

[0631] Next, in period t4, a low potential is supplied to wiring GLa, a low potential is supplied to wiring GLb, and a high potential is supplied to wiring GLc. As a result, transistor 5417 is turned on, and transistors 5416, 5440, 5441, and 5442 are turned off.

[0632] The potential Vano is supplied to the wiring VL, and the wiring ML is electrically connected to the monitor circuit.

[0633] By performing the above operation, the drain current Id of the transistor 5415 can flow through the wiring ML via the transistor 5417 without flowing through the light-emitting element 5414. The monitor circuit uses the drain current Id flowing through the wiring ML to generate a signal containing the value of the drain current Id as information. The magnitude of the drain current Id is determined by the mobility and size (channel length, channel width) of the transistor 5415. In addition, in the light-emitting device according to one embodiment of the present invention, the value of the potential Vdata of the pixel signal Sig supplied to the pixel 5411 can be corrected using the above signal. That is, the influence caused by the bias of the mobility of the transistor 5415 can be reduced.

[0634] In having Fig.35A In the light-emitting device of the pixel 5411 shown, the operation during the period t4 may not be performed after the operation during the period t3. For example, the operation from the period t1 to the period t3 may be repeatedly performed in the light-emitting device, and then the operation during the period t4 may be performed. In addition, the operation during the period t4 may be performed in the pixels 5411 of a row, and then the pixel signal corresponding to the minimum grayscale value 0 may be written to the pixels 5411 of the row that performed the operation, so that the operation during the period t4 may be performed in the pixels 5411 of the next row after the light-emitting element 5414 is placed in a non-luminous state.

[0635] In having Fig.35A In the light-emitting device of the pixel 5411 shown, since the other of the source and the drain of the transistor 5415 is electrically separated from the gate electrode of the transistor 5415, each potential can be controlled separately. Thus, in the period t2, the potential of the other of the source and the drain of the transistor 5415 can be set to a value higher than the potential of the gate of the transistor 5415 plus the threshold voltage Vth. Therefore, when the transistor 5415 is normally on, that is, when the threshold voltage Vth has a negative value, in the transistor 5415, the charge can be accumulated in the capacitor 5418 until the potential of the source becomes higher than the potential V1 of the gate. Thus, in the light-emitting device according to one embodiment of the present invention, even if the transistor 5415 is normally on, the threshold voltage Vth can be obtained in the period t2, and in the period t3, the gate voltage of the transistor 5415 can be set to a value including the threshold voltage Vth.

[0636] Therefore, in the light-emitting device according to one embodiment of the present invention, even if the transistor 5415 is normally off, display unevenness can be reduced and high-quality image display can be performed.

[0637] In addition, it is possible to monitor the characteristics of the transistor 5415 or the characteristics of the light-emitting element 5414. At this time, it is preferable to control the potential Vdata of the pixel signal Sig so that the current does not flow through the transistor 5415. In this way, the current of the light-emitting element 5414 can be taken out. As a result, the degradation and unevenness of the current characteristics of the light-emitting element 5414 can be obtained.

[0638] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0639] Implementation 7

[0640] In this embodiment, refer to Fig.36 as well as FIG. 37A to FIG. 37H A display module and an electronic device that can use a semiconductor device according to one embodiment of the present invention will be described.

[0641] Fig.36 The display module 8000 shown includes a touch panel 8004 connected to an FPC 8003 , a display panel 8006 connected to an FPC 8005 , a backlight unit 8007 , a frame 8009 , a printed circuit board 8010 , and a battery 8011 between an upper cover 8001 and a lower cover 8002 .

[0642] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0643] The shape or size of the upper cover 8001 and the lower cover 8002 may be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006 .

[0644] The touch panel 8004 can be a resistive film touch panel or an electrostatic capacitance touch panel, and can be formed to overlap with the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can also have the function of a touch panel. In addition, a light sensor can be provided in each pixel of the display panel 8006 to use it as an optical touch panel.

[0645] The backlight unit 8007 has a light source 8008. Note that although Fig.36 2 shows a structure in which the light source 8008 is arranged on the backlight unit 8007, but the present invention is not limited thereto. For example, the light source 8008 may be arranged at the end of the backlight unit 8007, and a light diffusion plate may be used. In addition, when a self-luminous light-emitting element such as an organic EL or a reflective panel is used, a structure in which the backlight unit 8007 is not arranged may be adopted.

[0646] The frame 8009 has a function of protecting the display panel 8006 and also has an electromagnetic shielding function for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. In addition, the frame 8009 has a function of a heat sink.

[0647] The printed circuit board 8010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, an external commercial power supply can be used, and a power supply of a separately provided battery 8011 can be used. When a commercial power supply is used, the battery 8011 can be omitted.

[0648] In addition, components such as a polarizing plate, a phase difference plate, and a prism sheet may also be provided in the display module 8000 .

[0649] FIG. 37A to FIG. 37H 9001, a speaker 9003, an LED lamp 9004, an operation key 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (which has a function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, smell or infrared), a microphone 9008, etc.

[0650] Fig.37A A mobile computer is shown, which may include a switch 9009, an infrared port 9010, etc. in addition to the above. Fig.37B A portable image reproducing device (for example, a DVD reproducing device) including a recording medium is shown. In addition to the above, the portable image reproducing device may include a second display portion 9002, a recording medium reading portion 9011, and the like. Fig.37C A goggle-type display is shown, which may include a second display portion 9002, a supporting portion 9012, headphones 9013, and the like in addition to the above. Fig.37D The portable game machine is shown, and the portable game machine may include a recording medium reading unit 9011 and the like in addition to the above. Fig.37E A digital camera having a television reception function is shown, and the digital camera may include an antenna 9014, a shutter button 9015, an image receiving unit 9016, and the like in addition to the above. Fig.37F 9002 , a recording medium reading portion 9011 , and the like in addition to the above-described features. Figure 37G A television receiver is shown, which may include a tuner, an image processing unit, and the like in addition to the above. Fig.37HA portable television receiver is shown, which may include a charger 9017 capable of transmitting and receiving signals, etc. in addition to the above.

[0651] FIG. 37A to FIG. 37H The electronic device shown may have various functions. For example, it may have the following functions: displaying various information (static images, dynamic images, text images, etc.) on the display unit; touch panel; displaying calendar, date or time, etc.; controlling processing by using various software (programs); performing wireless communication; connecting to various computer networks by using the wireless communication function; sending or receiving various data by using the wireless communication function; reading out programs or data stored in a recording medium to display them on the display unit, etc. Furthermore, in an electronic device having multiple display units, it may have the following functions: one display unit mainly displays image information, while another display unit mainly displays text information; or, images that take parallax into account are displayed on multiple display units to display stereoscopic images, etc. Furthermore, in an electronic device having an image receiving unit, it may have the following functions: shooting static images; shooting dynamic images; automatically or manually correcting the shot images; storing the shot images in a recording medium (external or built-in to the camera); displaying the shot images on the display unit, etc. Note that, FIG. 37A to FIG. 37H The functions that the electronic device shown may have are not limited to the above functions, but may have various functions.

[0652] The electronic device described in this embodiment is characterized by having a display portion for displaying certain information. In addition, the semiconductor device of one embodiment of the present invention can also be applied to an electronic device without a display portion.

[0653] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate. Example

[0654] In this example, a cross-sectional shape of a transistor which is one embodiment of the present invention is observed.

[0655] The following describes the method for making the sample observed in this example. Figure 1A and 1C The transistor 100 is shown as a transistor.

[0656] First, a substrate 102 is prepared. A glass substrate is used as the substrate 102. Next, a 100 nm thick silicon nitride film (SiN-1) is formed on the substrate 102 as an insulating film 108a. Next, a 400 nm thick silicon oxynitride film (SiON-1) is formed on the insulating film 108a as an insulating film 108b. In addition, the insulating film 108a and the insulating film 108b are continuously formed in a vacuum using a PECVD device.

[0657] Next, as a film for suppressing oxygen detachment, a 5 nm thick tantalum nitride film is formed on the insulating film 108b. The tantalum nitride film is formed by a sputtering device. Next, oxygen is added to the insulating film 108b through the tantalum nitride film by an ashing device. Next, the tantalum nitride film is removed by a dry etching device.

[0658] Next, as an oxide semiconductor film 110, a 50 nm thick oxide semiconductor film (IGZO) is formed on the insulating film 108b. The formation conditions of the oxide semiconductor film 110 are as follows: using a sputtering device; using a metal oxide of In:Ga:Zn=1:1:1.2 [atomic %] as a sputtering target; using an AC power supply as a power source added to the sputtering target. Then, the substrate on which the oxide semiconductor film 110 is formed is heat-treated. As for the heat treatment, the heat treatment is performed at 450°C for one hour in a nitrogen atmosphere, and the heat treatment is continuously performed at 450°C for one hour in a mixed atmosphere of nitrogen and oxygen.

[0659] Next, a mask is formed over the oxide semiconductor film 110 by a photolithography step, and the oxide semiconductor film 110 is processed into an island shape using the mask. In addition, the oxide semiconductor film 110 is processed by a wet etching method using a chemical solution.

[0660] Next, as the insulating film 112 , a silicon oxynitride film (SiON-2) is formed to a thickness of 100 nm on the island-shaped oxide semiconductor film 110 . The insulating film 112 is formed using a PECVD apparatus.

[0661] Next, as the conductive film 114a, a tantalum nitride film (TaN) with a thickness of 30 nm is formed on the insulating film 112. Then, as the conductive film 114b, a tungsten film (W) with a thickness of 150 nm is formed on the conductive film 114a. The conductive film 114a and the conductive film 114b are continuously formed in a vacuum by a sputtering device.

[0662] Next, a mask is formed on the conductive film 114b by a photolithography process, and the conductive film 114b, the conductive film 114a, and the insulating film 112 are processed into an island shape using the mask. The conductive film 114a, the conductive film 114b, and the insulating film 112 are processed using a dry etching device. Then, an impurity element is added to the oxide semiconductor film 110 while leaving the above-mentioned mask. As for the method of adding the impurity element, the substrate is arranged between parallel plates in the processing chamber of the etching device using an etching device. Then, argon gas is introduced into the above-mentioned processing chamber, and RF power is applied between the parallel plates in a manner that biases one side of the substrate.

[0663] Next, a 100 nm thick silicon nitride film (SiN-2) is formed as the insulating film 118 so as to cover the insulating film 108 b, the oxide semiconductor film 110, the insulating film 112, and the conductive films 114 a and 114 b. Next, a 300 nm thick silicon oxynitride film (SiON-3) is formed on the insulating film 118 as the insulating film 120. The insulating film 118 and the insulating film 120 are continuously formed in a vacuum using a PECVD apparatus.

[0664] Next, a mask is formed on the insulating film 120 by a photolithography process, and openings are formed in the insulating films 120 and 118 using the mask. The openings reach the oxide semiconductor film 110. The openings are processed using a dry etching apparatus.

[0665] Next, a conductive film is formed to cover the insulating film 120 and the opening. As the conductive film, a 50 nm thick tungsten film, a 400 nm thick aluminum film, and a 100 nm thick titanium film are stacked in this order. The conductive film is continuously formed in a vacuum using a sputtering device.

[0666] Next, a mask is formed over the conductive film by a photolithography step, and the conductive film 122 and the conductive film 124 are formed using the mask.

[0667] Through the above steps, the sample of this embodiment for observing its cross section is manufactured.

[0668] Fig.38A and 38B The results of cross-sectional observation are shown. In addition, a transmission electron microscope (TEM: Transmission Electron Microscope) was used when observing the cross-section.

[0669] Fig.38A is a cross-sectional TEM image showing that Figure 1A Near the conductive film 114 in the dotted line X1-X2 direction. Fig.38B is a cross-sectional TEM image showing that Figure 1A Near the conductive film 114 in the dotted line Y1-Y2 direction.

[0670] Notice, Fig.38A and 38B The SiN-1, SiN-2, SiON-1, SiON-2, SiON-3, TaN and W shown correspond to the film types described in parentheses in the above-mentioned embodiments. Fig.38A and 38B The Pt shown indicates platinum which is a surface coating when observing the cross section.

[0671] Depend on Fig.38AThe cross-sectional TEM image shows that the end of the tantalum nitride film (TaN) is located outside the end of the tungsten film (W); and the end of the silicon oxynitride film (SiON-2) is located outside the end of the tantalum nitride film (TaN). Fig.38B The cross-sectional TEM image shown shows that the end of the tantalum nitride film (TaN) is located outside the end of the tungsten film (W); the end of the silicon oxynitride film (SiON-2) is located outside the end of the tantalum nitride film (TaN); and there is a concave portion in the area where the silicon oxynitride film (SiON-1) does not overlap with the silicon oxynitride film (SiON-2). Fig.38A and 38B As can be seen from the cross-sectional TEM image shown, in the sample manufactured in this example, the silicon nitride film (SiN-2) has excellent coverage and a good cross-sectional shape.

[0672] The structure described in this embodiment can be used in combination with the structures described in other embodiment modes as appropriate.

[0673] Explanation of symbols

[0674] 100 transistors

[0675] 100A Transistor

[0676] 100B transistor

[0677] 100C transistor

[0678] 100D Transistor

[0679] 100E Transistor

[0680] 100F transistor

[0681] 100G transistors

[0682] 100H Transistor

[0683] 102 Substrate

[0684] 104 Insulation film

[0685] 106 Conductive film

[0686] 106a Conductive film

[0687] 106b Conductive film

[0688] 108 Insulation film

[0689] 108a Insulation film

[0690] 108b Insulation film

[0691] 108c Insulation film

[0692] 110 Oxide semiconductor film

[0693] 110_1 Oxide semiconductor film

[0694] 110_2 Oxide semiconductor film

[0695] 110a Channel region

[0696] 110a_1 Channel region

[0697] 110a_2 Channel region

[0698] 110b Low resistance area

[0699] 110b_1 Low resistance area

[0700] 110b_2 Low resistance area

[0701] 110c Low resistance area

[0702] 110c_1 Low resistance area

[0703] 110c_2 Low resistance area

[0704] 110d Low resistance area

[0705] 110e Low resistance area

[0706] 110f Area

[0707] 110g Region

[0708] 110h Low resistance area

[0709] 110i Low resistance area

[0710] 112 Insulation film

[0711] 112a Insulation film

[0712] 112b Insulation film

[0713] 113 Conductive film

[0714] 113a Conductive film

[0715] 113b Conductive film

[0716] 114 Conductive film

[0717] 114a Conductive film

[0718] 114b Conductive film

[0719] 116 Conductive film

[0720] 116a Conductive film

[0721] 116b Conductive film

[0722] 117 Insulation film

[0723] 118 Insulation film

[0724] 120 Insulation film

[0725] 121 Conductive film

[0726] 121a Conductive film

[0727] 121b Conductive film

[0728] 122 Conductive film

[0729] 122a Conductive film

[0730] 122b Conductive film

[0731] 124 Conductive film

[0732] 124a Conductive film

[0733] 124b Conductive film

[0734] 126 Conductive film

[0735] 126a Conductive film

[0736] 126b Conductive film

[0737] 128 Insulation film

[0738] 139 Opening

[0739] 140a Opening

[0740] 140b Opening

[0741] 140c Opening

[0742] 141 Membrane

[0743] 142 Oxygen

[0744] 143 Impurity Elements

[0745] 145 Mask

[0746] 150 Capacitor Components

[0747] 150A Capacitor Element

[0748] 150B capacitor element

[0749] 150C capacitor element

[0750] 150D Capacitor Element

[0751] 150E Capacitor Element

[0752] 150F capacitor element

[0753] 150G Capacitor Components

[0754] 210 Electron Gun Room

[0755] 212 Optical System

[0756] 214 Sample Room

[0757] 216 Optical System

[0758] 218 Photographic Device

[0759] 220 Observation Room

[0760] 222 Film Room

[0761] 224 Electronics

[0762] 228 Substance

[0763] 232 Fluorescent board

[0764] 306 Conductive film

[0765] 306a Conductive film

[0766] 306b Conductive film

[0767] 314 Conductive film

[0768] 314a Conductive film

[0769] 314b Conductive film

[0770] 316 Conductive film

[0771] 316a Conductive film

[0772] 316b Conductive film

[0773] 318 Conductive film

[0774] 318a Conductive film

[0775] 318b Conductive film

[0776] 324 Conductive film

[0777] 324a Conductive film

[0778] 324b Conductive film

[0779] 326 Conductive film

[0780] 326a Conductive film

[0781] 326b Conductive film

[0782] 328 Conductive film

[0783] 328a Conductive film

[0784] 328b Conductive film

[0785] 334 Conductive film

[0786] 334a Conductive film

[0787] 334b Conductive film

[0788] 338 Conductive film

[0789] 338a Conductive film

[0790] 338b Conductive film

[0791] 352 Opening

[0792] 353 Opening

[0793] 354 Opening

[0794] 355 Opening

[0795] 500 FET

[0796] 501 substrate

[0797] 502 substrate

[0798] 504B light emitting element

[0799] 504G Light Emitting Component

[0800] 504R light emitting element

[0801] 504W light emitting element

[0802] 506 Conductive film

[0803] 507 Conductive film

[0804] 508 Partition Wall

[0805] 509 Structure

[0806] 510 EL layer

[0807] 512 Conductive film

[0808] 514B Coloring layer

[0809] 514G Coloring Layer

[0810] 514R Coloring Layer

[0811] 514W Coloring Layer

[0812] 516 substrate

[0813] 518 Sealing Film

[0814] 520 Area

[0815] 522 Insulation film

[0816] 524 Opening

[0817] 700 Display Device

[0818] 701 Substrate

[0819] 702 Pixel Department

[0820] 704 Source driver circuit

[0821] 705 substrate

[0822] 706 Gate drive circuit unit

[0823] 708 FPC terminal

[0824] 710 signal line

[0825] 711 Wiring Department

[0826] 712 Sealant

[0827] 716 FPC

[0828] 730 Insulation Film

[0829] 732 Sealing film

[0830] 734 Insulation film

[0831] 736 Coloring Film

[0832] 738 shading film

[0833] 750 transistors

[0834] 752 transistors

[0835] 760 Connecting electrodes

[0836] 766 Insulation Film

[0837] 770 Planarization insulation film

[0838] 772 Conductive film

[0839] 774 Conductive film

[0840] 775 Liquid crystal element

[0841] 776 Liquid crystal layer

[0842] 778 Structure

[0843] 780 Anisotropic Conductive Film

[0844] 782 Light-emitting components

[0845] 784 Conductive film

[0846] 786 EL layer

[0847] 788 Conductive film

[0848] 790 Capacitor Components

[0849] 1100 granules

[0850] 1100a Particles

[0851] 1100b particles

[0852] 1101 particles

[0853] 1120 Substrate

[0854] 1130 Target

[0855] 5000 Substrate

[0856] 5001 Pixel Department

[0857] 5002 Scan line driver circuit

[0858] 5003 Scan line driver circuit

[0859] 5004 Signal line driver circuit

[0860] 5010 Capacitor Wiring

[0861] 5012 Gate wiring

[0862] 5013 Gate wiring

[0863] 5014 Drain electrode

[0864] 5016 transistor

[0865] 5017 Transistor

[0866] 5018 Liquid crystal element

[0867] 5019 Liquid crystal element

[0868] 5020 pixels

[0869] 5021 Switching Transistor

[0870] 5022 driver transistor

[0871] 5023 Capacitor Components

[0872] 5023a Capacitor element

[0873] 5023b Capacitor element

[0874] 5024 Light-emitting element

[0875] 5025 Signal Line

[0876] 5026 scan lines

[0877] 5027 Power Cord

[0878] 5028 Common electrode

[0879] 5111 pixels

[0880] 5154 Light-emitting element

[0881] 5155 transistor

[0882] 5156 Transistor

[0883] 5157 Transistor

[0884] 5158 Capacitor Components

[0885] 5211 pixels

[0886] 5214 Light-emitting components

[0887] 5215 Transistor

[0888] 5216 Transistor

[0889] 5217 Transistor

[0890] 5218 Capacitor Components

[0891] 5219 Transistor

[0892] 5311 pixels

[0893] 5314 Light-emitting components

[0894] 5315 Transistor

[0895] 5316 Transistor

[0896] 5317 Transistor

[0897] 5318 Capacitor Components

[0898] 5319 Transistor

[0899] 5320 Transistor

[0900] 5411 pixels

[0901] 5414 Light-emitting components

[0902] 5415 Transistor

[0903] 5416 Transistor

[0904] 5417 Transistor

[0905] 5418 Capacitor Components

[0906] 5440 Transistor

[0907] 5441 Transistor

[0908] 5442 Transistor

[0909] 8000 Display Module

[0910] 8001 Cover

[0911] 8002 Lower cover

[0912] 8003 FPC

[0913] 8004 Touch Panel

[0914] 8005 FPC

[0915] 8006 Display Panel

[0916] 8007 Backlight Unit

[0917] 8008 Light Source

[0918] 8009 Framework

[0919] 8010 Printed Circuit Board

[0920] 8011 Battery

[0921] 9000 Frame

[0922] 9001 Display unit

[0923] 9002 Display unit

[0924] 9003 Speaker

[0925] 9004 LED Light

[0926] 9005 Operation keys

[0927] 9006 Connection Terminal

[0928] 9007 Sensor

[0929] 9008 Microphone

[0930] 9009 Switch

[0931] 9010 Infrared port

[0932] 9011 Recording medium reading unit

[0933] 9012 Support

[0934] 9013 Headphones

[0935] 9014 Antenna

[0936] 9015 Shutter button

[0937] 9016 Image Receiving Unit

[0938] 9017 Charger.

Claims

1. A semiconductor device comprising: an oxide semiconductor film on the first insulating film; a gate insulating film on the oxide semiconductor film; a gate electrode on the gate insulating film; a second insulating film on the gate electrode; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, The second insulating film has a region in contact with the upper surface of the gate insulating film, a region in contact with the side surface of the gate insulating film, and a region in contact with the upper surface of the oxide semiconductor film, The first insulating film has a first region and a second region, The first region overlaps with the oxide semiconductor film, The second region does not overlap with any one of the oxide semiconductor film, the gate insulating film, and the gate electrode. The film thickness of the second region is smaller than the film thickness of the first region.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor film has a third region and a fourth region, The third region overlaps with the gate insulating film and the gate electrode, The fourth region does not overlap with either the gate insulating film or the gate electrode. The film thickness of the fourth region is smaller than the film thickness of the third region.

3. A semiconductor device comprising: a first gate electrode; a first insulating film on the first gate electrode; an oxide semiconductor film on the first insulating film; a gate insulating film on the oxide semiconductor film; a second gate electrode on the gate insulating film; a second insulating film on the second gate electrode; a source electrode electrically connected to the oxide semiconductor film; as well as a drain electrode electrically connected to the oxide semiconductor film, The second insulating film has a region in contact with the upper surface of the gate insulating film, a region in contact with the side surface of the gate insulating film, and a region in contact with the upper surface of the oxide semiconductor film, The first insulating film has a first region and a second region, The first region overlaps with the oxide semiconductor film, The second region does not overlap with any one of the oxide semiconductor film, the gate insulating film, and the second gate electrode, and a film thickness of the second region is smaller than a film thickness of the first region.

4. The semiconductor device according to claim 1 or claim 3, The first insulating film is made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and is provided in a single layer or a stacked layer.

5. The semiconductor device according to claim 3, The first gate electrode has a stacked structure of a conductive film including copper.

6. The semiconductor device according to claim 3, wherein the oxide semiconductor film has a third region and a fourth region, The third region overlaps with the gate insulating film and the second gate electrode, The fourth region does not overlap with either the gate insulating film or the second gate electrode. The film thickness of the fourth region is smaller than the film thickness of the third region.

7. A transistor, which is a top-gate transistor having an oxide semiconductor film, wherein: The oxide semiconductor film is in an island shape, The transistor has: a single-layer gate insulating film, the end of which is located on the upper surface of the oxide semiconductor film when viewed in a cross section parallel to the channel length direction; and a first insulating film having a region in contact with each of a side surface of the gate electrode, an upper surface of the single-layer gate insulating film, and an upper surface of the oxide semiconductor film, The upper surface of the single-layer gate insulating film has a region extending to the outside of the gate electrode, In the cross-sectional view, the oxide semiconductor film has: a first region overlapping with the gate insulating film; and a second region which does not overlap with the gate insulating film and has a smaller film thickness than the first region, The source electrode or the drain electrode has a region in contact with the upper surface of the second region, The oxide semiconductor film contains In, Ga, and Zn.

8. A transistor, being a top-gate transistor having an oxide semiconductor film, wherein: The oxide semiconductor film is in an island shape, The transistor has: a single-layer gate insulating film, the end of which is located on the upper surface of the oxide semiconductor film when viewed in a cross section parallel to the channel length direction; and a first insulating film having a region in contact with each of a side surface of the gate electrode, an upper surface of the single-layer gate insulating film, and an upper surface of the oxide semiconductor film, The upper surface of the single-layer gate insulating film has a region extending to the outside of the gate electrode, In the cross-sectional view, the oxide semiconductor film has: a first region overlapping with the gate insulating film; and a second region which does not overlap with the gate insulating film and has a smaller film thickness than the first region, The source electrode or the drain electrode has a region in contact with the upper surface of the second region.

9. A transistor according to claim 7 or claim 8, The oxide semiconductor film has a crystal portion, and the crystal portion is observed as a plurality of spots in a ring-shaped region in a nanobeam electron diffraction pattern.

10. A transistor according to claim 7 or claim 8, A conductive film is provided below the oxide semiconductor film, and the conductive film has a region overlapping with the oxide semiconductor film via a second insulating film.

Images