Alternative integration for redistribution layer processes

Abstract

In one example, a method for a redistribution layer (RDL) process is described. A substrate is provided. A dielectric layer is deposited on top of the substrate. The dielectric layer is patterned. A barrier layer and a copper seed layer are deposited on top of the dielectric layer. A photoresist layer is applied on top of the barrier layer and the copper seed layer. The photoresist layer is patterned to correspond to the dielectric layer pattern. Copper is electrodeposited in the patterned areas exposed by the photoresist layer. The photoresist layer is removed. The copper and seed barrier layers are etched.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Patent Application No. 62 / 703,762, filed on July 26, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to redistribution layer (RDL) processes, and more particularly to systems and methods for alternative integration of RDLs. Background Art

[0004] In a conventional RDL process flow, a thin barrier layer and a copper seed layer are both deposited on an incoming substrate (most commonly silicon). A photoresist layer is applied by spin coating or lamination. The photoresist is exposed, developed, and stripped to expose the copper seed in the RDL pattern. This patterned area is then filled with copper via an electroplating process. After electroplating, the photoresist is then removed. The copper seed and barrier layer are finally removed to electrically isolate the plated RDL pattern. During the seed removal step (via wet chemical etching), the etchant attacks the copper seed at the pattern / seed interface, resulting in undercuts beneath the RDL pattern. Undercuts degrade the mechanical integrity of the RDL pattern and produce poor signal integrity. Two types of undercuts can occur: (1) etching the seed beneath the RDL pattern, and (2) etching the seed and substrate of the plated RDL. As RDL dimensions continue to shrink, the problem becomes more prominent as undercuts occur in larger areas of the RDL.

[0005] The present disclosure attempts to address these shortcomings.It should be noted that the information described in this section is provided to provide technical personnel with some background to the following disclosed subject matter and should not be considered as admitted prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In the figures of the accompanying drawings, some embodiments are shown by way of example and not by way of limitation.

[0007] Figure 1A is a cross-sectional view of a substrate before conventional redistribution layer (RDL) processing.

[0008] Figure 1B is a cross-sectional view of a substrate after a conventional RDL process.

[0009] Figure 2 is a block diagram of a cross-section of a substrate after a conventional RDL process.

[0010] Figures 3A-3J is a block diagram illustrating a partially embedded replacement integrated RDL process according to a first exemplary embodiment.

[0011] Figures 4A-4J is a block diagram illustrating a partially embedded replacement integrated RDL process according to a second exemplary embodiment.

[0012] Figure 5A-5G is a block diagram illustrating a fully embedded alternative integrated RDL process according to an exemplary embodiment.

[0013] Fig. 6A is a cross-sectional view of a substrate showing an example of an engineered copper RDL seed post etch.

[0014] Figure 6B is a cross-sectional view of a substrate showing a conventional copper RDL post-seed etch.

[0015] Figure 7 is a flow chart illustrating a method for a partially embedded RDL process according to an exemplary embodiment.

[0016] Figure 8 is a flow chart illustrating a method for a fully embedded RDL process according to an exemplary embodiment. DETAILED DESCRIPTION

[0017] The following description includes systems, methods, techniques, instruction sequences, and computing machine program products that embody illustrative embodiments of the subject matter of the present invention. In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of the exemplary embodiments. However, it will be apparent to those skilled in the art that the provided embodiments may be practiced without these specific details.

[0018] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. The following notice applies to any data contained herein and in the accompanying drawings that constitute a part of this document: Copyright LAM Research Corporation, 2018. All rights reserved.

[0019] In this disclosure, various terms are used to describe semiconductor processing surfaces: "wafer" and "substrate" may be used interchangeably. The process of depositing or plating metal onto the conductive surface of a wafer via an electrochemical reaction is generally referred to as "electrodeposition" or "electroplating."

[0020] This document describes several alternatives to conventional redistribution layer (RDL) processes: three integration schemes and an electroplating process that results in minimized undercutting during the seed etch process. Figure 1A is a cross-sectional view of a substrate before conventional RDL processing. Figure 1B is a cross-sectional view of a substrate after a conventional RDL process. The following figure illustrates the undercut problem.

[0021] Figure 2 is a block diagram of a cross section of a substrate after an RDL process. The substrate 202 is deposited with a barrier layer 204, a copper seed 206, and an ECD copper 208. In the first type of problem, the copper seed 206 below the ECD copper 208 is etched, resulting in an undercut. In the second type of problem, both the copper seed 206 and the base of the electroplated RDL (ECD copper 208) are etched.

[0022] Figures 3A-3J FIG. 1 is a block diagram showing a partially embedded replacement integrated RDL process according to a first exemplary embodiment. Figure 3A At operation 302, a substrate 322 is provided. Figure 3B At operation 304, a dielectric (polyimide, nitride, etc.) layer 324 is applied to the incoming substrate 322. Figure 3C At operation 306, the dielectric layer 324 is patterned. For photosensitive polymer materials (polyimide), this will require exposure, development, and debonding steps. Figure 3D At operation 308, a barrier layer 326 and a copper seed layer 328 are applied on top of the dielectric layer 324. Figure 3E In operation 310, a photoresist layer 330 may be applied to substrate 322. Depending on the photoresist material (spin-on vs. lamination), the photoresist layer 330 may fill the underlying features or simply be placed on top of them. Figure 3E At operation 312, the photoresist layer 330 is exposed, developed, and stripped. In this process flow, the feature size of the pattern matches the feature size in the underlying dielectric, such as Figure 3F As shown in operation 312. Figure 3G At operation 314, a copper layer 322 is electroplated in the patterned area. Figure 3H At operation 316, the photoresist layer 330 is removed. Fig. 3I At operation 318, the copper seed layer 328 and the barrier layer 326 are etched and removed. Figure 3J At operation 320, optionally, the dielectric layer 324 may also be removed. In this integration scheme, the seed etch does not produce undercuts. The seed etch can only remove a small amount of material on the plated RDL side. It can remove the seed between the RDL structure and the barrier.

[0023] The plated RDL thickness can be in the range of 2 μm to 10 μm. For partial embedding, the dielectric layer has a minimum thickness of at least about 0.5 μm. Depending on the final thickness of the RDL, the thickness can range between 5-50%.

[0024] Figures 4A-4J is a block diagram showing a partially embedded replacement integrated RDL process according to a second exemplary embodiment. For the RDL size in the photoresist layer, FIG. 4A to FIG. 4J The process is different from FIG. 3A to FIG. 3J In Figure 4A At operation 402, a substrate 422 is provided. Figure 4B At operation 404, a dielectric layer 424 is deposited on the substrate 422. Figure 4C At operation 406, the dielectric layer 424 is patterned (for polymers: exposure, development, debonding). Figure 4D At operation 408 , a barrier layer 426 and a seed layer 428 are deposited on the dielectric layer 424 and the substrate 422 .

[0025] exist Figure 4E At operation 410, a photoresist layer 430 is applied to substrate 422. Figure 4F At operation 412, photoresist layer 430 is patterned similarly to dielectric layer 424. However, the features in photoresist layer 430 have a larger critical dimension (CD) or width than the corresponding features in dielectric layer 424. Figure 4G At operation 414, copper is electrodeposited 432. Figure 4H At operation 416, the photoresist 430 is removed. Fig. 4I At operation 418, copper seed 426 and barrier layer 424 are etched. Figure 4J At operation 420 , dielectric layer 424 is optionally removed.

[0026] This process results in a thicker RDL pattern near the top. This may be beneficial for maintaining the RDL size after the copper seed etch. This process can also minimize the cut into the sidewall after the seed etch, resulting in an RDL structure with excellent mechanical integrity.

[0027] Figure 5A-5G is a block diagram showing a fully embedded replacement integrated RDL process according to an exemplary embodiment. In this process flow, Figure 5A At operation 502, a substrate 516 is provided. Figure 5B At operation 504, a dielectric (polyimide, nitride, etc.) layer 518 is applied to the incoming substrate 516. Figure 5C At operation 506, the dielectric layer 518 is patterned. For photosensitive polymer materials (polyimide), the process includes exposure, development, and debonding steps. Figure 5D At operation 508, a barrier layer 520 and a copper seed layer 522 are applied over the patterned dielectric layer 518 and over the exposed surface of the substrate 516. Figure 5EAt operation 510, copper is electroplated 524 in the patterned areas. Fig. 5F At operation 512 , copper 524 is planarized. Figure 5G At operation 514 in FIG. , the evolution of electroplating is shown.

[0028] Fig. 6A is a cross-sectional view of a substrate showing an example of grain engineering. Cross section 604 shows substrate 610, barrier layer 608, and copper layer 606. To minimize seed etch effects, a stronger, more robust electroplated copper may be required. Various process parameters may be used for engineering including waveform, convection, and chemical reaction.

[0029] Some copper grain structures that can be engineered to exhibit etch resistance include large grains, columnar grains, and nanotwinned grains. For example, nanotwinned copper has previously been shown to have high tensile strength, excellent electrical conductivity, and high electromigration resistance. If formed early in the electroplating process, the engineered grain structure (including nanotwins) can reduce erosion of the electroplated copper, although it will not reduce undercutting of the copper seed layer beneath the RDL structure. In the above alternative process scheme described in detail above, grain engineered copper can minimize etching of the sides of the electroplated RDL structure. This will maintain the pattern size and mechanical integrity of the RDL

[0030] Figure 6B is a cross-sectional view of a substrate showing an example of a conventional copper RDL seed post etch. Cross section 604 shows an undercut 612 in copper 606 in a conventional copper RDL seed post etch.

[0031] Figure 7 7 is a flow chart showing a method for a partially embedded RDL process according to an exemplary embodiment. In operation 702, a substrate is provided. In operation 704, a dielectric (polyimide, nitride, etc.) is applied to the substrate. In operation 706, the dielectric layer is patterned. For photosensitive polymer materials (polyimide), this will require exposure, development, and degumming steps. In operation 708, a barrier layer and a copper seed layer are applied on top of the layer dielectric layer. In operation 710, a photoresist process is applied to the substrate. In operation 710, the photoresist is exposed, developed, and degummed. In this process flow, the feature size of the patterning will match the feature size in the underlying dielectric. In operation 712, copper is electroplated in the patterned area. In operation 714, the photoresist is removed. In operation 716, the copper seed and the blocking etchant are removed. In operation 718, optionally, the dielectric layer can also be removed. In this integration scheme, seed etching does not produce undercuts.

[0032] Figure 8802 is a flow chart illustrating a method for a fully embedded RDL process according to an exemplary embodiment. At operation 804, a substrate is provided. At operation 806, a dielectric layer is patterned. For photosensitive polymer materials (polyimide), this will require exposure, development, and debonding steps. At operation 808, a barrier layer and a copper seed layer are deposited on top of the dielectric layer. At operation 810, copper is electroplated in the patterned area. At operation 812, the copper (or copper / dielectric layer) is planarized.

[0033] Although the embodiments have been described with reference to specific exemplary embodiments, it is obvious that various modifications and changes can be made to these embodiments without departing from the scope of the present disclosure. Therefore, the description and the drawings should be considered illustrative rather than restrictive. The drawings forming a part thereof show, by way of illustration and not limitation, specific embodiments in which the present subject matter can be practiced. The illustrated embodiments are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments and other embodiments derived therefrom can be utilized so that structural and logical replacements and changes can be made without departing from the scope of the present disclosure. Therefore, this specific embodiment should not be understood in a limiting sense, and the scope of the various embodiments is limited only by the appended claims and the full scope of the equivalent schemes given by these claims. Such embodiments of the subject matter of the invention may be referred to herein individually and / or collectively by the term "invention", which is only for convenience and is not intended to automatically limit the scope of the present application to any single invention or inventive concept (if multiple are actually disclosed). Therefore, although specific embodiments have been illustrated and described herein, it should be understood that any arrangement calculated to achieve the same purpose can replace the specific embodiments shown. The present disclosure is intended to cover all modifications or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.

[0034] Example:

[0035] Embodiment 1 is a method for a redistribution layer (RDL) process, the method comprising: depositing a dielectric layer on a surface of a substrate; patterning the dielectric layer, the patterned dielectric layer exposing an area of ​​the surface of the substrate; depositing a protective layer on the patterned dielectric layer and the exposed area of ​​the surface of the substrate; depositing a photoresist layer on the protective layer; patterning the photoresist layer, the patterned photoresist layer exposing a first area of ​​the protective layer; electro-depositing a copper layer on the exposed first area of ​​the protective layer; removing the patterned photoresist layer to expose a second area of ​​the protective layer; and removing the exposed second area of ​​the protective layer to expose the patterned dielectric layer.

[0036] Embodiment 2 includes the method of embodiment 1, further comprising removing the exposed patterned dielectric layer to expose a region of the surface of the substrate.

[0037] Embodiment 3 includes the method of Embodiment 2, wherein a size of features in the patterned photoresist layer is larger than a size of features in the patterned dielectric layer.

[0038] Embodiment 4 includes the method of Embodiment 1, wherein a size of features in the patterned photoresist layer is smaller than a size of features in the patterned dielectric layer.

[0039] Embodiment 5 includes the method of embodiment 1, wherein the protective layer includes a barrier layer and a copper seed layer, and the copper seed layer is on the barrier layer.

[0040] Embodiment 6 includes the method of embodiment 1, wherein the dielectric layer comprises a photosensitive polyimide layer or a nitride layer.

[0041] Embodiment 7 includes the method of embodiment 6, wherein patterning the dielectric layer further comprises: forming the patterned dielectric layer using exposure, development, and resist removal processes.

[0042] Embodiment 8 includes the method of Embodiment 1, wherein dimensions of features of the patterned photoresist layer match dimensions of features of the underlying patterned dielectric layer.

[0043] Embodiment 9 includes the method of embodiment 1, wherein depositing the photoresist layer on top of the protective layer further comprises: filling features of the patterned dielectric layer with the photoresist layer.

[0044] Embodiment 10 includes the method of Embodiment 1, wherein the photoresist layer is located over the features of the patterned dielectric layer and does not fill the features of the patterned dielectric layer.

Claims

1. A method for a redistribution layer (RDL) process, the method comprising: depositing a dielectric layer on a surface of the substrate; patterning the dielectric layer, the patterned dielectric layer exposing regions of the surface of the substrate; depositing a protective layer over the patterned dielectric layer and the exposed areas of the surface of the substrate; depositing a photoresist layer on the protective layer; patterning the photoresist layer, wherein the patterned photoresist layer exposes a first region of the protective layer; electrodepositing a copper layer on the exposed first region of the protective layer; removing the patterned photoresist layer to expose a second region of the protective layer; removing the exposed second region of the protective layer to expose the patterned dielectric layer; as well as By removing the exposed patterned dielectric layer, a region of the surface of the substrate and a barrier layer of the protective layer are exposed along a bottom of the sidewall of the copper layer.

2. The method according to claim 1, wherein: The size of features in the patterned photoresist layer is larger than the size of features in the patterned dielectric layer.

3. The method according to claim 1, wherein: The size of features in the patterned photoresist layer is smaller than the size of features in the patterned dielectric layer.

4. The method according to claim 1, wherein: The protection layer includes the barrier layer and a copper seed layer, and the copper seed layer is on the barrier layer.

5. The method according to claim 1, wherein: The dielectric layer includes a photosensitive polyimide layer or a nitride layer.

6. The method of claim 5, wherein patterning the dielectric layer further comprises: The patterned dielectric layer is formed using exposure, development and resist removal processes.

7. The method according to claim 1, wherein: The dimensions of the features of the patterned photoresist layer match the dimensions of the features of the underlying patterned dielectric layer.

8. The method of claim 1, wherein depositing the photoresist layer on top of the protective layer further comprises: The features of the patterned dielectric layer are filled with the photoresist layer.

9. The method according to claim 1, wherein: The photoresist layer is located over the features of the patterned dielectric layer and does not fill the features of the patterned dielectric layer.

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