Multi-chip package structure with chip interconnect bridges providing power connection between chips and package substrate

Abstract

A multi-chip package structure and a method for constructing a multi-chip package structure are provided, which utilize a chip interconnect bridge device designed to provide a high interconnection density between adjacent chips (or bare dies) in the package structure, and provide vertical power distribution traces through the chip interconnect bridge device to supply power (and ground) connections from a package substrate to the chips connected to the chip interconnect bridge device.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor packaging technology, and in particular to a multi-chip package structure implementing a chip interconnect bridge device. Background Art

[0002] Innovations in semiconductor manufacturing and packaging technology have enabled the development of smaller-scale, higher-density integrated circuit (IC) chips (or bare die), as well as the development of highly integrated chip modules with wiring and area array input / output (I / O) contact density that enable dense packaging of IC chips (or bare die). For some applications, high-performance electronic modules are constructed with one or more multi-chip modules (MCMs) mounted to a circuit board (e.g., a system board (or node card), a printed circuit board, a printed wiring board, etc.) using suitable area array connection technology for module-to-board I / O interconnection (e.g., land grid array (LGA) or ball grid array (BGA) connection). MCM technology can be used to form a first-level packaging structure with high-density packaging of multiple IC processor chips for computer server applications or multiple heterogeneous chips for custom applications, etc.

[0003] MCM packaging structure can be constructed using different conventional techniques. For example, MCM can be constructed by directly connecting a plurality of semiconductor IC bare chips to a packaging substrate. These semiconductor IC bare chips can be connected to the surface of the packaging substrate using wire bonding, tape bonding or flip-chip bonding. For high-performance and high-density packaging, direct chip attachment (DCA) technology is usually used to form a regional array of solder interconnections between the contact pads formed on the active surface of the semiconductor IC bare chip and the matching array of the contact pads formed on the chip mounting surface (or top side surface) on the packaging substrate to flip-chip bond the IC bare chip to the packaging substrate. The packaging substrate includes wiring for providing a die-to-die connection between the IC bare chips mounted on the top side of the packaging substrate and wiring for connecting the top side contact pads to the bottom side contact pads.

[0004] In conventional MCM technology, the package substrate can be, for example, a glass ceramic substrate, or a laminated substrate. For example, a multilayer ceramic package substrate can be manufactured using low temperature co-fired ceramic (LTCC) substrate technology. In addition, a laminated package substrate can be manufactured using surface laminated circuit (SLC) technology to manufacture a low-cost organic package substrate with a built-in layer that is vertically connected by micro-vias to support solder bump flip chips.

[0005] There is a continuous need for IC chips with increased integrated functionality and smaller footprint sizes, which leads to an increase in the I / O count and I / O density of IC chips. In addition, high-performance and high-density integrated packaging solutions typically require small microbumps for flip-chip connections, which use, for example, interconnect pitches of 50 microns or less and line width and line spacing design rules of 10 microns or less. Although the MCM packaging structure allows heterogeneous IC dies to be directly connected (e.g., DCA) to each other through a packaging substrate, conventional ceramic-based packaging substrates and laminated substrate technologies are limited in terms of the minimum achievable contact pad spacing, line width, and line spacing. As such, conventional ceramic and organic stacked construction substrates are bottlenecks for high-density packaging because such substrate technologies cannot support the tight spacing required for high-density I / O flip-chip connections and high-density die-to-die interconnects.

[0006] To address these limitations, 2.5-D packaging technology is utilized to increase I / O density and provide high-density routing for low-power die-to-die communications. Typically, 2.5-D integration involves flip-chip bonding of multiple IC dies on a passive interposer substrate (e.g., silicon, glass, or fine-pitch organic fabrication substrate), which is bonded to a package substrate. Interposers include finer pitch routing, higher contact pad density, and shorter distances for die-to-die interconnects than package substrates.

[0007] Silicon interposers for 2.5D packaging consist of a thin layer of silicon disposed between the IC die and the package substrate and including through-silicon vias (TSVs) to provide a platform with high wiring density for I / O redistribution and die-to-die communication. Silicon interposers require large and expensive silicon chips with TSVs to accommodate multiple chips on the top surface. Unfortunately, silicon interposers are expensive due to the need for silicon interposer chip size to accommodate the footprint of multiple dies attached to the surface of the silicon interposer and due to the use of TSV technology which increases manufacturing cost and complexity.

[0008] On the other hand, fine-pitch organic construction interposers for 2.5D packaging utilize thin-film technology to construct fine-pitch organic redistribution layers on top of conventional organic laminate substrates. While fine-pitch organic redistribution layers provide the platform with high wiring density for I / O redistribution and die-to-die communication, this technology is limited in the number of fine-pitch redistribution layers and the minimum line spacing that can be achieved compared to silicon-based interposer solutions.

[0009] Other 2.5D packaging solutions utilize silicon bridge devices embedded in the package substrate to provide tighter interconnect density between adjacent dies. Silicon bridge devices are less expensive than conventional silicon interposers because they are much smaller (they only connect to the peripheral area of ​​adjacent dies) and do not utilize expensive TSVs. Although silicon bridge devices are simple in form, conventional bridge devices are designed to contain only wiring for die-to-die interconnection, and do not contain wiring for, for example, vertical power distribution from the package substrate through the bridge device to the die.

[0010] However, as the functionality and density of IC die increase, the number of power pins and ground pins needs to be increased to minimize ground bounce. As such, IC die are typically manufactured with power / ground pads dispersed over an area array of I / O contact pads on the back of the IC die. When silicon bridge devices are used for high-density die-to-die I / O interconnects, the bridge device blocks the vertical power distribution through the bridge structure to the power / ground pads arranged in the high-density I / O area of ​​the IC die overlapped by the bridge device. As such, connections to such power / ground pads must be made from the package substrate to other areas of the IC die that are not overlapped by the bridge device, and then routed through the IC die (and through lateral interconnects in the bridge device) to the power / ground pads blocked by the bridge device. This configuration increases the length of the power / ground traces, thereby increasing the voltage drop and IR heating within the package substrate. Summary of the invention

[0011] Embodiments of the present invention include multi-chip packaging structures that include chip interconnect bridge devices that are designed to provide high I / O interconnect density between adjacent chips in the packaging structure, and to provide vertical power distribution traces through the chip interconnect bridge devices to supply power (and ground) connections from a packaging substrate to chips connected to the chip interconnect bridge devices. For example, one embodiment includes a packaging structure that includes a packaging substrate, an interconnect bridge device connected to the packaging substrate, a first integrated circuit die connected to the interconnect bridge device and the packaging substrate, and a second integrated circuit die connected to the interconnect bridge device and the packaging substrate. The interconnect bridge device includes wiring for providing die-to-die connections between the first and second integrated circuit dies, and wiring for providing package-to-die connections between the packaging substrate and the first and second integrated circuit dies, wherein the package-to-die connections include power connections.

[0012] Other embodiments will be described in the following detailed description of the embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A multi-chip package structure including a chip interconnection bridge device according to an embodiment of the present invention is schematically shown.

[0014] Figure 2 A multi-chip package structure including a chip interconnection bridge device according to another embodiment of the present invention is schematically illustrated.

[0015] Figure 3 is a cross-sectional side view of a bridge wafer at an intermediate stage of fabrication, wherein an initial layer of the backside of the bridge wafer including bond pads is formed on a first temporary carrier substrate.

[0016] Figure 4 After forming the stack of signal interconnects and redistribution layers including fine pitch signal lines and vertical interlayer vias Figure 3 Cross-sectional side view of the bridge wafer.

[0017] Figure 5 After forming the stack of power distribution layers including coarse pitch wiring of the bridge wafer, vertical interlayer vias and topside bonding pads Figure 4 Cross-sectional side view of the bridge wafer.

[0018] Figure 6 After forming flip chip bumps on top side bond pads of bridge wafer Figure 5 Cross-sectional side view of the bridge wafer.

[0019] Figure 7 After bonding the second temporary carrier substrate to the front side of the bridge wafer Figure 6 Cross-sectional side view of the bridge wafer.

[0020] Figure 8 after removing the first temporary carrier substrate from the back side of the bridge wafer, forming solder bumps on the bonding pads on the back side of the bridge wafer, and dicing the bridge wafer and the second temporary carrier substrate to form individual chip interconnect bridge devices Figure 7 Cross-sectional side view of the bridge wafer.

[0021] Fig. 9 is a cross-sectional side view of a package structure in an intermediate stage of assembly, wherein: Figure 8 The chip interconnect bridge device is connected to the package substrate.

[0022] Fig.10 After removing the remaining portion of the second temporary carrier substrate from the chip interconnect bridge and connecting a plurality of IC chips to the chip interconnect bridge device and the package substrate Fig. 9 A cross-sectional side view of a package structure.

[0023] Fig.11 After dicing the bridge wafer and the first temporary carrier substrate to form individual chip interconnect bridge devices Figure 6 Cross-sectional side view of the bridge wafer.

[0024] Fig.12 is a cross-sectional side view of a package structure at an intermediate stage of assembly, wherein a plurality of IC chips mounted to a temporary chip carrier substrate are connected to Fig.11 Chip interconnect bridge device.

[0025] Fig.13 After removing the remaining portion of the first temporary carrier substrate from the bottom side of the chip interconnect bridge device and connecting the assembly of the IC chip and the chip interconnect bridge device to the package substrate Fig.12 A cross-sectional side view of a package structure.

[0026] Fig.14 is a plan view of a backside surface of an IC chip showing an arrangement of alignment pads for chip alignment using a layered soldering process to assemble a package structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] Embodiments of the present invention will now be discussed in more detail with respect to a multi-chip package structure that includes chip interconnect bridge devices designed to provide high I / O interconnect density between adjacent chips in the package structure, and to provide vertical power distribution traces through the chip interconnect bridge devices to supply power (and ground) connections from the package substrate to the chips connected to the chip interconnect bridge devices. It should be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations that are not drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions that are typically used to form a certain type of semiconductor device or structure may not be explicitly shown in a given drawing. This does not mean that any layers, structures, and regions that are not explicitly shown are omitted from the actual semiconductor structure.

[0028] Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and process steps shown and described herein. Specifically, with respect to semiconductor process steps, it is emphasized that the descriptions provided herein are not intended to cover all process steps that may be required to form a functional semiconductor integrated circuit device. Rather, for economy of description, certain process steps that are typically used to form semiconductor devices, such as wet cleaning and annealing steps, are purposely not described herein.

[0029] In addition, throughout the drawings, the same or similar reference numbers are used to represent the same or similar features, elements, or structures, and therefore, the detailed description of the same or similar features, elements, or structures will not be repeated for each drawing. It should be understood that the terms "about" or "substantially" as used herein with respect to thickness, width, percentage, range, etc. are intended to mean close or approximate, but not exactly. For example, the terms "about" or "substantially" as used herein imply that there may be a small margin of error, such as less than 1% or less of the specified amount.

[0030] Figure 1 A multi-chip package structure including a chip interconnect bridge device according to an embodiment of the present invention is schematically shown. Specifically, Figure 1 The package structure 100 is schematically illustrated and includes a package substrate 110, first and second chip interconnect bridge devices 120 and 130 (or “bridge devices”), a plurality of IC dies 140, 142, and 144, and a package cover 150. A bonding layer 152 (e.g., epoxy glue) bonds the package cover 150 to a peripheral surface area on the top side of the package substrate 110. An underfill material 160 is disposed between the IC dies 140, 142, 144 and the package substrate 110, and a thermal interface material 162 is disposed between the top sides of the IC dies 140, 142, and 144 and the package cover 150. The bottom fill material 160 includes an electrically insulating adhesive material for maintaining the structural integrity of the flip chip connections between (i) the IC die 140, 142, 144 and the package substrate 110, (ii) the IC die 140, 142, 144 and the bridge devices 120 and 130, and (iii) the bridge devices 120 and 130 and the package substrate 110. In alternative embodiments, the bottom fill material 160 can be composed of different bottom fill material layers, for example, one bottom fill material layer in the bridge area and another bottom fill material layer outside the bridge area. The thermal interface material 162 includes a thermally conductive paste designed to conduct the heat energy generated by the IC die 140, 142 and 144 to the package cover 150, wherein the package cover 150 acts as a heat sink to dissipate the heat energy and cool the IC die 140, 142 and 144.

[0031] For heterogeneous packaging applications, IC dies 140, 142, and 144 may include any type of integrated circuits and systems for implementing a given application. For illustrative purposes, Figure 1 The exemplary package structure 100 of FIG. 1 shows three IC dies, wherein a first IC die 140 includes a high bandwidth memory (HBM) dynamic random access memory (DRAM) device, a second IC die 142 includes a hardware accelerator device, and wherein a third IC die 144 includes a multi-core processor device. In other embodiments, the IC dies 140, 142, and 144 (and other additional IC dies) may include one or more memory devices, central processing units (CPUs), microcontrollers, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and other types of general-purpose processors or workload-optimized processors, such as graphics processing units (GPUs), digital signal processors (DSPs), systems on chips (SoCs), and other types of specialized processors or coprocessors configured to perform one or more fixed functions.

[0032] The package substrate 110 may be a ceramic substrate, a silicon substrate, or an organic laminate build substrate, or any other type of package substrate technology suitable for a given application. The package substrate 110 includes an area array of solder ball interconnects 112 (e.g., ball grid array (BGA) solder interconnects) formed on the bottom side of the package substrate 110, a network of package traces 114 extending vertically and horizontally through the package substrate 110, and a first cavity 116 and a second cavity 118 formed in the top side of the package substrate 110. Figure 1 In the exemplary embodiment of FIG. 1 , the first bridge device 120 is disposed in the first cavity 116 of the package substrate 110 , and the second bridge device 130 is disposed in the second cavity 118 of the package substrate 110 .

[0033] The first bridge device 120 is connected to the first and second IC dies 140 and 142 using an area array of flip chip bump connections 170, and the second bridge device 130 is connected to the second and third IC dies 142 and 143 using an area array of flip chip bump connections 172. Further, the first bridge device 120 is connected to the surface of the package substrate 110 at the bottom of the first cavity 116 using an area array of flip chip bump connections 180. Similarly, the second bridge device 130 is connected to the surface of the package substrate 110 at the bottom of the second cavity 118 using an area array of flip chip bump connections 182. The IC dies 142 and 144 are connected to the top side of the package substrate 110 using corresponding area arrays of flip chip bump connections 184 and 186.

[0034] In one embodiment, the area array of flip chip bump connections 170 and 172 includes micro bumps for high density I / O signal communication between adjacent dies, wherein, depending on the application, the flip chip micro bump connections 170 and 172 are formed with a contact pitch of about 55 microns or less. Further, flip chip bump connections 180, 182, 184 and 186 include I / O connections between (i) package substrate 110 and bridge devices 120 and 130 and (ii) package substrate 110 and IC dies 142 and 144. In one embodiment, flip chip bump connections 180, 182, 184 and 186 have a coarser pitch than flip chip bump connections 170 and 172. In another embodiment, flip chip bump connections 184 and 186 include fine pitch micro bump connections. In one embodiment, depending on the application, the area array of flip chip bump connections 180, 182, 184 and 186 is formed to have a contact pitch of about 75 microns or greater. An area array of solder ball interconnects 112 (eg, BGA C4) on the bottom side of the package substrate 110 is formed with a contact pitch of about 300 microns or more, depending on the application.

[0035] The first bridge device 120 includes fine pitch wiring 122 for connecting the area array of microbumps 170 to provide high density, high bandwidth I / O connectivity between the first and second IC dies 140 and 142. Similarly, the second bridge device 130 includes fine pitch wiring 132 for connecting the area array of microbumps 172 to provide high density, high bandwidth I / O connectivity between the second and third IC dies 142 and 144. The fine pitch wiring 122 and 132 of the bridge devices 120 and 130 can be formed with sub-micron line width and line spacing design rules using bridge manufacturing technology discussed in further detail below.

[0036] In addition, the first bridge device 120 includes vertical distribution traces 124 to provide direct power and ground connections from the package substrate 110 through the first bridge device 120 to the first IC die 140 and / or the second IC die 142. Similarly, the second bridge device 130 includes vertical distribution traces 134 to provide direct power and ground connections from the package substrate 110 through the second bridge device 130 to the second IC die 142 and / or the third IC die 144. As described above, with high density IC die functions and I / Os, multiple power and ground pads can be included within the area arrays of microbumps 170 and 172 of the IC dies 140, 142, and 144 to minimize ground bounce.

[0037] exist Figure 1 In the package structure of FIG. 1 , the first and second bridge devices 120 and 130 are designed to provide vertical power / ground distribution to power / ground pads arranged in high-density I / O area arrays 170 and 172 of IC dies 140, 142, and 144 through the bridge devices 120 and 130, and the vertical power / ground distribution is covered by the bridge devices 120 and 130. As such, the connection to such power / ground pads in the high-density I / O area arrays 170 and 172 of IC dies 140, 142, and 144 can be made directly from the package to the die through the bridge devices 120 and 130. For example, as Figure 1 As shown, the power / ground connection to the first IC die 140 can be routed along a path from the package trace 114 of the package substrate 110, to the flip chip connection 180 between the package substrate 110 and the first bridge device 120, through the first bridge device 120 to the vertical trace 124, and to the first IC die 140 through the flip chip connection 170 between the first bridge device 120 and the first IC die 140.

[0038] This does not include Figure 1 The vertical distribution traces 124 and 134 are shown in the opposite of the conventional bridge device. For example, assuming Figure 1The first bridge device 120 in the embodiment does not include vertical power / ground distribution wiring 124, and the area array of flip chip connections 170 to the first IC die 140 includes power / ground connections. In this case, the power / ground connections to the first IC die 140 will have to be routed along a path from the package traces 114 of the package substrate 110, to the flip chip connections 184 between the second IC die 142 and the package substrate 110, to the distribution wiring between the flip chip connections 184 and the flip chip connections 170 at the periphery of the second IC die 142, and to the power / ground connections within the area array of flip chip connections 170 of the first IC die 140 through the redistribution wiring 122 of the first bridge device 120. This conventional configuration will significantly increase the length of the power / ground traces (compared to the direct connection from the package to the die through the first bridge device 120 as described above).

[0039] Although for the sake of convenience, Figure 1 1 and 2, the flip chip bump connections 170, 172, 180, 182, 184, and 186 are generally described in the figure, but it should be understood that any suitable flip chip bump technology can be used to implement the flip chip bump connections 170, 172, 180, 182, 184, and 186. For example, the flip chip bump connections 170, 172, 180, 182, 184, and 186 can be implemented using a controlled collapse chip connection (C4) flip chip bump technology, wherein solder balls are formed on ball limit metallurgy (BLM) pads or under bump metallization (UBM) pads. The solder balls can be formed by solder paste printing or electroplating. In other embodiments, the flip chip bump connections 170, 172, 180, 182, 184, and 186 can be chip connections (C2) bumps including metal pillar structures (e.g., copper pillars) formed on metal pads. The metal pillar bump structures may or may not have solder end caps.In other embodiments, flip chip bump connections 170, 172, 180, 182, 184, and 186 may be C2 bumps with plated metal formed on UBM pads.

[0040] In other embodiments, solder microbumps including Cu and Sn may be electroplated on UBM pads, wherein the UBM pads include electroless nickel and immersion gold. The joining of two flip chip components may be performed by joining the CuSn solder microbumps on one flip chip component to the UBM pads on the other flip chip component or by joining the CuSn solder microbumps on one flip chip component to the CuSn solder microbumps on the other flip chip component. In other embodiments, an area array of copper pillar bumps on one flip chip component may be joined to an area array of solder balls on another flip chip component. In addition, an area array of high temperature solder bumps formed on the UBM pads on one flip chip component may be joined to an area array of low temperature solder bumps formed on the contact pads of another flip chip component.

[0041] like Figure 1 As further shown in , in some embodiments, the footprint of the first IC die 140 (e.g., HBMDRAM) completely or substantially overlaps the interconnect bridge device 120, so that all input / output, power / ground, and other connections between the first integrated circuit die 140 and the package substrate 110 are routed through the interconnect bridge device 120. In some embodiments of the package structure, there may be a small IC die (relative to a large IC die such as an accelerator (e.g., GPU)) that has a bridge device that fully supports the footprint of the smaller IC die while only partially overlapping the larger IC die. In this case, the bridge device can be irregularly shaped (e.g., non-rectangular) to accommodate both the smaller and larger IC die attached to the bridge. There are different advantages to forming a bridge device that fully supports the small IC die. For example, for a small IC die such as an HBM DRAM, the spacing between various areas of the bump footprint can be very small (e.g., the spacing between the power area and the signal I / O area can be 75 microns or less). This close spacing between the bump areas makes it very difficult to mount a small IC die to a bridge device using only a portion of the bump footprint of the small IC die while still accommodating the bumps with the package laminate substrate outside the area of ​​the bridge device. In this case, it may not be possible to engage some of the bumps near the edge of the bridge device. In addition, for an IC die with all microbumps, it may be difficult to flip-chip mount the IC die to both the bridge device and the package laminate substrate with microbumps because they are both at a fine pitch. Therefore, in this case, it is easier to flip-chip mount the entire IC die to the bridge device.

[0042] Figure 2 A multi-chip package structure including a chip interconnect bridge device according to another embodiment of the present invention is schematically shown. Specifically, Figure 2 Schematically shows a diagram similar to Figure 1 The package structure 100 is a package structure 200, except that Figure 2 In the package structure 200 , the first bridge device 120 and the second bridge device 130 are mounted to the top side of the package substrate 110 as compared to being disposed and mounted within the recessed cavities 116 and 118 of the package substrate 110 .

[0043] In addition, Figure 2 In the exemplary embodiment shown in , the area array of flip chip connections 184 and 186 between the IC dies 142 and 144 and the package substrate 110 includes a standoff structure 210 formed on the top side of the package substrate 110 to offset the height of the bridge devices 120 and 130. In addition, larger diameter solder bumps (or taller bump structures) 212 can be formed on the area array contact pads on the back side of the IC dies 142 and 144 to offset the height of the bridge devices 120 and 130. In one embodiment, as shown in FIG. Figure 2 As schematically shown, standoff structure 210 includes solder coated copper balls disposed on area array contact pads formed on the top side of package substrate 110. In another embodiment, standoff structure 210 may include copper pillars, or copper pillars with solder end caps, or other types of standoff structures suitable for a given application.

[0044] Now we will see Figures 4 to 14 Different methods for manufacturing a chip interconnect bridge and constructing a multi-chip package structure including a chip interconnect bridge are discussed in further detail. Typically, an interconnect bridge according to an embodiment of the present invention is formed on a temporary carrier substrate using wafer level fan-out (WLFO) technology in combination with a back-end of line (BEOL) manufacturing method and common BEOL dielectric and metal materials to form a bridge structure including multiple wiring layers and interlayer vias, which provide high-density die-to-die interconnect wiring for high-bandwidth I / O communication between packaged dies, and a redistribution layer for routing power / ground connections from the bottom-side flip-chip connection to the package substrate through the bridge structure to the top-side flip-chip connection to the IC die. In addition, in one embodiment, a "chip first" package assembly process is implemented, which includes flip-chip bonding a bridge device to two or more IC dies, and then flip-chip bonding the assembly of the bridge device and the IC die to the package substrate. In another embodiment, a "chip last" package assembly process is implemented that includes flip-chip bonding a bridge device to a package substrate, and then flip-chip bonding two or more IC dies to the assembly of the bridge device and package substrate.

[0045] Specifically, Figures 3 to 10 The process for manufacturing a bridge device and a "last chip" package assembly process according to an embodiment of the present invention are schematically shown. First, Figure 3is a cross-sectional side view of a bridge wafer at an intermediate stage of fabrication, wherein an initial layer of the back side of the bridge wafer including bond pads is formed on a first temporary carrier substrate. Specifically, Figure 3 A first temporary carrier substrate 300 (or carrier wafer) is shown on which a bridge wafer including a plurality of individual bridge devices will be formed using WLFO and BEOL process technologies. For example, the first temporary carrier substrate 300 may be a glass substrate or a silicon substrate. In addition, Figure 3 An initial stage of bridge wafer formation is shown, wherein an adhesive layer 302 is applied on the surface of a first temporary carrier substrate 300. The adhesive layer 302 is formed of any suitable adhesive material (e.g., epoxy) that acts as a release layer that can be ablated or evaporated using a suitable release technique (e.g., IR laser ablation) to release the first temporary carrier substrate 300 at a later stage in the manufacturing process flow. In another embodiment, when the first temporary carrier substrate 300 comprises a silicon carrier substrate, the bridge wafer can be formed directly on the surface of the silicon carrier substrate (without the adhesive layer 302) so that the silicon carrier substrate can be subsequently removed using a silicon grinding process. When bonded to the bridge wafer using an adhesive layer, a variety of techniques (e.g., laser ablation) can be used to release the glass or silicon carrier substrate.

[0046] Next, a bonding pad layer 310 is formed on the adhesive layer 302. The bonding pad layer 310 includes a passivation layer 312 and an area array of bonding pads 314. In one embodiment, the bonding pad layer 310 is formed by depositing and patterning a dielectric / insulating material layer (as the passivation layer 312) to form trenches, and depositing a metal material layer (e.g., copper) to fill the trenches with the metal material to form the bonding pads 314. A chemical mechanical polishing (CMP) process is then performed to remove excess metal material and flatten the bonding pad layer 310 down to the surface of the passivation layer 312. In another embodiment, the passivation layer 312 may include an organic polymer material. Although for ease of illustration, the bonding pad layer 310 is formed by depositing and patterning a dielectric / insulating material layer (as the passivation layer 312) to form trenches, and depositing a metal material layer (e.g., copper) to fill the trenches with the metal material to form the bonding pads 314. Figure 3 , but the bond pad layer 310 is formed to include an area array of bottom side bond pads for a plurality of bridge devices of the bridge wafer. In an alternative embodiment, the bond pad layer 310 may be formed using a backside process module after removing the first temporary carrier substrate 300. In yet another embodiment, the bridge wafer may include a stack of organic redistribution layers formed on the backside of the bridge wafer in addition to or in lieu of forming a redistribution layer formed on the front side of the bridge wafer.

[0047] Next, Figure 4 After forming a stack of signal interconnects and redistribution layers 320 including fine pitch signal lines and vertical interlayer vias Figure 33. A cross-sectional side view of a bridge wafer of FIG. 3. Specifically, the stack of signal interconnect and redistribution layers 320 includes a plurality of metallization layers and metal interconnect structures, the plurality of metallization layers including an interlayer dielectric (ILD) layer 322, the metal interconnect structure including vertical vias 324 (and associated via ground pads) and horizontal wiring 326 embedded in the ILD layer 322. The ILD layer 322 can be formed using dielectric materials commonly used for BEOL manufacturing, including but not limited to silicon oxide, hydrogenated silicon oxycarbide (SiCOH), SiCH, SiCNH or other types of silicon-based low-k dielectrics (e.g., k less than about 4.0), porous dielectrics or known ULK (ultra-low-k) dielectric materials (k less than about 2.5). The ILD layer 322 can be deposited using known deposition techniques, such as atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), or spin-on deposition.

[0048] The vertical vias 324 and horizontal wiring 326 embedded in the ILD layer 322 together provide high-density die-to-die I / O interconnects and redistribution wiring for connecting the bottom side bonding pads 312 to the top side bonding pads of the bridge wafer. The vertical vias 324 and horizontal wiring 326 (including via ground pads) can be formed using metal materials commonly used in BEOL manufacturing (including but not limited to copper, cobalt, ruthenium, etc.). For example, in one embodiment, the vertical vias 324 and horizontal wiring 326 are formed with copper using a single and / or dual damascene metallization process. In addition, depending on the dielectric and metal materials used to form the ILD layer 322 and the vertical vias 324 and horizontal wiring 326, a thin diffusion barrier layer and seed layer can be deposited to the line trenches formed in the ILD layer 322 before metal deposition using known materials and deposition techniques.

[0049] Next, Figure 5 After forming the stack of power distribution layers 330 Figure 4330 . A cross-sectional side view of a bridge wafer of FIG. 330 , the power distribution layer including coarse pitch wiring, vertical interlayer vias, and topside bonding pads of the bridge wafer. Specifically, the stack of power distribution layers 330 includes a plurality of insulating layers 332 and a metal interconnect structure including vertical vias 334 (and associated via grounding pads), horizontal wiring 336, and topside bonding pads 338. In one embodiment, the stack of power distribution layers 330 is formed using standard organic laminate build layers, wherein the insulating layer 332 is formed of an organic material (e.g., polyimide, FR4, etc.). The use of organic build-up layers facilitates the fabrication of thicker wiring and interconnects for the purpose of power distribution through the bridge structure, while also providing vertical via connections from the topside pads 338 to the stack of signal interconnects and redistribution layers 320. In other embodiments, the stack of power distribution layers 330 may be fabricated using standard BEOL fabrication methods using design rules that differ from the BEOL processes used to fabricate the stack of signal interconnects and redistribution layers 320. Figure 5 The resulting bridge wafer structure shown includes a thickness T in a range from about 50 microns to about 70 microns.

[0050] Figure 6 After forming flip chip bumps 340 on top side bonding pads 338 of the bridge wafer Figure 5 340. The flip chip bumps 340 may be formed using one of a variety of techniques. For example, the flip chip bumps 340 may be C4 solder bumps formed on UBM or BLM pads. In another embodiment, the flip chip bumps 340 may be electroplated bumps (e.g., nickel, copper, gold, tin-plated bumps) formed on the bonding pads 338 using chemical plating techniques. In another embodiment, the flip chip bumps may be copper pillar structures with or without solder end caps.

[0051] Next, Figure 7 After bonding the second temporary carrier substrate 360 ​​to the front side of the bridge wafer Figure 6 Specifically, Figure 7 An exemplary embodiment is shown in which a releasable adhesive layer 350 is applied to the top side of the bridge wafer, and in which a second temporary carrier substrate 360 ​​is bonded to the bridge wafer via the adhesive layer 350. The second temporary carrier substrate 360 ​​is an optional structure used when backside processing is required (e.g., grinding away the first temporary carrier substrate 300 and adhesive layer 302, or forming flip chip bumps on the bottom side bond pads 314, etc.). In another embodiment, when backside processing of the bridge wafer is not required, the bridge wafer can be mounted face down on a wafer dicing tape, followed by removing the first temporary carrier substrate 300 and dicing the bridge wafer into individual bridge devices.

[0052] Figure 8After removing the first temporary carrier substrate 300 from the back side of the bridge wafer Figure 7 , forming solder bumps 370 (e.g., C4 solder bumps) on the bonding pads 314 on the back side of the bridge wafer, and cutting the bridge wafer and the second temporary carrier substrate 360 ​​along the cut line D (shown by the dashed line) to form a separate chip interconnect bridge device 400. In an alternative embodiment of the assembly process, the back side process of the bridge wafer includes removing the first temporary carrier substrate 300, but not forming flip chip bumps on the bottom side bonding pads 314 of the bridge wafer. In this case, the bonding pads 314 will be bonded to the area array flip chip bumps formed on the surface of the package substrate. In another embodiment, as described above, the back side process can be performed after removing the first temporary carrier substrate 300 to form a pad array or a redistribution layer, etc. on the exposed back side of the bridge wafer.

[0053] Fig. 9 is a cross-sectional side view of the package structure at an intermediate stage of assembly, where Figure 8 The chip interconnect bridge device 400 is connected to a package substrate 410. The package substrate 410 includes an area array of bonding pads 412 (or pillar structures or solder capping bumps, etc.) formed on the surface of the package substrate 410. In one embodiment, Fig. 9 The surface area of ​​the portion of the package substrate 410 shown in FIG. 4 is the bottom surface of a cavity of the package substrate 410 in which the bridge device 400 is disposed (eg, Figure 1 ). In another embodiment, Fig. 9 The surface area of ​​the portion of the package substrate 410 shown in FIG. 4 is the upper surface of the package substrate 410 on which the bridge device 400 (eg, Figure 2 ). In yet another embodiment, Fig. 9 The solder bumps 370 shown in FIG. 4 may be initially formed on the bonding pads 412 of the package substrate 410, wherein the bottom side bonding pads 314 of the bridge device 400 will be bonded to the solder bumps 370 of the package substrate 410. The chip interconnect bridge device 400 may be connected to the package substrate 410 using solder reflow or thermocompression bonding.

[0054] Next, Fig.10 After removing the remaining portion of the second temporary carrier substrate 360 ​​(or wafer dicing tape) from the chip interconnection bridge device 400 and flip-chip connecting the plurality of IC chips 420 and 430 to the chip interconnection bridge device 400, Fig. 9 4. The IC chips 420 and 430 include respective fine pitch area arrays of flip chip bumps 422 and 432, which are bonded to the fine pitch flip chip bumps 340 on the top side of the bridge device 400. Fig.104. Although not specifically shown in FIG. 4, IC chips 420 and 430 will be flip-chip bonded to package substrate 410 using coarser pitch flip-chip connections (e.g., C4 connections, solder-covered copper pillars, etc.), as described above with reference to FIG. Figure 1 and 2 IC chips 420 and 430 may be connected to bridge device 400 and package substrate 410 using solder reflow or thermocompression bonding.

[0055] Figures 11 to 13 Schematically shows an embodiment of the present invention. Figures 1 to 6 The “chip first” package assembly process after the bridge wafer manufacturing process. Specifically, Fig.11 This is after cutting the bridge wafer and the first temporary carrier substrate 300 along the cutting line D (shown by the dashed line) to form the individual chip interconnection bridge devices 400. Figure 6 In this assembly process, the first temporary carrier substrate 300 remains bonded to the bridge wafer during the wafer dicing process, so that each bridge device formed by the dicing process is supported by a corresponding portion of the first temporary carrier substrate 300, such as Fig.11 shown.

[0056] Next, Fig.12 is a cross-sectional side view of a package structure at an intermediate stage of assembly, wherein a plurality of IC chips 420 and 430 mounted to a temporary chip carrier substrate 500 are connected to Fig.11 The chip interconnect bridge device 400 is provided. The chip carrier substrate 500 is bonded to the IC chips 420 and 430 using any suitable releasable adhesive layer 505. In another embodiment, a precision fixture can be used to temporarily hold the IC chips 420 and 420 using a vacuum system or a releasable adhesive layer. The IC chips 420 and 430 include corresponding fine pitch area arrays of flip chip bumps 422 and 432, and the flip chip bumps 422 and 432 are bonded to the fine pitch flip chip bumps 340 on the top side of the bridge device 400. In addition, the IC chips 420 and 430 include area arrays of flip chip bumps 424 and 434 (e.g., C4 connections, solder-covered copper pillars, etc.), which can be formed with coarse pitch or fine pitch. The flip chip bumps 424 and 434 can be bumps / pillars of the same size as the flip chip bumps 422 and 432 but with a relaxed pitch. IC chips 420 and 430 may be connected to bridge device 400 using solder reflow or thermocompression bonding.

[0057] Fig.13 The remaining portion of the first temporary carrier substrate 300 is removed from the bottom side of the bridge device 400, and the Fig.12 After the IC chips 420 and 430 and the chip interconnection bridge device 400 are connected to the package substrate 510 Fig.124. A cross-sectional side view of a package structure of FIG. 4. The package substrate 510 includes a cavity 512 formed in a top side surface of the package substrate 510. The package substrate 510 includes an area array of bonding pads 512 formed on the top side surface of the package substrate 510, the bonding pads 512 bonded to an area array of flip chip bumps 424 and 434 on the back side of the IC chips 420 and 430. In addition, the package substrate 510 includes an area array of flip chip bumps 516 formed on the bottom surface of the cavity 512, the flip chip bumps 516 bonded to corresponding bonding pads 314 of the area array of bonding pads exposed at the bottom surface of the bridge device 400. It should be understood that the exemplary chip-first assembly scheme can be used to assemble a package structure including a bridge structure mounted to the top side of a laminated package substrate.

[0058] The exemplary bridge manufacturing and assembly packaging techniques discussed above utilize WLFO technology and fine pitch BEOL patterning to enable the formation of an interconnect bridge device 400 that provides a high interconnect density between adjacent chips 420 and 430 while enabling vertical power distribution through the bridge device 400 using stacked wiring and vias in the bridge device 400, which provide package traces for routing and distributing power / ground bump connections between the package substrate 510 and the bottom side of the bridge device 400 to power / ground bump connections between the IC chips 420 and 430 and the top side surface of the bridge device 400. In an alternative embodiment, the chip interconnect bridges can be built on a ceramic or organic carrier with panel processing and relaxed feature sizes.

[0059] In other embodiments, solder hierarchies are implemented to assemble a package structure including a package substrate, a bridge device, and an IC chip. The solder hierarchies will vary depending on whether a "chip first" or "chip last" assembly process is implemented to build the package structure. The solder hierarchical structure takes into account potential misalignment of the flip chip bump connection, which may occur during a direct chip attach operation due to, for example, (i) differences in the coefficients of thermal expansion (CTE) of the different materials that make up the IC die and the interconnect bridge device, and (ii) surface tension of larger coarse pitch solder bumps, which can result, for example, in smaller misalignments of fine pitch solder bumps during solder reflow.

[0060] For example, through the "chip first" assembly process, low temperature solder can be used for small, fine pitch micro-bump connections between IC chips and bridge devices. Low temperature solder enables the bridge device and IC chip to be joined at a lower temperature, which minimizes the differential expansion between the IC chip and the bridge device. In this way, the low temperature solder will reflow and join at low temperatures and minimize the differential expansion between the IC die and the bridge interconnect structure. Therefore, when the assembly cools, the shrinking IC die will not cause considerable stress on the interconnect bridge device, which may otherwise cause bending and cracking of the interconnect bridge device.

[0061] Different solder level structures according to embodiments of the present invention can be implemented with a "chip last" assembly process. As described above, with the "chip last" assembly process, the interconnect bridge device is initially directly chip-attached to the package substrate, followed by direct chip-attachment of the IC die to both the bridge device and the package substrate. In this assembly process, fine pitch bump interconnects are used to join the IC die and the bridge device, and coarse pitch bump interconnects are used to join the IC die and the package substrate. As further explained in detail below, different soldering levels can be utilized to ensure alignment and engagement of the fine pitch bump interconnects between the IC die and the bridge device before joining the coarser pitch bump interconnects between the IC die and the package substrate.

[0062] In one embodiment, each IC die includes flip chip bumps having two sizes C4, for example, 150 micron pitch bumps (coarse pitch bumps) (such as SAC305 or SnBi95) and 55 micron pitch bumps (fine pitch bumps) (such as SAC305 or SnBi95). In addition, the bridge device includes fine pitch micro bumps, which include low temperature melting solder (such as SnBi (58%)) that melts at 138°C formed on the bonding pads of the bridge device. During solder reflow, the low temperature solder on the bonding pads of the bridge device will melt first and pull the corresponding fine pitch bumps on the bottom side of the IC die, which causes the IC die to align with both the bridge device and the package substrate. Using this process, the components are bonded into the melt by, for example, using a small mass of low melting point solder on one side and a large amount of low melting point solder on the other side, or by using a metallurgy (such as gold) on the low melting point side that will be pulled into the melt.

[0063] Other embodiments of the solder level structure of the "chip last" assembly method utilize alignment pads on the back side of the IC die. For example, Fig.145 is a plan view of the backside surface of an IC die 500 according to an embodiment of the present invention, which shows the arrangement of alignment pads for chip alignment of a package structure assembled using a layered soldering process. The backside of the IC die 500 includes a bump interconnection area 502, which includes a standard coarse pitch C4 bump for directly chip-attaching the IC die 500 to the package substrate, and a fine pitch micro-bump 504 (e.g., 55 micron pitch) for directly chip-attaching the IC die 500 to the bridge device. The fine pitch micro-bump 504 includes a solder having a lower melting temperature (e.g., 20°C lower) than the coarse pitch bump in the bump interconnection area 502. In addition, the backside of the IC die 500 includes an alignment pad area 506 in the corner of the IC die 500, the alignment pad area 506 having a large pitch alignment pad with a minimum melting temperature solder, and an alignment pad area 508 having a fine pitch (e.g., 20 to 40 micron pitch) with a minimum melting temperature solder.

[0064] In one embodiment, the solder layered structure utilizes three dimensions C4 with the largest pitch C4 (e.g., 250 micron pitch) in the alignment pad region 506 arranged on the corner of the IC die 500 for overall alignment. In particular, the IC die 500 includes the lowest temperature melting solder (e.g., 118 degrees Celsius) on the alignment pad 506 for overall alignment. The fine pitch bump region 504 (e.g., 55 micron pitch) of the bridge device has a second low temperature melting solder (e.g., 138 degrees Celsius), and the standard C4 bumps (e.g., 150 micron pitch) in the region 502 have the highest temperature melting solder.

[0065] In another embodiment, the solder layered structure utilizes three sizes of C4 with the smallest pitch / large area for finer alignment (finer than required for bridge devices). Specifically, the fine pitch alignment region (e.g., 20 micron to 40 micron pitch) has solder bumps with the lowest temperature melting solder (e.g., 118 degrees Celsius) for ultra-fine alignment. The fine pitch bump region 504 of the bridge device (e.g., 55 micron pitch) has a second low temperature melting solder (e.g., 138 degrees Celsius), and the standard C4 bumps in region 502 (e.g., 150 micron pitch) have the highest temperature melting solder.

[0066] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments and that various other changes and modifications may be made therein by those skilled in the art without departing from the scope of the appended claims.

Claims

1. A packaging structure, comprising: Package substrate; an interconnect bridge device connected to the package substrate, connected to the surface of the package substrate using a flip chip bump connection; a first integrated circuit die connected to the interconnect bridge device and the package substrate; as well as a second integrated circuit die connected to the interconnect bridge device and the package substrate; wherein the interconnect bridge device includes wiring for providing a die-to-die connection between the first and second integrated circuit dies, and wiring for providing a package substrate-to-die connection between the package substrate and the first and second integrated circuit dies, wherein the package substrate-to-die connection includes a power connection; wherein the interconnect bridge device and the first and second integrated circuit dies are connected to a planar top side surface of the package substrate; a standoff connection structure disposed between the planar topside surface of the package substrate and the first integrated circuit die and the second integrated circuit die, wherein the standoff connection structure provides a die-to-package substrate connection between the package substrate and the first integrated circuit die and the second integrated circuit die, wherein the standoff connection structure is configured to offset a height of the interconnect bridge device mounted to the planar topside surface of the package substrate; an underfill layer disposed between the planar topside surface of the packaging substrate and the first and second integrated circuit dies, wherein the standoff connection structure and the interconnect bridge device are encapsulated in the underfill layer; and The occupied area of ​​the first integrated circuit die completely overlaps the occupied area of ​​the interconnection bridge device, so that all inputs / outputs between the first integrated circuit die and the package substrate are routed through the interconnection bridge device.

2. The packaging structure according to claim 1, wherein: The standoff connection structure includes a copper pillar structure and a solder-coated copper ball formed on a contact pad on the top side surface of the package substrate.

3. The package structure according to claim 1, wherein: the first integrated circuit die being connected to a top surface of the interconnect bridge device using a first interconnect bump array; the second integrated circuit die being connected to the top surface of the interconnect bridge device using a second interconnect bump array; The interconnect bridge has a bottom surface connected to the planar topside surface of the package substrate using a third interconnect bump array; The first and second interconnect bump arrays have a first connection pitch; The third interconnect bump array has a second connection pitch; and The first connection pitch is smaller than the second connection pitch. 4 . The package structure of claim 3 , wherein the first connection pitch is 55 microns or less, and wherein the second connection pitch is greater than 55 microns.

5. The packaging structure according to claim 1, wherein: The interconnect bridge device includes a build-up of multiple layers of inorganic dielectric materials and patterned metallization layers to provide inter-layer vias and lateral traces to form the wiring of the interconnect bridge device.

6. The packaging structure according to claim 5, wherein: The construction of the multi-layer inorganic dielectric material and the patterned metallization layer includes a back-end-of-line (BEOL) interconnect structure formed using a BEOL manufacturing process.

7. The packaging structure according to claim 5, wherein: The interconnect bridge device includes at least one organic dielectric layer having a patterned metallization layer that provides the wiring for the package substrate to die connection.

8. The package structure of claim 1, wherein the first integrated circuit die comprises a memory die, and wherein the second integrated circuit die comprises a processor die.

9. The packaging structure according to claim 1, wherein: The package substrate includes one of a ceramic base substrate and an organic laminate construction substrate.

10. The package structure according to claim 1, wherein: The underfill layer includes an electrically insulating adhesive material.

11. A method for constructing a packaging structure, comprising: constructing an interconnect bridge wafer on a first carrier substrate, wherein the interconnect bridge wafer includes a first bonding pad layer, a second bonding pad layer, and a plurality of dielectric layers and metallization layers between the first and second bonding pad layers formed on the first carrier substrate to provide interconnect wiring between bonding pads of the second bonding pad layer and to provide interconnect wiring between bonding pads of the first and second bonding pad layers; attaching a second carrier substrate to the second bond pad layer of the interconnect bridge wafer; removing the first carrier substrate to expose the first bonding pad layer; cutting the interconnection bridge wafer and the second carrier substrate to form an interconnection bridge device, a portion of the second carrier substrate being connected to the interconnection bridge device; directly chip attaching the first bond pad layer of the interconnect bridge device to a package substrate; removing the portion of the second carrier substrate connected to the interconnect bridge device to expose the second bonding pad layer of the interconnect bridge device; and directly die attaching a first integrated circuit die and a second integrated circuit die to the second bond pad layer of the interconnect bridge device and the package substrate; wherein said interconnect routing between said bond pads of said second bond pad layer of said interconnect bridge device provides die-to-die interconnection between said first and second integrated circuit dies connected to said bridge device; wherein the interconnect routing between the bond pads in the first bond pad layer and the second bond pad layer provides a package-to-die connection between the package substrate and the first and second integrated circuit dies, wherein the package-to-die connection includes a power connection; wherein the interconnect bridge device and the first and second integrated circuit dies are connected to a planar top side surface of the package substrate; wherein direct chip attach comprises forming a standoff connection structure between the planar topside surface of the package substrate and the first and second integrated circuit dies, wherein the standoff connection structure provides a die-to-package connection between the package substrate and the first and second integrated circuit dies, wherein the standoff connection structure is configured to offset a height of the interconnect bridge device mounted to the planar topside surface of the package substrate; and An underfill layer is formed between the planar topside surface of the packaging substrate and the first and second integrated circuit dies, wherein the standoff connection structure and the interconnect bridge device are encapsulated in the underfill layer.

12. The method of claim 11, wherein: The interconnect bridge wafer is constructed layer by layer using a back-end-of-line process.

13. The method of claim 11, further comprising: Interconnect bumps are formed on the bonding pads of the first bonding pad layer of the interconnect bridge device before directly chip attaching the interconnect bridge device to the package substrate.

14. The method of claim 11, further comprising: Interconnect bumps are formed on the bond pads of the second bond pad layer of the interconnect bridge device prior to direct chip attaching the first and second integrated circuit dies to the interconnect bridge device.

15. The method of claim 11, wherein: The underfill layer includes an electrically insulating adhesive material.

16. A method for constructing a package structure, comprising: constructing an interconnect bridge wafer on a carrier substrate, wherein the interconnect bridge wafer includes a first bonding pad layer, a second bonding pad layer, and a plurality of dielectric layers and metallization layers between the first and second bonding pad layers formed on the first carrier substrate to provide interconnect wiring between bonding pads of the second bonding pad layer and to provide interconnect wiring between bonding pads of the first and second bonding pad layers; cutting the interconnection bridge wafer and the carrier substrate to form interconnection bridge devices, wherein a portion of the carrier substrate is connected to the interconnection bridge device; directly die attaching a first integrated circuit die and a second integrated circuit die to the second bond pad layer of the interconnect bridge device; removing a portion of the carrier substrate connected to the interconnect bridge device to expose the first bonding pad layer of the interconnect bridge device; and directly chip attaching the first bond pad layer of the interconnect bridge device and the first and second integrated circuit dies to a package substrate; wherein said interconnect routing between said bond pads of said second bond pad layer of said interconnect bridge device provides die-to-die interconnection between said first and second integrated circuit dies connected to said bridge device; wherein the interconnect routing between the bond pads in the first bond pad layer and the second bond pad layer provides a package-to-die connection between the package substrate and the first and second integrated circuit dies, wherein the package-to-die connection includes a power connection; wherein the interconnect bridge device and the first and second integrated circuit dies are connected to a planar top side surface of the package substrate; wherein direct chip attach comprises forming a standoff connection structure disposed between the planar topside surface of the package substrate and the first and second integrated circuit dies, wherein the standoff connection structure provides a die-to-package connection between the package substrate and the first and second integrated circuit dies, wherein the standoff connection structure is configured to offset a height of the interconnect bridge device mounted to the planar topside surface of the package substrate; and An underfill layer is formed between the planar topside surface of the packaging substrate and the first and second integrated circuit dies, wherein the standoff connection structure and the interconnect bridge device are encapsulated in the underfill layer.

17. The method of claim 16, wherein: The interconnect bridge wafer is constructed layer by layer using a back-end-of-line process.

18. The method of claim 16, further comprising: Interconnect bumps are formed on the bond pads of the second bond pad layer of the interconnect bridge device prior to direct chip attaching the first and second integrated circuit dies to the interconnect bridge device.

19. The method of claim 16, wherein: The underfill layer includes an electrically insulating adhesive material.

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