Method for forming semiconductor device

Abstract

The present invention provides a method for forming a semiconductor device, and the method comprises: providing a substrate, forming an etch stop layer on the substrate; forming an intermetallic dielectric layer on the etch stop layer; etching the intermetallic dielectric layer, forming a through hole in the intermetallic dielectric layer, and exposing the surface of the etch stop layer at the bottom of the through hole; and performing surface treatment on the etch stop layer at the bottom of the through hole. The present invention performs surface treatment on the etch stop layer exposed at the bottom of the through hole, changes the material properties of the etch stop layer exposed at the through hole, and changes the etching rate of the etch stop layer exposed at the bottom of the through hole. When the etch stop layer at the bottom of the through hole is subsequently etched along the side wall of the through hole, the unexposed etch stop layer will not be etched, and the etching process stops at the exposed etch stop layer that needs to be etched, thereby improving the performance and quality of the formed semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor device. Background Art

[0002] With the continuous advancement of semiconductor integrated circuit technology, when semiconductor devices are reduced to the deep submicron range, high-performance and high-density connections between semiconductor devices need to be achieved through interconnect structures. Parasitic resistance and parasitic capacitance are easily formed in the interconnect structure, resulting in parasitic effects and time delays in metal wire transmission. People are faced with the problem of how to overcome the significant increase in RC (R refers to resistance, C refers to capacitance) delay caused by the rapid increase in connection length.

[0003] In order to overcome the parasitic effects in the interconnection, in the integration process of the back-end process interconnection of large-scale integrated circuits, on the one hand, the parasitic capacitance is proportional to the relative dielectric constant K of the insulating medium of the interconnection layer. Therefore, the use of low-K materials, especially ultra-low dielectric constant (ULK) materials, to replace traditional SiO2 dielectric materials has become a need to meet the development of high-speed chips. On the other hand, since copper has lower resistivity, superior anti-electromigration properties and high reliability, it can reduce the interconnection resistance of the metal, thereby reducing the overall interconnection delay effect. It has now changed from conventional aluminum interconnection to low-resistance copper interconnection.

[0004] However, the performance of semiconductor devices formed by the prior art is relatively poor. Summary of the invention

[0005] The problem solved by the present invention is to provide a method for forming a semiconductor device to improve the performance of the semiconductor device.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, forming an etch stop layer on the substrate; forming an intermetallic dielectric layer on the etch stop layer; etching the intermetallic dielectric layer to form a through hole in the intermetallic dielectric layer, wherein the bottom of the through hole exposes the surface of the etch stop layer; and performing surface treatment on the etch stop layer at the bottom of the through hole.

[0007] Optionally, a ratio of an etching rate of the etch stop layer exposed at the bottom of the through hole to an etching rate of the unexposed etch stop layer is 5:1 to 20:1.

[0008] Optionally, the material of the etch stop layer is aluminum nitride or aluminum oxide.

[0009] Optionally, when the material of the etch stop layer is aluminum nitride, the process parameters of the surface treatment include: using O2 or O3 plasma, a reaction temperature of 20 to 200°C, and a reaction time of 20 to 100 seconds.

[0010] Optionally, when the material of the etch stop layer is aluminum oxide, the process parameters of the surface treatment include: using N2 or NH3 plasma, a reaction temperature of 20 to 200°C, and a reaction time of 20 to 100 seconds.

[0011] Optionally, the base includes a substrate, a metal layer and a dielectric layer, the dielectric layer is located on the substrate, a contact hole is formed in the dielectric layer, and the metal layer fills the contact hole.

[0012] Optionally, before etching the intermetallic dielectric layer, the method further includes: forming a hard mask layer on the intermetallic dielectric layer.

[0013] Optionally, the process of etching the intermetallic dielectric layer and forming the through hole in the intermetallic dielectric layer is a dry etching process.

[0014] Optionally, after surface treatment is performed on the etch stop layer at the bottom of the through hole, the method further includes: etching away the surface treated etch stop layer until the surface of the substrate is exposed.

[0015] Optionally, the process of etching and removing the etch stop layer after the surface treatment is a wet etching process.

[0016] Optionally, the process parameters of the wet etching process include: using an HF aqueous solution of 1:100 to 1:10000 or an HCL aqueous solution of 1:100 to 1:10000 or an NH4OH aqueous solution of 1:100 to 1:10000, and the etching time is 20 to 300 seconds.

[0017] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0018] After an etch stop layer is formed on the substrate, an intermetallic dielectric layer is formed on the etch stop layer, and the intermetallic dielectric layer is etched to form a through hole. The surface of the etch stop layer is exposed at the bottom of the through hole, and the etch stop layer exposed at the bottom of the through hole is surface treated to change the material properties of the etch stop layer exposed at the bottom of the through hole, so that the etching rate of the etch stop layer exposed at the bottom of the through hole is changed. When the etch stop layer at the bottom of the through hole is subsequently etched along the side wall of the through hole, the unexposed etch stop layer at the bottom of the intermetallic dielectric layer will not be etched, and the etching process stops on the exposed etch stop layer that needs to be etched, and other structures covered by the bottom of the etch stop layer will not be damaged, thereby improving the performance and quality of the formed semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 7 is a schematic structural diagram of a semiconductor device in one embodiment;

[0020] Figures 8 to 14 It is a structural schematic diagram of a semiconductor device forming process in one embodiment of the present invention. DETAILED DESCRIPTION

[0021] The quality of the interconnect structure currently formed is poor, which results in unstable performance of the formed semiconductor device, limiting the use of the semiconductor device. For the specific formation process, refer to Figures 1 to 7 .

[0022] First reference Figure 1 , providing a substrate 100 , forming a dielectric layer 110 on the substrate 100 , etching the dielectric layer 110 , and forming a first through hole 111 in the dielectric layer 110 .

[0023] refer to Figure 2 , filling the first metal layer 120 in the through hole 111 , and planarizing the first metal layer 120 until the top surface is flush with the top surface of the dielectric layer 110 .

[0024] refer to Figure 3 , forming an etch stop layer 130 on the dielectric layer 110 and the first metal layer 120 .

[0025] refer to Figure 4 , an intermetallic dielectric layer 140 is formed on the etch stop layer 130 .

[0026] refer to Figure 5 , the intermetallic dielectric layer 140 is etched to form a second through hole 141 in the intermetallic dielectric layer 140 , and the bottom surface of the second through hole 141 exposes the surface of the etch stop layer 130 .

[0027] refer to Figure 6 , using the intermetallic dielectric layer 140 as a mask, the etching stop layer 130 is continuously etched along the sidewall of the second through hole 141 until the top surface of the first metal layer 120 is exposed.

[0028] refer to Figure 7 , the second through hole 141 is fully filled with the second metal layer 150 , and the second metal layer 150 is planarized until the top surface is flush with the top of the intermetallic dielectric layer 140 .

[0029] The inventors have found that the semiconductor device formed by this method has poor stability and is prone to failure during use, which limits the use of the semiconductor device. When the intermetallic dielectric layer 140 is used as a mask and the etching stop layer 130 is continuously etched along the sidewall of the second through hole 141 until the top surface of the first metal layer 120 is exposed, the etching process not only removes the etching stop layer 130 at the top of the first metal layer 120, but also removes part of the etching stop layer 130 at the bottom of the intermetallic dielectric layer 140. When the second metal layer 150 is formed, there is still a hole between the intermetallic dielectric layer 140 and the etching stop layer 130 ( Figure 7 This affects the quality of the subsequently formed semiconductor devices.

[0030] The inventors have found that after etching the intermetallic dielectric layer and forming the through hole in the intermetallic dielectric layer, the etch stop layer exposed by the through hole is surface treated to change the material properties of the etch stop layer exposed by the through hole. When subsequently etching and removing the etch stop layer exposed by the through hole, it is not only ensured that the etching process only etches and removes the etch stop layer exposed by the through hole, and does not cause damage to the etch stop layer covering the bottom of the intermetallic dielectric layer, but also ensures that the etching process only acts on the etch stop layer exposed by the through hole, and does not cause damage to the metal layer at the bottom of the etch stop layer, thereby improving the performance and quality of the formed semiconductor device.

[0031] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 8 to 14 It is a structural schematic diagram of a semiconductor device forming process in one embodiment of the present invention.

[0033] First reference Figure 8 , providing a substrate 200 , and forming an etch stop layer 300 on the substrate 200 .

[0034] In this embodiment, the base 200 includes a substrate 201 , a metal layer 202 and a dielectric layer 203 . The dielectric layer 203 is located on the substrate 201 . A contact hole 204 is formed in the dielectric layer 203 . The metal layer 202 fills the contact hole 204 .

[0035] In this embodiment, the material of the substrate 201 is single crystal silicon; in other embodiments, the material of the substrate 201 may also be polycrystalline silicon, amorphous silicon, silicon, germanium, silicon germanium, gallium arsenide and other semiconductor materials.

[0036] In this embodiment, a memory device and a logic device (not shown in the figure) are formed on the substrate 201 .

[0037] In this embodiment, the material of the etch stop layer 300 is aluminum nitride; in other embodiments, the material of the etch stop layer 300 is aluminum oxide.

[0038] In this embodiment, the etch stop layer 300 is formed by chemical vapor deposition; in other embodiments, the etch stop layer 300 may also be formed by atomic layer vapor deposition or physical vapor deposition.

[0039] In this embodiment, the process parameters for forming the etch stop layer 300 include: the temperature of chemical vapor deposition is 200-400° C., the reaction gas includes a mixed gas of Al(CH 3 ) 3 , NH 3 and H 2 O, and the flow rate of the mixed gas is 200-1000 sccm.

[0040] In this embodiment, the etch stop layer 300 formed on the substrate 200 is used as a protective layer. In the subsequent etching process, the etch stop layer 300 ensures that the surface of the substrate 200 is not damaged, thereby improving the quality of the formed semiconductor device.

[0041] refer to Fig. 9 , the intermetallic dielectric layer 400 is formed on the etch stop layer 300 .

[0042] The material of the intermetallic dielectric layer 400 is a material with a dielectric constant less than 2.5.

[0043] In this embodiment, the material of the intermetallic dielectric layer 400 is silicon oxide. In other embodiments, the material of the intermetallic dielectric layer 400 may also be black diamond, carbon silicon oxyhydride (SiCOH), fluorine-doped silicon dioxide (FSG), boron-doped silicon dioxide (BSG), phosphorus-doped silicon dioxide (PSG), boron-phosphorus-doped silicon dioxide (BPSG), hydrogenated silsesquioxane or methyl silsesquioxane, etc.

[0044] In this embodiment, the intermetallic dielectric layer 400 is formed by a spin coating process; in other embodiments, the intermetallic dielectric layer 400 may also be formed by a chemical vapor deposition method, a physical vapor deposition method, or an atomic layer vapor deposition method.

[0045] refer to Fig.10 , a hard mask layer 410 is formed on the intermetallic dielectric layer 400 .

[0046] In this embodiment, the material of the hard mask layer 410 is silicon nitride; in other embodiments, the material of the hard mask layer 410 may also be silicon carbide, silicon oxide, silicon oxynitride, etc.

[0047] In this embodiment, the hard mask layer 410 is formed on the intermetallic dielectric layer 400 ; in other embodiments, the hard mask layer 410 may not be formed on the intermetallic dielectric layer 400 .

[0048] In this embodiment, the reason for forming the hard mask layer 410 on the surface of the intermetallic dielectric layer 400 is to facilitate accurate transfer of patterns and ensure the accuracy of patterns.

[0049] refer to Fig.11 , the intermetallic dielectric layer 400 is etched to form a through hole 420 in the intermetallic dielectric layer 400 , and the bottom of the through hole 420 exposes the surface of the etch stop layer 300 .

[0050] In this embodiment, the hard mask layer 410 and the intermetallic dielectric layer 400 are etched in sequence by dry etching process to form a through hole 420 in the intermetallic dielectric layer 400 . The bottom of the through hole 420 exposes the surface of the etch stop layer 300 .

[0051] In this embodiment, the process parameters of the dry etching include: the etching gas used is a mixed gas of CF4 and CCl4, and the flow rate of the mixed gas is 100-500sccm; the radio frequency power with a power range of 500-2000W and a frequency of 13.56MHz is used for dissociation, and the etching temperature is 20-200℃.

[0052] refer to Fig.12 , the etch stop layer 300 at the bottom of the through hole 420 is surface treated.

[0053] The arrows in the figure indicate the ion flow direction of the surface treatment.

[0054] In this embodiment, the surface treatment is a plasma surface treatment method; in other embodiments, the surface treatment may also be an ion doping surface treatment method.

[0055] In this embodiment, after the surface treatment, the ratio of the etching rate of the etch stop layer 300 exposed at the bottom of the through hole 420 to the etching rate of the unexposed etch stop layer 3000 is 5:1 to 20:1.

[0056] In this embodiment, after the surface treatment, the material properties of the etch stop layer 300 exposed at the bottom of the through hole 420 are changed.

[0057] In this embodiment, after surface treatment, the etching rate of the etch stop layer 300 exposed at the bottom of the through hole 420 is much greater than the etching rate of the unexposed etch stop layer 300, which ensures that when the etch stop layer 300 exposed at the bottom of the through hole 420 is etched away, the etching process only removes the etch stop layer 300 exposed at the bottom of the through hole 420, and does not damage the etch stop layer 300 covering the bottom of the intermetallic dielectric layer 400, ensuring that no holes are formed between the etch stop layer 300 on the side wall of the through hole 420 and the intermetallic dielectric layer 400, thereby ensuring the quality of the etch stop layer after etching and improving the performance stability of the formed semiconductor device; at the same time, when the etch stop layer 300 exposed by the through hole 420 is etched away, it is ensured that the etching process stops on the etch stop layer 300 on the metal layer 202, and does not damage the metal layer 202, thereby ensuring the quality of the formed metal layer 202, and facilitating the improvement of the quality of the formed semiconductor device.

[0058] The material of the etching stop layer 300 is aluminum nitride or aluminum oxide.

[0059] In this embodiment, when the material of the etching stop layer 300 is aluminum nitride, the process parameters of the surface treatment include: using O2 or O3 plasma to treat the surface, the reaction temperature is 20 to 200° C., and the reaction time is 20 to 100 seconds.

[0060] In other embodiments, when the material of the etch stop layer 300 is aluminum oxide, the process parameters of the surface treatment include: treating the surface with N2 or NH3 plasma, the reaction temperature is 20 to 200°C, and the reaction time is 20 to 100 seconds.

[0061] refer to Fig.13 , the etch stop layer 300 after surface treatment is removed by etching until the surface of the substrate 200 is exposed.

[0062] In this embodiment, the etch stop layer 300 after surface treatment is removed by etching until the surface of the metal layer 202 is exposed.

[0063] In this embodiment, a wet etching process is used to remove the etching stop layer 300 after surface treatment.

[0064] In other embodiments, the etch stop layer 300 after surface treatment may be removed by using a dry etching process or the like.

[0065] In this embodiment, the process parameters of the wet etching process include using an HF aqueous solution of 1:100 to 1:10000 or an HCL aqueous solution of 1:100 to 1:10000 or an NH4OH aqueous solution of 1:100 to 1:10000, and the etching time is 20-300 seconds.

[0066] In the present embodiment, since the adopted wet etching process has good etching selectivity, when etching and removing the etch stop layer 300 after surface treatment, the surface of the etch stop layer 300 that has not been surface treated (i.e., the etch stop layer covered by the intermetallic dielectric layer 400) will not be damaged. This ensures that there will be no holes between the intermetallic dielectric layer 400 and the etch stop layer 300, thereby improving the formation quality of the etch stop layer, thereby facilitating improving the stability of the performance of the formed semiconductor device.

[0067] In this embodiment, after the wet etching process, the bottom of the through hole 420 extends to the top surface of the metal layer 202 , that is, the bottom surface of the through hole 420 exposes the top surface of the metal layer 202 .

[0068] refer to Fig.14 , an interconnection metal layer 500 is formed on the surface of the metal layer 202 , and the interconnection metal layer 500 fills the through hole 420 .

[0069] In this embodiment, before forming the interconnection metal layer 500 , a diffusion barrier layer 501 is further formed on the bottom and sidewalls of the through hole 420 .

[0070] In this embodiment, the material of the diffusion barrier layer 501 is boron (B); in other embodiments, the material of the diffusion barrier layer 501 is sulfur (S), TaN, WN, CoW, AlN, TiN, etc.

[0071] In this embodiment, the material of the interconnection metal layer 500 is copper (Cu); in other embodiments, the material of the interconnection metal layer 500 may also be cobalt (Co), aluminum (Al), tungsten (W), Ag, Ta, etc.

[0072] In this embodiment, the method for forming the interconnection metal layer 500 is: first, an interconnection metal seed layer (not shown in the figure) is formed on the diffusion barrier layer 501, and then, the interconnection metal layer 500 is formed on the interconnection metal seed layer, and the interconnection metal layer 500 fills the through hole 420.

[0073] In this embodiment, the interconnection metal layer 500 is formed by electrochemical plating; in other embodiments, the interconnection metal layer 500 may be formed by chemical vapor deposition, atomic layer vapor deposition, or physical vapor deposition.

[0074] After forming the interconnection metal layer 500 , the process further includes planarizing the interconnection metal layer 500 (not shown in the figure).

[0075] Correspondingly, a semiconductor device formed by the above-mentioned formation method includes: a substrate 200, wherein the substrate 200 includes a substrate 201, a metal layer 202 and a dielectric layer 203; the dielectric layer 203 is located on the substrate 201; a contact hole 204 is located in the dielectric layer 203; the metal layer 202 fills the contact hole 204; an etch stop layer 300 is located on the substrate 200; an intermetallic dielectric layer 400 is located on the etch stop layer 300; a hard mask layer 410 is located on the surface of the intermetallic dielectric layer 400; a through hole 420 is located in the intermetallic dielectric layer 400, the bottom of which exposes the surface of the etch stop layer 300 and the etch stop layer 300 at the bottom of the through hole 420 is surface treated; a diffusion barrier layer 501 is located at the bottom and sidewalls of the through hole 420; and an interconnect metal layer 500 is located on the diffusion barrier layer 501 and fills the through hole 420.

[0076] In this embodiment, after surface treatment, the material properties of the etch stop layer 300 exposed at the bottom of the through hole 420 are changed, and the ratio of the etching rate of the etch stop layer 300 after surface treatment to the etching rate of the unexposed etch stop layer 300 is 5:1 to 20:1. This ensures that when the etch stop layer 300 exposed at the bottom of the through hole 420 is etched away, only the etch stop layer 300 exposed at the bottom of the through hole 420 is etched away, and the etch stop layer 300 covering the bottom of the metal interlayer dielectric layer 400 will not be damaged, so that the quality of the interconnection structure formed subsequently is improved, thereby forming a semiconductor device with good quality.

[0077] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor device, characterized in that: include: providing a substrate, and forming an etch stop layer on the substrate; forming an intermetallic dielectric layer on the etch stop layer; Etching the intermetallic dielectric layer to form a through hole in the intermetallic dielectric layer, wherein the bottom of the through hole exposes the surface of the etch stop layer; Performing surface treatment on the etch stop layer at the bottom of the through hole, wherein the ratio of the etch rate of the etch stop layer exposed at the bottom of the through hole to the etch rate of the unexposed etch stop layer is 5:1-20:1; The etching stop layer after the surface treatment is removed by a wet etching process.

2. The forming method according to claim 1, characterized in that: The material of the etching stop layer is aluminum nitride or aluminum oxide.

3. The forming method according to claim 2, characterized in that: When the material of the etching stop layer is aluminum nitride, the process parameters of the surface treatment include: using O2 or O3 plasma, a reaction temperature of 20-200° C., and a reaction time of 20-100 seconds.

4. The forming method according to claim 2, characterized in that: When the material of the etching stop layer is aluminum oxide, the process parameters of the surface treatment include: using N2 or NH3 plasma, a reaction temperature of 20-200°C, and a reaction time of 20-100 seconds.

5. The forming method according to claim 1, characterized in that: The base comprises a substrate, a metal layer and a dielectric layer, wherein the dielectric layer is located on the substrate, a contact hole is formed in the dielectric layer, and the metal layer fills the contact hole.

6. The forming method according to claim 1, characterized in that: Before etching the intermetallic dielectric layer, the method further includes: forming a hard mask layer on the intermetallic dielectric layer.

7. The forming method according to claim 1, characterized in that: The process of etching the intermetallic dielectric layer and forming the through hole in the intermetallic dielectric layer is a dry etching process.

8. The forming method according to claim 1, characterized in that: After surface treatment is performed on the etch stop layer at the bottom of the through hole, the method further includes: etching and removing the surface treated etch stop layer until the surface of the substrate is exposed.

9. The forming method according to claim 8, characterized in that: The process of etching and removing the etch stop layer after the surface treatment is a wet etching process.

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