Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming an active region on a substrate; forming a gate structure intersecting the active region on the substrate; removing an upper portion of the gate structure and forming a gate capping layer; forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including a first portion and a second portion; forming a mask pattern layer including a first pattern layer and a second pattern layer, the first pattern layer covering an upper surface of the gate capping layer, the second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug; and forming a contact plug using the mask pattern layer as an etching mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer from an upper surface of the preliminary contact plug to a predetermined depth.

Description

[0001] Cross-references to related applications

[0002] For all purposes, this application claims priority to Korean Patent Application No. 10-2019-0114042, filed on September 17, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Technology

[0004] To meet the demand for high performance, semiconductor devices operate at high speeds and with multiple functions, and their integration density is increasing. This trend towards high integration in semiconductor devices can include constituent elements such as gate electrodes or wirings that have fine patterns or are spaced apart from each other by fine spacing. Furthermore, to avoid limitations in operating characteristics due to the shrinking size of planar metal-oxide-semiconductor field-effect transistors (MOSFETs) under this trend of high integration, efforts have been made to develop semiconductor devices including channels with three-dimensional structures. Summary of the Invention

[0005] One aspect of the present invention is to provide a method for manufacturing a semiconductor device with improved reliability and productivity, and the semiconductor device thereby manufactured.

[0006] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming an active region extending along a first direction on a substrate; forming a sacrificial gate structure extending along a second direction and intersecting the active region on the substrate; forming source / drain regions on the active region on opposite sides of each of the sacrificial gate structures; forming a first interlayer insulating layer covering the source / drain regions and the sacrificial gate structures; removing the sacrificial gate structure and forming a gate structure where the sacrificial gate structure has been removed; removing the upper portion of the gate structure and forming a gate cover where the upper portion of the gate structure has been removed. The process includes: forming a first contact plug that passes through the first interlayer insulating layer to connect to the respective source / drain regions; forming a mask pattern layer that exposes a first portion of the first contact plug and covers a second portion of the first contact plug and at least a portion of the upper surface of each gate overlay; using the mask pattern layer as an etching mask, forming a contact plug by recessing the first portion of the first contact plug exposed by the mask pattern layer to form a recessed region, wherein the contact plug includes a first portion and a second portion extending upward from the first portion; and forming a contact insulating layer that fills the recessed region.

[0007] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming an active region extending along a first direction on a substrate; forming a gate structure on the substrate, the gate structure extending along a second direction to intersect the active region; removing an upper portion of the gate structure and forming a gate overlay where the upper portion of the gate structure has been removed; forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including a first portion and a second portion; forming a mask pattern layer including a first pattern layer and a second pattern layer, the first pattern layer covering an upper surface of the gate overlay and extending along the second direction, the second pattern layer extending from the first pattern layer along the first direction to cover the second portion of the preliminary contact plug; and using the mask pattern layer as an etching mask to form a contact plug by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer from the upper surface of the preliminary contact plug to a predetermined depth.

[0008] According to an exemplary embodiment of the present invention, a method of manufacturing a semiconductor device includes: forming an active region extending in a first direction on a substrate; forming a sacrificial gate structure extending in a second direction on the substrate to intersect the active region; forming source / drain regions on the active region on opposite sides of each of the sacrificial gate structures; removing the sacrificial gate structure and forming a gate structure where the sacrificial gate structure has been removed; removing an upper portion of the gate structure and forming a gate overlay where the upper portion of the gate structure has been removed; forming a preliminary contact plug extending to connect to a corresponding source / drain region; forming a mask pattern layer having a grid pattern on the preliminary contact plug and the gate overlay to expose a portion of the preliminary contact plug; and using the mask pattern layer as an etching mask to form a contact plug by recessing the portion of the preliminary contact plug exposed by the mask pattern layer to form a recessed region. The contact plug includes a first portion and a second portion extending upward from the first portion.

[0009] According to an exemplary embodiment of the present invention, a semiconductor device includes: an active region extending on a substrate along a first direction; a gate structure extending on the substrate along a second direction to intersect the active region; a gate cladding disposed on the gate structure; a source / drain region disposed on the active region on at least one side of the gate structure; and a contact plug extending perpendicularly on the substrate to connect to the source / drain region, the contact plug having a first region and a second region projecting upward from the first region. The gate cladding has a shape in which, in a region not adjacent to the second region of the contact plug, the edge of the gate cladding in the first direction is partially removed from the top. Attached Figure Description

[0010] The above and other aspects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a layout diagram of a semiconductor device according to an example embodiment;

[0012] Figure 2A and Figure 2B This shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0013] Figure 3A and Figure 3B This is a perspective view showing a portion of the components of a semiconductor device according to an example embodiment;

[0014] Figure 4A and Figure 4B This shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Figure 5 This shows a cross-sectional view of a semiconductor device according to an example embodiment;

[0016] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an example embodiment; and

[0017] Figures 7 to 16 This is a diagram illustrating the process of a method for manufacturing a semiconductor device according to an example embodiment, in the order of process steps. Detailed Implementation

[0018] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0019] Figure 1 This is a layout diagram of a semiconductor device according to an example embodiment.

[0020] Figure 2A and Figure 2B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 2A and Figure 2B It shows along Figure 1 The cross-sections of the semiconductor device are taken by lines I-I', II-II', III-III', and IV-IV'. For ease of description, in Figure 1 The diagram only shows the layout of the main components of the semiconductor device.

[0021] Reference Figures 1 to 2B The semiconductor device 100 may include a substrate 101, active fins 105 located on the substrate 101, a gate structure 160 extending intersecting with the active fins 105, a gate capping layer 169 disposed on the gate structure 160, a source / drain region 150 disposed on the active fins 105 on at least one side of the gate structure 160, and a contact plug 180 connected to the source / drain region 150. The semiconductor device 100 may also include a device isolation layer 110 located between the active fins 105, a gate contact plug 185 connected to the gate structure 160, an interlayer insulating layer 190, and a first passage 187 and a second passage 189 respectively connected to the contact plug 180 and the gate contact plug 185. The gate structure 160 may include a first gate dielectric layer 162, a second gate dielectric layer 163, a gate spacer layer 164, and a gate electrode 165. The semiconductor device 100 may include a fin field-effect transistor (FinFET) device in which each active fin 105 has a fin structure. In an example embodiment, the FinFET device may include a gate structure 160 intersecting with the active fin 105.

[0022] Substrate 101 may have an upper surface extending along the X and Y directions. Substrate 101 may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc.

[0023] Active fin 105 may be defined by device isolation layer 110 in substrate 101 and may be configured to extend along a first direction (e.g., the X direction). Active fin 105 forms an active region and may have a structure protruding from substrate 101. Active fin 105 may be configured such that the upper end of active fin 105 protrudes upward from the upper surface of device isolation layer 110 to a predetermined height. Active fin 105 may be formed on a portion of substrate 101 or may include an epitaxial layer grown from substrate 101. Active fin 105 on substrate 101 may be partially recessed on opposite sides of gate structure 160, and source / drain regions 150 may be disposed on the recessed active fin 105. Thus, as Figure 2A As shown, the active fin 105 may have a relatively high height below the gate structure 160. According to the example embodiment, the active fin 105 may include impurities, and at least a portion of the active fin 105 may include impurities of different conductivity types, but is not limited thereto.

[0024] Device isolation layer 110 may define active fins 105 within substrate 101. Device isolation layer 110 may be formed using, for example, a shallow trench isolation (STI) process. Device isolation layer 110 may partially expose the upper sidewalls of the active fins 105. According to an example embodiment, device isolation layer 110 may include a region extending deeper into the lower portion of substrate 101 between the active fins 105. Device isolation layer 110 may have a curved upper surface that has a relatively higher horizontal height as it approaches the active fins 105, but the shape of the upper surface of device isolation layer 110 is not limited thereto. Device isolation layer 110 may be formed of an insulating material. Device isolation layer 110 may be formed of, for example, oxides, nitrides, or combinations thereof. Figure 2B As shown, the device isolation layer 110 may have upper surfaces with different heights at the bottom and outside of the gate structure 160. However, the invention is not limited thereto. In the example embodiment, the height difference of the upper surface of the device isolation layer 110 may vary depending on the manufacturing process.

[0025] The source / drain regions 150 can be respectively disposed on the recessed regions where the source fin 105 is recessed on opposite sides of the gate structure 160. The source / drain regions 150 can be configured as either the source or drain region of a transistor. The upper surface of the source / drain regions 150 can be located at a height similar to or higher than the bottom surface of the gate structure 160, such as... Figure 2A As shown. However, according to the example embodiment, the relative heights of the source / drain region 150 and the gate structure 160 can be varied. For example, the source / drain region 150 can also have an elevated source / drain shape with its top surface higher than the bottom surface of the gate structure 160 (e.g., gate electrode 165).

[0026] The source / drain region 150, on the opposite side of the gate structure 160, can have a pentagonal, hexagonal, or similar shape along the Y direction, such as... Figure 2B As shown. However, in the example embodiment, the source / drain region 150 can have various shapes, for example, it can have any shape of polygon, circle, ellipse and rectangle. The source / drain region 150 can have a substantially flat top surface in a cross-section along the X direction, such as Figure 2A As shown, it may have a curved lower portion, such as a circular shape, an elliptical shape, or a portion of a similar shape. However, such a shape may vary differently in the example embodiment depending on the distance between adjacent gate structures 160, the height of the active fin 105, etc. The term "substantially" may be used herein to emphasize this meaning unless the context or other expression otherwise indicates. For example, items described as "substantially flat" or "substantially coplanar" may be completely flat or coplanar, or may be flat or coplanar within acceptable variations that may occur, for example, due to manufacturing processes.

[0027] The source / drain region 150 can be formed of a semiconductor material. For example, the source / drain region 150 can include at least one of silicon germanium (SiGe), silicon (Si), silicon arsenide (SiAs), silicon phosphide (SiP), and silicon carbide (SiC). For example, the source / drain region 150 can be formed of an epitaxial layer. For example, the source / drain region 150 can include n-type doped silicon (Si) and / or p-type doped silicon germanium (SiGe). In an example embodiment, the source / drain region 150 can include multiple regions containing elements of different concentrations and / or different dopants. Furthermore, in an example embodiment, the source / drain region 150 can be connected to or merged with each other on two or more adjacent active fins 105, thereby forming a single source / drain region 150.

[0028] Gate structure 160 may be configured to extend in one direction (e.g., the Y direction) on top of active fin 105 to intersect with active fin 105. A channel region of the transistor may be formed in the active fin 105 intersecting with gate structure 160. As used herein, "channel region" refers to the region comprising the depletion region of the transistor, and specifically to the region of active fin 105 that intersects with and is adjacent to gate structure 160. Each gate structure 160 may include a first gate dielectric layer 162, a second gate dielectric layer 163, a gate spacer layer 164, and a gate electrode 165.

[0029] The first gate dielectric layer 162 and the second gate dielectric layer 163 may be disposed between the active fin 105 and the gate electrode 165 and below the bottom surface of the gate electrode 165. The first gate dielectric layer 162 may be disposed on the bottom surface of the second gate dielectric layer 163. The second gate dielectric layer 163 may be configured to cover the bottom surface and the opposite side of the gate electrode 165. In an example embodiment, either the first gate dielectric layer 162 or the second gate dielectric layer 163 may be omitted. The first gate dielectric layer 162 and the second gate dielectric layer 163 may include oxides, nitrides, or high-k dielectric materials. High-k dielectric materials may refer to dielectric materials with a dielectric constant higher than that of silicon oxide (SiO2). High-k dielectric materials may be, for example, alumina (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi). x O y Hafnium oxide (HfO2), hafnium silicon oxide (HfSi) x O y ), Lanthanum oxide (La₂O₃), Lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) x O y ), Hafnium aluminum oxide (HfAl) x O y It can be any of praseodymium oxide (Pr2O3) or praseodymium oxide (Pr2O3).

[0030] The gate electrode 165 may comprise a conductive material, such as a metal nitride like titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal like aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material like doped polycrystalline silicon. The gate electrode 165 may also consist of two or more multilayers. According to an example embodiment, depending on the construction of the semiconductor device 100, the gate electrode 165 may be disposed separately from each other along the Y direction between at least some adjacent transistors.

[0031] A gate spacer layer 164 may be disposed on the opposite side of the gate electrode 165. The gate spacer layer 164 may insulate the source / drain region 150 from the gate electrode 165. According to an example embodiment, the gate spacer layer 164 may be formed in a multilayer structure. The gate spacer layer 164 may be formed of oxides, nitrides, and oxide oxynitrides, for example, it may be formed of a low dielectric constant film.

[0032] A gate capping layer 169 may be disposed on the upper surface of the gate structure 160. In an example embodiment, the upper surface of the gate structure 160 may be curved. Therefore, the gate capping layer 169 may have a lower surface with a downwardly convex curved surface and a substantially flat upper surface. In an example embodiment, each gate capping layer 169 may include an upper portion that contacts a contact region CR of contact plugs 180 spaced apart from each other in the X direction and a contact insulating layer 194. The width of the top surface of the gate capping layer 169 in the X direction may be greater than the width of the gate structure 160 in the X direction, and the top surface of the gate capping layer 169 may have a maximum width that fills the space between adjacent contact plugs 180. The lower surface of the gate capping layer 169 may contact the second gate dielectric layer 163, the gate spacer layer 164, the gate electrode 165, and the first interlayer insulating layer 192. The invention is not limited thereto. In some embodiments, the gate capping 169 may be configured to be confined to the upper portion of the gate spacer layer 164 without extending beyond the gate spacer layer 164, and may be confined between the gate spacer layers 164 to be covered by both sides of the gate spacer layer 164 in the X direction. As used herein, the term “contact” means direct connection (i.e., touching) unless the context otherwise indicates.

[0033] The gate capping 169 may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. According to an example embodiment, the gate capping 169 may include a material different from that of the first interlayer insulating layer 192. When forming contact holes, the gate capping 169 can be used to form contact plugs 180, allowing for self-alignment between the gate cappings 169.

[0034] Contact plug 180 may be connected to source / drain region 150 to apply an electrical signal to source / drain region 150. Contact plug 180 may extend from the top to the bottom of first interlayer insulation layer 192 while passing through first interlayer insulation layer 192. Contact plug 180 may be disposed on source / drain region 150, and in some embodiments, contact plug 180 may extend in the Y direction, thereby having a length longer than the length of source / drain region 150. Each contact plug 180 may have a sloped side surface and may have a downwardly decreasing width depending on the aspect ratio of the contact hole (i.e., the width of the lower portion of contact plug 180 is smaller than the width of the upper portion of contact plug 180), but exemplary embodiments thereof are not limited thereto. In exemplary embodiments, the lower portion of contact plug 180 may be buried in source / drain region 150 to a predetermined depth. In some embodiments, the contact plug 180 may also be configured to contact along the top surface of the source / drain region 150 without causing the source / drain region 150 to be recessed.

[0035] Each contact plug 180 may include a first portion 180-1 and a second portion 180-2 extending upward from the first portion 180-1 (see...). Figure 3A and Figure 3B The second part 180-2 can be located in the contact area CR that passes through the first interlayer insulation layer 192. For example... Figure 1 As shown, for example, when gate contact plugs 185 and 180 are located on top of active fin 105 and overlap with it, each contact plug 180 may include a second portion 180-2 of the gate contact plug 185 disposed in the contact region CR and extending upward from a first portion 180-1 without contacting a second portion 180-2 of the gate contact plug 185 spaced apart from the contact plug 180 in the X direction. The first portion 180-1 of the contact plug 180 may be disposed in the lower part of the recessed region instead of in the contact region CR, and the recessed region may be filled with a contact insulating layer 194. The contact region CR may not be disposed side-by-side with the gate contact plug 185 in the X direction. The contact region CR may be disposed side-by-side with the contact insulating layer 194 in the X direction on the first portion 180-1 of the contact plug 180. Since the upper portions of the contact plug 180 and the gate contact plug 185, which have relatively wide areas, are not arranged side by side, the contact plug 180 and the gate contact plug 185 can be stably electrically isolated from each other even when the distance L1 between the contact plug 180 and the gate contact plug 185 is relatively small.

[0036] The length L3 of the contact region CR in the Y direction can be less than the length L2 of a contact plug 180 in the Y direction. The length L3 of the contact region CR can be less than the length of the recessed region, which is the region that does not overlap with the contact region CR in the top view. The length L3 of the contact region CR can range, for example, from about 10 nm to about 40 nm. The length L3 of the contact region CR can be varied differently in the example embodiments and can be determined within the range where the contact region CR is not arranged side-by-side with the adjacent gate contact plug 185. Reference will be made below. Figure 3A and Figure 3B The shape of the contact plug 180 is described in more detail. Terms such as “approximately” can reflect a quantity, size, orientation, or arrangement that varies only in a relatively small way and / or in a way that does not significantly alter the operation, function, or structure of certain elements. For example, a range of “approximately 0.1 to approximately 1” can cover ranges such as 0%–5% deviations near 0.1 and 0%–5% deviations near 1, especially if the deviation maintains the same effect as the listed range.

[0037] Gate contact plug 185 may be connected to gate structure 160 and pass through gate cladding 169, and may apply electrical signals to gate electrode 165. Gate contact plug 185 may include a lower end buried in gate electrode 165 to a predetermined depth, but exemplary embodiments thereof are not limited thereto. The height of the lower surface of gate contact plug 185 may be similar to or higher than the height of the upper surface of the recessed region of contact plug 180, but is not limited thereto. Contact plug 180 and gate contact plug 185 may include conductive materials, such as metals such as tungsten (W), aluminum (Al), copper (Cu), etc., or semiconductor materials such as doped polycrystalline silicon.

[0038] Interlayer insulating layer 190 may include a first interlayer insulating layer 192 covering the top surface of the source / drain region 150 and the device isolation layer 110, as well as the side surface of the gate structure 160; a contact insulating layer 194 filling the recessed region of the contact plug 180; and a second interlayer insulating layer 196 located on the contact plug 180. The top surface of the contact insulating layer 194 may be substantially coplanar with the top surface of the contact plug 180. According to an example embodiment, the top surface of the contact insulating layer 194 may also be substantially coplanar with the top surface of the gate contact plug 185. In some embodiments, the contact insulating layer 194 and the second interlayer insulating layer 196 may be formed from a single layer. Interlayer insulating layer 190 may include at least one of, for example, oxides, nitrides, and oxynitrides. In an example embodiment, interlayer insulating layer 190 may include a low dielectric constant material.

[0039] The first passage 187 and the second passage 189 can pass through the second interlayer insulating layer 196 and connect to the contact plug 180 and the gate contact plug 185, respectively. The first passage 187 and the second passage 189 may include conductive materials, such as metals like tungsten (W), aluminum (Al), copper (Cu), or semiconductor materials like doped polysilicon. Although not shown, wiring structures such as metal wires connecting to the first passage 187 and the second passage 189 may be further provided on the first passage 187 and the second passage 189. However, according to some embodiments, the first passage 187 and the second passage 189 may be integrated with the contact plug 180 and the gate contact plug 185, respectively.

[0040] Figure 3A and Figure 3B This is a perspective view showing some components of a semiconductor device according to an example embodiment. Figure 3A and Figure 3B Contact plugs 180 and 180a are shown respectively.

[0041] Reference Figure 3AThe contact plug 180 may include a first portion 180-1 disposed in a first region R1, which is a lower region, and a second portion 180-2 disposed in a second region R2. The second portion 180-2 may protrude upward from one end of the first portion 180-1. In various embodiments, the relative height of the first portion 180-1 and the second portion 180-2 may be varied. The first region R1 (or the first portion 180-1) may be located at one end of the second region R2 (or the second portion 180-2).

[0042] The second region R2 can correspond to the above reference. Figures 1 to 2B The described contact area CR can be connected to the first path 187 thereon (see...). Figure 2A (or wiring). After the initial contact plug recess, the second portion 180-2 of the contact plug 180 is retained. In the second region R2, the first side surface of the second portion 180-2 may form the sidewall of the recessed region RE, and the second side surface of the second portion 180-2 opposite to the first side surface may form the outer sidewall of the contact plug 180 that does not face the recessed region RE. The first and second side surfaces may have negative slopes relative to the upper surface of the first portion 180-1, forming a first obtuse angle and a second obtuse angle, respectively. The first and second obtuse angles may be the same or different. The side surface of the second region R2 facing the recessed region RE is shown as a convex shape toward the recessed region RE, but its shape is not limited to this and can be varied according to exemplary embodiments. For example, in some embodiments, the side surface of the second region R2 facing the recessed region RE may be a substantially flat surface or may have a concave shape toward the recessed region RE.

[0043] As described above, in the extending direction of the contact plug 180, the length L3 of the second region R2 can be less than the length L2 of the first region R1 and the length L6 of the recessed region RE. The contact plug 180 can have inclined side surfaces with a width that decreases toward its lower surface according to the aspect ratio. Therefore, in the direction perpendicular to the extending direction, the length L4 of the upper surface of the second region R2 can be greater than the length L5 of the lower surface of the first region R1.

[0044] Reference Figure 3BThe contact plug 180a may have the following shape: the second portion 180a-2 is not disposed at one end of the first portion 180a-1, but is disposed at a position spaced apart from the opposite end of the first portion 180a-1. The first portion 180a-1 may be disposed in the first region R1, and the second portion 180a-2 may be disposed in the second region R2. Therefore, the first recessed region RE1 and the second recessed region RE2 may be formed on opposite sides of the second portion 180a-2. As described above, in the example embodiment, the relative positions of the first portion 180a-1 and the second portion 180a-2 may be varied. In this example embodiment, the first side surface of the second portion 180a-2 may form the sidewall of the first recessed region RE1, and the second side surface of the second portion 180a-2 may form the sidewall of the second recessed region RE2 spaced apart from the first recessed region RE1 in the second direction (e.g., the Y direction). The first side surface of the second part 180a-2 may have a negative slope relative to the upper surface of the first part 180a-1, and its second side surface may have a positive slope relative to the upper surface of the first part 180a-1.

[0045] Figure 4A and Figure 4B This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 4A and Figure 4B It shows the relationship with Figure 2A The corresponding cross section.

[0046] Reference Figure 4A In semiconductor device 100a, the top surface of gate cladding 169a may be partially removed to give it a recessed edge 169E. For example, gate cladding 169a may have a recessed edge 169E that contacts contact insulating layer 194. Alternatively, gate cladding 169a may have a non-recessed edge that contacts second portion 180-2 of contact plug 180.

[0047] The recessed edge 169E of the gate cladding 169a may have a shape that is recessed from the upper surface to the lower side, and its detailed shape is not limited to that shown in the figures. The gate cladding 169a may have a portion removed from the recessed edge 169E, while having a substantially flat top surface. The recessed edge 169E of the gate cladding 169a may contact the contact insulating layer 194. The shape of the gate cladding 169a can be described by referring to the following... Figures 14A to 14C The shape of the mask pattern layer MA is described to form the mask pattern.

[0048] Reference Figure 4B In semiconductor device 100b, gate capping 169b may have a recessed edge 169E, and is connected to... Figure 4AUnlike the example embodiments, it may have a shape that is asymmetrical in the X direction.

[0049] The gate capping 169b may have a non-recessed edge extending flatly from the top surface at one end along the X direction, and a recessed edge 169E in a recessed shape at the other end. Such a structure can be described according to the following reference. Figures 14A to 14C The mask pattern layer MA and the gate cover 169b are arranged as described. Therefore, in some embodiments, the gate cover 169b may also be configured to have recessed edges 169E, which have a shape such that opposite ends of the gate cover in the X direction are recessed edges, and the recess depths or widths are different from each other.

[0050] Figure 5 This is a cross-sectional view of a semiconductor device according to an example embodiment. Figure 5 It shows the relationship with Figure 1 The cross sections corresponding to lines I-I' and III-III'.

[0051] Reference Figure 5 The semiconductor device 100c may include a substrate 101, an active fin 105 located on the substrate 101, a channel structure 140 located on the active fin 105 including a plurality of channel layers 141, 142, and 143 perpendicularly spaced from each other, a source / drain region 150 contacting the plurality of channel layers 141, 142, and 143, a gate structure 160a extending intersecting the active fin 105, a gate capping layer 169 disposed on the gate structure 160a, and a contact plug 180 connected to the source / drain region 150. The semiconductor device 100c may also include a device isolation layer 110, an internal spacer layer 130, an interlayer insulating layer 190, and a via 187. The gate structure 160a may include a gate dielectric layer 162, a gate spacer layer 164, and a gate electrode 165.

[0052] In semiconductor device 100c, active fin 105 has a fin structure, and gate electrode 165 is disposed between active fin 105 and channel structure 140 and between multiple channel layers 141, 142, and 143 of channel structure 140. Therefore, semiconductor device 100c may include a multi-bridge channel FET (MBCFET) constructed from channel structure 140, source / drain regions 150, and gate structure 160a. TM ) device. In the following text, with Figures 1 to 2B The same reference numerals in the accompanying drawings indicate the corresponding components, and the descriptions above will be omitted.

[0053] The channel structure 140 may include first to third channel layers 141, 142, and 143 as two or more channel layers located on the active fin 105. The first to third channel layers 141, 142, and 143 are multiple channel layers spaced apart from each other in a direction perpendicular to the top surface of the active fin 105 (e.g., the Z direction). The channel structure 140 may form an active region together with the active fin 105. The first to third channel layers 141, 142, and 143 may be connected to the source / drain region 150 and may be spaced apart from the top surface of the active fin 105. The width of the first to third channel layers 141, 142, and 143 in the Y direction may be the same as or similar to the width of the active fin 105 in the Y direction, and the width of the first to third channel layers 141, 142, and 143 in the X direction may be the same as or similar to the width of the gate structure 160a in the X direction. However, according to some embodiments, the first to third channel layers 141, 142 and 143 may have a reduced width, such that the side surfaces in the X direction are disposed below the gate structure 160a.

[0054] The first to third channel layers 141, 142, and 143 may be formed of a semiconductor material and may include at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge). For example, the first to third channel layers 141, 142, and 143 may be formed of the same material as the substrate 101. In various embodiments, the number and shape of the channel layers 141, 142, and 143 constituting a channel structure 140 may be varied.

[0055] The gate structure 160a may be configured to extend in one direction (e.g., the Y direction) on top of the active fin 105 and the channel structure 140, while intersecting with the active fin 105 and the channel structure 140. The channel region of the transistor may be formed in the active fin 105 and the channel structure 140 intersecting with the gate structure 160a. The gate structure 160a includes a gate electrode 165, a gate dielectric layer 162 located between the gate electrode 165 and a plurality of channel layers 141, 142, and 143, and a gate spacer layer 164 located on the side of the gate electrode 165.

[0056] The gate dielectric layer 162 may be disposed between the active fin 105 and the gate electrode 165, and between the channel structure 140 and the gate electrode 165, and may be configured to cover at least a portion of the surface of the gate electrode 165. For example, the gate dielectric layer 162 may be configured to surround all surfaces of the gate electrode 165 except for the top surface. The gate dielectric layer 162 may extend between the gate electrode 165 and the gate spacer layer 164, but exemplary embodiments thereof are not limited thereto. The gate dielectric layer 162 may comprise an oxide, a nitride, or a high-k dielectric material.

[0057] The gate electrode 165 may fill the gap between the channel layers 141, 142, and 143 on top of the active fin 105 and may extend to the top of the channel structure 140. The gate electrode 165 may be spaced apart from the plurality of channel layers 141, 142, and 143 by a gate dielectric layer 162. The gate electrode 165 may include a conductive material, such as a metal nitride like titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal like aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polycrystalline silicon. The gate electrode 165 may also include two or more layers. Depending on the construction of the semiconductor device 100c, the gate electrode 165 may be divided by separate partitions between at least some adjacent transistors.

[0058] Internal spacer layers 130 may be disposed parallel to the gate electrode 165 between the channel structures 140. Below the third channel layer 143, a portion of the gate electrode 165 may be spaced from the source / drain regions 150 by the respective internal spacer layers 130 for electrical isolation. Each internal spacer layer 130 may have curved sides spaced apart from the respective gate electrode 165. For example, the curved sides of the internal spacer layer 130 may be convex towards a portion of the respective gate electrode 165, but exemplary embodiments are not limited thereto. The internal spacer layers 130 may be formed of oxides, nitrides, or oxynitrides, for example, they may be formed of a low-dielectric-constant film. In some embodiments, the internal spacer layers 130 may be omitted, in which case the gate dielectric layer 162 and the gate electrode 165 may extend in the X direction.

[0059] Above, FinFET and MBCFET are shown as examples of semiconductor devices according to exemplary embodiments. TM The invention is not limited to the examples described herein. Semiconductor devices according to some embodiments may include tunneling field-effect transistors (tunneling FETs), three-dimensional (3D) transistors, etc.

[0060] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0061] Figures 7 to 16 This is a diagram illustrating a method for manufacturing a semiconductor device according to an example embodiment. Figures 7 to 16 Manufacturing process is shown Figures 1 to 2B as well as Figure 4A and Figure 4B Embodiments of methods for semiconductor devices are shown, and the relationship with along... Figure 1 The cross sections corresponding to the sections intercepted by lines I-I' and III-III'.

[0062] Reference Figure 6 and Figure 7 After patterning the substrate 101 to define an active region including the active fin 105 and forming a device isolation layer 110, a sacrificial gate structure 170 can be formed (S110).

[0063] First, active fins 105 can be formed by anisotropically etching the substrate 101 to create trenches using a mask layer. Because trenches with a relatively high aspect ratio can have a downwardly decreasing width, each active fin 105 can have an upwardly decreasing width. A device isolation layer 110 can be formed by filling the trenches with an insulating material layer and then planarizing the insulating material layer and the upper surface of the active fins 105. Figure 5 In the case of semiconductor device 100c, in this operation, first to third channel layers 141, 142 and 143 constituting the active region can be stacked on the active fin 105. The first to third channel layers 141, 142 and 143 and the sacrificial layer can be stacked alternately and perpendicularly on each other.

[0064] Next, a sacrificial gate structure 170 can be formed on the active fin 105, such that the sacrificial gate structure 170 has a linear shape extending along the Y direction and intersecting with the active fin 105. This can be achieved through subsequent processes. Figure 2A A sacrificial gate structure 170 is formed at the locations of the first gate dielectric layer 162, the second gate dielectric layer 163, and the gate electrode 165. The sacrificial gate structure 170 may include a first sacrificial gate layer 172, a second sacrificial gate layer 175, and a gate mask patterning layer 176. The first sacrificial gate layer 172 and the second sacrificial gate layer 175 can be patterned using the gate mask patterning layer 176.

[0065] The first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be an insulating layer and a conductive layer, respectively, but are not limited thereto. For example, the first sacrificial gate layer 172 and the second sacrificial gate layer 175 may be formed from a single layer. For example, the first sacrificial gate layer 172 may include silicon oxide, and the second sacrificial gate layer 175 may include polysilicon. The gate mask patterning layer 176 may include silicon oxide and / or silicon nitride. In the example embodiment, the structure of the sacrificial gate structure 170 may be varied.

[0066] Reference Figure 6 and Figure 8 A gate spacer layer 164 can be formed on the opposite sidewalls of the sacrificial gate structure 170, and the active fins 105 exposed between the sacrificial gate structures 170 can be recessed to form source / drain regions 150 (S120).

[0067] First, a gate spacer layer 164 may be formed on the side surface of the sacrificial gate structure 170. The gate spacer layer 164 may be formed of a low dielectric constant material and may include at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0068] Next, the active fin 105 can be recessed from its top surface to a predetermined depth to form a recessed region. For example, the recess process can be performed by sequentially applying a dry etching process and a wet etching process. Therefore, in this operation, the height of the active fin 105 outside the sacrificial gate structure 170 can be lower than its height in the lower portion of the sacrificial gate structure 170. In some embodiments, the recessed region can have a shape extending to the gate spacer layer 164 or the lower portion of the sacrificial gate structure 170. Optionally, after performing the recess process, an additional process can be performed to solidify the surface of the recessed active fin 105.

[0069] Next, the source / drain region 150 can be formed by growing from the active fin 105 using, for example, a selective epitaxial growth (SEG) process. The source / drain region 150 may include in-situ doped impurities.

[0070] Reference Figure 6 , Figure 9 and Figure 10 After forming the first interlayer insulating layer 192 on the source / drain region 150, the sacrificial gate structure 170 is removed, and the first gate dielectric layer 162, the second gate dielectric layer 163 and the gate electrode 165 can be formed in the opening OR, thereby forming the gate structure 160 (S130).

[0071] First, such as Figure 9 As shown, a first interlayer insulating layer 192 can be formed by depositing an insulating material to cover the source / drain region 150, the sacrificial gate structure 170, and the gate spacer layer 164, followed by a planarization process to expose the top surface of the second sacrificial gate layer 175 or the top surface of the gate mask pattern layer 176. According to an example embodiment, the gate mask pattern layer 176 can be removed during the planarization process. The first interlayer insulating layer 192 may include at least one of, for example, oxides, nitrides, and oxide oxynitrides. In an example embodiment, the first interlayer insulating layer 192 may include a low-dielectric-constant material.

[0072] Next, the remaining sacrificial gate structure 170, including the first sacrificial gate layer 172 and the second sacrificial gate layer 175, can be selectively removed relative to the underlying active fin 105 and device isolation layer 110, thereby forming the opening OR. The removal process of the sacrificial gate structure 170 can use at least one of dry etching and wet etching processes.

[0073] Next, as Figure 10 As shown, a first gate dielectric layer 162 and a second gate dielectric layer 163 can be formed substantially conformally along the sidewalls and bottom surface of the opening OR. Both the first gate dielectric layer 162 and the second gate dielectric layer 163 can comprise an oxide, a nitride, or a high-k dielectric material. A gate electrode 165 can be formed to fill the opening OR within the first gate dielectric layer 162 and the second gate dielectric layer 163. The gate electrode 165 can comprise a metal or a semiconductor material.

[0074] After the first gate dielectric layer 162, the second gate dielectric layer 163 and the gate electrode 165 are formed, a planarization process such as chemical mechanical polishing (CMP) can be used to remove these layers remaining on the upper surface of the first interlayer insulating layer 192.

[0075] Reference Figure 6 , Figure 11 and Figure 12 A gate recess region GR can be formed by partially removing the gate structure 160 from the top, a gate overlay 169 can be formed to fill the gate recess region GR, and a contact hole CH (S140) can be formed.

[0076] First, such as Figure 11 As shown, the gate recess region GR can be formed using a dry etching process and / or a wet etching process. The width W1 of the gate recess region GR can be greater than the width of the gate structure 160, but is not limited thereto. In the example embodiment, the depth D1 of the gate recess region GR can be varied. The lower surface of the gate recess region GR can protrude downwards, but the example embodiment is not limited thereto. For example, the lower surface of the gate recess region GR can have a flat shape.

[0077] Next, as Figure 12 As shown, the gate cap 169 can be formed through a deposition process and a planarization process. The contact hole CH can be formed by removing the first interlayer insulating layer 192 from the top. The gate cap 169 can be used to enable self-alignment of the contact hole CH when it is formed. For this purpose, the gate cap 169 can be formed of a material different from the material of the first interlayer insulating layer 192. When forming the contact hole CH, the first interlayer insulating layer 192 can be selectively removed relative to the gate cap 169.

[0078] Reference Figure 6 and Figure 13 The initial contact plug 180P (S150) can be formed by filling the contact hole CH with conductive material.

[0079] The initial contact plug 180P can be formed through a deposition process and a planarization process. The initial contact plug 180P can be formed by completely filling the contact hole CH with conductive material and then using a planarization process to remove the conductive material remaining on the gate cap 169.

[0080] Reference Figure 6 and Figures 14A to 14C A mask pattern layer MA (S160) can be formed for performing a process of removing a portion of the initial contact plug 180P.

[0081] A mask pattern layer MA can be formed to cover the area of ​​the initial contact plug 180P where the contact region CR will be formed, thereby exposing other areas of the initial contact plug 180P. The mask pattern layer MA can also expose the first interlayer insulating layer 192 between the initial contact plugs 180P. For example, the mask pattern layer MA can be formed to completely cover the entire upper surface of the gate overlay 169 on the gate structure 160, or expose areas such as... Figures 14A to 14C The opposite edges of each gate cover 169 in the X direction, or the edges of each gate cover 169, are shown. The mask pattern layer MA may include a photoresist layer, and in some embodiments, may include a hard mask layer and a photoresist layer.

[0082] The mask pattern layer MA may include a first pattern layer P1 and a second pattern layer P2. The first pattern layer P1 is disposed on the gate cover 169 and extends in the Y direction, while the second pattern layer P2 is disposed on the initial contact plug 180P to connect the first pattern layers P1 to each other and extends in the X direction. The end of the first pattern layer P1 in the X direction may be spaced inwardly from the edge of the gate cover 169 by a predetermined length D2 to partially expose the gate cover 169. The length D2 can be determined within a range that ensures process margin in the photolithography process. The minimum width of the second pattern layer P2 in the Y direction may be, for example, in the range of about 10 nm to about 40 nm.

[0083] The mask pattern layer MA can have a grid shape where the first pattern layer P1 and the second pattern layer P2 are connected. The mask pattern layer MA increases the contact area between the mask pattern layer MA and the underlying structure. Therefore, in this case, defects caused by raising the mask pattern layer MA can be prevented compared to forming a mask layer with an island pattern that only covers the area corresponding to the contact area CR. Furthermore, because the mask pattern layer MA includes the first pattern layer P1, loss of the gate cover 169 can be prevented during the subsequent process of removing the initial contact plug 180P. Meanwhile, if a mask layer with an island pattern is used, gate contact plug 185 (see [link to relevant documentation]) will occur because the contact insulating layer 194 fills the area where the gate cover 169 is lost. Figure 2AThe poor connection between the gate overlay 169 and the gate electrode 165. However, in an exemplary embodiment of the present invention, such connection failures can be prevented because the gate overlay 169 is protected by a mask pattern layer MA having a grid shape.

[0084] Reference Figure 6 and Figure 15 The contact plug 180 with a recessed area can be formed by partially removing the initial contact plug 180P exposed by the mask pattern layer MA from the top (S170), and the contact insulation layer 194 can be formed (S180).

[0085] First, the initial contact plug 180P can be partially removed to a predetermined depth using a dry etching process and / or a wet etching process, so that only the contact area CR can protrude upwards. The detailed shape of the contact plug 180 can be referenced in the same manner. Figures 1 to 3B The description.

[0086] The initial contact plug 180P can be selectively removed relative to the gate cap 169 and the first interlayer insulating layer 192. However, even in this case, at least a portion of the first interlayer insulating layer 192 and the gate cap 169 exposed from the mask pattern layer MA can still be removed together. Therefore, as Figures 14A to 14C As shown, when the edge of the gate cladding 169 is exposed for a length D2, a pattern can be formed according to the arrangement of the mask pattern layer MA, as shown. Figure 4A and Figure 4B The recessed edge 169E of each of the gate cappings 169a and 169b shown.

[0087] Next, the contact insulating layer 194 can be formed by the following steps: depositing insulating material to fill the recessed area of ​​the contact plug 180; and removing the insulating material remaining on top using a planarization process such as CMP. When the gate caps 169a and 169b have such Figure 4A and Figure 4B When the recessed edge 169E is shown, the insulating material forming the contact insulating layer 194 can be formed to fill the recessed area of ​​the recessed edge 169E. Through a planarization process, the top surface of the contact plug 180, the top surface of the gate cover 169, and the top surface of the contact insulating layer 194 can be substantially coplanar.

[0088] According to the example embodiment, even when the edge of the gate capping 169 is partially removed as described above, the gate capping 169 can still be planarized together in the planarization process, thereby ultimately obtaining the desired result. Figure 2AThe structure is shown. For example, the gate capping 169 may have a flat structure after a portion of the initial contact plug 180P has been removed, or it may have an edge that is partially removed according to the position of the end of the mask pattern layer MA. In the case of having a partially removed edge, the gate capping 169 may have a structure in which the following are provided: Figure 4A and Figure 4B The final structure of the recessed edge 169E shown can also be achieved through a planarization process, resulting in a structure similar to... Figure 2A The flat top surface is shown.

[0089] Although not shown in the figure, further steps can be performed to form the gate contact plug 185 (see Figure 185). Figure 2A The process involves forming a contact hole on top of the active fin 105, passing through the gate overlay 169 and connecting to the gate structure 160, and then depositing a conductive material to form the gate contact plug 185. According to an example embodiment, the gate contact plug 185 can be formed in a separate process, or it can be formed in a process described above. Figure 13 The initial contact plug 180P is formed together as described.

[0090] Reference Figure 16 A second interlayer insulating layer 196 can be formed on the gate cover 169, the first interlayer insulating layer 192 and the contact insulating layer 194, and a via VH can be formed in the second interlayer insulating layer 196.

[0091] A via VH can be formed by partially removing the second interlayer insulating layer 196 using a separate mask layer, thereby forming the first passage 187 and the second passage 189 (see...). Figure 2A The contact area CR of the contact plug 180 can be exposed to the lower part of the through hole VH.

[0092] Next, refer to Figure 2A and Figure 2B The first passage 187 and the second passage 189 can be formed by filling the through-hole VH with a conductive material.

[0093] As described above, according to the example embodiment, by using a mask pattern layer with a grid shape in the recess process for contact plugs, a method for manufacturing semiconductor devices with improved reliability and thus manufactured semiconductor devices can be provided with increased productivity.

[0094] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: An active region extending along a first direction is formed on the substrate; A sacrificial gate structure extending in a second direction to intersect with the active region is formed on the substrate; Source / drain regions are formed on the active region on opposite sides of each of the sacrificial gate structures; A first interlayer insulating layer is formed covering the source / drain regions and the sacrificial gate structure; Remove the sacrificial gate structure and form a gate structure where the sacrificial gate structure has been removed; Remove the upper portion of the gate structure and form a gate capping layer at the location where the upper portion of the gate structure has been removed; Form an initial contact plug through the first interlayer insulation layer to connect to a corresponding source / drain region; A mask pattern layer is formed that exposes a first portion of the initial contact plug and covers a second portion of the initial contact plug and at least a portion of the upper surface of each gate cover; Using the mask pattern layer as an etching mask, a contact plug is formed by recessing the first portion of the initial contact plug exposed by the mask pattern layer to form a recessed region, wherein the contact plug includes a first portion and a second portion extending upward from the first portion; and A contact insulating layer is formed to fill the recessed area. The mask pattern layer includes: A first patterned layer, disposed on the gate cover layer, extending along the second direction and spaced apart from each other in the first direction; and A second pattern layer is disposed on the second portion of the initial contact plug, extends along the first direction to connect with the first pattern layer and is spaced apart from each other in the second direction.

2. The method according to claim 1, in, Each of the first patterned layers partially exposes at least one edge of a corresponding gate overlay, and Wherein, at least one edge of the corresponding gate coating extends along the second direction.

3. The method according to claim 2, in, When the recessed region is formed, at least one edge of the corresponding gate cover is partially removed.

4. The method according to claim 1, in, The minimum width of the second patterned layer in the second direction is in the range of 10 nm to 40 nm.

5. The method according to claim 1, in, The length of the second portion of the contact plug in the second direction is less than the length of the recessed area in the second direction.

6. The method according to claim 1, in, The second portion of the contact plug extends upward from one end of the first portion of the contact plug.

7. The method according to claim 6, in, The second portion of the contact plug has a first side surface forming the sidewall of the recessed region and a second side surface opposite the first side surface forming the outer surface of the contact plug. The first side surface and the second side surface have a first negative slope and a second negative slope, respectively, relative to the upper surface of the first portion of the contact plug.

8. The method according to claim 1, in, The second portion of the contact plug extends upward from a portion of the first portion of the contact plug, and Wherein, a portion of the first portion of the contact plug is disposed between opposite ends of the first portion of the contact plug in the second direction.

9. The method according to claim 8, in, The second portion of the contact plug has a first side surface and a second side surface that are opposite each other, and The first side surface and the second side surface have slopes with opposite signs relative to the upper surface of the first portion of the contact plug.

10. The method according to claim 1, in, At least except for the recessed edges, the upper surface of each of the gate coatings is substantially flat.

11. The method according to claim 10, in, The upper surface of each of the gate coatings is substantially coplanar with the upper surface of the second portion of the contact plug.

12. The method according to claim 1, further comprising: A second interlayer insulating layer is formed on the contact plug and the gate cover; Forming a through hole that exposes a portion of the second part of the contact plug; as well as The through-hole is filled with a conductive material.

13. The method according to claim 1, further comprising: A gate contact plug is formed through the gate cladding to connect to the gate structure. The gate contact plug is configured to overlap with the active region.

14. The method according to claim 13, in, The contact insulating layer is spaced apart from the gate contact plug in the first direction.

15. A method for manufacturing a semiconductor device, the method comprising: An active region extending along a first direction is formed on the substrate; A gate structure is formed on the substrate, the gate structure extending along a second direction to intersect with the active region; Remove the upper portion of the gate structure and form a gate cladding layer at the location where the upper portion of the gate structure has been removed; A preliminary contact plug is formed that is electrically connected to a portion of the active region, the preliminary contact plug comprising a first portion and a second portion; A mask pattern layer is formed, the mask pattern layer including a first pattern layer and a second pattern layer, the first pattern layer covering the upper surface of the gate cover and extending along the second direction and spaced apart from each other in the first direction, the second pattern layer extending from the first pattern layer along the first direction to cover the second portion of the initial contact plug and spaced apart from each other in the second direction; as well as Using the mask pattern layer as an etching mask, a contact plug is formed by recessing the first portion of the initial contact plug exposed by the mask pattern layer from the upper surface of the initial contact plug to a predetermined depth.

16. The method according to claim 15, in, The active region includes: Active fins, the active fins extending on the substrate along the first direction; and Multiple channel layers are configured to be perpendicularly spaced from each other on a portion of the active fin, and Wherein, a portion of the active fin overlaps with the gate structure.

17. The method according to claim 15, in, The first patterned layer exposes the relative edges of the gate overlay in the first direction, and When the first portion of the initial contact plug is recessed, the opposite edge of the gate coating exposed by the first pattern layer is partially removed.

18. A method for manufacturing a semiconductor device, the method comprising: An active region extending along a first direction is formed on the substrate; A sacrificial gate structure extending in a second direction to intersect with the active region is formed on the substrate; Source / drain regions are formed on the active region on opposite sides of each of the sacrificial gate structures; Remove the sacrificial gate structure and form a gate structure where the sacrificial gate structure has been removed; Remove the upper portion of the gate structure and form a gate cladding layer at the location where the upper portion of the gate structure has been removed; Forming an initial contact plug that extends to connect to a corresponding source / drain region, the initial contact plug comprising a first portion and a second portion; A mask pattern layer in the form of a grid is formed on the initial contact plug and the gate cover to expose the first portion of the initial contact plug; as well as Using the mask pattern layer as an etching mask, a contact plug is formed by recessing the first portion of the initial contact plug exposed by the mask pattern layer to form a recessed region, wherein the contact plug includes a first portion and a second portion extending upward from the first portion. The mask pattern layer includes: A first patterned layer, disposed on the gate cover layer, extending along the second direction and spaced apart from each other in the first direction; and A second pattern layer is disposed on the second portion of the initial contact plug, extends along the first direction to connect with the first pattern layer and is spaced apart from each other in the second direction.

19. The method according to claim 18, in, The mask pattern layer, in addition to exposing the first portion of the initial contact plug, also exposes the edge of the gate overlay, and The edge of the gate coating is recessed.

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