SiC MOSFET power devices

Abstract

The present invention provides a novel SiC MOSFET power device, comprising: a substrate; a drain metal layer disposed under the substrate; a drift region disposed on the substrate; a well region disposed on the drift region; a source region disposed on the well region; a channel region disposed on the well region; a trench disposed parallel to the direction of channel current in the channel region and passing through the channel region and reaching the source region; a gate metal layer disposed on the trench; and a source metal layer disposed on the gate metal layer. The present invention can increase the channel width of the trench sidewalls, and because different surfaces of silicon carbide have different electron mobilities, a side with relatively high electron mobility can be selected, thereby ensuring that the electron mobility of the inversion layer of the trench sidewalls is higher than that of the inversion layer on the device surface, thereby effectively reducing the channel resistance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a novel SiC MOSFET power device. Background Art

[0002] Currently, the main types of SiC power MOSFET devices are planar MOSFET and trench MOSFET. However, the thermally grown oxide layer of planar MOSFET and the low surface quality of the SiC surface make the inversion layer mobility only 5%-10% of that in the body, making the device channel resistance very high. In addition, trench MOSFET also has similar problems. Summary of the Invention

[0003] The present invention aims to at least partially address one of the technical problems in the above-mentioned technologies. To this end, the present invention provides a novel SiC MOSFET power device that increases the channel width of the trench sidewalls. Because different surfaces of silicon carbide have different electron mobilities, the side surfaces with relatively high electron mobility can be selected, thereby ensuring that the electron mobility of the inversion layer of the trench sidewalls is higher than that of the device surface, thereby effectively reducing the channel resistance of the device.

[0004] To achieve the above objectives, an embodiment of the present invention provides a novel SiC MOSFET power device, comprising: a substrate; a drain metal layer, the drain metal layer being disposed under the substrate; a drift region, the drift region being disposed on the substrate; a well region, the well region being disposed on the drift region; a source region, the source region being disposed on the well region; a channel region, the channel region being disposed on the well region; a trench, the trench being disposed parallel to a direction of channel current in the channel region, and the trench passing through the channel region and reaching the source region; a gate metal layer, the gate metal layer being disposed on the trench; and a source metal layer, the source metal layer being disposed on the gate metal layer.

[0005] According to the novel SiC MOSFET power device proposed in an embodiment of the present invention, a substrate is provided, a drain metal layer is sputtered under the substrate, a drift region and a channel region are epitaxially formed on the substrate, a well region and a source region are formed by implantation, a trench parallel to the direction of the channel current in the channel region is provided, and the trench passes through the channel region and reaches the source region, and a gate metal layer and a source metal layer are also provided. Thus, the channel width of the trench sidewall can be increased, and because different surfaces of silicon carbide have different electron mobilities, a side with relatively high electron mobility can be selected, thereby ensuring that the electron mobility of the inversion layer of the trench sidewall is higher than the electron mobility of the inversion layer of the device surface, thereby effectively reducing the channel resistance of the device.

[0006] In addition, the novel SiC MOSFET power device proposed in the above embodiment of the present invention may also have the following additional technical features:

[0007] According to one embodiment of the present invention, the well region includes a first well region and a second well region; the depths of the source region and the channel region are the same as the depth of the trench, and a third well region is further provided at the bottom of the trench.

[0008] According to an embodiment of the present invention, the depth of the third well region is the same as the depth of the second well region.

[0009] According to one embodiment of the present invention, the well region includes a first well region and a second well region; the depths of the source region and the channel region are greater than the depth of the trench, and the depth of the second well region is greater than the depths of the channel region and the source region.

[0010] According to an embodiment of the present invention, a floating region is provided at the bottom of the trench, and doping materials are further provided around the floating region to form a doping region. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Schematic diagram of the structure of a novel SiC MOSFET power device according to an embodiment of the present invention;

[0012] Figure 2 A top view of a novel SiC MOSFET power device according to an embodiment of the present invention;

[0013] Figure 3 A2A2' is a schematic cross-sectional view of a novel SiC MOSFET power device according to an embodiment of the present invention;

[0014] Figure 4 Schematic cross-sectional view of B1B1′ of a novel SiC MOSFET power device according to an embodiment of the present invention;

[0015] Figure 5 Schematic cross-sectional view of B2B2' of a novel SiC MOSFET power device according to an embodiment of the present invention;

[0016] Figure 6 Schematic cross-sectional view of B3B3' of a novel SiC MOSFET power device according to an embodiment of the present invention;

[0017] Figure 7 Schematic diagram of the structure of a novel SiC MOSFET power device according to another embodiment of the present invention;

[0018] Figure 8A schematic cross-sectional view of A2A2′ of a novel SiC MOSFET power device according to another embodiment of the present invention;

[0019] Figure 9 FIG1 is a schematic cross-sectional view of B1B1′ of a novel SiC MOSFET power device according to another embodiment of the present invention;

[0020] Figure 10 FIG2 is a schematic cross-sectional view of B2B2′ of a novel SiC MOSFET power device according to another embodiment of the present invention;

[0021] Figure 11 FIG3 is a schematic cross-sectional view of a novel SiC MOSFET power device taken along line B3B3′ according to another embodiment of the present invention;

[0022] Figure 12 FIG. 1 is a schematic cross-sectional view of B4B4′ of a novel SiC MOSFET power device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] Figure 1 Schematic diagram of the structure of a new SiC MOSFET power device according to an embodiment of the present invention.

[0025] like Figure 1 As shown, the novel SiC MOSFET power device according to an embodiment of the present invention includes a substrate 10; a drain metal layer 20; the drain metal layer 20 is disposed under the substrate 10; a drift region 30, the drift region 30 is disposed on the substrate 10; a well region 40, the well region 40 is disposed on the drift region 30; a source region 50, the source region 50 is disposed on the well region 40; a channel region 60, the channel region 60 is disposed on the well region 40; a trench 70, the trench 70 is disposed parallel to the direction of the channel current in the channel region 60, the trench 70 passes through the channel region 60 and reaches the source region 50; a gate metal layer 80, the gate metal layer 80 is disposed on the trench 70; and a source metal layer 90, the source metal layer 90 is disposed on the gate metal layer 80. Among them, Figure 1 The channel region 60 shown is penetrated by the trench 70 , so a dotted line is used to indicate the location of the channel region 60 .

[0026] Specifically, the substrate 10 may be an N+ substrate, and the drain metal layer 20 may be sputtered under the substrate 10, i.e., the N+ substrate; the drift region 30 may be an N-drift region, which may be epitaxially formed on the substrate 10, i.e., the N+ substrate; the well region 40 may be a P+ well region, which may be formed on the drift region 30, i.e., the N-drift region, by photolithographic implantation; the source region 50 may be an N+ source region, which may be formed on the well region 40, i.e., the P+ well region, by photolithographic implantation; the channel region 60 may be a P-channel region; the trench 70 may be formed at the bottom of the gate metal layer 80 by etching, and is arranged parallel to the direction of the channel current in the channel region 60, thereby increasing the channel width of the trench sidewall, and since different surfaces of silicon carbide have different electron mobilities, a side with relatively high electron mobility may be selected, thereby ensuring that the inversion layer electron mobility of the trench sidewall is higher than the inversion layer electron mobility of the device surface, thereby effectively reducing the channel resistance of the device.

[0027] In one embodiment of the present invention, Figure 1 As shown, the well region 40 may include a first well region 401, i.e., a P+1 well region and a second well region 402, i.e., a P+2 well region. The depth of the source region 50 and the channel region 60 is the same as the depth of the trench 70, and a third well region 100, i.e., a P+3 well region, is also provided at the bottom of the trench 70.

[0028] It should be noted that the above Figure 1 It is only a partial cross-sectional schematic diagram of the novel SiC MOSFET power device of the present invention, specifically, only Figure 2 In order to further illustrate the structure of the novel SiC MOSFET power device of the present invention, the following will be combined with Figure 2 The cross-sectional schematic diagrams of A2A2', B1B1', B2B2', and B3B3' in FIG. 1 illustrate the structure of the novel SiC MOSFET power device of the present invention.

[0029] Combine Figure 3 ,Right now Figure 2 A2A2' cross-sectional diagram, Figure 4 ,Right now Figure 2 Schematic diagram of the cross section of B1B1', Figure 5 ,Right now Figure 2 Schematic cross-sectional view of B2B2', Figure 6 ,Right now Figure 2 As shown in the cross-sectional diagram of B3B3′, the third well region, ie, the P+3 well region, is disposed at the bottom of the trench 70, and the depth of the third well region, ie, the P+3 well region, is the same as the depth of the second well region, ie, the P+2 well region.

[0030] It should be further explained that the above embodiment Figure 1The new SiC MOSFET power device shown can be manufactured using the following two processes, which are described below.

[0031] First, the above embodiment Figure 1 The manufacturing process of the new SiC MOSFET power device shown is as follows: 1. Epitaxy: a drift region, i.e., an N-drift region, and a channel region, i.e., a P-channel region, can be formed by epitaxy on the surface of a substrate, such as a SiC substrate; 2. Doping region implantation: a doping region, i.e., an N+1 region, can be first defined by photolithography, and then nitrogen ions or phosphorus ions of different energies can be implanted to compensate the corresponding channel region, i.e., the P-channel region, to be N-type doped to form an N+1 doping region; 3. Source region photolithography and implantation: a region to be implanted can be first defined by photolithography, and then nitrogen ions or phosphorus ions of different energies can be implanted in the corresponding region to form an N+ source region; 4. First well region photolithography and implantation: a first well region to be implanted, i.e., a P+1 well region, can be first defined by photolithography, and then aluminum ions of different energies can be implanted in the corresponding region to form a P+1 well region; 5. Second well region photolithography and implantation: a second well region to be implanted, i.e., a P+2 well region, can be first defined by photolithography, and then aluminum ions of different energies can be implanted in the corresponding region to form a P+2 well region. Well area; 6. Groove etching, define the groove area by photolithography, and perform silicon carbide etching; 7. Third well area injection, which can form a P+3 well area by injecting aluminum ions of different energies in the corresponding area; 8. Gate oxidation, using thermal oxidation to grow an oxide layer on the silicon surface to form gate oxide; 9. Polysilicon deposition, deposit a layer of polysilicon on the gate oxide, fill the trench, and form a polysilicon gate; 10. Polysilicon photolithography and etching, photolithography defines different polysilicon gate areas, and etches away unnecessary polysilicon; 11. Dielectric layer deposition, depositing an insulating dielectric layer on the surface as electrical isolation between the polysilicon and the metal; 12. Hole lithography and etching, lithography defines the hole layer in the well area and the hole layer on different polysilicon gates, and etches away the dielectric layer in unnecessary areas; 13. Metal layer deposition, depositing a layer of metal on the insulating dielectric layer; 14. Metal layer lithography and etching, lithography defines the active layer metal area and the gate metal area, and performs etching to form the source metal layer and gate metal layer of the device.

[0032] It should be noted that steps 2-5 of the above production process can be adjusted according to actual production conditions.

[0033] Second, the above embodiment Figure 1The manufacturing process of the new SiC MOSFET power device shown is as follows: 1. Epitaxy: a drift region, i.e., an N-drift region, can be formed by epitaxy on the surface of a substrate, such as a SiC substrate; 2. Channel region implantation: a P-region can be first defined by photolithography, and aluminum ions can be implanted to form a P-channel region; 3. Doping region implantation: a doping region, i.e., an N+1 region, can be first defined by photolithography, and then nitrogen ions or phosphorus ions of different energies can be implanted to compensate the corresponding channel region, i.e., the P-channel region, for N-type doping to form an N+1 doping region; 4. Source region photolithography , injection, you can first photolithography to define the area to be injected, and then you can inject nitrogen ions or phosphorus ions of different energies into the corresponding area to form an N+ source area; 5, the first well area photolithography, injection, you can first photolithography to define the first well area to be injected, that is, the P+1 well area, and then you can inject aluminum ions of different energies into the corresponding area to form a P+1 well area; 6, the second well area photolithography, injection, you can first photolithography to define the second well area to be injected, that is, the P+2 well area, and then you can inject aluminum ions of different energies into the corresponding area to form a P+2 well area. Amount of aluminum ions to form a P+2 well region; 7. Trench etching, photolithography defines the trench area and performs silicon carbide etching; 8. Third well region injection, by injecting aluminum ions of different energies into the corresponding area, a P+3 well region with a well area is formed; 9. Gate oxidation, using thermal oxidation to grow an oxide layer on the silicon surface to form a gate oxide; 10. Polysilicon deposition, depositing a layer of polysilicon on the gate oxide, filling the trench to form a polysilicon gate; 11. Polysilicon lithography and etching, photolithography defines different polysilicon gate areas, and Etch away the unnecessary polysilicon; 12. Dielectric layer deposition, deposit an insulating dielectric layer on the surface to serve as electrical isolation between the polysilicon and the metal; 13. Hole lithography and etching, lithography defines the hole layer in the well area and the hole layer on different polysilicon gates, and etches away the dielectric layer in the unnecessary area; 14. Metal layer deposition, deposit a layer of metal on the insulating dielectric layer; 15. Metal layer lithography and etching, lithography defines the active layer metal area and the gate metal area, and performs etching to form the source metal layer and gate metal layer of the device.

[0034] It should be noted that steps 2-6 of the above production process can be adjusted according to actual production conditions.

[0035] In another embodiment of the present invention, as shown in FIG7 , the well region 40 includes a first well region 401 and a second well region 402 , and a floating region 200 is provided at the bottom of the trench 70 , such as a P+4 floating region, and an impurity is also provided around the floating region 200 to form a doped region 300 , such as an N+1 doped region.

[0036] It should be noted that the above Figure 7 It is only a partial cross-sectional schematic diagram of the novel SiC MOSFET power device of the present invention, specifically, only Figure 2In order to further illustrate the structure of the novel SiC MOSFET power device of the present invention, the following will be combined with Figure 2 The cross-sectional schematic diagrams of A2A2', B1B1', B2B2', B3B3', and B4B4' in FIG. 1 illustrate the structure of the novel SiC MOSFET power device of the present invention.

[0037] Combine Figure 8 ,Right now Figure 2 A2A2' cross-sectional diagram, Figure 9 ,Right now Figure 2 Schematic diagram of the cross section of B1B1', Figure 10 ,Right now Figure 2 Schematic cross-sectional view of B2B2', Figure 11 ,Right now Figure 2 Schematic diagram of the cross section of B3B3', Figure 12 ,Right now Figure 2 As can be seen from the cross-sectional schematic diagram B4B4′ in FIG, the depths of the source region 50 and the channel region 60 are greater than the depth of the trench 70 , and the depth of the second well region 402 is greater than the depths of the channel region 60 and the source region 50 .

[0038] It should be further explained that the above embodiment Figure 7 The new SiC MOSFET power device shown can be manufactured using the following two processes, which are described below.

[0039] First, the above embodiment Figure 7The manufacturing process of the new SiC MOSFET power device shown is as follows: 1. Epitaxy, which can form a drift region, i.e., an N-drift region, and a channel region, i.e., a P-channel region, on the surface of a substrate, such as a SiC substrate; 2. Doping region implantation, which can first be photolithographically defined to define the doping region, i.e., the N+1 region, and then can be implanted with nitrogen ions or phosphorus ions of different energies to compensate the corresponding channel region, i.e., the P-channel region, for N-type doping to form an N+1 doping region; 3. Photolithography and implantation of the first well region, which can first be photolithographically defined to define the first well region to be implanted. Region, namely P+1 well region, and then different energy aluminum ions can be injected into the corresponding region to form a P+1 well region; 4. Floating region injection, the floating region to be injected can be defined by photolithography first, namely P+4 region, and then aluminum ions can be injected into the region to form a floating region, namely P+4 region; 5. Source region photolithography and injection, the region to be injected can be defined by photolithography first, and then different energy nitrogen ions or phosphorus ions can be injected into the corresponding region to form an N+ source region; 6. Second well region photolithography and injection, the floating region to be injected can be defined by photolithography first, and then different energy nitrogen ions or phosphorus ions can be injected into the corresponding region to form an N+ source region; Photolithography defines the second well area that needs to be injected, namely the P+2 well area, and then the P+2 well area can be formed by injecting aluminum ions of different energies into the corresponding area; 7. Trench etching, photolithography defines the trench area and performs silicon carbide etching; 8. Gate oxidation, using thermal oxidation to grow an oxide layer on the silicon surface to form a gate oxide; 9. Polysilicon deposition, depositing a layer of polysilicon on the gate oxide, filling the trench to form a polysilicon gate; 10. Polysilicon photolithography and etching, photolithography defines different polysilicon gate areas and etches Etch away the unnecessary polysilicon; 11. Dielectric layer deposition, deposit an insulating dielectric layer on the surface to serve as electrical isolation between the polysilicon and the metal; 12. Hole lithography and etching, lithography defines the hole layer in the well area and the hole layer on different polysilicon gates, and etches away the dielectric layer in the unnecessary area; 13. Metal layer deposition, deposit a layer of metal on the insulating dielectric layer; 14. Metal layer lithography and etching, lithography defines the active layer metal area and the gate metal area, and performs etching to form the source metal layer and gate metal layer of the device.

[0040] It should be noted that steps 2-6 of the above production process can be adjusted according to actual production conditions.

[0041] Second, the above embodiment Figure 7The manufacturing process of the new SiC MOSFET power device shown is as follows: 1. Epitaxy: a drift region, i.e., an N-drift region, can be formed on the surface of a substrate, such as a SiC substrate; 2. Channel region implantation: a P-region can be first defined by photolithography, and aluminum ions are implanted to form a P-channel region; 3. Doping region implantation: a doping region, i.e., an N+1 region, can be first defined by photolithography, and then nitrogen ions or phosphorus ions of different energies can be implanted to compensate the corresponding channel region, i.e., the P-channel region, for N-type doping to form an N+1 doping region; 4. Photolithography and implantation of the first well region. Injection, the first well area to be injected can be defined by photolithography, that is, the P+1 well area, and then aluminum ions of different energies can be injected into the corresponding area to form the P+1 well area; 5. Floating area injection, the floating area to be injected can be defined by photolithography, that is, the P+4 area, and then aluminum ions can be injected into the area to form the floating area, that is, the P+4 area; 6. Source area photolithography and injection, the area to be injected can be defined by photolithography, and then nitrogen ions or phosphorus ions of different energies can be injected into the corresponding area to form the N+ source area; 7. Second well area lithography and implantation: first, the second well area to be implanted, namely the P+2 well area, can be defined by lithography, and then aluminum ions of different energies can be injected into the corresponding area to form the P+2 well area; 8. Groove etching: lithography defines the groove area and performs silicon carbide etching; 9. Gate oxidation: thermal oxidation is used to grow an oxide layer on the silicon surface to form a gate oxide; 10. Polysilicon deposition: a layer of polysilicon is deposited on the gate oxide to fill the trench and form a polysilicon gate; 11. Polysilicon lithography and etching: lithography defines different polysilicon Gate area, and etch away unnecessary polysilicon; 12. Dielectric layer deposition, depositing an insulating dielectric layer on the surface as an electrical isolation between polysilicon and metal; 13. Hole lithography and etching, lithography defines the hole layer in the well area and the hole layer on different polysilicon gates, and etches away the dielectric layer in unnecessary areas; 14. Metal layer deposition, depositing a layer of metal on the insulating dielectric layer; 15. Metal layer lithography and etching, lithography defines the active layer metal area and the gate metal area, and etching is performed to form the source metal layer and gate metal layer of the device.

[0042] It should be noted that steps 2-7 of the above production process can be adjusted according to actual production conditions.

[0043] According to the novel SiC MOSFET power device proposed in an embodiment of the present invention, a substrate is provided, a drain metal layer is sputtered under the substrate, a drift region and a channel region are epitaxially formed on the substrate, a well region and a source region are formed by implantation, a trench parallel to the direction of the channel current in the channel region is provided, and the trench passes through the channel region and reaches the source region, and a gate metal layer and a source metal layer are also provided. Thus, the channel width of the trench sidewall can be increased, and because different surfaces of silicon carbide have different electron mobilities, a side with relatively high electron mobility can be selected, thereby ensuring that the electron mobility of the inversion layer of the trench sidewall is higher than the electron mobility of the inversion layer of the device surface, thereby effectively reducing the channel resistance of the device.

[0044] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. "Multiple" means two or more, unless otherwise specifically defined.

[0045] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0046] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0047] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

Claims

1. A SiC MOSFET power device, characterized in that: include: substrate; a drain metal layer, the drain metal layer being disposed under the substrate; a drift region, wherein the drift region is disposed on the substrate; a well region, the well region being disposed on the drift region; a source region, the source region being disposed on the well region; a channel region, the channel region being disposed on the well region; a trench, wherein the trench is arranged parallel to a direction of a channel current in the channel region and passes through the channel region and reaches the source region; a gate metal layer, the gate metal layer being disposed on the trench; a source metal layer, the source metal layer being disposed on the gate metal layer, The well region includes a first well region and a second well region; the depths of the source region and the channel region are greater than the depth of the trench, and the depth of the second well region is greater than the depths of the channel region and the source region; a floating region is provided at the bottom of the trench, and doping materials are further provided around the floating region to form a doped region. The drift region is an N-region, the well region is a P+ region, the source region is an N+ region, the channel region is a P-region, the floating region is a P+ region, and the doped region is an N+ region.

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