Efficient high voltage digital i / o protection

Abstract

Embodiments of the present disclosure generally relate to efficient high voltage digital I / O protection. A circuit to protect digital input and output (I / O) terminals from overvoltage externally applied to the digital I / O terminals. The circuit is arranged similar to a bootstrap switch such that a pass device protects an output driver from overvoltage applied to the digital I / O terminals, and the output driver controls operation of the pass device, such as a N-channel metal-oxide-semiconductor (NMOS) transistor. The circuit can include a capacitor and a diode coupled to a gate of the NMOS transistor. A digital zero from the output driver charges the capacitor. A digital one from the output driver causes the charged capacitor coupled between a source and the gate of the NMOS transistor to provide sufficient gate-source voltage to pass the digital one from the driver to the digital I / O terminal. The circuit further includes a refresh circuitry configured to maintain the gate-source voltage on the capacitor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to overvoltage protection of digital circuits. BACKGROUND

[0002] Digital circuits can operate in environments where digital output terminals can be subjected to voltages high enough to damage the digital circuit, for example, high voltages caused by a fault or a transient voltage in the system can be applied to the digital output terminals. To protect the digital circuit device, the digital circuit can utilize an output driver to drive the digital output terminals, which can withstand damage from overvoltage at the digital output terminals. The output driver that withstands overvoltage damage can have drawbacks in that the driver can take up a relatively large area on an integrated circuit (IC) and can have a slower operating speed when compared to a low voltage output driver that has a lower overvoltage withstand capability. In other examples, a pass device, such as a transistor, can protect a lower voltage output driver from overvoltage at the digital output terminals. SUMMARY

[0003] Generally, the present disclosure is directed to a circuit configured to protect a digital input and output (I / O) terminal from an overvoltage externally applied to the digital I / O terminal. The circuit can be arranged to include a circuit device similar to a bootstrap switch such that a pass device protects an output driver from a possible overvoltage applied to the digital I / O terminal and the output driver controls operation of the pass device. In one example, the pass device is an N-channel metal-oxide-semiconductor (NMOS) transistor. The circuit can include a capacitor and a diode coupled to a gate of the NMOS transistor. A digital zero from the output driver to the output terminal can charge the capacitor. When the output driver sends a digital one to the output terminal, the charged capacitor coupled between a source and the gate of the NMOS transistor is configured to provide enough gate-source voltage to pass the digital one from the driver to the digital I / O terminal. The circuit can also include a refresh circuit device configured to maintain the gate-source voltage on the capacitor.

[0004] In one example, the present disclosure is directed to a circuit, the circuit comprising: a driver circuit including an input element and an output element, wherein the output element is electrically coupled to a digital output terminal via a pass device. The pass device includes a first terminal, a second terminal, and a control terminal, the pass device is configured to protect the driver circuit from an overvoltage applied to the digital output terminal, the output element of the driver circuit is electrically connected to the first terminal of the pass device and connected to the control terminal of the pass device via a capacitor, the control terminal of the pass device is coupled to a supply voltage through a switch, and the second terminal of the pass device is coupled to the digital output terminal.

[0005] In another example, the disclosure is directed to a method, the method comprising: in response to receiving a digital zero at an input element of a driver circuit, charging a capacitor such that a magnitude of a voltage across the capacitor is approximately a first supply voltage, wherein the capacitor is coupled to the first supply voltage through a switch, and wherein the capacitor is connected between a gate and a source of an N-channel metal-oxide-semiconductor (NMOS) pass device. In response to receiving a digital one at the input element of the driver circuit, applying a second voltage to the source of the NMOS pass device through the driver circuit such that a gate-source voltage of the NMOS pass device is approximately the magnitude of the voltage across the capacitor.

[0006] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a block diagram illustrating a digital I / O terminal with output driver protection circuitry in accordance with one or more techniques of the disclosure.

[0008] Figure 2 is a schematic diagram of a digital I / O terminal illustrating an example implementation of a refresh circuit in accordance with one or more techniques of the disclosure.

[0009] Figure 3 is a timing diagram depicting example operations of the refresh circuit described with respect to Figure 1 and Figure 2 is a timing diagram depicting example operations of the refresh circuit described with respect to

[0010] Figure 4A is a schematic diagram of an example digital I / O protection circuit with overvoltage monitoring in accordance with one or more techniques of the disclosure.

[0011] Figure 4B is a schematic diagram of an example digital I / O protection circuit illustrating details of an example implementation with overvoltage monitoring in accordance with one or more techniques of the disclosure.

[0012] Figure 5 is an example digital output protection circuit that operates a pass device using a charge pump and a pull-down circuit.

[0013] Figure 6 is a flow diagram illustrating example operations of a circuit of the disclosure. DETAILED DESCRIPTION

[0014] The present disclosure is directed to a circuit configured to protect a digital input and output (I / O) terminal from an externally applied overvoltage to the digital I / O terminal. The circuit protects the digital I / O terminal with a pass device that protects an output driver for the digital I / O terminal from a possible overvoltage applied to the digital I / O terminal. The circuit can be arranged similar to a bootstrap switch, but unlike other examples of protection circuits, the output driver can control the operation of the pass device rather than controlling the operation of an additional circuit device, such as a charge pump.

[0015] In some examples, the pass device can include an N-channel metal-oxide-semiconductor (NMOS) transistor. The circuit can include a capacitor and a diode coupled to a gate of the NMOS transistor. A digital zero from the output driver to the output terminal charges the capacitor. When the output driver sends a digital one to the output terminal, the charged capacitor coupled between a source and the gate of the NMOS transistor is configured to provide enough gate-source voltage to the NMOS transistor to pass the digital one from the driver to the digital I / O terminal.

[0016] In some examples, such as when the digital I / O terminal outputs a digital one for an extended period of time, components in the circuit can suffer from leakage. Some examples of sources of leakage can include gate leakage for the NMOS transistor, leakage across the capacitor, and the like. To counteract these or other types of leakage, the circuit can also include a refresh circuit device that maintains the gate source voltage across the capacitor to ensure that the pass device remains in a conductive state when outputting a digital one.

[0017] Figure 1 is a block diagram illustrating a digital I / O terminal with an output driver protection circuit device according to one or more techniques of the present disclosure. The circuit 100 can be implemented in many different types of circuits, where the digital output terminal provides a digital output signal to one or more other components in a system.

[0018] In Figure 1 the example, the circuit 100 includes a driver circuit 102 that is electrically coupled to the digital output terminal 106 through a pass device 112. A bootstrap circuit device 110 includes a capacitor CI 114 and a diode DI 116 that connects a control terminal 134 of the pass device 112 to Vdd. The capacitor CI 114 connects an output element 132 of the driver circuit 102 to the control terminal 134. In Figure 1 the example, the output element 132 of the driver circuit 102 is electrically directly connected to an input terminal of the pass device 112.

[0019] The refresh circuit 120 receives a signal from the input element 104 and includes an output element, a refresh output element 130, which is coupled to a control terminal 134 of the pass device 112. The refresh circuit 120 also includes a clock input element 122.

[0020] The driver circuit 102 can include a digital output driver that receives a digital signal at the input element 104 and outputs a buffered digital signal at the output element 132. In some examples, the digital signal to the input element 104 can come from a digital circuitry on the same IC as the circuit 100. The driver circuit 102 can also be connected to a digital supply voltage V DDIO and a reference voltage Vss. In Figure 1 the example, V DDIO is approximately 5V and the reference voltage Vss is approximately zero volts. A digital zero received at the input element 104 can cause the driver circuit 102 to output a digital zero at the output element 132, i.e., approximately zero volts. Similarly, a digital one at the input element 104 can cause the driver circuit 102 to output a digital one at the output element 132, i.e., approximately V DDIO .

[0021] The bootstrap circuitry 110 works using principles similar to a bootstrap switch circuit, which is a circuit that can be used to drive a gate voltage on a high-side switch to be higher than the supply rail. However, unlike a typical bootstrap switch circuit, in the example of the circuit 100, the anode of the diode D1 116 is connected to Vdd, while the cathode is connected to the control terminal 134 and one terminal of the capacitor C1 114.

[0022] In operation, when the circuit 100 receives a digital zero at the input element 104, the driver circuit 102 outputs a digital zero at the output element 132, causing the capacitor C1 114 to charge to approximately Vdd. In other words, the driver circuit 102 is configured to output the reference voltage Vss to the first plate of the capacitor C1 114, causing the second plate of the capacitor C1 114, which is coupled to the cathode of D1 116, to charge to approximately the size of the supply voltage (Vdd). The voltage across C1 114 becomes Vdd, minus the voltage drop across D1 116, minus any further voltage drop between the output element 132 and the reference voltage Vss. In Figure 1 the example, Vss is zero volts. In Figure 1 the example, Vdd is approximately half the size of V DDIO . In Figure 1 the example, V DDIO is approximately 5V and Vdd is approximately 2.5V. In another example, Vdd and V DDIOSet to different voltage values, such as V DDIO = 3.3V. In other examples, Vdd can be set to the same value as V. DDIO Half of the same size.

[0023] When circuit 100 receives the digital number 1 at input element 104, driver circuit 102 outputs the digital number 1 at output element 132. Figure 1 The number in the example is approximately V DDIO Subtract V DDIO Any voltage drop between the output element 132 and the output element 132. Capacitor C1 114 can maintain the voltage between its first and second plates, thus maintaining the voltage between the input terminal and control terminal 134 of the transfer device 112 at approximately Vdd, ensuring that the transfer device 112 allows the digital signal from the driver circuit 102 to be output from the digital output terminal 106. In the example where the transfer device 112 is an NMOS transistor, capacitor C1 114 can provide sufficient gate-source voltage (Vgs) to keep the NMOS transistor on. In the example of an insulated-gate bipolar transistor (IGBT), capacitor C1 114 can provide sufficient gate voltage to ensure the IGBT remains on. Note that the terms "first plate" and "second plate" are used for simplification. Figure 1 Explanation of the bootstrap circuit device 110 shown. A practical capacitor can be constructed using multilayer plates and dielectric materials. Furthermore, in this disclosure, the first plate can be described as being connected to a first terminal or a first element of the capacitor C1 114. Similarly, the second plate can be described as being connected to a second terminal or a second element of the capacitor C1 114.

[0024] In some examples, diode D1 116 can operate as a switch because it conducts when the voltage at control terminal 134 is less than Vdd. When the voltage at control terminal 134 is greater than Vdd, D1 116 will prevent current from flowing from control terminal 134 to Vdd. Therefore, when the voltage at control terminal 134 is greater than Vdd, diode D1 116 can be considered an open switch.

[0025] The refresh output element 130 of the refresh circuit 120 is connected to the control terminal 134. In operation, when the circuit 100 receives a digital '1' at the input element 104, the enable input element 136 activates the refresh circuit 120 to apply a predetermined voltage amplitude at the control terminal 134 of the transfer device 112. The refresh circuit 120 is configured to periodically apply a predetermined voltage at the gate of the transfer device based on a clock signal received at the clock input element 122 to counteract any leakage in the bootstrap circuit arrangement 110 (e.g., at capacitor C1 114). The circuit arrangement of the circuit 100 offers the advantage of reduced current consumption compared to other techniques.

[0026] Figure 2 This is a schematic diagram illustrating an example implementation of a digital I / O terminal with a refresh circuit according to one or more techniques of this disclosure. Circuit 200 is as described above regarding... Figure 1 An example of the described circuit 100.

[0027] exist Figure 2 In the example, circuit 200 includes driver circuitry 202, which is electrically coupled to digital output terminal 206 via a pass-through device (such as transistor M1 212). Bootstrap circuitry 210 also includes capacitor C1 214 and diode D1 216, diode D1 216 connecting the gate 234 of transistor M1 212 to Vdd. Capacitor C1 214 connects the output element 232 of driver circuitry 202 to gate 234. Figure 2 In this example, the output element 232 of the driver circuit 102 is electrically connected to the input terminal, namely the source of transistor M1 212. The components include driver circuit 202, digital output terminal 206, transistor M1 212, bootstrap circuit device 210, C1 214, diode D1 216, gate 234, Vss, Vdd, and V... DDIO The refresh circuit 220 is respectively Figure 1 The driver circuit 102, digital output terminal 106, transmission device 112, bootstrap circuit device 110, C1114, diode D1 116, control terminal 134, Vdd, V DDIO Example of refresh circuit device 120. Driver circuit 202, digital output terminal 206, transistor M1 212, bootstrap circuit device 210, C1 214, diode D1 216, gate 234, Vss, Vdd, V DDIO The characteristics and functions of the refresh circuit device 220 can be respectively related to Figure 1 The driver circuit 102, digital output terminal 106, transmission device 112, bootstrap circuit device 110, C1 114, diode D1 116, control terminal 134, Vdd, VDDIO and the refresh circuitry 120 are similar or identical in nature and function.

[0028] The pass device in the example of the circuit 200 is a high voltage NMOS transistor M1 212, the drain of which is connected to the digital output terminal 206. For an N-channel MOSFET, due to the low on-resistance (R DS-ON ), the NMOS transistor M1 212 can provide improved efficiency when compared to other types of pass devices. Also, for the same on-resistance, N-channel MOSFETs can be lower cost compared to P-channel MOSFETs, e.g., N-channel MOSFETs can require less die real estate on an IC compared to P-channel MOSFETs. However, turning an N-channel MOSFET fully on requires a sufficiently high V GS to minimize R DS-ON and avoid losses (such as heat losses) that can reduce efficiency.

[0029] As described above with respect to Figure 1 the bootstrap circuitry 210 can provide a gate-source voltage to ensure that the transistor M1 212 remains on when the driver circuit 202 outputs a digital one (having a magnitude of approximately V DDIO .

[0030] Thus, when the driver circuit 202 outputs a digital zero, the V GS of the transistor M1 212 is equal to Vdd - Vdiode1, where Vdiode1 is the diode drop of D1 216. If the input element 204 receives a logic "1", then the driver circuit 202 outputs V DDIO (e.g., 5V) and the gate-source voltage V GS of the transistor M1 212 will be:

[0031]

[0032] where Cg represents the total parasitic capacitance seen at the gate 234 of the transistor M1 212. The capacitance value (i.e., magnitude) of C1 214 should be chosen such that the capacitance of C1 214 is sufficiently high to limit the voltage drop caused by the parasitic capacitance of the NMOS transistor M1 212, which can be affected by any parasitic gate current and non-ideal (i.e., finite) internal resistance at the gate of the transistor M1 212.

[0033] When the circuit 200 holds the digital one for a long period of time, the capacitor CI 214 and other components of the bootstrap circuit arrangement 220 can allow current to leak. The refresh circuit arrangement 220 is one example implementation of a refresh circuit configured to apply a predetermined voltage magnitude at the control terminal of the pass device transistor Ml 212 to counteract any leakage. The predetermined voltage magnitude can provide sufficient gate-source voltage at the gate 234 to ensure that the transistor Ml 212 remains fully on when the driver circuit 202 outputs a digital one. The refresh circuit 220 includes an AND gate 224, an auxiliary driver circuit 226, a capacitor C2 228, diodes D2 236 and D3 238. An enable input 236 is connected to one input element of the AND gate 224 and the clock input element 222 is connected to a second input element of the AND gate 224. The output of the AND gate 224 is connected to an input of the auxiliary driver circuit 226. The capacitor C2 228 connects the output of the auxiliary driver 226 to the cathode of the diode D2 236 and the anode of the diode D3 238. The cathode of the diode D3 238 is the refresh output 230 connected to the gate 234. The refresh output 230 is the example refresh output 130 described above with respect to Figure 1 the driver circuit 202 and the driver circuit 102 described above with respect to

[0034] Similarly to the driver circuit 202 and the driver circuit 102 described above with respect to Figure 1 the driver circuit 202 and the driver circuit 102 described above with respect to DDIO the driver circuit 202 and the driver circuit 102 described above with respect to DDIO .

[0035] In operation, a digital one received by the circuit 200 at the input element 204 will enable the clock signal received at the clock input element 222 to pass through the AND gate 224 to the auxiliary driver 226. When the clock signal is a logic low, i.e. a digital zero, the capacitor C2 228 charges to approximately Vdd. Similarly to the charging of the capacitor CI 114 described above with respect to Figure 1 the driver circuit 202 and the driver circuit 102 described above with respect to the driver circuit 202 and the driver circuit 102 described above with respect to

[0036] When the clock signal is logic one, the refresh output 230 will couple a voltage of approximately Vdd+V DDIO the size of diode D3 238 to the gate 234. The voltage applied to the gate 234 can be of a predetermined size as described above with respect to Figure 1 the examples described above with respect to the voltage applied to the control terminal 134.

[0037] Because the auxiliary driver circuitry 226 in the arrangement of the circuit 200 does not need to drive large currents, the auxiliary driver circuitry 226 can be much smaller than the main driver (i.e., the driver circuitry 202). Thus, the examples of the circuit 200 can provide advantages in reduced cost, reduced IC footprint, and reduced current consumption when compared to other techniques. Also, the frequency of the clock signal applied to the clock input element 222 can be a relatively low frequency when compared to other techniques. The lower frequency clock signal can also reduce cost, reduce interference, and reduce current consumption when compared to other techniques. The selected frequency for the clock input to the clock input element 222 can depend on the arrangement and selection of components used for the circuit 200, the size of the NMOS, or other switches used as pass devices, and the type of technology used to implement the circuit 200.

[0038] Figure 3 is a timing diagram depicting the example operation of the refresh circuit 120 and the refresh circuit 220 described above with respect to Figure 1 and Figure 2 is a timing diagram depicting the example operation of the refresh circuit 120 and the refresh circuit 220 described above with respect to Figure 3 In the example of FIG. 3B, the signal received at the input element 304 is a digital one (342) when the clock signal 322 is disabled, as shown by the refresh output 330 having the size of Vdd. As described above with respect to Figure 2 the clock signal 322 can be applied to the auxiliary driver circuitry 226 through the AND gate 224 when the signal at the input element 304 transitions to a digital one (342).

[0039] The refresh output 330 will apply a voltage of approximately Vdd+V DDIO to the control terminal of a pass device, such as the gate 234 of the transistor M1 212 depicted in Figure 2 As described above with respect to Figure 2 the voltage applied to the control terminal can be reduced by the voltage drop across the diode D3 238, such as a voltage drop.

[0040] The voltage at the control terminal can decay slightly (344) based on the amount of leakage that can be present at the control terminal. The refresh output 330 periodically applies approximately Vdd+V DDIOa predetermined magnitude is applied to a control terminal of the pass device. Applying the predetermined magnitude can maintain a gate-source voltage across the capacitor to ensure that the pass device remains conductive when the circuit outputs a digital one at a digital output terminal (such as the digital output terminal 106 described above with respect to Figure 1 the circuit 100). When the signal received at the input element 304 is a digital zero (346), the refresh circuit is disabled and the refresh output 330 returns to a magnitude of Vdd.

[0041] Figure 4A is a schematic diagram illustrating an example digital I / O protection circuit with overvoltage monitoring in accordance with one or more techniques of the present disclosure. The circuit 400A is another example of the circuit 100 and the circuit 200 described above with respect to Figure 1 and Figure 2 . Figure 4A The items depicted in the circuit 400A, such as the driver circuit device 402, the auxiliary driver circuit device 426, the AND gate 424, the input element 404, the clock input terminal 422, Vdd, V DDIO 446, the reference voltage Vss, and the digital output terminal 406 can have the same or similar characteristics as the driver circuit device 102, the auxiliary driver circuit device 226, the AND gate 224, the input element 104, the clock input terminal 122, Vdd, V Figure 1 and Figure 2 ss, and the digital output terminal 106 described above with respect to DDIO .

[0042] Similar to the circuit 100, the circuit 400A includes a pass device transistor Mpass 412 to protect the driver circuit device 402 from overvoltage events at the digital output terminal 406 as well as the bootstrap circuit to ensure that the Mpass 412 remains conductive when the circuit 400A receives a digital one at the input element 404. In the example of the circuit 400A, the pass device Mpass 412 is an NMOS transistor with a source connected to the output of the driver circuit device 402 and a drain connected to the digital output terminal 406.

[0043] The bootstrap circuit device of the circuit 400A includes a capacitor CI 414 connected between the source of the Mpass 412 and the gate of the Mpass 412 and an NMOS transistor MN0 416, which is a switch connecting the pass device Mpass 412 to the power supply Vdd. The transistor MN0 416 performs similarly to the transistor 116 described above with respect to Figure 1The function of diode D1116 is described. The drain of MN0 416 is connected to the gate of Mpass 412, and the gate of MN0 416 is controlled by the enable signal EN 452 from comparator circuit device 450A.

[0044] The bootstrap circuitry also includes pull-down transistors MP0 460 and MN1 470, which are controlled by a pull-down signal PD 454 from the comparator circuitry 450A. Transistor MP0 460 may be a PMOS transistor, with its source connected to the power supply voltage Vdd and its drain connected to the source of MN0 416. MN1 470 is an NMOS transistor, with its drain connected to the gate of Mpass 412 and its source connected to the reference voltage Vss. In operation, when MP0 460 receives a pull-down signal (i.e., logic high) from the comparator circuitry 450A via PD 454, MP0 460 can be turned off, isolating Vdd from the gates of MN0 416 and Mpass 412. When MN1 470 receives a pull-down signal via PD 454, MN1 470 can be turned on, MN1 470 connects the gate of Mpass 412 to Vss, and ensures that Mpass 12 is turned off to isolate the driver circuit device 402 from the digital output terminal 406.

[0045] The refresh circuit device of circuit 400A can be similar to the above-mentioned... Figure 2 The refresh circuit 220 is described. The refresh circuit arrangement of circuit 400A includes a clock input element 422 connected to one of the two input terminals of AND gate 424. Input element 404 is connected to the second input terminal of AND gate 424. The output of AND gate 424 is connected to the input of auxiliary driver circuit 426. The first terminal of capacitor C2 428 is connected to the output of auxiliary driver circuit 426. The second terminal of capacitor C2 428 is connected to the drain of transistor MN2 436 and to the source and gate of transistor MN4 438. Transistor MN2 436 is controlled by an enable signal EN 452 from comparator circuit arrangement 450A and performs the above-described... Figure 2 The diode D2 236 described above performs a similar function. Transistor MN4 438 is a diode-connected transistor and performs the same function as described above. Figure 2 The described diode D3238 has a similar function. The drain of transistor MN4238 is connected to the gate of Mpass 412 and comparator circuit device 450A.

[0046] The refresh circuit arrangement further includes pull-down transistors MP1 464 and MN3 472, which are controlled by a pull-down signal PD 454 from the comparison circuit arrangement 450A, and function similarly to the pull-down transistors MP0 460 and MN1 470 described above. Transistor MP1 464 is a PMOS transistor with its source connected to the supply voltage Vdd and its drain connected to the source of MN2 466. MN3 472 is an NMOS transistor with its drain connected to the drain of MN2 466 and its source connected to the reference voltage Vss. In operation, when MP1 464 receives a pull-down signal from the comparison circuit arrangement 450A via PD 454, MP1 464 can turn off and isolate Vdd from MN2 466. When MN3 472 receives a pull-down signal via PD 454, MN3 472 can turn on, connecting the second terminal of capacitor C2 428 to Vss, thereby preventing the refresh output signal from turning on Mpass 412 via the diode connected to transistor MN4 438.

[0047] Similar to the circuits 100 and 200 described above with respect to Figure 1 and Figure 2 In operation, when the circuit 400A receives a digital zero at the input element 404, the driver circuit 402 outputs a digital zero such that the capacitor CI 414 charges to approximately Vdd. In other words, the driver circuit 402 is configured to output the reference voltage Vss to the first terminal of the capacitor CI 414, which causes the second plate of the capacitor to be coupled to the supply voltage Vdd via MN0 416 and MP0 460 to charge to approximately the size of the supply voltage (Vdd).

[0048] In the example of the circuit 400A, the comparison circuit arrangement 450A is configured to output an enable signal (i.e., a logic high) via EN 452 to turn on the transistor MN0 416 when the size of the voltage at the digital output terminal 406 is less than the size of the voltage at the gate of Mpass 412. The comparison circuit 450A is configured to output a logic low via the pull-down PD 454 when the comparison circuit 450A determines that there is no overvoltage at the digital output terminal 406. The enable signal EN 452 and the pull-down signal PD 454 can be configured to be complementary to each other. That is, when EN 452 is high, PD 454 is low, and vice versa.

[0049] The comparison circuit 450A can be implemented by any combination of hardware, firmware, or software, such as an application specific integrated circuit (ASIC), microcontroller, or any other type of processing circuit. In some examples, the comparison circuit 450A can include one or more processors, one or more analog-to-digital converters (ADCs), and similar circuitry. If implemented in software, the functions can be stored on a tangible computer readable storage medium and executed by a processor or hardware-based processing unit. The instructions can be executed by one or more processors such as one or more DSPs, general purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuitry. Accordingly, the term “processor” as used herein can refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Also, the techniques could be fully implemented in one or more circuits or logic elements.

[0050] When the circuit 400A receives a digital one at the input element 404, the driver circuit 402 outputs a digital one, which is passed through the pass device Mpass 412 to the digital output terminal 406. The digital one at the digital output terminal 406 is passed through the pass device Mpass 412 to the digital output terminal 406. Figure 4A In the example described above, the voltage across the capacitor CI 414 is approximately Vdd. DDIO The capacitor CI 414 can maintain the voltage between the first plate and the second plate of the capacitor CI 414, and thus, the voltage between the source and the gate V GS of the pass device Mpass 412 remains approximately Vdd. The V GS of Vdd magnitude can ensure that the Mpass 412 remains in the on state and allows the digital one from the driver circuit 402 to be output from the digital output terminal 406.

[0051] As described above with respect to Figure 1 and Figure 2 the refresh circuitry of the circuit 400A is configured to periodically apply a predetermined voltage to the control terminal (i.e., the gate of Mpass 412) to counteract any leakage in the bootstrap circuitry, such as at the capacitor CI 414. The digital one at the input element 404 enables the clock signal received at the clock input element 422 to be passed through the AND gate 424 to the auxiliary driver circuit 426. When the clock signal is a logic low (i.e., a digital zero), the capacitor C2 428 is charged to approximately Vdd via the capacitors MP1 464 and MN2 466. Similar to the capacitor CI 114 described above with respect to Figure 1 the auxiliary driver circuit 426 is configured to connect the reference voltage Vss to the first plate of the capacitor C2 428, which causes the second plate of the capacitor coupled to MN2 466 to charge to approximately the magnitude of the supply voltage Vdd. The voltage across C2 228 will be Vdd minus any voltage drop across the transistors MP1 463 and MN2 466.

[0052] When the clock signal is logic 1, refresh output 230 will couple voltage to the gate of Mpass412 via transistor MN4438. Transistor MN4438 has approximately Vdd+V DDIO The size of the voltage applied to the gate 434 can be determined according to the above. Figure 1 An example of a predetermined voltage magnitude applied to control terminal 134 is described. Transistors MN0 416 and MN2 466 perform the same operation as described above. Figure 1 and Figure 2 The diodes D1 116 and D2 236 are described as having similar switching functions.

[0053] Figure 4B This is a schematic diagram illustrating details of an example digital I / O protection circuit with overvoltage monitoring according to one or more techniques of this disclosure. Circuit 400B is an example of circuit 400A, and unless otherwise stated, the functions and characteristics of the components of circuit 400B are the same as those described above. Figure 4A The components of circuit 400A described herein have the same function and characteristics. Circuit 400B includes an example implementation of a comparator circuit, similar to the above description. Figure 4A The circuit described is 450A. In other examples, the arrangement and selection of components in circuits 400A and 400B can be similar to... Figure 4A and Figure 4B The arrangement and selection of components shown differ. As an example, MN0 416 and MN3 472 can be implemented using diodes, while retaining... Figure 4A and 4B The remaining arrangements are shown.

[0054] Comparator circuit 450B includes comparator 480, whose non-inverting input is connected to digital output terminal 406 via resistor R1 482 and to reference voltage Vss via Zener diode D4 456. The inverting input of comparator 480 is connected to the gate of Mpass 412. Therefore, if the overvoltage at digital output terminal 406 exceeds the threshold voltage compared to the voltage at the control terminal of the transmission device Mpass 412, comparator 480 can output a logic high. In the example of comparator circuit 450B, the threshold is set by selecting the characteristics of Zener diode D4 456 and the value of resistor R1 482.

[0055] The output of the comparator 480 is connected to the gate of a transistor MN4 488. The source of the transistor MN4 488 is connected to a reference voltage Vss, and the drain of MN4 488 is connected to Vdd via a resistor R2 484. The drain of MN4 488 is also connected to the gates of transistors MP2 486 and MN5 490. The source of MN5 490 is connected to Vss and the drain of MN5 490 is connected to the drain of MP2 486. The source of MP2 is connected to Vdd.

[0056] Figure 5 is an example digital output protection circuit that uses a charge pump and a pull-down circuit to operate a pass device. The example of the circuit 500 uses additional circuitry including a charge pump to control the operation of the pass device, rather than using the output driver described above with respect to Figures 1-4B to control the pass device.

[0057] In the example of the circuit 500, the driver 505 receives a digital input at the input element 504 and outputs a buffered digital output to the digital output terminal 506 via a pass device Mpass 515. The circuit 500 includes a low voltage driver 505 with a high voltage NMOS pass device Mpass 515 in series. The Mpass 515 prevents the propagation of high voltages that can be applied at the digital output terminal 506 to the LV driver, such as preventing a battery short. The high voltage NMOS pass device Mpass 515 is driven by a charge pump 513 to provide a high enough V GS 525, so the Mpass 515 turns on with a low enough drain-source resistance R DS-ON on. In some examples, depending on the technology used, the circuit (such as the circuit 500) can also include a pull-down circuit 510 that dynamically lowers the gate voltage of the pass device when the driver 505 propagates a logic "0". As one example, for an SPT9U MOSFET, to meet the required gate-source voltage (e.g., for a 5V output "high" level), the maximum V GS can be 2.65V. The pull-down circuit 510 is coupled to the gate of Mpass 515 and is controlled by the driver 505. Thus, in the example of the circuit 500, the charge pump 513 needs to drive enough current to operate the pull-down circuit 510. Thus, the capacitor that recharges for the charge pump 513 needs a high enough speed clock 527, which can increase cost and increase the risk of interfering with other areas of the circuit (not shown in Figure 5 may have drawbacks, as the circuit 500 can also require a large area on the IC.

[0058] The above with respect to Figures 1-4BOne advantage of the described techniques of the present disclosure is that, in terms of current consumption, the techniques can achieve improved power efficiency. In the example of circuit 100-400B, there is no need for a high-speed running charge pump to drive the gate of the pass device, and there is no static current consumption caused by the pull-down circuitry that the circuit 500 would need to limit the V GS .

[0059] Figure 6 is a flowchart illustrating example operations of a circuit of the present disclosure. Unless otherwise noted, the blocks of Figure 4B will be described in accordance with Figure 6 .

[0060] In response to receiving a digital zero at the input element 404 connected to the input of the driver circuit 402, the capacitor CI 414 is charged via the transistor MNO 416 such that the magnitude of the voltage across CI 414 is approximately equal to the supply voltage Vdd, minus the voltage drop across the MP0 460 and MN0 416 (90). CI 414 is also connected between the gate and the source of the NMOS pass device Mpass 412.

[0061] In response to receiving a digital one at the input element 404, the driver circuit 402 can apply a digital supply voltage V DDIO to the source of Mpass 412. Since CI 414 holds Vdd across its two terminals, the gate-source voltage of Mpass 412 is approximately the magnitude of the voltage across the capacitor (92). As described above with respect to Figure 4B , the voltage Vdd across CI 414 is configured to ensure that the transistor Mpass 412 remains turned on to send the digital one to the digital output terminal 406.

[0062] Also, receiving a digital one at the input element 404 enables the clock signal received at the clock input element 422 to pass through the AND gate 424. The clock signal enables the refresh circuit (e.g., the refresh circuit 220 described above with respect to Figure 2 to periodically apply a voltage to the control terminal of the pass device Mpass 412 (94).

[0063] The comparison circuit 450B is configured to compare the voltage at the gate of the pass device Mpass 412 to the voltage at the digital output terminal 406 (96). Based on the comparison, the comparator 180 controls the operation of the pull-down transistors (e.g., MP0 460 and MN1 470) and the operation of the switches MN0 416 and MN3 472.

[0064] To protect the driver 402 from damage caused by an overvoltage, in response to a voltage at the digital output terminal 406 exceeding a voltage at the gate of the Mpass 412 by an overvoltage threshold, the comparison circuit 450B is configured to control the switch MN0 416 to turn off (i.e., disable) the Mpass 412, thereby isolating the digital output terminal from the driver circuit (98).

[0065] The techniques of this disclosure can be implemented in a variety of devices or apparatuses including an integrated circuit (IC) or a collection of ICs such as a set of chips. Various components, modules, or units described in the present disclosure can be implemented as hardware, software, or a combination thereof. Various components, modules, or units described in the present disclosure can be implemented as one or more software programs or applications which run on one or more processors or hardware units.

[0066] The techniques of this disclosure can also be described in the following examples.

[0067] Example 1. A circuit comprising: a driver circuit, the driver circuit comprising an input element and an output element, wherein the output element is electrically coupled to a digital output terminal via a pass device. The pass device comprises a first terminal, a second terminal, and a control terminal, the pass device is configured to protect the driver circuit from an overvoltage applied to the digital output terminal, the output element of the driver circuit is electrically connected at the first terminal of the pass device and at the control terminal of the pass device via a capacitor, the control terminal of the pass device is coupled to a supply voltage through a switch, and the second terminal of the pass device is coupled to the digital output terminal.

[0068] Example 2. The circuit of example 1, wherein the pass device comprises a N-channel metal-oxide-semiconductor (NMOS) transistor, and wherein the first terminal is a source of the NMOS transistor, the second terminal is a drain, and the control terminal is a gate.

[0069] Example 3. The circuit of any combination of examples 1-2, further comprising a refresh circuit, the refresh circuit configured to apply a predetermined voltage amplitude at the control terminal of the pass device, the refresh circuit comprising: an enable input element electrically coupled to the input element of the driver circuit, a refresh output element coupled to the control terminal of the pass device, and a clock input element.

[0070] Example 4. The circuit of any combination of examples 1-3, wherein the capacitor is a first capacitor, the refresh circuit further comprising: a second capacitor; and an auxiliary driver circuit, the auxiliary driver circuit configured to charge the second capacitor in response to a digital one received at the enable input element.

[0071] Example 5. The circuit of any combination of examples 1-4, wherein the switch is a first switch, the refresh circuit further comprising a second switch, the second switch arranged such that the second switch controls the refresh output element.

[0072] Example 6. The circuit of any combination of examples 1-5, wherein in response to receiving a digital zero at the input element: the driver circuit is configured to output the reference voltage to the first plate of the capacitor, and the second plate of the capacitor is configured to charge to approximately the size of the supply voltage.

[0073] Example 7. The circuit of any combination of examples 1-6, wherein the pass device is configured to protect the driver circuit from an overvoltage greater than the reference voltage by at least forty volts applied to the digital output terminal.

[0074] Example 8. The circuit of any combination of examples 1-7, wherein in response to receiving a digital one at the input element: the driver circuit is configured to output a first voltage, wherein: the size of the first voltage is approximately equal to the digital supply voltage, and the size of the voltage between the first terminal of the pass device and the control terminal is approximately equal to the supply voltage.

[0075] Example 9. The circuit of any combination of examples 1-8, wherein the overvoltage is a voltage at the digital output terminal that exceeds the size of a threshold voltage compared to the size of the voltage at the control terminal of the pass device.

[0076] Example 10. The circuit of any combination of examples 1-9, further comprising a comparison circuit arrangement, wherein the comparison circuit arrangement is configured to: determine whether the size of the voltage at the digital output terminal is an overvoltage. In response to determining that the size of the voltage at the digital output terminal is an overvoltage, control the switch to disable the pass device, thereby preventing the overvoltage from reaching the output element of the driver circuit.

[0077] Example 11. The circuit of any combination of examples 1-10, further comprising a refresh circuit, wherein in response to determining that the size of the voltage at the digital output terminal is an overvoltage, the comparison circuit arrangement is further configured to disable the refresh circuit.

[0078] Example 12. The circuit of any combination of examples 1-11, wherein the comparison circuit arrangement comprises one or more processors.

[0079] Example 13. The circuit of any combination of examples 1-12, wherein the comparison circuit comprises a comparator having a first input element and a second input element and an output element, wherein the first input element of the comparator is electrically coupled to the digital output terminal, the second input element of the comparator is electrically coupled to the control terminal of the pass device, and the output element of the comparator causes the switch to pull down the control terminal to isolate the digital output terminal from the output element of the driver circuit.

[0080] Example 14. A method comprising: in response to receiving a digital zero at an input element of a driver circuit, charging a capacitor such that a magnitude of a voltage across the capacitor is approximately a first supply voltage, wherein the capacitor is coupled to the first supply voltage through a switch, and wherein the capacitor is connected between a gate and a source of an N-channel metal-oxide-semiconductor (NMOS) pass device. In response to receiving a digital one at the input element of the driver circuit, applying a second voltage to the source of the NMOS pass device through the driver circuit such that a gate-source voltage of the NMOS pass device is approximately the magnitude of the voltage across the capacitor.

[0081] Example 15. The method of example 14, further comprising, in response to receiving the digital one at the input element of the driver circuit, enabling a refresh circuit.

[0082] Example 16. The method of any combination of examples 14-15, wherein the refresh circuit is configured to maintain a predetermined magnitude of voltage at the gate of the pass device, and wherein the refresh circuit comprises: an enable input electrically coupled to the input element of the driver circuit, and a refresh output element coupled to the gate of the pass device.

[0083] Example 17. The method of any combination of examples 14-16, wherein the refresh circuit is configured to periodically maintain the predetermined magnitude of voltage at the gate of the pass device based on a clock signal input to the refresh circuit.

[0084] Example 18. The method of any combination of examples 14-17, wherein the pass device is configured to isolate the driver circuit from a digital output element, the method further comprising: comparing the voltage at the gate of the pass device to a voltage at the digital output element. In response to the voltage at the digital output element exceeding the voltage at the gate of the pass device by an overvoltage threshold, controlling the switch such that the NMOS pass device is disabled, thereby isolating the digital output terminal from the driver circuit.

[0085] Example 19. The method of any combination of examples 14-18, further comprising, in response to the voltage at the digital output element exceeding the voltage at the gate of the pass device by an overvoltage threshold, controlling a second switch to disable a refresh circuit, wherein the refresh circuit is configured to maintain a pre-determined size of voltage at the gate of the pass device.

[0086] Various examples of the present disclosure have been described. These and other examples are within the scope of the claims.

Claims

1. A circuit comprising: A driver circuit includes an input element and an output element, wherein the output element is electrically coupled to a digital output terminal via a transmission device, wherein: The transmission device includes a first terminal, a second terminal, and a control terminal. The transmission device is configured to protect the driver circuit from overvoltages applied to the digital output terminal. The output element of the driver circuit is electrically connected to the first terminal of the transmission device and the first terminal of the capacitor. A second terminal of the capacitor, different from the first terminal, is connected to the control terminal of the transmission device. The control terminal of the transmission device and the second terminal of the capacitor are coupled to the power supply voltage via a switch, and The second terminal of the transmission device is coupled to the digital output terminal.

2. The circuit of claim 1, wherein the transmission device comprises an N-channel metal-oxide-semiconductor (NMOS) transistor, and wherein the first terminal is the source of the NMOS transistor, the second terminal is the drain, and the control terminal is the gate.

3. The circuit of claim 1, further comprising a refresh circuit configured to apply a predetermined voltage amplitude at the control terminal of the transmission device, the refresh circuit comprising: An enable input element electrically coupled to the input element of the driver circuit; A refresh output element coupled to the control terminal of the transmission device; as well as Clock input element.

4. The circuit according to claim 3, wherein the capacitor is a first capacitor, and the refresh circuit further comprises: Second capacitor; as well as The auxiliary driver circuit is configured to charge the second capacitor in response to receiving a digital signal at the enable input element.

5. The circuit of claim 4, wherein the switch is a first switch, and the refresh circuit further includes a second switch arranged such that the second switch controls the refresh output element.

6. The circuit of claim 1, wherein in response to receiving a digital zero at the input element: The driver circuit is configured to output a reference voltage to the first plate of the capacitor; and The second plate of the capacitor is configured to be charged to the magnitude of the power supply voltage.

7. The circuit of claim 6, wherein the transmission device is configured to protect the driver circuit from an overvoltage greater than the reference voltage of at least forty volts applied to the digital output terminal.

8. The circuit of claim 1, wherein in response to receiving a digital number at the input element: The driver circuit is configured to output a first voltage, wherein: The magnitude of the first voltage is equal to the digital power supply voltage, and The voltage between the first terminal and the control terminal of the transmission device is equal to the power supply voltage.

9. The circuit of claim 1, wherein the magnitude of the overvoltage is the magnitude of the voltage exceeding a threshold voltage at the digital output terminal, compared to the magnitude of the voltage at the control terminal of the transmission device.

10. The circuit of claim 9, further comprising a comparison circuit device, wherein the comparison circuit device is configured to: Determine whether the magnitude of the voltage at the digital output terminal is the overvoltage; In response to determining that the magnitude of the voltage at the digital output terminal is an overvoltage, the switch is controlled to disable the transmission device, thereby preventing the overvoltage from reaching the output element of the driver circuit.

11. The circuit of claim 10, further comprising a refresh circuit, wherein in response to determining that the magnitude of the voltage at the digital output terminal is the overvoltage, the comparator circuit means is further configured to disable the refresh circuit means.

12. The circuit of claim 10, wherein the comparison circuit means comprises one or more processors.

13. The circuit of claim 10, wherein the comparison circuit means comprises a comparator having a first input element, a second input element, and an output element, wherein: The first input element of the comparator is electrically coupled to the digital output terminal. The second input element of the comparator is electrically coupled to the control terminal of the transmission device, and The output element of the comparator causes the switch to pull down the control terminal to isolate the digital output terminal from the output element of the driver circuit.

14. The circuit according to claim 1, The switch mentioned is a first switch, and The control terminal of the transmission device and the second terminal of the capacitor are coupled to the power supply voltage via a second switch connected in series with the first switch.

15. A method comprising: In response to receiving a digital zero at the input element of the driver circuit, the capacitor is charged such that the voltage across the capacitor is equal to the first supply voltage. The capacitor is coupled to the first power supply voltage via a switch, and The capacitor is connected between the gate and source of the N-channel metal-oxide-semiconductor (NMOS) transfer device. The output element of the driver circuit is directly connected to the control terminal of the transmission device via the capacitor; In response to receiving a digital '1' at the input element of the driver circuit, a second voltage is applied to the source of the NMOS transfer device via the driver circuit, such that the gate-source voltage of the NMOS transfer device is equal to the magnitude of the voltage across the capacitor.

16. The method of claim 15, further comprising enabling a refresh circuit in response to receiving the digital number 1 at the input element of the driver circuit.

17. The method of claim 16, wherein the refresh circuit is configured to maintain a predetermined voltage at the gate of the transfer device, and wherein the refresh circuit comprises: Enable input, electrically coupled to the input element of the driver circuit, and The refresh output element is coupled to the gate of the transmission device.

18. The method of claim 17, wherein the refresh circuit is configured to periodically maintain a predetermined voltage at the gate of the transmission device based on a clock signal input to the refresh circuit.

19. The method of claim 15, wherein the transmission device is configured to isolate the driver circuitry from the digital output element, the method further comprising: The voltage at the gate of the transmission device is compared with the voltage at the digital output element; In response to the voltage at the digital output element exceeding an overvoltage threshold at the gate of the transfer device, the switch is controlled to disable the NMOS transfer device, thereby isolating the digital output element from the driver circuit.

20. The method of claim 19, further comprising controlling a second switch to disable a refresh circuit in response to the voltage at the digital output element exceeding the voltage at the gate of the transfer device to reach the overvoltage threshold, wherein the refresh circuit is configured to maintain a predetermined voltage at the gate of the transfer device.

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