Method for controlling MMC

Abstract

The present disclosure relates to a method for controlling an MMC (7) in an inverter arrangement (4) between a DC network (2) and a three-phase AC network (5). The method includes detecting an internal AC fault in the inverter arrangement. The method further includes controlling the MMC by blocking each of the cells in the negative arm while keeping the positive arm in operation and controlling the current of each phase to zero.

Description

Technical Field

[0001] The present disclosure relates to a method for controlling a direct current (DC) to alternating current (AC) modular multilevel converter (MMC). Background Art

[0002] MMC is a power converter of the voltage source converter (VSC) type, also known as a voltage source inverter, which includes cells (also known as modules or sub-modules) connected in series to form converter branches (also known as arms). These branches can be configured in several ways to obtain a dedicated converter topology. According to the output voltage requirements that these branches only provide positive voltages or also provide negative voltages, the cells in the branches can be implemented by only half-bridge (HB, also known as unipolar or unidirectional) cells or full-bridge (FB, also known as bipolar, bidirectional or H-bridge) cells, or a combination of HB and FB cells, respectively. The MMC inverter structure of DC to three-phase AC in a double star configuration can be used for the interconnection of a three-phase power grid (e.g., 50 or 60 Hz) with a DC power grid (e.g., a high-voltage DC (HVDC) power grid).

[0003] HVDC connected MMC inverters are prone to high cell overvoltages during internal AC faults, which are faults between the MMC (particularly its cells / valves) and the auxiliary side of the transformer interfaced to the AC grid (also called the valve side, i.e. the side facing the MMC and away from the AC grid).

[0004] WO 2017 / 080597 discloses an MMC for handling AC side faults. The MMC includes a control unit configured to enter a first protection control mode when an operational disturbance of the converter is detected, the first protection control mode including controlling all bipolar voltage contribution units to operate as unipolar voltage contribution units, and if the operational disturbance is identified as a fault on the phase of the connected AC link, then the units of the phase leg connected to the phase are blocked for the remainder of the first protection control mode, and the units of the phase leg connected to the healthy phase of the AC link are controlled to handle the effects of the fault. This solution is mainly applicable to MMC arms with only FB units, while the case of arms with mixed FB and HB units may be more challenging to handle. Summary of the invention

[0005] The object of the present invention is to provide a new method for detecting and handling internal AC faults in an inverter arrangement comprising at least one MMC, in particular when the inverter arrangement comprises a plurality of MMCs connected in series. Some embodiments of the present invention are particularly useful for MMCs having arms with a mixture of FB and HB cells. Moreover, some embodiments of the present invention are particularly useful for MMCs connected in series with at least one other MMC.

[0006] According to one aspect of the present invention, there is provided a method of controlling an inverter arrangement between a DC network and a three-phase AC network. The inverter arrangement comprises a plurality of converter arrangements connected in series, each converter arrangement comprising a controller and an MMC having a topology with one positive arm and one negative arm per phase. Each of the arms comprises a plurality of converter units connected in series, each of these units comprising an energy storage device and a plurality of valves. At least 50% of the plurality of converter units connected in series in each arm are full-bridge units. The method comprises, in each of the plurality of converter arrangements, by the controller in the converter arrangement: sensing at least one characteristic of the MMC; based on the sensed characteristic, detecting that an internal AC fault has occurred in one of the plurality of converter arrangements; and in response to the detection of the fault, controlling the MMC in the converter arrangement by blocking the negative arm of the MMC while keeping the positive arm of the MMC unblocked and controlling the current amplitude of each phase to approach zero.

[0007] According to another aspect of the present invention, there is provided a computer program product comprising computer-executable components for causing a controller to perform an embodiment of the method of the present disclosure when the computer-executable components are run on a processing circuit comprised in the controller.

[0008] According to another aspect of the present invention, there is provided an inverter arrangement configured for between a DC network and a three-phase AC network. The inverter arrangement comprises a plurality of converter arrangements connected in series, each converter arrangement comprising a controller and an MMC having a topology with one positive arm and one negative arm per phase. Each of the arms comprises a plurality of converter units connected in series, each of these units comprising an energy storage device and a plurality of valves, and at least 50% of the plurality of converter units connected in series in each arm are full-bridge units. In each of the plurality of converter arrangements connected in series, the controller comprises a processing circuit and a data storage device storing instructions executable by the processing circuit, whereby the controller is operable to: sense at least one characteristic of the MMC in the converter arrangement; based on the sensed characteristic, detect that an internal AC fault has occurred in one of the plurality of converter arrangements; and in response to the detection of the fault, control the MMC in the converter arrangement by blocking the negative arm of the MMC while keeping the positive arm of the MMC unblocked and controlling the current amplitude of each phase to approach zero.

[0009] By the method of detecting internal AC faults outlined herein, an MMC can itself detect internal AC faults in another MMC connected in series therewith, without the need for time-consuming inter-MMC communication, which may delay the effective handling of faults. According to the present disclosure, regardless of whether the internal AC fault is at its own MMC or at another serially connected MMC, the controller can control the MMC in the same manner by blocking all negative arm units while keeping the positive arm unblocked and controlling the current of each phase to zero.

[0010] It should be noted that any feature of any aspect can be applicable to any other aspect where appropriate. Similarly, any advantage of any aspect can be applied to any one of the other aspects. From the following detailed disclosure, from the appended dependent claims, and from the drawings, other objects, features, and advantages of the embodiments included will become apparent.

[0011] In general, all terms used in the claims should be interpreted according to their ordinary meaning in the technical field, unless otherwise clearly defined herein. All references to "a / an / element, device, component, apparatus, step, etc." should be interpreted openly as referring to at least one instance of the element, device, component, apparatus, step, etc., unless otherwise clearly stated. The steps of any method disclosed herein need not be performed in the exact order disclosed, unless clearly stated. The use of "first," "second," etc. for different features / components of the present disclosure is only intended to distinguish the features / components from other similar features / components, and not to assign any order or hierarchy to these features / components. Description of the Drawings

[0012] Embodiments will be described by way of example with reference to the drawings, in which:

[0013] Figure 1 is a schematic circuit diagram of an embodiment of an HVDC system according to the present invention.

[0014] Figure 2 is a schematic circuit diagram of an embodiment of a DC-AC converter arrangement according to the present invention.

[0015] Figure 3 is a schematic circuit diagram of an embodiment of a converter arm of an MMC including both HB and FB converter units according to the present invention.

[0016] Figure 4 is a schematic functional block diagram showing an embodiment of a control method for internal AC fault detection without communication according to the present invention.

[0017] Figure 5Schematic diagram of an embodiment of a sensing arrangement in a converter arrangement according to the present invention.

[0018] Figure 6 Schematic block diagram of an embodiment of a controller of an inverter arrangement according to the present invention.

[0019] Figure 7 Schematic flowchart of an embodiment of a control method for internal AC fault handling according to the present invention.

[0020] Figure 8 More detailed schematic flowchart of an embodiment of the method steps for detecting an internal AC fault according to the present invention. Detailed Description of the Invention

[0021] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which some embodiments are shown. However, many different forms of other embodiments are possible within the scope of the present disclosure. Rather, the following embodiments are provided by way of example so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the description, the same numerals refer to the same elements.

[0022] Figure 1 System 1, particularly an HVDC system, is shown, in which a DC network 2 is connected to an AC network 5 via an inverter arrangement 4. The inverter arrangement 4 includes at least one VSC in the form of an MMC 7, for example, as shown, at least two MMCs 7 connected in series. On the other hand, on the rectifier side, the rectifier arrangement 3 may include at least one line commutated converter (LCC), for example, as shown, at least two LCCs connected in series. However, the present disclosure focuses on the inverter arrangement 4.

[0023] The inverter arrangement 4 includes at least one converter arrangement 6 and a controller 10 (see Figure 6)。Each converter arrangement 6 includes an MMC and a converter transformer 8 that interfaces the MMC with the AC network 5. Given the rated voltage of each MMC, it may be convenient to connect the MMCs 7 in series and thus connect the converter arrangements 6 in series, especially for high-voltage applications such as HVDC. For example, as illustrated in the figure, if the nominal voltage of the HVDC network 2 is 800 kV and the available MMCs have a rated voltage of 400 kV, then two serially connected MMCs 7 are required in the inverter arrangement 4. In this figure, these MMCs 7 include an upper MMC 7a in the upper converter arrangement 6a, which also includes an upper transformer 8a, and the upper MMC 7a has a positive terminal p at 800 kV (the voltage of the HVDC network 2) and a negative terminal n at 400 kV. The serially connected MMCs 7 also include a lower MMC 7b in the lower converter arrangement 6b, which also includes a lower transformer 8b, and the lower MMC 7b has a positive terminal p at 400 kV (the same voltage as the negative terminal of the upper MMC 7a) and a negative terminal n at 0 kV (connected to ground). Each MMC has two DC terminals: a positive DC terminal p that connects the positive arms 21p together; and a negative DC terminal n that connects the negative arms 21n together. Generally, positive current flows into the MMC at the positive terminal and out of the MMC at the negative terminal.

[0024] As discussed herein, the first MMC can (in the Figure 1 system) be either the upper MMC or the lower MMC, and the second MMC is the other. It should be noted that in other embodiments, the inverter arrangement 4 can include more than two converter arrangements 6, where the respective MMCs 7 are in series connection.

[0025] Figure 2 A converter arrangement 6 is shown that includes an MMC and a transformer 8, as discussed above with reference to Figure 1 . Since the AC network 5 is a three-phase AC network, the MMC 7 includes three phases 20, here denoted as 20a, 20b, and 20c respectively, with each phase connected to a corresponding one of the three phases of the AC network. Each phase 20 includes two arms 21, namely a negative arm 21n connected to the negative terminal n and a positive arm 21p connected to the positive terminal p. Thus, the MMC 7 has a modular multilevel topology, where each phase 20 has one positive arm 21p and one negative arm 21n, and each of the arms 21 includes a plurality of serially connected converter units. In some embodiments of the present invention, the MMC has a double-star topology (also known as double-Y or double-Y topology), as Figure 2 shown.

[0026] In this figure, the valves V of the different arms 21 of the MMC 7 are collectively referred to as: Vap for the positive arm 21p of phase 20a, Van for the negative arm 21n of phase 20a, Vbp for the positive arm 21p of phase 20b, Vbn for the negative arm 21n of phase 20b, Vcp for the positive arm 21p of phase 20c, and Vcn for the negative arm 21n of phase 20c.

[0027] Internal AC fault 22 is schematically shown in Figure 2 As discussed herein, an internal AC fault is a fault that occurs in the converter arrangement 6 between the valve side of the transformer 8 and the MMC 7 (which is generally defined as the valve of the MMC).

[0028] Figure 3 An arm 21 of the MMC 7 is shown, for example, Figure 2 either the positive or negative arm in Figure 3 The arm includes a plurality of converter units 31 connected in series, and (optionally) at least one reactor 34 connected in series. Each of the units includes an energy storage device 33 and a plurality of valves 35. In the example of

[0029] the arm includes both full-bridge (FB) units 31F and half-bridge (HB) units 31H, in a 1:1 ratio of 50% each here. Generally, at least 50% of FB units 31F are required, and thus at most 50% of HB units. Thus, according to an embodiment of the present disclosure, each arm 21 has FB units between 50% and 100%. However, as discussed further below, embodiments of the present invention may be particularly useful when each arm 21 includes at least one HB unit, such as up to 50% of HB units.

[0029] Each valve 35 includes a semiconductor switch S, which is conventionally denoted as S1, S2, S3, and S4 in the FB unit 31F here, and as S1 and S2 in the HB unit 31H. In the figure, each of the semiconductor switches S includes a bi-mode insulated gate transistor (BIGT), which may be suitable in some embodiments. However, in some other embodiments, another type of semiconductor switch may be suitable, for example, an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a forced-commutated thyristor, or any other forced-commutated switch. Each valve 35 generally also includes a reverse-parallel unidirectional semiconductor device 36, for example, including a diode, such as a freewheeling diode. To avoid clutter in the drawings, the reference numerals for the valves 35 and the reverse-parallel unidirectional semiconductor devices 36 are given only in the top unit of the drawing.

[0030] The energy storage device 33 may include a capacitor arrangement including at least one capacitor. The energy storage device 33 and thus its cells 31 can be charged and discharged during operation when its cells 31 are inserted in its arms 21 rather than being wound around in its arms 21. The cells 31 can only be charged or discharged when inserted. Moreover, the charging or discharging of the cells depends on the current direction. Thus, due to the different structures of the FB cells 31F compared to the HB cells 31H, the charging and discharging of the cells may be different for the FB and HB cells in the same arm 21. For example, when the negative arm 21n is blocked, for the current flowing from the ground through the negative arm, the HB cells will be bypassed (and thus not charged) via the anti-parallel unidirectional semiconductor devices 36, while the FB cells will be inserted (and thus charged and causing an increased voltage) via the anti-parallel unidirectional semiconductor devices 36. Thus, a reverse voltage can be generated by the FB cells in the negative arm, which can limit the cell charging current (also referred to herein as the fault current) caused by the internal AC fault 22 in the inverter arrangement 4. Thus, if all the cells in each arm are FB cells, the fault current is more effectively limited. However, embodiments of the present invention are useful with up to 50% HB cells in each arm.

[0031] Another factor to consider is the time period from the occurrence of the fault 22 to the detection of the fault, i.e., the detection delay. The smaller the detection delay, the more effective the limitation of the fault current. According to the above discussion, it may be particularly important to effectively limit the fault current when HB cells are in the arm. Thus, according to the present invention, a communicationless detection of an internal AC fault in a series-connected converter arrangement 6 is proposed, i.e., an internal AC fault in a second converter arrangement including a second MMC is typically detected by a converter arrangement sub-controller in a controller 10 in a first converter arrangement including a first MMC without the need to signal from the second converter arrangement to the first converter arrangement to inform the first converter arrangement about the fault in the second converter arrangement.

[0032] Figure 4 An example embodiment of a process for communicationless detection of an internal AC fault in a second converter arrangement 6b or 6a in a first converter arrangement 6a or 6b, for example, performed by a converter arrangement controller 10 of the first converter arrangement, is shown.

[0033] For Figure 4 the process of the embodiment is the input (expressed herein as per unit, i.e., pu):

[0034] - The DC current Idc, which is followed over time, for example sampled continuously or periodically, such as as measured at the positive terminal p and / or negative terminal n of the MMC. The direction of the DC current measurement at the positive terminal p is positive in the direction of entry into the MMC 7 (the current towards the valves of the MMC is positive), while the direction of the DC current measurement at the negative terminal n is positive in the direction of exit from the MMC 7 (the current in the direction away from the valves of the MMC is positive). The sum of the currents flowing in the positive valve arms 21p (Vap, Vbp, and Vcp) is equal to the DC current Idcp, and similarly, the sum of the currents flowing in the negative valve arms 21n (Van, Vbn, and Vcn) is equal to the DC current Idcn. Thus, the sum of the arm currents in 21p / 21n can also be used instead of the DC current.

[0035] o Based on the DC current Idc, the pre-fault DC current (Idcpreflt) measured, for example, at the positive terminal p and / or negative terminal n of the MMC before the fault 22 can be compared with the DC current during the fault 22.

[0036] - The DC voltage (Udc) of the MMC, which is followed over time, for example sampled continuously or periodically.

[0037] o Sensing the DC voltage allows determination of the voltage difference ΔUdc over a predetermined number of control cycles. In an embodiment, the number of control cycles can be 3, i.e., ΔUdc is calculated as the difference between the measured Udc of the current control cycle minus the measured Udc of the control cycle three cycles ago. Generally, based on experimental results, the number of control cycles is an integer in the range of 1 to 10, or 2 to 5, preferably 3. A typical example of the control cycle duration is in the range from 100 to 200 μs.

[0038] - Optionally, in some embodiments, the DC rated voltage of the MMC can be used as the predetermined threshold voltage value Um1.

[0039] - Based on the sensed voltage and current Udc and Idc, the pre-fault power of the first MMC can optionally be obtained,

[0040] which can be used to determine whether the converter was in inverter operation before the fault (during steady-state operation).

[0041] This can be optional, for example because it may already be known whether the MMC is operating as an inverter or a rectifier.

[0042] Then, the process steps for non-communicative fault detection in the first MMC 7 connected in series with other MMC(s) can be:

[0043] a) During fault 22, if the DC current Idc in the converter changes its direction from positive to negative with a magnitude greater than a predetermined second threshold current value (e.g., in the range of -1.2 to -2.0 pu, e.g., -1.5 pu) (where the negative sign indicates that the current has changed its direction), then an internal AC fault has occurred in the upper converter arrangement 6a (the first MMC is part of the lower converter arrangement 6b relative to the upper converter arrangement where the fault has occurred). Note that both the DC currents at the poles and the neutral point of the lower converter can typically change at the same level and in the same direction. Also note that the converter arrangement controller 10 may not know in advance whether its converter arrangement with the first MMC is connected as the upper converter arrangement or the lower converter arrangement in the inverter arrangement 4.

[0044] b) During fault 22, if the DC current Idc increases in the same direction with a magnitude greater than a predetermined first threshold current Im1 (e.g., in the range of 0.2 to 1.0 pu, e.g., 0.5 pu) (which means there is no negative sign as the current has not changed direction), then an internal AC fault has occurred in the lower converter arrangement 6b (the first MMC is part of the upper converter arrangement 6a relative to the lower converter arrangement 6b where the fault has occurred). Note that both the DC currents at the poles and the neutral point of the upper converter can typically increase at the same level and in the same direction. Again, note that the converter arrangement controller 10 may not know in advance whether its converter arrangement with the first MMC is connected as the upper converter arrangement or the lower converter arrangement in the inverter arrangement 4, which is why both steps a) and b) can be performed for the first MMC, and Figure 4 the "OR" function shown in indicates that an internal AC fault may have occurred if any of the situations discussed in a) and b) occurs.

[0045] c) Optionally, during fault 22, for example, the DC voltage difference (ΔUdc) within, say, three control cycles can meet the requirement of being above a predetermined threshold voltage value Um1 and / or below the negative value -Um1 of the said predetermined threshold voltage value. The predetermined threshold voltage value Um1 can be in the range of, for example, 0.5 to 1.0 pu, e.g., corresponding to the rated voltage of the MMC. In some embodiments, during a predefined time window of, for example, a few milliseconds (such as five milliseconds or three milliseconds or a quarter of the fundamental frequency period of the AC network 5), the difference in the sensed DC voltage difference (ΔUdc) is above the predetermined threshold voltage value Um1 and below the negative value of the said predetermined threshold voltage value Um1. This condition in step c) together with the conditions in steps a) and b) mentioned above can distinguish an internal AC fault from other types of faults (such as DC faults).

[0046] An OFF-delay can be applied when criterion a) or b), or criterion c) has occurred, which means that when the signal goes high and then low again, it remains high for a set time specified by the OFF-delay time. Voltage and current transients due to fault 22 may occur at slightly different times in the MMC. After determining that either of conditions a) or b) is met or condition c) is met, the OFF-delay can be used to see if the other condition [c) or a) / b)] is also met. Typical examples of the OFF-delay duration can be in the range from 10 to 20 ms. Figure 4 The output in Figure 4 refers to the output from the communication-less fault detection algorithm.

[0047] Note that the communication-less fault detection method for series converters is faster than using direct communication, which always includes some communication delay. The reason is that the communication-less method detects fault 22 in the initial stage of the fault and does not wait for the faulty second converter arrangement to detect the fault first and then communicate the fault to the first converter arrangement.

[0048] If the internal AC fault 22 occurs alternatively in the first converter arrangement, the converter arrangement sub-controller of the controller 10 directly detects the fault by conventional means, such as using differential protection.

[0049] Regardless of whether fault 22 is detected directly in the first converter arrangement by the first converter arrangement or through communication-less detection in the second converter arrangement, the same processing steps for controlling the first MMC are taken, namely:

[0050] - The positive arm 21p of the first MMC should remain in operation, i.e., remain unblocked, so as to control the phase current as it converges towards zero, for example, to zero or close to zero, by controlling the positive arm, such as controlling the phase current until the amplitude of the phase current approaches zero.

[0051] - The negative arm 21n of the first MMC should be blocked, thereby causing the FB unit 31F in the arm 21n to establish a reverse voltage on the negative arm.

[0052] The result of this control method is that the reverse voltage generated by the FB unit on the negative arm is sufficient to limit the cell charging current due to the internal AC fault 22.

[0053] Figure 5Shows the sensing arrangement 51 in the converter arrangement 6 at each terminal of the MMC 7 in the converter arrangement 6, at which terminals the positive current (the current flowing in the positive direction from the DC grid 2 towards the ground) flows into and out of the valve arrangement of the MMC respectively. As discussed herein, the sensing arrangement can be used to sense the DC current Idc and the DC voltage Udc. The sensing arrangement (51) includes a current sensor (52) and a voltage sensor (53). The current sensor is arranged to locally sense the DC current within the converter arrangement 6, for example without the need for a separate communication channel. Similarly, the voltage sensor is arranged to locally sense the DC voltage within the converter arrangement. The converter arrangement further includes a controller (54), which receives the sensed DC current and DC voltage from the current sensor and the voltage sensor respectively. The controller 54 can be part of or a sub - controller of the controller 10 of the converter arrangement 6, as discussed herein.

[0054] Figure 6 Schematically shows an embodiment of the controller 10 of the inverter arrangement 4 of the present disclosure. The controller can be, for example, centralized or distributed, and the controller can include, for example, sub - controllers for each of the MMCs 7 in each of the converter arrangements 6, in the inverter arrangement 4, and / or in each of the cells 31 and / or valves 35 of the MMC. Typically, each converter arrangement 6 includes a controller 10, which may or may not communicate with other controllers in the inverter arrangement. The controller can be arranged to control the (one or more) MMCs of the inverter arrangement 4 by using a reference, and based on the reference to control the on - and off - states of the valve switches S of the (one or more) MMCs. The controller 10 includes a processing circuit 11, such as a central processing unit (CPU). The processing circuit 11 can include one or more processing units in the form of (one or more) microprocessors. However, other suitable devices with computing capabilities can be included in the processing circuit 301, for example, application - specific integrated circuits (ASICs), field - programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs). The processing circuit 11 is configured to run one or more computer programs or software (SW) 13 stored in a data storage device 12 of one or more storage units (such as a memory). The storage unit is considered a computer - readable device as discussed herein, and can be, for example, in the form of a random - access memory (RAM), flash memory, or other solid - state memory or hard disk, or a combination thereof. The processing circuit 11 can also be configured to store data in the storage device 12 as needed.

[0055] Figure 7Some embodiments of the method of the present disclosure are shown. The method includes sensing characteristics of M1 MMC, such as the DC current Idc and DC voltage Udc of the MMC. The method further includes detecting that an internal AC fault 22 has occurred in one of the converter arrangements of M2 based on the sensed characteristics of M1. For example, the detecting of M2 includes: in some embodiments, detecting that an internal AC fault has occurred in its own converter arrangement, or in some other embodiments, detecting that an internal AC fault has occurred in another converter arrangement of the plurality of converter arrangements.

[0056] As discussed herein, the detecting of M2 can be performed by a communicationless detection process, especially when detecting the fault 22 in a series-connected converter arrangement 6 rather than in the converter arrangement where the detecting of M2 is being performed. Refer to Figure 8 , then the communicationless detection of M2 includes: determining the DC current Idcpreflt before the fault 22, for example, at the positive terminal p and / or negative terminal n of the MMC. Further, the detecting of M2 can include: determining that the difference between the DC current Idc sensed by M11 and the DC current Idcpreflt before the fault is above a predetermined first threshold current value Im1 or below a predetermined second threshold current value Im2. In some embodiments, the predetermined first threshold current value Im1 is in the range from 0.2 to 1.0 pu. In some embodiments, the predetermined second threshold current value Im2 is in the range from -1.2 to -2.0 pu. Further, the detecting of M2 can include: determining that the absolute value of the difference ΔUdc of the DC voltage sensed by M12 on M1 over a plurality of control cycles during the fault 22 is above a predetermined threshold voltage value Um1. In some embodiments, the predetermined threshold voltage value Um1 is in the range from 0.5 to 1.0 pu. In some embodiments, during a predefined time window, the difference ΔUdc of the DC voltage sensed by M1 is above the predetermined threshold voltage value Um1 and below the negative value -Um1 of the predetermined threshold voltage value.

[0057] However, in some embodiments, where the detecting of M2 includes detecting that an internal AC fault has occurred in its own converter arrangement, the detecting of M2 includes using differential protection instead of the so-called communicationless detection described herein and referred to Figure 8 described. Then, in some embodiments, the method includes signaling information about the detected internal AC fault of M2 to the corresponding controller(s) 10 of the other converter arrangements of the inverter arrangement.

[0058] The detection M1 further includes determining that M11, for example, at the positive terminal p and / or the negative terminal n of the MMC, during the fault 22, the DC current Idc changes its direction by at least 1.5 pu compared to the pre-fault DC current (e.g., according to Idc - Idcpreflt < -1.5 pu), or increases by at least 0.5 pu compared to the pre-fault DC current (e.g., according to Idc - Idcpreflt > 0.5 pu). According to │Idcp - Idcn│ < 0.1 pu, the detection M1 further includes determining that the difference between the DC current Idcp at the positive terminal p and the DC current Idcn at the negative terminal n during the fault is at most 0.1 pu. The detection M1 further includes: determining M14 that during a predetermined time window, the difference ΔUdc in the DC voltage over n control cycles during the fault 22 is above a predefined factor "a" between 0 and 1 times the positive rated voltage +Udc_rate of the MMC and below a predefined factor "a" between 0 and 1 times the negative rated voltage -Udc_rate of the MMC.

[0059] In some embodiments of the present invention, the DC current Idc and the DC voltage Udc are sensed M1 at one or both of the positive and negative terminals p and / or n of the MMC 7. In some embodiments, the DC current Idc is sensed as the DC current flowing into the positive DC terminal p of the MMC, the DC current flowing out of the negative terminal n of the MMC, or the current of the (e.g., six) arms 21 of the MMC. In some embodiments, the DC voltage Udc is sensed as the voltage between the positive DC terminal p and ground, the voltage between the negative DC terminal n and ground, or the voltage between the two DC terminals p and n.

[0060] Reference Figure 8 , in some embodiments of the present invention, detecting that an internal AC fault has occurred in another converter arrangement among a plurality of converter arrangements in M2 includes: determining M11 that the change in the sensed DC current Idc during the fault 22 compared to the pre-fault DC current Idc - preflt is equal to or greater than a predetermined first threshold, and determining M12 that the difference ΔUdc in the DC voltage sensed M1 over a plurality of control cycles during the fault 22 is equal to or greater than a predetermined second threshold. In some embodiments, the number of control cycles is an integer in the range of 1 to 10, or 2 to 5, preferably 3.

[0061] In some embodiments, the sensed change in the DC current being equal to or greater than a predetermined first threshold corresponds to the DC current Idc sensed M1 changing its direction by at least 1.5 pu compared to the pre-fault DC current Idcpreflt (e.g., according to Idc - Idcpreflt < -1.5 pu), where Idc can be sensed at the positive terminal p of the MMC 7, i.e., Idcp, or at the negative terminal n of the MMC 7, i.e., Idcn.

[0062] In some other embodiments, the sensed DC current change being equal to or greater than a predetermined first threshold corresponds to the DC current Idc of the sensed M1 increasing by at least 0.5 pu compared to the pre-fault DC current Idcpreflt.

[0063] Thus, in some embodiments, the absolute value of the first threshold is at least 0.5 pu, i.e., the first threshold is -0.5 pu or +0.5 pu.

[0064] In some embodiments of the present invention, the absolute value of the second threshold is at least the DC rated voltage Udc_rate of the MMC, i.e., the second threshold is +Udc_rate or -Udc_rate. In some embodiments, the difference ΔUdc in the DC voltage of the sensed M1 over a plurality of control cycles during a fault 22 being equal to or greater than a predetermined second threshold corresponds to the difference ΔUdc in the DC voltage being above the positive DC rated voltage +Udc_rate of the MMC and below the negative DC rated voltage -Udc_rate of the MMC during a predetermined time window. In some embodiments of the present invention, the predetermined time window in the determination step M14 is less than 5 ms, e.g., a quarter of the fundamental frequency period of the AC network 5.

[0065] In some embodiments of the present invention, at least one of the plurality of serially connected converter units 31 of each arm 21 is a half-bridge unit 31H and up to 50% are half-bridge units 31H, i.e., each arm includes both FB units and HB units.

[0066] In some embodiments of the present invention, the MMC has a double-star topology.

[0067] In at least one of the converter arrangements 6, the detection M2 includes detecting an internal AC fault between another MMC 7b or 7a and the valve side of the transformer 8b or 8a, the other MMC being connected to the AC network 5 through the valve side, wherein the other MMC is included in an external converter arrangement 6 and at least one converter arrangement 6 is connected in series with the external converter arrangement 6.

[0068] Additionally, in at least another of the converter arrangements 6, the detection M2 includes: internally detecting an internal AC fault between its MMC 7a or 7b and the valve side of its transformer 8a or 8b in the converter arrangement, its MMC being connected to the AC network 5 through the valve side, that is, the converter arrangement 6 can detect a fault 22 inside itself through a conventional detection process (e.g., differential protection).

[0069] Regardless of whether the fault 22 is detected in its own converter arrangement or externally, in response to the detection of the fault, each of the plurality of serially connected converter arrangements 6 controls its MMC by blocking each of the cells 31 in the negative arm 21n while keeping the positive arm 21p in operation and controlling the current of each phase 20 to zero.

[0070] An embodiment of the method of the present invention may be performed by a controller 10 (e.g., including a converter controller 51, which is the converter controller 51 of each converter arrangement 6 included in the inverter arrangement 4), the controller 10 including a processing circuit 11 associated with a data storage device 12. The processing circuit may be equipped with one or more processing units CPU in the form of one or more microprocessors, which execute appropriate software stored in the associated memory to obtain the required functions. However, other suitable devices with computing capabilities may be included in the processor, such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., in order to control the valves of the respective MMCs 7 in the inverter arrangement 4 and perform embodiments of the method of the present disclosure, while executing appropriate software 13, which is stored, for example, in a suitable data storage device 12 (such as RAM, flash memory or a hard disk), or in the processing circuit itself (e.g., in the case of an FPGA).

[0071] Embodiments of the present invention may be conveniently implemented using one or more conventional general or special purpose digital computers, computing devices, machines or microprocessors, including one or more processors, memories and / or computer-readable storage media programmed according to the teachings of the present disclosure. Appropriate software code may be readily prepared by a skilled programmer based on the teachings of the present disclosure, as will be apparent to those skilled in the software art.

[0072] In some embodiments, the present invention includes a computer program product 12, which is a non-transitory storage medium or computer-readable medium (media) on / wherein instructions 13 are stored in the form of computer-executable components or software (SW), and the instructions may be used to program a computer to perform any one of the methods / procedures of the present invention. Examples of storage media may include, but are not limited to, any type of disk (including floppy disks, optical disks, DVDs, CD-ROMs, microdrives and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, DRAMs, VRAMs, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs)), or any type of medium or device suitable for storing instructions and / or data.

[0073] In a more general embodiment of the present invention, a method of controlling an MMC 7 in an inverter arrangement 4 between a DC network 2 and a three-phase AC network 5 is provided, wherein the method includes detecting an internal AC fault 22 in an M1 inverter arrangement and controlling the M2 MMC by blocking each of the cells 31 in a negative arm 21n while keeping a positive arm 21p in operation and controlling the current of each phase 20 to zero.

[0074] The present disclosure has been mainly described above with reference to several embodiments. However, as will be readily understood by those skilled in the art, other embodiments are equally possible within the scope of the present disclosure defined by the appended claims, in addition to the embodiments disclosed above.

Claims

1. A method for controlling an inverter assembly (4) between a DC network (2) and a three-phase AC network (5), The inverter assembly includes a plurality of converter arrangements (6a, 6b) connected in series, each converter arrangement including a controller (10) and a modular multilevel converter MMC (7), the modular multilevel converter MMC (7) having a topology with a positive arm (21p) and a negative arm (21n) for each phase (20), wherein, Each of the arms (21) includes a plurality of converter units (31) connected in series, each of the units including an energy storage device (33) and a plurality of valves (35), at least 50% of the plurality of converter units connected in series in each arm being full-bridge units (31F), at least one of the plurality of converter units connected in series in each arm being a half-bridge unit (31H) and up to 50% being the half-bridge units (31H). The method includes, in each converter arrangement of the plurality of converter arrangements (6), by a controller (10) in the converter arrangement: sensing (M1) at least one characteristic of the MMC, wherein the at least one characteristic includes a DC current (Idc) and a DC voltage (Udc); detecting (M2) that an internal AC fault (22) has occurred in one of the plurality of converter arrangements based on the sensed (M1) characteristic; and in response to the detection (M2) of the fault (22), controlling (M3) the MMC in the converter arrangement by blocking the negative arm (21n) of the MMC while keeping the positive arm (21p) of the MMC unblocked and controlling the current amplitude of each phase (20) to approach zero. wherein detecting (M2) that an internal AC fault has occurred in at least one of the plurality of converter arrangements includes detecting that an internal AC fault has occurred in another one of the plurality of converter arrangements (6); and wherein detecting that an internal AC fault has occurred in another one of the plurality of converter arrangements (6) includes: determining (M11) the difference between the sensed DC current (Idc) and the pre-fault DC current (Idcpreflt): being higher than a predetermined first threshold current value (Im1); or being lower than a predetermined second threshold current value (Im2); and determining (M12) that the absolute value of the difference in the sensed (M1) DC voltage (ΔUdc) during the fault (22) over a number of control cycles is higher than a predetermined threshold voltage value (Um1).

2. The method according to claim 1, wherein, The at least one characteristic includes sensing (M1) at one or both of the positive and negative DC terminals (p, n) of the MMC (7), sensing (M1) between the positive DC terminal and / or the negative DC terminal and ground or between the positive DC terminal and the negative DC terminal.

3. The method according to claim 1, wherein, The predetermined first threshold current value (Im1) is in the range from 0.2 to 1.0 per unit.

4. The method according to claim 1, wherein, The predetermined second threshold current value (Im2) is in the range from -1.2 to -2.0 per unit.

5. The method according to claim 1, wherein, The predetermined threshold voltage value (Um1) is in the range from 0.5 to 1.0 per unit.

6. The method according to claim 1, wherein, During a predefined time window, the difference (ΔUdc) in the sensed DC voltage is above the predetermined threshold voltage value (Um1) and below the negative value (-Um1) of the predetermined threshold voltage value.

7. The method according to claim 1, wherein, The detection (M2) in at least one of the plurality of converter arrangements includes: detecting, by differential protection, that an internal AC fault has occurred in its own converter arrangement.

8. The method according to claim 7, wherein, The method includes: signaling information about the detected internal AC fault to the respective controllers (10) of the other converter arrangements among the plurality of converter arrangements.

9. The method according to claim 1, wherein, The maintaining to unblock the positive arm (21p) of the MMC includes: keeping the positive arm (21p) in operation.

10. A computer program product (12) including computer-executable components (13) for causing the controller (10) to execute the method according to any one of the preceding claims when the computer-executable components run on a processing circuit (11) included in the controller.

11. An inverter assembly (4) configured between a DC network (2) and a three-phase AC network (5), the inverter assembly including: A plurality of serially-connected converter arrangements (6a, 6b), each converter arrangement including a controller (10) and a modular multilevel converter MMC (7), the modular multilevel converter MMC (7) having a topology with one positive arm (21p) and one negative arm (21n) for each phase (20), wherein each of the arms (21) includes a plurality of serially-connected converter units (31), each of the units including an energy storage device (33) and a plurality of valves (35), at least 50% of the plurality of serially-connected converter units in each arm being full-bridge units (31F), at least one of the plurality of serially-connected converter units in each arm being a half-bridge unit (31H) and up to 50% being the half-bridge units (31H); wherein, in each of the plurality of serially-connected converter arrangements, the controller (10) includes a processing circuit (11) and a data storage device (12) storing instructions (13) executable by the processing circuit, whereby the controller is operable to: sense at least one characteristic of the MMC in the converter arrangement, wherein the at least one characteristic includes DC current (Idc) and DC voltage (Udc); detect, based on the sensed characteristic, that an internal AC fault (22) has occurred in one of the plurality of converter arrangements; and in response to the detection of the fault (22), control the MMC in the converter arrangement by blocking the negative arm (21n) of the MMC while maintaining to unblock the positive arm (21p) and controlling the current amplitude of each phase (20) to approach zero. wherein the detection (M2) in at least one of the plurality of converter arrangements includes detecting that an internal AC fault has occurred in another one of the plurality of converter arrangements (6); and wherein detecting that an internal AC fault has occurred in another one of the plurality of converter arrangements (6) includes: determining (M11) the difference between the sensed DC current (Idc) and the pre-fault DC current (Idcpreflt): being higher than a predetermined first threshold current value (Im1); or being lower than a predetermined second threshold current value (Im2); and determining (M12) that the absolute value of the difference in the sensed DC voltage (ΔUdc) during the fault (22) over a number of control cycles is higher than a predetermined threshold voltage value (Um1).

12. The inverter assembly according to claim 11, wherein, The controller can be operated to keep the positive arm (21p) of the MMC in operation when the blocking of the positive arm (21p) of the MMC is released and maintained.

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