Embedded packaging concepts for integrating ASICs and optical components

Abstract

The present disclosure relates to embedded packaging concepts for integrating application specific integrated circuits and optical components. The present disclosure describes an optical package and a manufacturing method. In one embodiment, a controller chip is embedded in a single package together with an optical component including a photodetector (PD) and one or more emitters.

Description

[0001] Related patent applications

[0002] This application claims the benefit of priority to Singapore Patent Application No. 10201908828W filed on September 23, 2019, which is incorporated herein by reference. Technical Field

[0003] Embodiments described herein relate to microelectronic packaging and, more particularly, to optical packaging. Background Art

[0004] As microelectronic devices become smaller and more portable, sensors are increasingly incorporated to detect the environment or context associated with the use of the device. These sensors include light sensors or proximity sensors, which can detect ambient light or proximity to a target object such as a user's ear or face. In one specific implementation, a proximity sensor may include a light source and a photodetector (PD). In application, the PD can detect proximity to a target object by measuring the amount of light from the light source. Summary of the invention

[0005] The present disclosure describes an optical package and a manufacturing method in which a controller chip is embedded in a single package together with optical elements, which include one or more photodetectors (PDs) and one or more emitters. In one specific implementation, the controller chip and the optical elements are arranged side by side in a single packaging level. In other specific implementations, the controller chip is embedded in a first packaging level, and the optical elements are stacked on top of the controller chip in a second packaging level. Various solutions can be used to route the optical elements, including redistribution layers (RDLs), printed circuit boards (PCBs), vertical vias, and wire bonding. In some specific implementations, laser direct structuring (LDS) technology is used for electrical line connections. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic cross-sectional side view of an optical package including a controller chip and an optical element in parallel according to one embodiment.

[0007] Figure 2 According to one embodiment of the invention, Figure 1 The process flow of the method for optical packaging is disclosed.

[0008] FIG. 3A to FIG. 3F According to one embodiment of the invention, Figure 1 Schematic cross-sectional side view of a method for an optical package.

[0009] FIG. 4A to FIG. 4Bis a schematic cross-sectional side view of an optical package according to an embodiment, wherein optical elements are stacked on top of a controller chip.

[0010] Figure 5A Is manufactured according to the embodiment FIG. 4A to FIG. 4B The process flow of the method for optical packaging is disclosed.

[0011] Figure 5B According to one embodiment of the invention, Figure 4A The process flow of the method for optical packaging is disclosed.

[0012] Figure 5C According to one embodiment of the invention, Figure 4B The process flow of the method for optical packaging is disclosed.

[0013] Fig. 6A is a schematic cross-sectional side view of an optical package including optical elements stacked on top of a controller chip and laser direct structuring of a second packaging level according to one embodiment.

[0014] Figure 6B is a schematic cross-sectional side view of a laser directly structured via according to one embodiment.

[0015] Figure 7 According to one embodiment of the invention, Fig. 6A The process flow of the method for optical packaging is disclosed.

[0016] Figure 8 is a schematic cross-sectional side view of an optical package including an optical element stacked on top of a controller chip with laser direct structuring of a first packaging level and a second packaging level according to one embodiment.

[0017] Fig. 9 According to one embodiment of the invention, Figure 8 The process flow of the method for optical packaging is disclosed.

[0018] FIG. 10A to FIG. 10F According to one embodiment of the invention, Figure 8 Schematic cross-sectional side view of a method for an optical package.

[0019] Fig.11 is a schematic cross-sectional side view of an optical package including an optical element stacked on top of a controller chip with laser direct structuring of a first packaging level and a second packaging level according to one embodiment.

[0020] Fig.12 According to one embodiment of the invention, Fig.11 The process flow of the method for optical packaging is disclosed.

[0021] FIG. 13A to FIG. 13H According to one embodiment of the invention, Fig.11 Schematic cross-sectional side view of a method for an optical package.

[0022] Fig.14 is a schematic cross-sectional side view of an optical package including an optical element stacked on top of a controller chip with laser direct structuring of a first packaging level and a second packaging level according to one embodiment.

[0023] Fig.15 According to one embodiment of the invention, Fig.14 The process flow of the method for optical packaging is disclosed.

[0024] 16A to 16H According to one embodiment of the invention, Fig.14 Schematic cross-sectional side view of a method for an optical package.

[0025] Fig.17 is a schematic cross-sectional side view of an optical package including optical elements and wire bonds stacked on top of a controller chip according to one embodiment.

[0026] Fig.18 According to one embodiment of the invention, Fig.17 The process flow of the method for optical packaging is disclosed.

[0027] Fig.19 is a schematic cross-sectional side view of an optical package including optical elements and wire bonds stacked on top of a controller chip according to one embodiment.

[0028] Fig. 20 According to one embodiment of the invention, Fig.19 The process flow of the method for optical packaging is disclosed.

[0029] FIG. 21A to FIG. 21B is a schematic side view of an earplug according to one embodiment.

[0030] Fig. 22 is a schematic side view of an earpiece according to one embodiment.

[0031] Fig.23 is a schematic side view of a mobile phone according to one embodiment. DETAILED DESCRIPTION

[0032] The embodiment describes an optical package and a manufacturing method. Specifically, the optical package can be incorporated into a portable electronic device as a light sensor or a proximity sensor. On the one hand, the optical package according to the embodiment embeds a controller chip and one or more photodetectors (PD) and one or more transmitters in a single package. The controller chip can be used to control the operation of one or more PDs and transmitters. For example, the controller chip can be an application specific integrated circuit (ASIC) or a field programmable gate array (FPBA). It is observed that the traditional optical package for proximity sensors mounts the PD and the light source on a flexible circuit. This end of the flexible circuit can be mounted to the housing, and the opposite end of the flexible circuit is guided to the controller on the circuit board located at other positions in the housing. It is observed that such configurations can be particularly susceptible to mechanical shocks and external electromagnetic interference (EMI). On the one hand, compared with traditional optical packages, the optical package and the manufacturing method according to the embodiment provide alternative layouts and form factors. In some embodiments, the optical package can provide EMI suppression and mitigate mechanical shock. For example, EMI suppression can be achieved by adding an EMI cover or a metal cover to the finished package. By embedding multiple components into a single package, rather than connecting multiple components at opposite ends of a flexible circuit, mechanical shock can be mitigated. In addition, the optical package according to the embodiment can be viewed as a system-level package that allows independent testing and calibration. Some embodiments can be compatible with flexible substrates and silicone molding compounds.

[0033] In various embodiments, description is made with reference to the accompanying drawings. However, certain embodiments may be implemented without one or more of these specific details or in combination with other known methods and configurations. In the following description, many specific details such as specific configurations, sizes and processes are shown to provide a thorough understanding of the embodiments. In other cases, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. "One embodiment" mentioned throughout the specification refers to the specific features, structures, configurations or characteristics described in conjunction with the embodiments being included in at least one embodiment. Therefore, the phrase "in one embodiment" that appears in multiple places throughout the specification does not necessarily refer to the same embodiment. In addition, specific features, structures, configurations or characteristics can be combined in one or more embodiments in any appropriate manner.

[0034] As used herein, the terms "over," "to," "between," and "on" may refer to the relative position of one layer with respect to other layers. A layer that is "over" or "on" another layer or bonded "to" another layer or "in contact with another layer may be directly in contact with the other layer or may have one or more intervening layers. A layer that is "between" multiple layers may be directly in contact with the multiple layers or may have one or more intervening layers.

[0035] As used herein, the term "routing layer" may refer to various routings including single-layer structures and multi-layer structures, including redistribution layers (RDLs), printed circuit boards (PCBs), and metal trace layers, such as those formed by laser direct structuring. The term "emitter" as used herein includes light emitting diodes (LEDs), including vertical cavity surface emitting lasers (VCSELs).

[0036] In the following description, various configurations and manufacturing sequences that may share similar materials, arrangements, or processes are described. For the sake of clarity and brevity, similar features may not necessarily be described in the same detail in the subsequent illustrations and processes. Therefore, it should be understood that a specific description relative to a specific illustration may also apply to alternative configurations and illustrations that share the same or similar features.

[0037] Reference now Figure 1 According to one embodiment, a cross-sectional side view of an optical package 100 is provided, which includes a controller chip 120 and optical elements in parallel, which include one or more emitters 140 and PD 130. For example, multiple different emitters 140 can be designed to emit at different wavelengths or intensities. In one embodiment, the optical package 100 includes a backside wiring layer 102, which includes a top side 103 and a bottom side 104, and a printed circuit board (PCB) core 110 on the top side 103 of the backside wiring layer 102. The PCB core 110 may include a plurality of vertical through holes 112 and a plurality of cavities 115. The controller chip 120 is positioned face-up in a first cavity of the plurality of cavities 115, and the photodetector (PD) 130 is positioned in a second cavity of the plurality of cavities 115. The molding compound 150 encapsulates the controller chip 120 in the first cavity 115, and encapsulates the PD 130 in the second cavity 115. The molding compound 150 may be formed of a suitable molding material including epoxy resins and more flexible materials such as silicone. The front wiring layer 160 is positioned on top of the controller chip 120, the molding compound 150, and the PCB core 110. The aperture 162 is formed in the front wiring layer 160 above the PD 130. The optical package 100 may additionally include a plurality of solder bumps 170 on the bottom side 104 of the back wiring layer 102, for example, for mounting on a motherboard or other system components of an electronic device.

[0038] The optical package 100 according to the embodiment may include one or more emitters 140 and one or more PDs 130. Figure 1 In the specific embodiment shown, one or more emitters 140 are positioned within a corresponding cavity 115, and similar to the PD 130, a corresponding aperture 162 is formed within the front-side wiring layer 160 above the corresponding emitter 140. As shown, the maximum width of the aperture 162 can be less than the maximum width of the top surface of the corresponding optical element (e.g., emitter, PD).

[0039] According to an embodiment, the PCB core 110 can be a laminate 114. For example, the PCB core 110 can be a composite of a glass fiber woven cloth and a polymer (e.g., a resin). The PCB core 110 can be formed of various suitable PCB materials including FR4, prepreg, polyimide, etc. The PCB core 110 can be rigid or flexible. The vertical through hole 112 can be a copper column, such as a copper column formed using a plating technique after drilling through a through hole through the PCB core 110. The PCB core 110 can include a top side ground pad 116 and a bottom side ground pad 118.

[0040] The optical element according to the embodiment may be a vertical element, including a top electrode and a bottom electrode. Specifically, the PD 130 may have a top electrode 132 and a bottom electrode 134, and the emitter may have a top electrode 142 and a bottom electrode 144. The front side wiring layer 160 may include a contact pad 165 formed on the top electrode 132 of the PD 130 and the top electrode 142 of the emitter 140, and may be directly on them. The contact pad 165 may also be formed on the contact pad 122 of the controller chip 120 facing upward and the vertical through hole 112 or the top side ground pad 116, and may be directly on them.

[0041] In such Figure 1 In the illustrated embodiment, the front wiring layer 160 can be a front redistribution layer (RDL), which can be formed directly on the underlying structure in a layer-by-layer process using thin film processing technology. For example, the front RDL may include one or more metal traces 166, one or more dielectric layers 164, through holes 168, and contact pads 165. The RDL can be formed of suitable materials. For example, the dielectric layer 164 can be formed of a photoimageable dielectric material, including a polymer (e.g., polyimide, epoxy resin, epoxy blend, etc.) or an inorganic material (e.g., oxide, nitride), and the metal traces 166 and through holes 168 can be formed of suitable metals including copper. Similarly, the contact pads 165 can be formed of one or more metals including copper.

[0042] In such Figure 1 In the embodiment shown, the backside wiring layer 102 is an RDL. The backside wiring layer 102 can be formed similarly to the frontside wiring layer 160 described previously. The backside wiring layer 102 can include one or more dielectric layers 107, vias 108, contact pads 109, and optional metal traces 106. In one embodiment, the one or more dielectric layers 107 are formed of the same material as the molding compound 150 and can be formed simultaneously with the molding compound 150. According to an embodiment, the PD 130 has a bottom electrode 134 electrically connected to the backside wiring layer 102. Similarly, each emitter 140 has a bottom electrode 144 electrically connected to the backside wiring layer 102. The vias 108 of the backside wiring layer 102 can be formed through the dielectric layer 107 to contact the PD 130 and the emitter 140. The dielectric layer 107 can be separate from the molding compound 150 or part of the molding compound. In one embodiment, vias 108 extend through molding compound 150 to contact bottom electrodes 134, 144 of PD 130 and emitter 140, respectively, and may optionally extend through one or more additional dielectric layers 107. Vias 108 may additionally contact metal traces 106 or bottom side ground pads 118 of PCB core 110.

[0043] Figure 2 According to one embodiment of the invention, Figure 1 The process flow of the method for optical packaging is disclosed. FIG. 3A to FIG. 3F According to one embodiment of the invention, Figure 1 Schematic cross-sectional side view of a method for an optical package. For the sake of clarity and brevity, the following description describes Figure 2 and FIG. 3A to FIG. 3F structure and process flow.

[0044] At operation 2010, the PCB core 110 is placed on the carrier substrate 200. Figure 3A As shown, the carrier substrate 200 may include a support substrate 202 and an adhesive layer 204. Then, at operation 2020, the controller chip 120 and the optical elements (eg, PD 130, emitter 140) are placed into the cavity 115 in the PCB core 110, as shown in FIG. Figure 3B In one embodiment, the cavity 115 is deeper than the controller chip 120 and the optical element is taller so that there is a gap height.

[0045] Reference now Figure 3C At operation 2030, the controller chip 120 and the optical components are packaged in the PCB core 110 using, for example, a molding compound 150. Figure 3CIn the particular embodiment shown, the molding compound 150 fills the remaining volume within the cavity 115 not already occupied by the controller chip 120 and the optical elements, and may (at this stage of processing) additionally cover the top surface of the PCB core 110 including portions that will serve as bottom-side ground pads 118. The carrier substrate 200 may then be removed at operation 2040 to expose the top-side ground pads 116, the controller chip 120, and the contact pads 122 at the top electrodes 142, 132 of the emitters 140 and PDs 130.

[0046] Then, at operation 2050, a front side wiring layer 160 is formed. Figure 3E As shown, front side wiring layer 160 is an RDL including one or more metal traces 166, one or more dielectric layers 164, vias 168, and contact pads 165. Apertures 162 are additionally formed in front side wiring layer 160 to expose the top surface of the optical element.

[0047] Then, at operation 2060, a backside wiring layer 102 is formed. Figure 3F As shown, the backside wiring layer 102 is an RDL including one or more dielectric layers 107, vias 108 and contact pads 109, and optionally one or more metal traces 106. Figures 3D to 3F As shown, the backside wiring layer 102 may include a portion of the molding compound 150. Thus, the formation of the backside wiring layer 102 may include forming a through hole 108 through the molding compound 150 covering the existing portion of the PCB core 110 starting from operation 2030. An additional dielectric layer 107 may also be formed. The dielectric layer 107 may be formed of a suitable material, including the molding compound 150 material, a polymer, an oxide, a nitride, etc. The solder bump 170 is then placed on the contact pad 109.

[0048] FIG. 4A to FIG. 4B 1 is a schematic cross-sectional side view of an optical package 100 according to an embodiment, wherein optical elements are stacked on top of a controller chip 120. In each embodiment, the optical package 100 includes a first (lower) packaging level 180 and a second (upper) packaging level 480 on top of a first packaging level 180. Note that FIG. 4A to FIG. 4B The first packaging level 180 in each of the embodiments shown may be similar to Figure 1 The optical package 100, wherein FIG. 4A to FIG. 4B The second packaging level 480 is formed using alternative materials and processes.

[0049] In one embodiment, such as FIG. 4A to FIG. 4BAs shown, the optical package 100 includes a first packaging level 180, which includes a backside wiring layer 102 including a top side 103 and a bottom side 104, and a controller chip 120 on the top side 103 of the backside wiring layer 102. The first packaging level 180 additionally includes a frontside wiring layer 160 on top of the controller chip 120, and a first plurality of vertical vias 112 extending between the frontside wiring layer 160 and the backside wiring layer 102. In addition to the optical elements, the first packaging level 180 can be substantially similar to Figure 1 An optical package 100.

[0050] Still refer to FIG. 4A to FIG. 4B , the second packaging level 480 may include one or more PDs 130 mounted on and in electrical contact with the front side wiring layer 160, and one or more emitters 140 mounted on and in electrical contact with the front side wiring layer 160. The top side wiring layer 460 is also positioned on and in electrical contact with the one or more PDs 130 and emitters 140, and a second plurality of vertical vias 412 extend between the top side wiring layer 460 and the front side wiring layer 160. Apertures 162 are formed in the top side wiring layer 460 above the respective emitters 140 and PDs 130, similar to the apertures 162 described previously.

[0051] exist FIG. 4A to FIG. 4B In each of the embodiments shown, the controller chip 120 is on the backside wiring layer 102 and faces upward. Figure 1 ,exist FIG. 4A to FIG. 4B In each of the embodiments shown, the first packaging level 180 may include a PCB core 110 on the top side 103 of the backside wiring layer 102, wherein the PCB core 110 includes a first plurality of vertical vias 112 and a cavity 115, wherein the controller chip 120 is within the cavity 115 and faces upward. The PCB core 410 may include a top side ground pad 416 and a bottom side ground pad 418.

[0052] The top side wiring layer 460 can be a top redistribution layer (RDL), which can be formed on the lower structure in a layer-by-layer process. For example, the top RDL can include one or more metal traces 466, one or more dielectric layers 464, through holes 468, and contact pads 465. The contact pads 465 are formed on the top electrode 132 of the PD 130 and the top electrode 142 of the emitter 140 and can be directly above them. The RDL can be formed of suitable materials. For example, the dielectric layer 464 can be formed of a photoimageable dielectric material, including a polymer (e.g., polyimide, epoxy resin, epoxy blend, etc.) or an inorganic material (e.g., oxide, nitride), and the metal traces 466 and through holes 468 can be formed of suitable metals including copper. Similarly, the contact pads 465 can be formed of one or more metals including copper.

[0053] refer to Figure 4A , the second packaging level 480 can be formed similarly to the first packaging level 180. In one embodiment, the second packaging level 480 includes a second PCB core 410 on the front wiring layer 160. Similar to the PCB core 110, the second PCB core 410 includes a plurality of vertical through holes 412 and a plurality of cavities 415, and each PD 130 and emitter 140 is located in a corresponding cavity 415. The second packaging level 480 can be manufactured substantially separately from the first packaging level 180 and then combined together. In one embodiment, the second packaging level 480 is hybrid bonded with the first packaging level 180. For example, this can occur at the panel level. Hybrid bonding can include multiple metal-metal bonds between the PCB core 410 and the front wiring layer 160. For example, a metal-metal bond may be formed between the bottom side ground pad 418 or vertical via 412 of the PCB core 410 and / or the bottom electrode 144, 134 of the optical element and the metal trace 166 (including the contact pad 169) or via 168 of the front side wiring layer 160. An oxide-oxide bond may be formed between the dielectric layer 164 of the PCB core 410 and the dielectric layer of the PCB core 410, which may be a surface layer or a portion of the body 414. Alternatively, the second packaging layer 480 is hybrid-bonded to the first packaging level 180 using a plurality of conductive joints, such as conductive paste, conductive film, or solder bumps. In one embodiment, solder bumps (not shown) are used to bond the bottom side ground pad 418 or vertical via 412 of the PCB core 410 and the metal trace 166 or via 168 of the front side wiring layer 160.

[0054] refer to Figure 4B , the second packaging level 480 can be formed on the first packaging level 180, for example using the first packaging level 180 as a reconstructed substrate. In such an embodiment, the PD 130, the emitter 140, and the second plurality of vertical vias 412 can be encapsulated in the molding compound 490. The top side wiring layer 460 can be similar to Figure 4A A top side wiring layer 460 is formed.

[0055] Figure 5A Is manufactured according to the embodiment FIG. 4A to FIG. 4B At operation 5010, a first packaging level 180 is formed to include a controller chip 120 packaged in a PCB core 110. In addition to the optical components, the process flow can be similar to the process flow of the embodiment of the present invention. Figures 1 to 3FThe manufacturing sequence may then take different paths depending on the structure of the second packaging level 480. In one embodiment, at operation 5020, the second packaging level 480 is bonded to the first packaging level 180. For example, this may correspond to Figure 4A 4. The embodiment shown, wherein the second packaging level 480 includes optical components packaged within the PCB core 410. In one embodiment, at operation 5060, the second packaging level 480 is formed on the first packaging level 180. For example, this may correspond to Figure 4B The embodiment shown, in which the second packaging level includes optical components encapsulated in a molding compound 490. In further variations, the molding compound may be a laser direct structuring compatible molding compound.

[0056] Reference now Figure 5B , providing a method of manufacturing according to one embodiment Figure 4A The process flow of the method for forming an optical package of the present invention is as follows. At operation 5022, the PCB core 410 is placed on the carrier substrate. At operation 5024, the optical element (e.g., one or more PDs 130 and one or more emitters 140) is placed in the cavity 415 in the PCB core 410. Then at operation 5026, the optical element is encapsulated in the PCB core 410 with the molding compound 450. At this time, the top side wiring layer 460 can be optionally formed at operation 5028, and then the carrier substrate is removed at operation 5030. Then at operation 5032, the bottom side grounding pad 418 or additional wiring can be optionally formed on the surface exposed after removing the carrier substrate. Then at operation 5034, the second packaging level 480 is bonded to the first packaging level 180. For example, this can be a hybrid bond or a bond with conductive bumps such as solder bumps. In one variation, the top side wiring layer 460 can be formed after the second packaging level 480 is bonded to the first packaging level 180.

[0057] Figure 5C According to one embodiment of the invention, Figure 4B. At operation 5062, an optical element (e.g., one or more PDs 130 and one or more emitters 140) is placed on the front wiring layer 160 of the first packaging level 180. For example, the optical element can be bonded using conductive bumps such as conductive films, pastes, solder bumps, etc. As shown, the bottom electrodes 144, 134 are bonded to the metal traces 166 (or contact pads 169) or vias 168 of the front wiring layer 160. Then at operation 5064, the optical element is packaged on the front wiring layer 160 with a molding compound 490. In some embodiments, the molding compound 490 can be opaque, such as black. In some embodiments, a vertical through hole 412 is then formed at operation 5066, wherein the molding compound 490 is first etched and then the vertical through hole 412 is plated. Alternatively, the vertical through hole 412 can be formed before packaging with the molding compound 490. For example, this can be accomplished by plating or gang bonding copper pins with solder to the front side wiring layer 160. A second package level top side wiring layer 460 can then be formed over the molding compound 490 and the optical element, as previously described at operation 5068.

[0058] As described in various embodiments, the molding compound can be used to encapsulate the optical element in the second packaging level. In addition, although the PCB core 110 has been described and shown in at least the first packaging level, this is not necessary according to the embodiment, and similar to the optical element, the controller chip can alternatively be sealed with a molding compound. In another variation, the molding compound used to encapsulate the optical element and / or the controller chip can be a laser direct structuring (LDS) compatible material. In this way, LDS molding can be used to form various interconnect structures through or on the molding compound, including vertical vias and wiring layers (including contact pads).

[0059] The LDS compatible molding compound according to the embodiment may include a matrix material and an LDS additive dispersed in the matrix material. For example, the LDS additive may be a non-conductive metal organic compound. This may include various metal oxide compositions, which may be mixed (e.g., compounded) with a matrix material (e.g., a resin). In an exemplary embodiment, the LDS additive is a dispersed tin oxide composition compounded with a matrix material. The embodiment is not limited to tin oxide, and a variety of other non-conductive metal organic compounds may be used, including other composite metal oxides.

[0060] A variety of organic materials can be used for the matrix material, which can depend on the temperature of exposure. Low temperature materials include polycarbonate (PC) and acrylonitrile butadiene styrene (ABS). Medium temperature materials that can withstand welding temperatures include polycaprolactam (PA6 / 6) and polyphthalamide (PPA). High temperature materials of polyetheretherketone (PEEK) that can withstand almost any welding. Other suitable materials can include polypropylene (PP), polyethylene terephthalate (PET), polybutylene terephthalate (PBT), polyphenylene sulfide (PPS), and liquid crystal polymer (LCP).

[0061] The LDS additive and laser parameters are selected so that when the laser is applied to the molding compound, the elemental metal in the non-conductive metal organic compound separates from the compound and forms nucleation particles, thereby forming a conductive path corresponding to the laser pattern. The nucleation particles can then be used as a nucleation layer for a subsequent electroless plating process to fully form the interconnect structure. Various metal layers can be formed by the electroless plating process, including gold, nickel, silver, zinc, tin, etc.

[0062] Fig. 6A is a schematic cross-sectional side view of an optical package 100 including optical elements and second package level laser direct structuring stacked on top of a controller chip 120 according to one embodiment. Fig. 6A The embodiment shown is substantially similar to that described with respect to Figure 4B The embodiment shown and described, except that the molding compound 491 is an LDS compatible material including a dispersed non-conductive metal organic compound. In such a configuration, LDS can be used to form trace wiring 497 and vertical vias 493. Alternatively, trace wiring 497 can be formed similar to metal trace 466. In one embodiment, the topside wiring layer 460 includes trace wiring 497, which includes a nucleation layer of metal particles of metal in a dispersed non-conductive metal organic compound. Similarly, the vertical via 493 can include a nucleation layer of metal particles of metal in a dispersed non-conductive metal organic compound. Both trace wiring 497 and vertical via 493 can additionally include a bulk conductive layer (e.g., copper) that is plated on top of the nucleation layer of metal particles. Trace wiring 497 and vertical via 493 can have a layout and connection similar to metal trace 466 and vertical via 412 in other ways.

[0063] Brief reference Figure 6B, shows an exemplary vertical via 693 formed in an LDS compatible molding compound 600 including a top side 602 and a bottom side 604. As shown, a metal nucleation layer 610 can be formed along the sidewalls of the molding compound 600 that will become the vertical via 693 using a laser pattern. Additionally, nucleation layers 612, 614 can be formed on the top and bottom sides of the molding compound to support additional electrical wiring layers. In the illustrated embodiment, the vertical via 693 is filled with plated metal 620. Likewise, in some embodiments, plated metal can be formed on the nucleation layers 612, 614 formed on the top and bottom sides of the molding compound to form trace wiring or ground / contact pads. Figure 6B The exemplary vertical vias 693 and nucleation layer shown are intended to serve as an exemplary illustration of laser patterning of an LDS-compatible molding compound 600 and may be implemented in various embodiments described herein using such materials.

[0064] exist Fig. 6A In the specific embodiment shown, the first packaging level 180 includes a PCB core 110 on the top side of the backside wiring layer 102, and a controller chip 120 facing upward within a cavity 115 in the PCB core 110. The PD 130, the transmitter 140, and the second plurality of vertical vias 493 are encapsulated in a second level molding compound 491, which is an LDS compatible material including a dispersed non-conductive metal organic compound. The topside wiring layer 460 includes trace wiring 497, which optionally includes a nucleation layer of metal particles of metal in the dispersed non-conductive metal organic compound. The second plurality of vertical vias 493 can be similarly formed with a nucleation layer of metal particles.

[0065] Figure 7 According to one embodiment of the invention, Fig. 6A. At operation 7010, the first packaging level 180 is formed to include a controller chip 120 encapsulated in a PCB core 110, as previously described. At operation 7020, the optical components (PD and emitter) are placed on the front side wiring layer 160 of the first packaging level 180. For example, the front side wiring layer 160 can be an RDL. The optical components are then packaged with an LDS compatible molding compound 491 at operation 7030. In one embodiment, vertical vias 493 are then formed in the molding compound 491 at operation 7040. The formation of the vertical vias 493 can include directing a laser at the molding compound 491 to form a nucleation layer of metal particles, followed by a chemical plating operation to form a bulk metal layer of the vertical vias 493 on top of the nucleation layer. A top side wiring layer (e.g., trace wiring 497) is then formed on the molding compound 491 at operation 7050. For example, the top side wiring layer (e.g., trace wiring 497) can also be formed by applying a laser pattern to the surface of molding compound 491 and then electroplating a bulk metal layer pattern on the nucleation layer of metal particles. Alternatively, the top side wiring layer (e.g., trace wiring 497) can be formed similar to metal trace 466.

[0066] Reference now Figure 8 , according to an embodiment, a cross-sectional side view of an optical package 100 is provided, the optical package including an optical element stacked on top of a controller chip, an LDS having a first packaging level and a second packaging level. Figure 8 The illustrated embodiment is similar in several respects to Fig. 6A The embodiment shown is different. It is noted that the first packaging level 180 is formed with an LDS compatible molding compound 411. In addition, the processing sequence used results in the controller chip 120 facing down on the backside wiring layer 102, which can optionally be a printed circuit board (PCB). In the illustrated embodiment, the controller chip 120 is encapsulated in the LDS compatible molding compound 411. The front side wiring layer 160 can additionally include trace wiring 467, which includes a nucleation layer of metal particles of metal in a dispersed non-conductive metal organic compound in the LDS compatible molding compound 411. Likewise, the vertical vias 413 can be similarly formed.

[0067] Fig. 9 According to one embodiment of the invention, Figure 8 The process flow of the method for optical packaging is disclosed. FIG. 10A to FIG. 10F According to one embodiment of the invention, Figure 8 Schematic cross-sectional side view of a method for an optical package. For the sake of clarity and brevity, the following description describes Fig. 9 and FIG. 10A to FIG. 10FAt operation 9010, the controller chip 120 may be mounted on the backside wiring layer 102, which may be a PCB in one embodiment. Fig. 10A As shown, the controller chip 120 can be mounted face down, wherein the contact pads 122 are bonded to the backside wiring layer 102 or the ground pads 105 or the through holes 107 of the PCB. In one embodiment, a conductive film, conductive glue or solder bumps facilitate bonding. Then at operation 9020, the controller chip is packaged together with the LDS compatible molding compound 411.

[0068] Reference now Fig. 10B , at operation 9030, vertical vias 413 are formed in the molding compound, and at operation 9040, a front side wiring layer 160 is formed on the molding compound. The vertical vias 413 may contact the ground pads 105. The front side wiring layer 160 may include a single layer of trace wiring 467 formed using LDS, but may optionally include additional dielectric and metal wiring layers. Alternatively, the vertical vias 413 may be formed before sealing with the molding compound 411. For example, this may be achieved by plating or group bonding a copper pin to the back side wiring layer 102 with solder.

[0069] Then, at operation 9050, the optical components including the PD 130 and the emitter 140 are placed on the front side wiring layer 160, as shown in FIG. Fig. 10C In one embodiment, this can be accomplished using a conductive film, conductive paste, or solder bonding so that the bottom electrodes 144, 134 are bonded to the trace wiring 467 and electrically connected thereto.

[0070] Then, at operation 9060, the optical element may be encapsulated with a second LDS compatible molding compound 491, such as Fig. 10D Now refer to Fig. 10E , vertical vias 493 are formed in the molding material 491 at operation 9070, and a topside wiring layer 460 is formed on the molding material 491 at operation 9080. The vertical vias 493 can be in contact with the trace wiring 467. The topside wiring layer 460 can optionally include a single layer of trace wiring 497 formed using LDS, but can optionally include or form additional dielectric and metal wiring layers using alternative techniques. In addition, the aperture 162 is formed with the topside wiring layer 460 to expose the top surface of the optical element. As shown, the trace wiring 497 can be formed on and in electrical contact with the top electrodes 132, 142 of the optical element. The solder bump 170 can then be placed on the contact pad 109, as shown. Fig.10F As shown, the optical package 100 is used for further system integration.

[0071] Fig.11 is a schematic cross-sectional side view of another variation of an optical package 100 including optical elements stacked on top of a controller chip 120 with laser direct structuring of a first packaging level and a second packaging level according to an embodiment. Fig.11 Basically similar to Figure 8 , except that the manufacturing method may be substrate-less, and the backside wiring layer 102 may instead be formed of an RDL instead of a PCB. Fig.12 According to one embodiment of the invention, Fig.11 The process flow of the method for optical packaging is disclosed. FIG. 13A to FIG. 13H According to one embodiment of the invention, Fig.11 Schematic cross-sectional side view of a method for an optical package. For the sake of clarity and brevity, the following description describes Fig.11 The structure and Fig.12 and FIG. 13A to FIG. 13H At operation 1210, the controller chip 120 is placed on the carrier substrate 200. Fig.13A As shown, at operation 1220 , the controller chip may be placed face down on a carrier substrate and then encapsulated with an LDS compatible molding compound 411 .

[0072] Reference now Fig. 13B , vertical vias 413 are formed in the molding material 411 at operation 1230, and a front side wiring layer 160 is formed on the molding material 411 at operation 1240. The front side wiring layer 160 may include a single layer of trace wiring 467 formed using LDS, but may optionally include additional dielectric and metal wiring layers. Then, at operation 1250, an optical component including the PD 130 and the emitter 140 is placed on the front side wiring layer 160, as shown in FIG. Fig. 13C In one embodiment, this can be accomplished using a conductive film, conductive paste, or solder bonding so that the bottom electrodes 144, 134 are bonded to the trace wiring 467 and electrically connected thereto.

[0073] Then, at operation 1260, the optical component may be encapsulated with a second LDS-compatible molding compound 491, such as Fig.13D Now refer to FIG. 13E to FIG. 13F , the carrier substrate is removed at operation 1270, and then a backside wiring layer 102, which may be an RDL, is formed at operation 1280. As shown, the backside wiring layer 102 may include a dielectric layer 107, a plurality of through-vias 108, and contact pads 109. In one embodiment, the dielectric layer 107 is a photoimageable polymer and may be a molding compound material.

[0074] Reference now Figure 13G, vertical vias 493 are formed in the molding material 491 at operation 1290, and a topside wiring layer 460 is formed on the molding material 491 at operation 1292. The topside wiring layer 460 may include a single layer of trace wiring 497 formed using LDS, but may optionally include additional dielectric and metal wiring layers. In addition, the aperture 162 is formed with the topside wiring layer 460 to expose the top surface of the optical element. As shown, the trace wiring 497 can be formed on and electrically contact the top electrodes 132, 142 of the optical element. The solder bump 170 can then be placed on the contact pad 109, as shown. Fig.13H As shown, the optical package 100 is used for further system integration.

[0075] Fig.14 is a schematic cross-sectional side view of an optical package including an optical element stacked on top of a controller chip with laser direct structuring of a first packaging level and a second packaging level according to one embodiment. Fig.14 The optical package 100 may be similar to other optical packages including LDS, except that Fig.14 The optical package 100 shown may be manufactured using a substrate-less packaging method with the controller chip 120 finally integrated. Fig.15 According to one embodiment of the invention, Fig.14 The process flow of the method for optical packaging is disclosed. 16A to 16H According to one embodiment of the invention, Fig.14 Schematic cross-sectional side view of a method for an optical package. For the sake of clarity and brevity, the following description describes Fig.14 The structure and Fig.15 and 16A to 16H process and structure.

[0076] At operation 1510, an optical element is placed on a carrier substrate 200. Fig.16A As shown, the top electrodes 142, 132 of the optical element can be placed face down on a carrier substrate and then encapsulated with an LDS compatible molding compound 491 at operation 1520. Referring now to Fig. 16B , a vertical via 413 is formed in the molding material 491 at operation 1530, and a front side wiring layer 160 is formed on the molding material 491 at operation 1540. Fig. 16C As shown, the front side wiring layer 160 may be an RDL including one or more dielectric layers and metal wiring layers, as described above, and may include a metal wiring layer formed directly on the bottom electrodes 144, 134 of the optical element. Then, at operation 1550, the controller chip 120 is placed face down on the front side wiring layer 160, as shown in FIG. Fig.16DIn one embodiment, this can be accomplished using a conductive film, conductive paste, or using solder bumps 270 as shown. Then, at operation 1560, the controller chip 120 can be packaged with a second LDS-compatible molding compound 411, such as Fig.16E Now refer to Fig.16F At operation 1570, vertical vias 413 are formed in the molding compound 411, and a backside wiring layer 102 is formed on the molding compound 411. The backside wiring layer 102 may include a single layer of trace wiring formed using LDS, and may include contact pads 109, but may optionally include additional dielectric and metal wiring layers.

[0077] Reference now FIG. 16G to FIG. 16H , the carrier substrate 200 is removed at operation 1580, and then a topside wiring layer 460, which may be an RDL, is formed at operation 1590. As shown, the aperture 162 is formed with the topside wiring layer 460 to expose the top surface of the optical element. As shown, trace wiring 497 may be formed on and electrically contact the top electrodes 132, 142 of the optical element. Solder bumps 170 may then be placed on the contact pads 109 for further system integration of the optical package 100.

[0078] Fig.17 is a schematic cross-sectional side view of an optical package 100 including optical components and wire bonds stacked on top of a controller chip according to one embodiment. Fig.18 According to one embodiment of the invention, Fig.17 1. The process flow of the method for an optical package of the present invention. In the illustrated embodiment, the optical package may include a backside wiring layer 102, which may be a PCB. The backside wiring layer 102 includes a top side 103 and a bottom side 104. At operation 1810, the controller chip 120 is mounted face down on the backside wiring layer 102. For example, this can be achieved by bonding to the pad 105 with a solder bump 510. At operation 1820, one or more photodetectors 130 and emitters 140 are attached to the controller chip 120, and wire bonding is performed using a wire 502 bonded to the backside wiring layer 102 at operation 1830. As shown, the top electrodes 142, 132 are bonded to the ground pad 105 using the wire 502. The bottom electrodes 144, 134 can be bonded to the traces 504 formed on the top of the controller chip 120. The traces 504 are then wire bonded to the ground pad 105 using the wire 502. At operation 1840 , the wire-bonded controller chip and optical components are encapsulated. This can be accomplished, for example, by mounting a metal cap onto the backside wiring layer 102 or using a molding compound 500 . Fig.17A molding compound 500 is shown for encapsulating the controller chip 120, PD 130, and emitter 140 on the backside wiring layer 102. As previously described, the aperture 162 may additionally be formed above the top surface of the optical element. In one embodiment, the molding compound 500 is opaque (e.g., a black mold). Alternatively, a metal cover with similarly positioned apertures may be used. For example, the exemplary cover may have a shape corresponding to the outer contour of the molding compound 500 shown.

[0079] Fig.19 1 is a schematic cross-sectional side view of an optical package 100 according to one embodiment, the optical package including optical elements and wire bonds stacked on top of a controller chip 120. Specifically, Fig.19 The embodiment combines certain aspects of the first packaging level 180 of the previous embodiment with the wire bonding of the optical element. In one embodiment, the optical package 100 includes a backside wiring layer 102, which includes a top side 103 and a bottom side 104, and a PCB core 110 on the top side of the backside wiring layer 102. The PCB core 110 includes a plurality of vertical through holes 112 and a cavity 115. The controller chip 120 is in the cavity 115 and faces upward, and the molding compound 150 encapsulates the controller chip 120 in the cavity 115. The front side wiring layer 160 is on top of the controller chip 120, the molding compound 150, and the PCB core 110. For example, the front side wiring layer 160 can be an RDL as described above. One or more PDs 130 and emitters 140 are mounted on the top side of the front side wiring layer 160.

[0080] In one embodiment, the PD 130 includes a bottom electrode 134 directly above a first contact pad 169 of the front-side wiring layer 160, and a top electrode 132 wire-bonded to a second contact pad 169 of the front-side wiring layer 160. The top electrode 142 and the bottom electrode 144 of one or more emitters 140 may be similarly connected. In the illustrated embodiment, the PD 130 (and corresponding wires 502) are encapsulated in a first transparent molding compound 600, and the emitters 140 (and corresponding wires 502) are encapsulated in a second transparent molding compound 600 separate from the first transparent molding compound.

[0081] Different techniques such as metal caps or molding compounds can be used to encapsulate the optical elements. In the illustrated embodiment, an opaque molding compound is encapsulated on the front side wiring layer 160 and surrounds the pre-molded PD 130 and emitter 140 (including transparent molding compound 600). The aperture 162 can be formed as described above. In one embodiment, a filter layer 601 such as a bandpass filter can be formed below the aperture 162 to select the wavelength of light transmitted through the aperture 162. Alternatively, a metal cap with a similar aperture can be used instead of the molding compound 605.

[0082] Similar to the previously described embodiments, a plurality of solder bumps 170 may be placed on the bottom side 104 of the backside wiring layer 102 for additional integration. Additionally, the PCB core 110 may include a laminate 114. The frontside wiring layer 160 may be an RDL including one or more metal traces 166 and a dielectric layer 164. The backside wiring layer 102 may additionally be an RDL and may optionally include a portion of a molding compound 150 and a plurality of through vias 108 extending through the molding compound 150. Fig.19 The optical package 100 may share additional features of the other optical packages previously described.

[0083] Fig. 20 According to one embodiment of the invention, Fig.19 Except for the optical elements, operations 2010 to 2035 associated with the formation of the first packaging level 180 can be substantially similar to those described with respect to Figure 2 At operation 2010, the PCB core 110 is placed on the carrier substrate 200. At operation 2015, the controller chip 120 is placed in the cavity 115 within the PCB core 110, and it is sealed at operation 2020. The carrier substrate 200 can then be removed at operation 2025, and then the front side wiring layer 160 is formed at operation 2030, and the back side wiring layer 102 is formed at operation 2035.

[0084] Optical elements including one or more PDs 130 and emitters 140 are then placed on the front-side wiring layer 160 at operation 2040 and wire-bonded to the front-side wiring layer 160 at operation 2045. Each of the optical elements is then encapsulated within a transparent molding compound 600 at operation 2050, and then the molded optical elements are encapsulated at operation 2055, for example, by attaching a cover or molding with an opaque molding compound 605.

[0085] FIG. 21A to FIG. 23 Various portable electronic devices are shown in which various embodiments may be implemented. FIG. 21A to FIG. 21B is a schematic side view of an earbud according to one embodiment, the earbud comprising a housing 2102 and one or more openings 2110 with which the aperture 162 of the optical package 100 described herein may be aligned. Fig. 22 is a schematic side view of an earpiece according to one embodiment, the earpiece including a housing 2202 including an opening 2210 with which the aperture 162 of the optical package 100 described herein can be aligned. Fig.23is a schematic side view of a mobile phone according to one embodiment, the mobile phone including a housing 2302 including an opening 2310 with which the aperture 162 of the optical package 100 described herein may be aligned. These illustrations are intended to be exemplary and not exhaustive of specific implementations.

[0086] The following are some example implementations of the present disclosure:

[0087] Embodiment 19. An optical package comprising:

[0088] The first packaging level includes:

[0089] a backside wiring layer, the backside wiring layer comprising a top side and a bottom side;

[0090] A controller chip, wherein the controller chip is on the backside wiring layer;

[0091] a front-side wiring layer on top of the controller chip; and

[0092] a first plurality of vertical vias extending between the front-side wiring layer and the back-side wiring layer;

[0093] The second packaging level includes:

[0094] a photodetector (PD) mounted on and in electrical contact with the front-side wiring layer;

[0095] a transmitter mounted on and in electrical contact with the front-side wiring layer;

[0096] a topside wiring layer over and in electrical contact with the PD and the emitter; and

[0097] A second plurality of vertical vias extends between the topside wiring layer and the frontside wiring layer.

[0098] Embodiment 20. The optical package of embodiment 19, wherein the controller chip is on the backside wiring layer and faces upward.

[0099] Embodiment 21. The optical package according to embodiment 20:

[0100] wherein the first packaging level further comprises a printed circuit board (PCB) core on the top side of the backside wiring layer, the PCB core comprising the first plurality of vertical vias and cavities; and

[0101] The controller chip is within the cavity and faces upward.

[0102] Embodiment 22. The optical package according to embodiment 21:

[0103] wherein the second packaging level further comprises a second PCB core on the front wiring layer, the second PCB core comprising the second plurality of vertical through holes and the plurality of cavities; and

[0104] The PD is within a first cavity among the plurality of cavities, and the transmitter is within a second cavity among the plurality of cavities.

[0105] Embodiment 23. The optical package of embodiment 22, wherein the second packaging level is hybrid bonded to the first packaging level using a plurality of oxide-oxide bonds and metal-metal bonds.

[0106] Embodiment 24. The optical package of embodiment 22, wherein the second packaging level is solder bonded to the first packaging level.

[0107] Embodiment 25. The optical package of Embodiment 21, wherein the PD, the emitter, and the second plurality of vertical vias are encapsulated in a molding compound.

[0108] Embodiment 26. The optical package of embodiment 25, wherein the top-side wiring layer is a top redistribution layer (RDL) comprising one or more metal traces and one or more dielectric layers.

[0109] Embodiment 27. The optical package according to embodiment 25:

[0110] wherein the molding compound is a laser direct structuring (LDS) compatible material comprising a dispersed non-conductive metal organic compound; and

[0111] Wherein the top side wiring layer comprises trace wiring, the trace wiring comprises a nucleation layer of metal particles of the metal in the dispersed non-conductive metal-organic compound.

[0112] Embodiment 28. The optical package of Embodiment 27, wherein the second plurality of vertical vias comprises the nucleation layer of metallic particles of the metal in the dispersed non-conductive metal-organic compound.

[0113] Embodiment 29. The optical package according to embodiment 19:

[0114] wherein the PD, the emitter, and the second plurality of vertical vias are encapsulated in a second level molding compound; and

[0115] The second-stage molding compound is a laser direct structuring (LDS) compatible material including dispersed non-conductive metal organic compounds.

[0116] Embodiment 30. The optical package according to embodiment 29:

[0117] wherein the first packaging level further comprises a printed circuit board (PCB) core on the top side of the backside wiring layer, the PCB core comprising the first plurality of vertical vias and cavities; and

[0118] The controller chip is within the cavity and faces upward.

[0119] Embodiment 31. The optical package of embodiment 29, wherein the controller chip is on the backside wiring layer and faces downward.

[0120] Embodiment 32. The optical package according to embodiment 31:

[0121] wherein the controller chip is packaged in a first-level molding compound;

[0122] wherein the first stage molding compound is a laser direct structuring (LDS) compatible material comprising a first dispersed non-conductive metal organic compound; and

[0123] Wherein the front side wiring layer comprises a first trace wiring comprising a first nucleation layer of first metal particles of a first metal in the first dispersed non-conductive metal-organic compound.

[0124] Embodiment 33. The optical package of embodiment 32, wherein the backside wiring layer is a printed circuit board (PCB).

[0125] Embodiment 34. The optical package of embodiment 32, wherein the backside wiring layer is a redistribution layer (RDL) including a molding compound and a plurality of through vias passing through the molding compound.

[0126] Embodiment 35. An optical package comprising:

[0127] a backside wiring layer, the backside wiring layer comprising a top side and a bottom side;

[0128] A controller chip, the controller chip being mounted face-down on the back wiring layer;

[0129] a photodetector (PD) attached to the controller chip and wire-bonded to the backside wiring layer;

[0130] a transmitter attached to the controller chip and wire-bonded to the backside wiring layer; and

[0131] A molding compound encapsulates the controller chip, the PD, and the transmitter on the backside wiring layer.

[0132] Embodiment 36. The optical package of embodiment 35, wherein the molding compound is opaque.

[0133] When utilizing various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming optical packages. Although the embodiments are described in language specific to structural features and / or methodological acts, it should be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed should instead be understood as embodiments of the claims for exemplification.

Claims

1. An optical package, comprising: a backside wiring layer, the backside wiring layer comprising a top side and a bottom side; a printed circuit board (PCB) core on the top side of the backside wiring layer, the PCB core comprising a plurality of vertical through holes and a plurality of cavities; a controller chip, the controller chip facing upward in a first cavity among the plurality of cavities; a photodetector (PD), the PD being within a second cavity of the plurality of cavities; A molding material, wherein the molding material encapsulates the controller chip in the first cavity and encapsulates the PD in the second cavity; a front-side wiring layer on top of the controller chip, the molding compound, and the PCB core; as well as An aperture is in the front-side wiring layer above the PD. 2 . The optical package of claim 1 , further comprising an emitter within a third cavity of the plurality of cavities, and a second aperture in the front-side wiring layer above the emitter. 3 . The optical package of claim 2 , further comprising a plurality of solder bumps on the bottom side of the backside wiring layer. The optical package of claim 2 , wherein the PCB core comprises a laminate. 5 . The optical package of claim 1 , wherein the front-side wiring layer comprises a first contact pad on a top electrode of the PD, and the PD comprises a bottom electrode electrically connected to the back-side wiring layer. 6 . The optical package of claim 5 , further comprising a through-hole extending through a portion of the molding compound to electrically connect the bottom electrode of the PD to the backside wiring layer. 7 . The optical package of claim 1 , wherein the front-side wiring layer is a front redistribution layer (RDL) comprising one or more metal traces and one or more dielectric layers. 8 . The optical package according to claim 1 , wherein the backside wiring layer is a redistribution layer (RDL) including the molding compound and a plurality of through vias passing through the molding compound.

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