Charge pump circuit and image sensor including the charge pump circuit

Abstract

A charge pump circuit and an image sensor including the charge pump circuit are disclosed. The charge pump circuit includes a first pump unit and a second pump unit. The first pump unit includes a first capacitor and a first transistor, and generates a first node voltage by using a clock signal. The second pump unit includes a second capacitor, a second transistor, and a third transistor, and generates a negative output voltage by using the first node voltage. The clock signal and the first node voltage are each switched between a low level voltage and a high level voltage. The magnitude of the absolute value of the negative output voltage is greater than the magnitude of the absolute value of the high level voltage of the clock signal. The body of the third transistor is electrically isolated from the body of the second transistor.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2019-0116880 filed on September 23, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a charge pump circuit and an image sensor including the charge pump circuit. Background Art

[0003] An image sensor, which is a semiconductor-based sensor that receives light and generates an electrical signal, may include a pixel array having a plurality of pixels and a circuit configured to drive the pixel array, etc. Recently, as the demand for performance of image sensors increases, various studies have been conducted to improve dark current characteristics of image sensors. Summary of the invention

[0004] One aspect is to provide a charge pump circuit capable of outputting a high negative voltage.

[0005] According to one aspect of an example embodiment, a charge pump circuit is provided, comprising: a first pump unit, including a first capacitor and a first transistor, the first pump unit being configured to generate a first node voltage by using a clock signal; and a second pump unit, including a second capacitor, a second transistor and a third transistor, the second pump unit being configured to generate a negative output voltage by using the first node voltage, wherein the clock signal and the first node voltage are each switched between a low-level voltage and a high-level voltage, an absolute value of the negative output voltage has a magnitude greater than an absolute value of the high-level voltage of the clock signal, and a body of the third transistor is electrically isolated from a body of the second transistor.

[0006] According to another aspect of an example embodiment, a charge pump circuit is provided, the charge pump circuit being configured to generate a negative output voltage by receiving a clock signal, the charge pump circuit comprising: a substrate in which a first well and a second well are formed; a first pump unit comprising a first capacitor and a first transistor formed in the first well; a second pump unit comprising a second capacitor and a second transistor formed in the second well; and an isolation layer configured to electrically insulate the first well from the second well, wherein the clock signal switches between a low-level voltage and a high-level voltage in a regular cycle, and the magnitude of the absolute value of the negative output voltage is greater than the magnitude of the absolute value of the high-level voltage.

[0007] According to another aspect of an example embodiment, an image sensor is provided, comprising: a pixel array including a plurality of pixels defined by a first isolation layer; and a charge pump circuit including: a first pump unit including a first capacitor and a first transistor, the first pump unit being configured to generate a first node voltage by using a clock signal; and a second pump unit including a second capacitor, a second transistor, and a third transistor, the second pump unit being configured to generate a negative output voltage by using the first node voltage, and a body of the third transistor being electrically isolated from a body of the second transistor.

[0008] According to another aspect of the example embodiment, a charge pump circuit is provided, which is configured to generate a negative output voltage by receiving a clock signal, and the charge pump circuit includes: a substrate, an epitaxial layer is formed in the substrate, wherein a first well, a second well and a third well are formed in the epitaxial layer; a first pump unit, including a first capacitor and a P-type transistor formed in the first well; a second pump unit, including a second capacitor, a P-type transistor formed in the second well and an N-type transistor formed in the third well; and an isolation layer, formed between the first well, the second well and the third well, and configured to electrically insulate the first well, the second well and the third well from each other, wherein the clock signal switches between a low-level voltage and a high-level voltage in a regular period, and the magnitude of the absolute value of the negative output voltage is greater than the magnitude of the absolute value of the high-level voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram for describing an image sensor including a charge pump circuit according to example embodiments;

[0011] Figure 2 is used to describe the Figure 1 A block diagram of a charge pump circuit;

[0012] Figure 3 is used to describe the Figure 2 A circuit diagram of a charge pump circuit;

[0013] Figure 4 is used to describe the Figure 3 A graph of the operation of a charge pump circuit;

[0014] Figure 5 is used to describe the Figure 3 A cross-sectional view of a charge pump circuit;

[0015] FIG. 6A to FIG. 6C is used to describe the Figure 3 A cross-sectional view of a charge pump circuit;

[0016] Figure 7 is a circuit diagram for describing a charge pump circuit according to an example embodiment;

[0017] Figure 8 is used to describe the Figure 7 A graph of the operation of a charge pump circuit;

[0018] Fig. 9 is used to describe the Figure 7 A cross-sectional view of a charge pump circuit;

[0019] Fig.10 is a block diagram for describing a charge pump circuit according to an example embodiment;

[0020] Fig.11 is used to describe the Fig.10 A circuit diagram of a charge pump circuit;

[0021] Fig. 12A and Fig. 12B is used to describe the Fig.11 A cross-sectional view of a charge pump circuit;

[0022] Fig.13 is a top view for describing an active pixel sensor array of an image sensor according to example embodiments;

[0023] FIG. 14A to FIG. 14C is along Fig.13 A cross-sectional view taken along line XX' shown in FIG.

[0024] Fig.15A is a circuit diagram for describing an active pixel sensor array of an image sensor according to example embodiments; and

[0025] Fig. 15B is used to describe an example embodiment according to which an Fig.15A Schematic diagram of control signals for an active pixel sensor array shown in FIG. DETAILED DESCRIPTION

[0026] Figure 1 is a block diagram for describing an image sensor 1 including a charge pump circuit 10 according to example embodiments. Figure 2 is a block diagram for describing a charge pump circuit 10 according to an example embodiment.

[0027] Reference Figure 1 and Figure 2, the image sensor 1 may include a charge pump circuit 10, an active pixel sensor array 20, a row decoder 30, a row driver 40, a column decoder 50, a timing generator 60, a correlated double sampler (CDS) 70, an analog-to-digital converter (ADC) 80 and an input / output buffer 90.

[0028] The active pixel sensor array 20 may include a plurality of pixels PX (eg, Fig.13 The active pixel sensor array 20 may convert the optical signal into an electrical signal. The active pixel sensor array 20 may be driven by a plurality of driving signals (e.g., a pixel selection signal, a reset signal, and a charge transfer signal) provided from the row driver 40. The electrical signal converted from the active pixel sensor array 20 may be provided to the CDS 70.

[0029] The row driver 40 may provide a plurality of driving signals for driving a plurality of pixels to the active pixel sensor array 20 according to the result of decoding in the row decoder 30. When the pixels included in the active pixel sensor array 20 are arranged in a matrix, the driving signal may be provided to each row.

[0030] The timing generator 60 may provide a timing signal and a control signal to the row decoder 30 and the column decoder 50. According to an example embodiment, the timing generator 60 may provide a clock signal CLK to the charge pump circuit 10.

[0031] The CDS 70 may receive, hold, and sample an electrical signal generated in the active pixel sensor array 20. The CDS 70 may perform double sampling of a specific noise level and a signal level due to the electrical signal, thereby outputting a difference level corresponding to a difference between the noise level and the signal level.

[0032] The ADC 80 may convert an analog signal corresponding to the difference level output from the CDS 70 into a digital signal and output the digital signal. The input / output buffer 90 latches the digital signal and may sequentially output the digital signal according to the decoding result in the column decoder 50.

[0033] The charge pump circuit 10 may receive a clock signal CLK from the timing generator 60 to generate an output voltage VOUT and output the output voltage VOUT to the active pixel sensor array 20. The clock signal CLK may be a signal in which the low level voltage VL and the high level voltage VH each maintain a certain period of time and the low level voltage VL and the high level voltage VH appear periodically and alternately. That is, the clock signal CLK may switch between the low level voltage VL and the high level voltage VH at regular intervals or cycles. For example, in some example embodiments, the low level voltage VL may be a ground voltage, and the high level voltage VH may be a power supply voltage.

[0034] The output voltage VOUT may be a negative voltage and have a constant amplitude. In an example embodiment, the amplitude of the absolute value of the output voltage VOUT may be greater than the amplitude of the absolute value of the high-level voltage VH. For example, the amplitude of the output voltage VOUT may be equal to or greater than twice the amplitude of the high-level voltage VH. For example, the amplitude of the absolute value of the output voltage VOUT may be n times the amplitude of the absolute value of the high-level voltage VH, for example, n times the power supply voltage, where n may be a natural number equal to or greater than 2.

[0035] The charge pump circuit 10 may include first to n-th pump units 100_1 to 100_n. The first to n-th pump units 100_1 to 100_n may be connected in series to each other, and the first to n-th pump units 100_1 to 100_n may generate negative voltages with gradually increasing absolute values. For example, n may be a natural number equal to or greater than 2. In an example embodiment, n may be a natural number equal to or greater than 3.

[0036] The first pump unit 100_1 may output a first node voltage VN1 that has the same period as that of the clock signal CLK and may switch between a low level voltage lower than a low level voltage VL of the clock signal CLK and a high level voltage lower than a high level voltage VH of the clock signal CLK.

[0037] The nth pump unit 100_n may receive the (n-1)th node voltage VNn-1 and output an output voltage VOUT, which is a negative voltage having an absolute value greater than the absolute value of the low-level voltage of the (n-1)th node voltage VNn-1. In this case, the (n-1)th node voltage VNn-1 may be a voltage having a period that is the same as that of the clock signal CLK and that changes between a low-level voltage lower than the low-level voltage VL of the clock signal and a high-level voltage lower than the high-level voltage VH of the clock signal CLK. For example, the (n-1)th node voltage VNn-1 may periodically change between a negative voltage having an amplitude of (n-2) times the power supply voltage and a negative voltage having an amplitude of (n-1) times the power supply voltage.

[0038] In an example embodiment, the first pump unit 100_1 may include a capacitor and a transistor, and the nth pump unit 100_n may include a capacitor and a plurality of transistors. In an example embodiment, a well formed with transistors of the first pump unit 100_1 and a well formed with transistors of the nth pump unit 100_n may be electrically insulated from each other. In some example embodiments, different wells formed with transistors included in the nth pump unit 100_n may be electrically insulated from each other.

[0039] In order to reduce the dark current of the image sensor 1, the output voltage VOUT may be provided to the isolation layer of the active pixel sensor array 20. The charge pump circuit 10 may include a first pump unit 100_1 to an nth pump unit 100_n, and the first pump unit 100_1 to the nth pump unit 100_n may respectively generate negative voltages with gradually increasing absolute values. Therefore, the image sensor 1 may apply a high voltage to the isolation layer of the active pixel sensor array 20, and the dark current characteristics of the image sensor 1 may be improved. FIG. 14A to FIG. 14C In the description of FIG. 1 , an example embodiment of providing the output voltage VOUT to the isolation layer of the active pixel sensor array 20 will be described.

[0040] The output voltage VOUT may be provided to the gate of the transfer transistor of each of the plurality of pixels of the active pixel sensor array 20. The image sensor 1 may provide a high negative voltage to the gate of the transfer transistor to increase the potential of the gate of the transfer transistor and increase the full well capacity (FWC) of the photoelectric conversion element of each of the plurality of pixels. Optionally, the output voltage VOUT may be provided to the gate of the reset transistor of each of the plurality of pixels of the active pixel sensor array 20. The image sensor 1 may provide a high negative voltage to the gate of the reset transistor to increase the potential of the gate of the reset transistor and increase the FWC of the floating diffusion region of each of the plurality of pixels. Fig.15A and Fig. 15B In the description of FIG. 1 , an example embodiment of providing the output voltage VOUT to the pixel PX of the active pixel sensor array 20 will be described later.

[0041] Figure 3 is a circuit diagram for describing a charge pump circuit 10 according to an example embodiment. Figure 4 is a graph for describing the operation of the charge pump circuit 10 according to an example embodiment.

[0042] Reference Figure 3 , the charge pump circuit 10 may include an inverter INV and first to nth pump units 100_1 to 100_n. Here, n may be a natural number equal to or greater than 2. The first to nth pump units 100_1 to 100_n may each include a capacitor and a transistor configured to accumulate charge.

[0043] The inverter INV may invert the clock signal CLK to output an inverted clock signal CLKb. The ground voltage GND and the power supply voltage VDD may be applied to the inverter INV as operating voltages. Figure 3 The charge pump circuit 10 is shown to include the inverter INV, but in some example embodiments, the charge pump circuit 10 may omit the inverter INV. The clock signal CLK may be a signal that periodically changes between a ground voltage GND and a power supply voltage VDD.

[0044] The first pump unit 100_1 may include a first capacitor C1 and a first P-type transistor PT1. A first terminal of the first capacitor C1 may be connected to the inverter INV, and a second terminal of the first capacitor C1 may be connected to the first node N1.

[0045] The drain of the first P-type transistor PT1 may be connected to the first node N1, and the first source voltage VS1 may be applied to the source of the first P-type transistor PT1. For example, the first source voltage VS1 may be the ground voltage GND.

[0046] The first body voltage VB1 may be applied to the body of the first P-type transistor PT1. For example, the first body voltage VB1 may be a power supply voltage VDD. The switch signal SW11 may be provided as a control signal to the gate of the first P-type transistor PT1.

[0047] The nth pump unit 100_n may include an nth capacitor Cn, an nth P-type transistor PTn, and an N-type transistor NT. A first terminal of the nth capacitor Cn may be connected to the (n-1)th node Nn-1, and a second terminal of the nth capacitor Cn may be connected to the nth node Nn. For example, when n is 2, the first terminal of the nth capacitor Cn may be connected to the first node N1.

[0048] The drain of the nth P-type transistor PTn may be connected to the nth node Nn, and the nth source voltage VSn may be applied to the source of the nth P-type transistor PTn. For example, the nth source voltage VSn may be a negative voltage having a magnitude (n-1) times the absolute value of the power supply voltage VDD.

[0049] The nth body voltage VBn may be applied to the body of the nth P-type transistor PTn. For example, the nth body voltage VBn may be a negative voltage having an amplitude (n-2) times the absolute value of the power supply voltage VDD. The switch signal SWn1 may be provided as a control signal to the gate of the nth P-type transistor PTn.

[0050] The drain of the N-type transistor NT may be connected to the nth node Nn, and the body of the N-type transistor NT may be connected to the nth node Nn. A switching signal SWn2 may be provided to the gate of the N-type transistor NT as a control signal. The source of the N-type transistor NT may be connected to the output terminal OP and output an output voltage VOUT in response to the switching signal SWn2.

[0051] Reference Figure 3 and Figure 4, the clock inversion signal CLKb may be a signal that periodically changes between the power supply voltage VDD and the ground voltage GND. For example, the clock inversion signal CLKb may maintain the power supply voltage VDD from the reference time t0 to the first time t1, from the second time t2 to the third time t3, and from the fourth time t4 to the fifth time t5. The clock inversion signal CLKb may maintain the ground voltage GND from the first time t1 to the second time t2, and from the third time t3 to the fourth time t4.

[0052] Here, the first to fifth times t1, t2, t3, t4, and t5 may be times that arrive sequentially after the reference time t0. The difference between adjacent times in the time sequence may be constant, but example embodiments are not limited thereto. For example, the time difference between the reference time t0 and the first time t1 (wherein the clock inversion signal CLKb maintains the power supply voltage VDD) may be greater than or less than the time difference between the first time t1 and the second time t2 (wherein the clock inversion signal CLKb maintains the ground voltage GND). In other words, in some example embodiments, the duty cycle of the clock inversion signal CLKb may be different from Figure 4 The duty cycle is shown in .

[0053] According to an example embodiment, when the clock inversion signal CLKb is the power supply voltage VDD, the switch signal SW11 controlling the first P-type transistor PT1 may be a first negative voltage -VDD having the same magnitude as the power supply voltage VDD. The first P-type transistor PT1 may be turned on in response to the switch signal SW11, and the first node voltage VN1 of the first node N1 may be substantially the same as the ground voltage GND as the first source voltage VS1. Therefore, the potential difference between the first terminal and the second terminal of the first capacitor C1 may be substantially the same as the power supply voltage VDD.

[0054] According to an example embodiment, when the clock inversion signal CLKb is the ground voltage GND, the switch signal controlling the first P-type transistor PT1 may be the ground voltage GND. The first P-type transistor PT1 may be turned off in response to the switch signal SW11. As the voltages at the two terminals of the first capacitor C1 continuously change, the potential difference between the first terminal and the second terminal of the first capacitor C1 may maintain the power supply voltage VDD. Therefore, the first node voltage VN1 may be a first negative voltage -VDD having the same amplitude as the power supply voltage VDD.

[0055] Therefore, the first pump unit 100_1 may receive a clock inversion signal CLKb that periodically changes between the power supply voltage VDD and the ground voltage GND, and output a first node voltage VN1 that periodically changes between the ground voltage GND and the first negative voltage -VDD. For example, the first pump unit 100_1 to the n-th pump unit 100_n may each output a voltage that is lower than the received voltage by the magnitude of the power supply voltage VDD. The (n-1)th node voltage VNn-1 of the (n-1)th node Nn-1 may be a voltage that periodically changes between the (n-2)th negative voltage -(n-2)·VDD having an amplitude (n-2) times that of the power supply voltage VDD and the (n-1)th negative voltage -(n-1)·VDD having an amplitude (n-1) times that of the power supply voltage VDD. However, when n is 2, the (n-2)th negative voltage -(n-2)·VDD may not be a negative voltage but the ground voltage GND, and when n is equal to or greater than 3, the (n-2)th negative voltage -(n-2)·VDD may be a negative voltage.

[0056] According to an example embodiment, when the clock inversion signal CLKb is the power supply voltage VDD, the switch signal SWn1 controlling the nth P-type transistor PTn may be the nth negative voltage -n·VDD having an amplitude n times the power supply voltage VDD. The nth P-type transistor PTn may be turned on in response to the switch signal SWn1, and the nth node voltage VNn of the nth node Nn may be substantially the same as the (n-1)th negative voltage -(n-1)·VDD as the nth source voltage VSn. Therefore, the potential difference between the first terminal and the second terminal of the nth capacitor Cn may be substantially the same as the power supply voltage VDD.

[0057] The switch signal SWn2 controlling the N-type transistor NT may be substantially the same as the switch signal SWn1 controlling the nth P-type transistor PTn. Therefore, when the clock inversion signal CLKb is the power supply voltage VDD, the switch signal SWn2 controlling the N-type transistor NT may be the nth negative voltage -n·VDD, and the N-type transistor NT may be turned off. The nth node Nn and the output terminal OP may not be connected to each other.

[0058] According to an example embodiment, when the clock inversion signal CLKb is Figure 4 When the ground voltage in the nth node VNn is 0, the switch signal SWn1 controlling the nth P-type transistor PTn may be the (n-1)th negative voltage -(n-1)·VDD having an amplitude (n-1) times the power supply voltage VDD. The nth P-type transistor PTn may be turned off in response to the switch signal SWn1. As the voltage at the two terminals of the nth capacitor Cn continuously changes, the potential difference between the first terminal and the second terminal of the nth capacitor Cn may maintain the power supply voltage VDD. Therefore, the nth node voltage VNn may be the nth negative voltage -n·VDD.

[0059] When the clock inversion signal CLKb is Figure 4 When the ground voltage in the n-type transistor NT is turned on, the switch signal SWn2 controlling the N-type transistor NT may be the (n-1)th negative voltage -(n-1)·VDD. The N-type transistor NT may be turned on, and the n-th node voltage VNn may be output as the output voltage VOUT from the output terminal OP of the n-th pump unit 100_n. When the N-type transistor NT is turned off, the capacitor may be connected to the output terminal OP, and the output voltage may be the n-th negative voltage -n·VDD.

[0060] Figure 3 The configuration of the charge pump circuit 10 shown in FIG. 1 is merely an example, and example embodiments are not limited thereto. The charge pump circuit 10 configured to accumulate charge to output a negative voltage may be implemented differently. Figure 3 Only the circuits for generating the output voltage VOUT by using the clock inversion signal CLKb from the first pump unit 100_1 to the nth pump unit 100_n are described, but example embodiments are not limited to the described circuits. For example, in some example embodiments, the charge pump circuit 10 may further include a complementary circuit connected to the output terminal OP and generating an output voltage of the nth negative voltage -n·VDD by using a re-inversion signal of the clock inversion signal CLKb when the clock inversion signal CLKb is the power supply voltage VDD. This will be referred to later. Figure 7 etc. describe complementary circuits according to example embodiments.

[0061] The charge pump circuit 10 is configured such that the first to n-th pump units 100_1 to 100_n are electrically insulated from each other, and thus the number of pump units included in the charge pump circuit 10 can be increased. Therefore, the magnitude of the output voltage VOUT increases in proportion to the number of pump units, and thus the charge pump circuit 10 can generate a high negative voltage.

[0062] Figure 5 is a cross-sectional view for describing a charge pump circuit 10 according to an example embodiment. Figure 5 yes Figure 3 In the diagram of the charge pump circuit 10 shown in FIG. 1 , only the inverter INV is excluded for simplicity.

[0063] Reference Figure 5 , the charge pump circuit 10 may include a substrate SUB, an epitaxial layer P-EPI formed in the substrate SUB, and wells NW1, NW2, and PW formed in the epitaxial layer P-EPI. Note that, Figure 5The lines between the substrate SUB, the epitaxial layer P-EPI, and the wells NW1, NW2, and PW shown in the figure are for the convenience of description and explanation. The wells NW1, NW2, and PW may include an N well doped with N-type impurities and a P well doped with P-type impurities. For example, the first well NW1 and the second well NW2 may be an N well doped with N-type impurities, and the third well PW may be a P well doped with P-type impurities.

[0064] According to an example embodiment, the substrate SUB may be any one of a bulk silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, or a silicon germanium substrate, but example embodiments are not limited thereto. According to an example embodiment, the substrate SUB may include at least one of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium-arsenic (GaAs), indium-gallium-arsenic (InGaAs), aluminum-gallium-arsenic (AlGaAs), or a combination thereof. In this specification, the phrase "at least one of A or B" includes "only A", "only B", and "both A and B".

[0065] According to one example embodiment, the substrate SUB may be a doped semiconductor layer. According to one example embodiment, the substrate SUB may be doped with P type impurities, but example embodiments are not limited thereto.

[0066] The substrate SUB may include a first surface 100f and a second surface 100b facing each other. The first surface 100f of the substrate SUB may be a front surface of the substrate SUB, and the second surface 100b of the substrate SUB may be a rear surface of the substrate SUB.

[0067] According to an example embodiment, the epitaxial layer P-EPI may be a semiconductor material layer formed due to selective epitaxial growth. According to an example embodiment, the epitaxial layer P-EPI may be doped with P-type impurities and doped at a concentration higher than that of the substrate SUB, but example embodiments are not limited thereto. In some example embodiments, the epitaxial layer P-EPI may be omitted. Therefore, the wells NW1, NW2, and PW may be formed in the substrate SUB, and the substrate SUB may be doped with high-concentration P-type impurities.

[0068] The first P-type transistor PT1 may be formed in the first well NW1. The first P-type region 103, the second P-type region 105, and the N-type region 101 formed in the first well NW1, and the gate insulating layer 107 and the gate electrode 109 formed above the first well NW1 may constitute the first P-type transistor PT1. The gate insulating layer 107 may be formed between the first well NW1 and the gate electrode 109.

[0069] The first P-type region 103 and the second P-type region 105 formed in the first well NW1 may constitute different electrodes of the first P-type transistor PT1 and may be a source and a drain, respectively. Figure 5 As shown in the example of , the first source voltage VS1 may be applied to the first P-type region 103 , and the second P-type region 105 may be connected to the first node N1 and receive the first node voltage VN1 . The switching signal SW11 may be applied to the gate electrode 109 .

[0070] The N-type region 101 formed in the first well NW1 may be a contact region for applying a voltage to the body of the first P-type transistor PT1 . For example, the first body voltage VB1 may be applied to the first well NW1 through the N-type region 101 .

[0071] The nth P-type transistor PTn may be formed in the second well NW2. The first P-type region 103n, the second P-type region 105n, and the N-type region 101n formed in the second well NW2, and the gate insulating layer 107n and the gate electrode 109n formed above the second well NW2 may constitute the nth P-type transistor PTn. The gate insulating layer 107n may be formed between the second well NW2 and the gate electrode 109n.

[0072] The first P-type region 103n and the second P-type region 105n formed in the second well NW2 may constitute different electrodes of the nth P-type transistor and may be a source and a drain, respectively. Figure 5 As shown in the example of , the nth source voltage VSn may be applied to the first P-type region 103n, and the second P-type region 105n may be connected to the nth node Nn and receive the nth node voltage VNn. The switching signal SWn1 may be applied to the gate electrode 109n.

[0073] The N-type region 101n formed in the second well NW2 may be a contact region for applying a voltage to the body of the nth P-type transistor PTn. For example, the nth body voltage VBn may be applied to the second well NW2 through the N-type region 101n.

[0074] The N-type transistor NT may be formed in the third well PW. The first N-type region 113n, the second N-type region 115n, and the P-type region 111n formed in the third well, and the gate insulating layer 117n and the gate electrode 119n formed over the third well PW may constitute the N-type transistor NT. The gate insulating layer 117n may be formed between the third well PW and the gate electrode 119n.

[0075] The first N-type region 113n and the second N-type region 115n formed in the third well PW may constitute different electrodes of the N-type transistor NT and may be a source and a drain, respectively. The first N-type region 113n may be connected to the nth node Nn, and the nth node voltage VNn may be applied to the first N-type region 113n. The second N-type region 115n may be connected to the output terminal OP. The switching signal SWn2 may be applied to the gate electrode 119n.

[0076] The P-type region 111n formed in the third well PW may be a contact region for applying a voltage to the body of the N-type transistor NT. For example, the third well PW may be connected to the nth node Nn through the P-type region 111n and the nth node voltage VNn may be applied to the third well PW.

[0077] According to an example embodiment, the P-type regions (i.e., first P-type region 103, second P-type region 105, first P-type region 103n, second P-type region 105n, and P-type region 111n) may be regions doped at a high concentration using P-type impurities, and the N-type regions (i.e., N-type region 101, N-type region 101n, first N-type region 113n, and second N-type region 115n) may be regions doped at a high concentration using N-type impurities.

[0078] According to an example embodiment, the first to n-th capacitors C1 to Cn may be formed at the same level as a line layer formed by a backend of line (BEOL) process and / or a front end of line (FEOL) process. According to an example embodiment, the first to n-th capacitors C1 to Cn may be formed by a BEOL process and / or a FEOL process.

[0079] The isolation layer 120 may be formed between the first well NW1, the second well NW2, and the third well PW to which different voltages are applied, respectively. In other words, the isolation layer 120 is formed between the first well NW1 and the second well NW2, and between the second well NW2 and the third well PW. The isolation layer 120 may be formed to surround each of the first well NW1, the second well NW2, and the third well PW. In an example embodiment, the isolation layer 120 may include an insulating material. However, the isolation layer 120 may include silicon oxide, but example embodiments are not limited thereto, and various modifications may be made to the insulating material constituting the isolation layer 120.

[0080] In an example embodiment, the isolation layer 120 may extend from the first surface 100f of the substrate SUB to the second surface 100b of the substrate SUB. In an example embodiment, the width of the cross-section of the isolation layer 120 may decrease away from the first surface 100f of the substrate SUB and toward the second surface 100b of the substrate SUB. In other words, the width of the cross-section of the isolation layer 120 may decrease as the distance from the first surface 100f of the substrate SUB increases. For example, in the isolation layer 120, the first width FW of the surface contacting the first surface 100f may be greater than the second width BW of the surface contacting the second surface 100b. In an example embodiment, the isolation layer 120 may be formed by etching a portion of the substrate SUB in a vertical direction from the first surface 100f of the substrate SUB and filling an insulating material in the etched portion. (It should be noted that the break in the isolation layer 120 between the first well NW1 and the second well NW2 is intended to illustrate that there may be more than two charge pump units (i.e., n may be greater than 2 as described above), so for convenience, the break corresponding to Figure 5 The CLKb line is shown at the top of the .

[0081] In the charge pump circuit according to various example embodiments, a plurality of transistors in which different voltages are respectively applied to the bodies are respectively formed in different wells, and the different wells can be isolated from each other by using an isolation layer 120. The isolation layer 120 can prevent junction breakdown that may occur due to the difference between the voltages respectively applied to the different wells. For example, the junction breakdown between the second well NW2 and the third well PW that may occur due to the difference between the nth body voltage VBn and the nth node voltage VNn respectively applied to the second well NW2 and the third well PW can be prevented. Therefore, the number of pump cells included in the charge pump circuit and connected in series with each other can be increased, and the charge pump circuit can generate a high negative voltage.

[0082] FIG. 6A to FIG. 6C is a cross-sectional view for describing a charge pump circuit 10 according to an example embodiment. FIG. 6A to FIG. 6C yes Figure 3 The charge pump circuit 10 shown in FIG. 1 excludes only the inverter INV. FIG. 6A to FIG. 6C In the description of Figure 5 The same reference numerals as those in the description are used herein.

[0083] Reference Fig. 6A , the isolation layer 120B may be formed between the first well NW1, the second well NW2, and the third well PW. The isolation layer 120B may be formed to surround each of the first well NW1, the second well NW2, and the third well PW. In an example embodiment, the isolation layer 120B may include an insulating material.

[0084] In an example embodiment, the width of the cross section of the isolation layer 120B may increase away from the first surface 100f of the substrate SUB and toward the second surface 100b of the substrate SUB. In other words, the width of the cross section of the isolation layer 120B may increase as the distance from the first surface 100f of the substrate SUB increases. For example, in the isolation layer 120B, the first width FWB of the surface contacting the first surface 100f may be smaller than the second width BWB of the surface contacting the second surface 100b. In an example embodiment, the isolation layer 120B may be formed by etching a portion of the substrate SUB in a vertical direction from the second surface 100b of the substrate SUB and filling an insulating material in the etched portion.

[0085] Reference Figure 6B , the isolation layer 120R may be formed between the first well NW1, the second well NW2, and the third well PW. The isolation layer 120R may be formed to surround the first well NW1, the second well NW2, and the third well PW. In an example embodiment, the isolation layer 120R may include an insulating layer.

[0086] In an example embodiment, the width of the cross section of the isolation layer 120R may decrease from the first surface 100f toward the center of the substrate SUB, and may decrease from the second surface 100b of the substrate SUB toward the center of the substrate SUB. In other words, the width of the cross section of the isolation layer 120R may decrease as the distance from the first surface 100f of the substrate SUB increases, and may decrease as the distance from the second surface 100b of the substrate SUB increases. For example, in the isolation layer 120R, the first width FWF of the surface contacting the first surface 100f may be greater than the third width MW of the cross section of the center of the isolation layer 120R, and the second width BWF of the surface contacting the second surface 100b may be greater than the third width MW. In an example embodiment, the isolation layer 120R may be formed by etching a portion of the substrate SUB in a vertical direction from the first surface 100f of the substrate, etching another portion of the substrate SUB in a vertical direction from the second surface 100b of the substrate SUB, and then filling an insulating material in the etched portion. Alternatively, in another example embodiment, the isolation layer 120R may be formed by etching a portion of the substrate SUB along a vertical direction from the second surface 100b of the substrate SUB, etching another portion of the substrate SUB along a vertical direction from the first surface 100f of the substrate SUB, and filling an insulating material in the etched portion.

[0087] Reference Figure 6C , the substrate N_SUB may be doped with N-type impurities. In some example embodiments, the epitaxial layer P-EPI may be omitted. Thus, the first and second wells NW1 and NW2 and the third well PW may be formed in the substrate N_SUB.

[0088] Figure 7is a circuit diagram for describing a charge pump circuit according to example embodiments. Figure 8 is used to describe the Figure 7 The operation of the charge pump circuit is shown in Figure 2. Figure 7 and Figure 8 In the description of Figure 3 and Figure 4 The descriptions are repeated with the same reference numerals as those in the drawings.

[0089] Reference Figure 7 The nth pump unit 100_n' of the charge pump circuit 10 may include an nth capacitor Cn, an nth P-type transistor PTn and an N-type transistor NT', and may further include a capacitor Cnb, a first transistor PTnb as a P-type transistor, and a second transistor NTb, a third transistor NTnab and a fourth transistor NTna as N-type transistors.

[0090] The drain of the N-type transistor NT' may be connected to the nth node Nn, and the body of the N-type transistor NT' may be connected to the nth node Nn through the fourth transistor NTna. For example, the body of the N-type transistor NT' may be connected to the second body node NB2n; the first electrode of the fourth transistor NTna may be connected to the nth node Nn; and the second electrode of the fourth transistor NTna may be connected to the second body node NB2n. The switching signal SWn2 input to the gate of the N-type transistor NT' may be provided as a control signal to the gate of the fourth transistor NTna, and the fourth transistor NTna may electrically connect the nth node Nn to the second body node NB2n in response to the switching signal SWn2.

[0091] and Figure 3 Compared with the nth pump unit 100_n shown in FIG. Figure 7 The n-th pump unit 100_n′ shown in FIG. 1 may further include a complementary circuit. The complementary circuit may include a capacitor Cnb, a first transistor PTnb, a second transistor NTb, and a third transistor NTnab.

[0092] The complementary voltage VNn-1b of the (n-1)th node voltage VNn-1 may be input to one end of the capacitor Cnb of the complementary circuit. The other end of the capacitor Cnb of the complementary circuit may be connected to the subnode Nnb. In an example embodiment, the gate of the N-type transistor NT' and the gate of the fourth transistor NTna may be connected to the subnode Nnb. Therefore, the switch signal SWn2 applied to the gate of the N-type transistor NT' may be the subnode voltage VNnb of the subnode Nnb.

[0093] The drain of the first transistor PTnb of the complementary circuit may be connected to the subnode Nnb, and the nth source voltage VSn may be applied to the source of the first transistor PTnb of the complementary circuit. For example, the nth source voltage VSn may be a negative voltage having an amplitude (n-1) times the absolute value of the power supply voltage VDD.

[0094] The nth body voltage VBn may be applied to the body of the first transistor PTnb of the complementary circuit. For example, the nth body voltage VBn may be a negative voltage having an amplitude of (n-2) times the absolute value of the power supply voltage VDD. In other words, the same voltage may be applied to the body of the first transistor PTnb of the complementary circuit and the body of the nth P-type transistor PTn, and in an example embodiment, the body of the first transistor PTnb of the complementary circuit and the body of the nth P-type transistor PTn may be connected to the first body node NB1n.

[0095] The switching signal SWn1b may be provided as a control signal to the gate of the first transistor PTnb of the complementary circuit. The switching signal SWn1b applied to the gate of the first transistor PTnb of the complementary circuit and the switching signal SWn1 input to the gate of the nth P-type transistor PTn may be complementary.

[0096] The source of the second transistor NTb of the complementary circuit can be connected to the output terminal OP and output the output voltage VOUT in response to the switch signal SWn2b. The gate of the second transistor NTb can be connected to the nth node Nn, and the switch signal SWn2b input to the gate of the second transistor NTb can be the nth node voltage VNn.

[0097] A drain of the second transistor NTb may be connected to the sub-node Nnb, and a body of the second transistor NTb may be connected to the sub-node Nnb through the third transistor NTnab.

[0098] For example, the body of the third transistor NTnab may be connected to the second body node NB2n; the first electrode of the third transistor NTnab may be connected to the subnode Nnb; and the second electrode of the third transistor NTnab may be connected to the second body node NB2n. A switching signal SWn2b may be provided as a control signal to the gate of the third transistor NTnab, and in response to the switching signal SWn2b, the subnode Nnb and the second body node NB2n may be electrically connected to each other.

[0099] Reference Figure 7 and Figure 8, the complementary voltage VNn-1b of the (n-1)th node voltage VNn-1 can be a voltage that periodically changes between the (n-2)th voltage -(n-2)·VDD having an amplitude of (n-2) times the power supply voltage VDD and the (n-1)th voltage -(n-1)·VDD having an amplitude of (n-1) times the power supply voltage VDD.

[0100] The switching signal SWn1b input to the gate of the first transistor PTnb of the complementary circuit and the switching signal SWn2b input to the gate of the second transistor NTb may be the same as the nth node voltage VNn. The switching signals SWn1b and SWn2b may be complementary to the switching signal SWn2 controlling the N-type transistor NT' and the switching signal SWn1 controlling the nth P-type transistor PTn.

[0101] The subnode voltage VNnb of the subnode Nnb may be the same as the switch signal SWn2 controlling the N-type transistor NT' and the switch signal SWn1 controlling the nth P-type transistor PTn. The capacitor Cnb of the complementary circuit receives the complementary voltage VNn-1b of the (n-1)th node voltage VNn-1, and the first transistor PTnb of the complementary circuit is controlled by the switch signal SWn1b complementary to the switch signal SWn1 of the nth P-type transistor PTn, and therefore, the subnode voltage VNnb of the subnode Nnb may be complementary to the nth node voltage VNn.

[0102] According to an example embodiment, when the clock inversion signal CLKb is Figure 8 When the power supply voltage VDD is in the nth node, the switching signal SWn2b input to the gate of the second transistor NTb may be the (n-1)th negative voltage -(n-1)·VDD, and the second transistor NTb may be turned on. The nth node Nn and the output terminal OP are connected to each other, and the sub-node voltage VNnb may be output as the output voltage VOUT from the output terminal OP of the nth pump unit 100_n'.

[0103] On the contrary, when the clock inversion signal CLKb is Figure 8 When the clock inversion signal CLKb is the ground voltage GND or the power supply voltage VDD, the switch signal SWn2 controlling the N-type transistor NT' may be the (n-1)th negative voltage -(n-1)·VDD. The N-type transistor NT' may be turned on, and the n-th node voltage VNn may be output as the output voltage VOUT from the output terminal OP of the n-th pump unit 100_n'. Therefore, when the clock inversion signal CLKb is the ground voltage GND or the power supply voltage VDD, the output voltage VOUT output from the output terminal OP may be constantly and stably maintained at an amplitude n times that of the power supply voltage VDD.

[0104] Fig. 9 is used to describe the Figure 7 A cross-sectional diagram of a charge pump circuit. Fig. 9 Shows Figure 7 The nth pump unit shown in .

[0105] Reference Fig. 9 The charge pump circuit may include a substrate SUB, an epitaxial layer P-EPI formed in the substrate SUB, and wells NW and PW formed in the epitaxial layer P-EPI. The wells NW and PW may include an N well NW doped with N-type impurities and a P well PW doped with P-type impurities.

[0106] The nth P-type transistor PTn and the first transistor PTnb of the complementary circuit may be formed in the N-well NW. The first P-type region 103n, the second P-type region 105n, and the N-type region 101n formed in the N-well NW, and the first gate insulating layer 107n and the first gate electrode 109n formed above the N-well NW may constitute the nth P-type transistor PTn. The third P-type region 103nb, the fourth P-type region 105nb, and the N-type region 101n formed in the N-well NW, and the second gate insulating layer 107nb and the second gate electrode 109nb formed above the N-well NW may constitute the first transistor PTnb of the complementary circuit.

[0107] The first P-type region 103n and the second P-type region 105n formed in the N-well NW may constitute different electrodes of the nth P-type transistor PTn, and may be the source and the drain, respectively. The third P-type region 103nb and the fourth P-type region 105nb formed in the N-well NW may constitute different electrodes of the first transistor PTnb of the complementary circuit, and may be the source and the drain, respectively.

[0108] The N-type region 101n formed in the N-well NW may be a contact region for applying a voltage to the body of the nth P-type transistor PTn and the body of the first transistor PTnb of the complementary circuit. For example, the nth body voltage VBn may be applied to the N-well NW through the N-type region 101n.

[0109] N-type transistors NT', NTb, NTna, and NTnab may be formed in the P-well PW. The first N-type region 113n, the second N-type region 115n, and the P-type region 111n formed in the P-well PW, and the first gate insulating layer 117n and the first gate electrode 119n formed above the P-well PW may constitute the N-type transistor NT'. The first N-type region 113n and the second N-type region 115n formed in the P-well PW may constitute different electrodes of the N-type transistor NT', and may be a source and a drain, respectively.

[0110] The third N-type region 113nb, the fourth N-type region 115nb, and the P-type region 111n formed in the P-well PW, and the second gate insulating layer 117nb and the second gate electrode 119nb formed above the P-well PW may constitute a second transistor NTb of a complementary circuit. The third N-type region 113nb and the fourth N-type region 115nb formed in the P-well PW may constitute different electrodes of the second transistor NTb, and may be a source and a drain, respectively.

[0111] The fifth N-type region 123nb, the sixth N-type region 125nb, the P-type region 111n formed in the P-well PW, and the third gate insulating layer 127nb and the third gate electrode 129nb formed above the P-well PW may constitute a third transistor NTnab of a complementary circuit. The fifth N-type region 123nb and the sixth N-type region 125nb formed in the P-well PW may constitute different electrodes of the third transistor NTnab, and may be a source and a drain, respectively.

[0112] The seventh N-type region 123n, the eighth N-type region 125n, and the P-type region 111n formed in the P-well PW, and the fourth gate insulating layer 127n and the fourth gate electrode 129n formed above the P-well PW may constitute a fourth transistor NTna. The seventh N-type region 123n and the eighth N-type region 125n formed in the P-well PW may constitute different electrodes of the fourth transistor NTna, and the electrodes may be a source and a drain, respectively.

[0113] Fig. 9 The charge pump circuit of the example embodiment shown in FIG. 1 may include wells NW and PW formed in a substrate SUB and formed with a plurality of transistors. In this case, an isolation layer 120 may be formed to surround the wells NW and PW to which different voltages are applied, respectively. Therefore, due to the isolation layer 120, junction breakdown that may occur due to a difference between voltages applied to different wells NW and PW, respectively, may be prevented, and the number of pump cells included in the charge pump circuit and connected in series with each other may be increased.

[0114] Fig.10 is a block diagram for describing a charge pump circuit 10A according to an example embodiment. Fig.11 is used to describe the Fig.10 A circuit diagram of a charge pump circuit 10A is shown in FIG. Fig.10 and Fig.11 In the description of Figure 2 and Figure 3 Descriptions of the same reference numerals are repeated.

[0115] Reference Fig.10 and Fig.11The charge pump circuit 10A may receive the clock signal CLK to generate first to nth output voltages VOUT_1 to VOUT_n, and output the first to nth output voltages VOUT_1 to VOUT_n to an active pixel sensor array (eg, Figure 1 In this case, n may be a natural number equal to or greater than 2, and in an example embodiment, n may be a natural number equal to or greater than 3.

[0116] The charge pump circuit 10A may include an inverter INV and first to n-th pump units 100_1A and 100_nA. The first to n-th pump units 100_1A and 100_nA may be connected in series to each other, and the first to n-th pump units 100_1A and 100_nA may output corresponding output voltages, respectively. For example, the first pump unit 100_1A may output a first output voltage V_OUT1 from a first output terminal OP1, and the n-th pump unit 100_nA may output an n-th output voltage VOUT_n from an n-th output terminal OPn. The first to n-th pump units 100_1A and 100_nA may output negative voltages, respectively, and the absolute values ​​of the negative voltages increase sequentially and gradually.

[0117] In an example embodiment, the magnitude of the absolute value of the nth output voltage VOUT_n may be greater than the magnitude of the absolute value of the high level voltage VH. For example, the magnitude of the nth output voltage VOUT_n may be n times the magnitude of the absolute value of the high level voltage VH.

[0118] The first to nth pumping units 100_1A to 100_nA may each include a capacitor for accumulating charges, a P-type transistor, and an N-type transistor. However, example embodiments are not limited thereto, and at least one of the first to nth pumping units 100_1A to 100_nA may omit one of the N-type transistor or the P-type transistor.

[0119] The first pump unit 100_1A may include a first capacitor C1, a first P-type transistor PT1, and a first N-type transistor NT1. The drain of the first N-type transistor NT1 may be connected to the first node N1, and the body of the first N-type transistor NT1 may be connected to the first node N1. The switching signal SW12 may be provided to the gate of the first N-type transistor NT1 as a control signal. The source of the first N-type transistor NT1 may be connected to the first output terminal OP1 and output the first output voltage VOUT_1 in response to the switching signal SW12.

[0120] The nth pump unit 100_nA may include an nth capacitor Cn, an nth P-type transistor PTn, and an nth N-type transistor NTn. The drain of the nth N-type transistor NTn may be connected to the nth node Nn, and the body of the nth N-type transistor NTn may be connected to the nth node Nn. The switch signal SWn2 may be provided as a control signal to the gate of the nth N-type transistor NTn. The source of the nth N-type transistor NTn may be connected to the nth output terminal OPn and output the nth output voltage VOUT_n in response to the switch signal SWn2.

[0121] Fig. 12A and Fig. 12B is used to describe the Fig.11 10A is a cross-sectional view of a charge pump circuit 10A. Fig. 12A and Fig. 12B yes Fig.11 The charge pump circuit 10A shown in FIG. 1 excludes only the inverter INV. Fig. 12A and Fig. 12B In the description of Figure 5 The descriptions are repeated with the same reference numerals as those in the drawings.

[0122] Reference Fig. 12A , the charge pump circuit may include a substrate SUB, an epitaxial layer P-EPI formed in the substrate SUB, and wells NW1, PW1, NW2, and PW2 formed in the epitaxial layer P-EPI. The wells NW1, PW1, NW2, and PW2 may include a first well NW1 and a second well NW2 doped with N-type impurities, and a third well PW1 and a fourth well PW2 doped with P-type impurities.

[0123] The first N-type transistor NT1 may be formed in the third well PW1. The first N-type region 113, the second N-type region 115, the P-type region 111 formed in the third well PW1, and the gate insulating layer 117 and the gate electrode 119 formed above the third well PW1 may constitute the first N-type transistor NT1. The gate insulating layer 117 may be formed between the third well PW1 and the gate electrode 119.

[0124] The first N-type region 113 and the second N-type region 115 formed in the third well PW1 may constitute different electrodes of the first N-type transistor NT1, respectively, and may be a source and a drain, respectively. The first N-type region 113 may be connected to the first node N1, and the first node voltage VN1 may be applied to the first N-type region 113. The second N-type region 115 may be connected to the first output terminal OP1. The switching signal SW12 may be applied to the gate electrode 119.

[0125] The P-type region 111 formed in the third well PW1 may be a contact region for applying a voltage to the body of the first N-type transistor NT1. For example, the third well PW1 may be connected to the first node N1 through the P-type region 111, and the first node voltage VN1 may be applied to the third well PW1.

[0126] The nth N-type transistor NTn may be formed in the fourth well PW2. The first N-type region 113n, the second N-type region 115n, the P-type region 111n formed in the fourth well PW2, and the gate insulating layer 117n and the gate electrode 119n formed over the fourth well PW2 may constitute the nth N-type transistor NTn. The gate insulating layer 117n may be formed between the fourth well PW2 and the gate electrode 119n.

[0127] The first N-type region 113n and the second N-type region 115n formed in the fourth well PW2 may constitute different electrodes of the nth N-type transistor NTn, respectively, and may be a source and a drain, respectively. The first N-type region 113n may be connected to the nth node Nn, and the nth node voltage VNn may be applied to the first N-type region 113n. The second N-type region 115n may be connected to the nth output terminal OPn. The switching signal SWn2 may be applied to the gate electrode 119n.

[0128] The P-type region 111n formed in the fourth well PW2 may be a contact region for applying a voltage to the body of the nth N-type transistor NTn. For example, the fourth well PW2 may be connected to the nth node Nn through the P-type region 111n, and the nth node voltage VNn may be applied to the fourth well PW2.

[0129] The isolation layer 120 may be formed between the first well NW1, the third well PW1, the second well NW2, and the fourth well PW2 to which respectively different voltages are applied. The isolation layer 120 may be formed to surround each of the first well NW1, the second well NW2, the third well PW1, and the fourth well PW2.

[0130] Reference Fig. 12B , a third well PW1' formed with a first N-type transistor NT1 included in the first pump cell may be formed in a first well NW1' formed with a first P-type transistor PT1 included in the first pump cell. A voltage having a relatively small amplitude may be applied to the first pump cell of the charge pump circuit compared to the nth pump cell. Therefore, the first pump cell has a relatively small possibility of occurrence of junction breakdown compared to the nth pump cell. Therefore, the area occupied by the charge pump circuit may be reduced by forming the third well PW1' in the first well NW1' without forming an isolation layer 120' between the first well NW1' and the third well PW1'.

[0131] However, example embodiments are not limited to Fig. 12B, and in some example embodiments, it is also feasible that the first well NW1' may be formed in the third well PW1'. In addition, when n is equal to or greater than 3, the N well formed with the second P-type transistor included in the second pump unit and the P well formed with the second N-type transistor may not be insulated by using the isolation layer 120'. That is, in some example embodiments, the P well may be formed in the N well formed with the second pump unit.

[0132] Fig.13 is a top view for describing an active pixel sensor array of an image sensor according to example embodiments. FIG. 14A to FIG. 14C is along Fig.13 A cross-sectional view taken along line XX' is shown in FIG.

[0133] Reference Fig.13 and Fig.14A , the active pixel sensor array 20 may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix. The isolation layer DTI may surround each of the plurality of pixels PX and separate the plurality of pixels PX from each other. That is, the plurality of pixels PX may each be defined by the isolation layer DTI.

[0134] In an example embodiment, the isolation layer DTI may include a first isolation layer 220_1 and a second isolation layer 220_2. The first isolation layer 220_1 may include a material having excellent gap fill performance, for example, polysilicon. According to an example embodiment, the first isolation layer 220_1 may be doped with a P-type impurity such as boron (B), but example embodiments are not limited thereto. According to an example embodiment, the first isolation layer 220_1 may have the same length in a vertical direction to separate the plurality of pixels PX from each other.

[0135] The second isolation layer 220_2 may include an insulating material. According to one example embodiment, the second isolation layer 220_2 may include a material having a high dielectric constant, but example embodiments are not limited thereto.

[0136] In an example embodiment, the width of the isolation layer DTI may decrease away from the first surface 200f and toward the second surface 200b. In other words, the width of the isolation layer DTI may decrease as the distance from the first surface 200f increases. For example, in the isolation layer DTI, the first width of the surface contacting the first surface 200f may be greater than the second width of the surface contacting the second surface 200b. In an example embodiment, the isolation layer DTI may be formed by etching a portion of the photodiode region PDR from the first surface 200f in a vertical direction, and the etched portion may be filled with a material included in the second isolation layer 220_2 and a material included in the first isolation layer 220_1.

[0137] According to an example embodiment, the output voltage (eg, Figure 1 The output voltage VOUT) can be applied to the first isolation layer 220_1 through the contact via 223. The output voltage VOUT applied to the first isolation layer 220_1 can be, for example, a reference voltage VOUT. Figures 2 to 9 describes the output voltage VOUT and can be referenced Fig.10 and Fig.11 One of the first output voltage VOUT_1 to the nth output voltage VOUT_n described. Fig.14A The contact via 223 configured to apply the output voltage VOUT is shown to be arranged adjacent to the first surface 200f, but example embodiments are not limited thereto. For example, the contact via 223 may be arranged adjacent to the second surface 200b, or adjacent to the first surface 200f and the second surface 200b.

[0138] A photodiode may be formed in the photodiode region PDR. According to an example embodiment, a voltage lower than that of the photodiode region PDR may be applied to the first isolation layer 220_1 to reduce dark current by increasing an energy barrier between the first isolation layer 220_1 and the photodiode region PDR. Therefore, the reliability of the image sensor may be improved.

[0139] The interlayer insulating layer 211 and the front surface line 213 may be disposed over and on the first surface 200f. The front surface line 213 may be covered, protected, and insulated by the interlayer insulating layer 211.

[0140] The interlayer insulating layer 211 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, etc. The front surface line 213 may include, for example, aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), etc.

[0141] The front surface line 213 may include a plurality of lines stacked sequentially. Fig.14A It is illustrated that the front surface line 213 includes three layers sequentially stacked, but example embodiments are not limited thereto.

[0142] The insulating layer 221 may be disposed between the first surface 200f and the interlayer insulating layer 211. The insulating layer 221 may cover the contact via 223 and protect the contact via 223. According to an example embodiment, the insulating layer 221 may include an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0143] The color filter CF may be disposed on the photodiode region PDR, and the microlens ML may be disposed on the color filter CF. The microlens ML may include an organic material such as a photosensitive resin or an inorganic material. The microlens ML may collect incident light to the pixel PX.

[0144] Reference Fig. 14B, the isolation layer DTI' may include a first isolation layer 220_1' and a second isolation layer 220_2'. According to an example embodiment, the width of the cross section of the isolation layer DTI' may increase away from the first surface 200f and toward the second surface 200b. In other words, the width of the cross section of the isolation layer DTI' may increase as the distance from the first surface 200f increases. For example, in the isolation layer DTI', the first width of the surface contacting the first surface 200f may be smaller than the second width of the surface contacting the second surface 200b. According to an example embodiment, the isolation layer DTI' may be formed by etching a portion of the photodiode region PDR from the second surface 200b in a vertical direction and filling the etched portion with a material.

[0145] However, with Fig. 14B Unlike shown in FIG. 2 , in some example embodiments, the isolation layer DTI′ may not contact the first surface 200f. In this case, the contact via 223 may be formed to contact the second surface 200b and provide the output voltage VOUT to the isolation layer DTI′.

[0146] Reference Fig. 14C , the isolation layer DTI" may include a first isolation layer 220_1" and a second isolation layer 220_2". According to an example embodiment, the width of the cross-section of the isolation layer DTI" may decrease from the first surface 200f toward the center, and may decrease from the second surface 200b toward the center. In other words, the width of the cross-section of the isolation layer DTI" may decrease as the distance from the first surface 200f increases, and may decrease as the distance from the second surface 200b increases. For example, in the isolation layer DTI", the first width of the surface contacting the first surface 200f may be greater than the third width of the cross-section of the center of the isolation layer DTI", and the second width of the surface contacting the second surface 200b may be greater than the third width. In an example embodiment, the isolation layer DTI" may be formed by etching a portion of the photodiode region PDR from the first surface 200f in a vertical direction, etching another portion of the photodiode region PDR from the second surface 200b in a vertical direction, and filling the etched portion with a material. Alternatively, in some example embodiments, the isolation layer DTI" may also be formed by etching a portion of the photodiode region PDR from the second surface 200b along a vertical direction, etching another portion of the photodiode region PDR from the first surface 200f along a vertical direction, and filling the etched portion with a material.

[0147] Fig.15A is a circuit diagram for describing an active pixel sensor array 20 of an image sensor according to example embodiments. Fig. 15B is used to describe the Fig.15A FIG. 4 is a diagram of control signals for the active pixel sensor array 20 shown in FIG.

[0148] Reference Fig.15A , the active pixel sensor array 20 includes a plurality of pixels PX, and the pixels PX may be arranged in a matrix. According to an example embodiment, each pixel PX may include a transmission transistor TX and logic transistors RX, SX, and DX. Here, the logic transistor may include a reset transistor RX, a selection transistor SX, and a drive transistor DX.

[0149] The photoelectric conversion element PD can generate and accumulate photocharges proportional to the amount of light incident from the outside. Any one of a photodiode, a phototransistor, a photogate, a pinned photodiode (PPD), or a combination thereof can be used as the photoelectric conversion element PD.

[0150] The transfer transistor TX may transmit the photocharge accumulated in the photoelectric conversion element PD to the floating diffusion area FD in response to the charge transfer signal TG, and the photocharge generated in the photoelectric conversion element PD may be stored in the floating diffusion area FD. The drive transistor DX may be controlled based on the amount of photocharge accumulated in the floating diffusion area FD.

[0151] The reset transistor RX may periodically reset the photocharge accumulated in the floating diffusion area FD in response to the reset signal RG. The drain electrode of the reset transistor RX may be connected to the floating diffusion area FD, and the source electrode of the reset transistor RX may be connected to the power supply voltage VDD. When the reset transistor RX is turned on, the power supply voltage VDD connected to the source electrode of the reset transistor RX may be transmitted to the floating diffusion area FD. Therefore, when the reset transistor RX is turned on, the photocharge accumulated in the floating diffusion area FD may be discharged and the floating diffusion area FD may be reset.

[0152] The driving transistor DX is combined with a positive current source outside the pixel PX to perform a source follower function, amplifying the potential change in the floating diffusion area FD and outputting the potential change through the output line Lout. The selection transistor SX can select the pixel PX to be read in units of columns in response to the pixel selection signal SG. When the selection transistor SX is turned on, the power supply voltage VDD can be transmitted to the source electrode of the driving transistor DX.

[0153] Reference Fig.15A and Fig. 15B When light is incident on the photoelectric conversion element PD, the photoelectric conversion element PD may generate and accumulate photocharges. According to an example embodiment, the output voltage (eg, Figure 1 The output voltage VOUT shown in FIG. 1 may be applied as a charge transfer signal TG to a transfer transistor TX of at least one pixel among the plurality of pixels PX. The output voltage VOUT may be, for example, a reference voltage VOUT. Figures 2 to 9describes the output voltage VOUT and can also be referenced from Fig.10 and Fig.11 An output voltage selected from among the first output voltage VOUT_1 to the nth output voltage VOUT_n is described.

[0154] When a high negative voltage is applied to the transfer transistor TX, the difference between the potential of the gate of the transfer transistor TX and the potential of the photoelectric conversion element PD can be increased. Therefore, the full well capacity as the capacitance of the photocharge accumulated in the photoelectric conversion element PD can be increased.

[0155] According to an example embodiment, the output voltage VOUT may be applied to at least one reset transistor RX of the plurality of pixels PX as a reset signal RG. When a high negative voltage is applied to the reset transistor RX, the difference between the potential of the gate of the reset transistor RX and the potential of the floating diffusion area FD may increase. Therefore, the full well capacity as the capacitance of the photocharge in the floating diffusion area FD may increase.

[0156] While the inventive concept has been particularly shown and described with reference to various example embodiments of the inventive concept, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the claims.

Claims

1. A charge pump circuit in a semiconductor substrate, the charge pump circuit comprising: a first pump unit including a first capacitor and a first transistor, wherein the first capacitor is connected to a first node, the first transistor has a drain connected to the first node, a source to which a first source voltage is applied, and a gate to which a first switching signal is applied, and the first pump unit is configured to generate a first node voltage at the first node by using a clock signal; and a second pump unit, comprising a second capacitor, a second transistor, and a third transistor, wherein the second capacitor has a first terminal connected to the first node and a second terminal connected to the second node, the second transistor has a drain connected to the second node, a gate to which a second switching signal is applied, and a source connected to the output terminal, the third transistor has a drain connected to the second node, a source to which a second source voltage is applied, and a gate to which a third switching signal is applied, and the second pump unit is configured to generate a negative output voltage by using the first node voltage, The clock signal and the first node voltage are switched between a low level voltage and a high level voltage respectively. The magnitude of the absolute value of the negative output voltage is greater than the magnitude of the absolute value of the high level voltage of the clock signal, and The body of the third transistor is physically isolated from the body of the second transistor by forming an isolation layer through the semiconductor substrate.

2. The charge pump circuit according to claim 1, wherein: The second transistor comprises an n-type transistor, and the third transistor comprises a p-type transistor.

3. The charge pump circuit according to claim 2, wherein: The n-type transistor is formed in the well in which the second transistor is formed.

4. The charge pump circuit according to claim 1, wherein: The magnitude of the absolute value of the negative output voltage is equal to or greater than twice the magnitude of the absolute value of the high level voltage of the clock signal.

5. The charge pump circuit according to claim 1, wherein: The first pump unit outputs a first output voltage having a constant amplitude, The second pump unit outputs a second output voltage having a constant amplitude, and The magnitude of the absolute value of the second output voltage is greater than the magnitude of the absolute value of the first output voltage.

6. The charge pump circuit according to claim 1, wherein: The first pump unit further includes a fourth transistor, and The charge pump circuit also includes an isolation layer that physically isolates a body of the fourth transistor from a body of the first transistor.

7. The charge pump circuit according to claim 1, wherein: The first pump unit further includes a fourth transistor, and A well forming a body of the fourth transistor is formed in the well forming the body of the first transistor.

8. The charge pump circuit according to claim 1, wherein: The charge pump circuit further includes an inverter configured to receive the clock signal and provide an inverted clock signal to the first pump unit.

9. A charge pump circuit, configured to generate a negative output voltage by receiving a clock signal, the charge pump circuit comprising: a substrate in which a first well, a second well, and a third well are formed; a first pump unit including a first capacitor and a first transistor formed in a first well, wherein the first capacitor is connected to a first node, and the first transistor has a drain connected to the first node, a source to which a first source voltage is applied, and a gate to which a first switching signal is applied; a second pump unit including a second capacitor, a second transistor formed in the second well, and a third transistor formed in the third well, wherein the second capacitor has a first terminal connected to the first node and a second terminal connected to the second node, the second transistor has a drain connected to the second node, a gate to which the second switching signal is applied, and a source connected to the output terminal, and the third transistor has a drain connected to the second node, a source to which the second source voltage is applied, and a gate to which the third switching signal is applied; and an isolation layer configured to physically insulate the first well, the second well, and the third well from each other, The clock signal switches between a low level voltage and a high level voltage at a regular cycle, and The magnitude of the absolute value of the negative output voltage is greater than the magnitude of the absolute value of the high level voltage. The substrate includes a first surface on which a first transistor is formed and a second surface opposite to the first surface, and The isolation layer extends from the first surface to the second surface.

10. The charge pump circuit according to claim 9, wherein: A first width of a cross section of the isolation layer contacting the first surface is smaller than a second width of a cross section of the isolation layer contacting the second surface.

11. The charge pump circuit according to claim 9, wherein: A first width of a cross section of the isolation layer contacting the first surface is greater than a third width of a central cross section of the isolation layer between the first surface and the second surface, and A second width of a cross section of the isolation layer contacting the second surface is greater than the third width.

12. The charge pump circuit according to claim 9, wherein: The substrate is doped with P-type impurities.

13. An image sensor, comprising: a pixel array comprising a plurality of pixels defined by a first isolation layer; as well as A charge pump circuit, in a semiconductor substrate, the charge pump circuit comprising: a first pump unit including a first capacitor and a first transistor, wherein the first capacitor is connected to a first node, the first transistor has a drain connected to the first node, a source to which a first source voltage is applied, and a gate to which a first switching signal is applied, and the first pump unit is configured to generate a first node voltage at the first node by using a clock signal; and a second pump unit, comprising a second capacitor, a second transistor, and a third transistor, wherein the second capacitor has a first terminal connected to the first node and a second terminal connected to the second node, the second transistor has a drain connected to the second node, a gate to which a second switching signal is applied, and a source connected to the output terminal, the third transistor has a drain connected to the second node, a source to which a second source voltage is applied, and a gate to which a third switching signal is applied, and the second pump unit is configured to generate a negative output voltage by using the first node voltage, and The body of the third transistor is physically isolated from the body of the second transistor by a second isolation layer formed through the semiconductor substrate.

14. The image sensor according to claim 13, wherein: The negative output voltage is provided to the first isolation barrier.

15. The image sensor according to claim 13, wherein: The plurality of pixels each include: a photoelectric conversion element configured to generate and accumulate photocharges proportional to the amount of incident light; a transfer transistor configured to transmit photocharges accumulated in the photoelectric conversion element to the floating diffusion region; and a reset transistor configured to reset the charge accumulated in the floating diffusion region, and The negative output voltage is provided to the gate of the pass transistor.

16. The image sensor according to claim 13, wherein: The plurality of pixels each include: a photoelectric conversion element configured to generate and accumulate photocharges proportional to the amount of incident light; a transfer transistor configured to transmit photocharges accumulated in the photoelectric conversion element to the floating diffusion region; and a reset transistor configured to reset the charge accumulated in the floating diffusion region, and The negative output voltage is provided to the gate of the reset transistor.

17. The image sensor according to claim 13, wherein: The first pump unit outputs a first output voltage having a constant amplitude, The second pump unit outputs a second output voltage having a magnitude greater than that of the first output voltage, and At least one of the first output voltage and the second output voltage is selectively provided to the pixel array.

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