Memory devices and memory modules

Abstract

A memory device and a memory module are provided. The memory device includes: a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including a row switch and configured to perform a selection operation on the plurality of word lines; a column decoder including a column switch and configured to perform a selection operation on the plurality of bit lines; and control logic configured to control a pre-charge operation to be performed on a selected word line in a word line pre-charge period in a data read operation, and to control a pre-charge operation to be performed on a selected bit line in a bit line pre-charge period, wherein the row switch connected to the selected word line is weakly turned on in the bit line pre-charge period.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0118378, filed on September 25, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a memory device, and more specifically, to a resistive memory device and a method for reading the resistive memory device. Background Technology

[0003] In addition to flash memory, resistive memory devices, such as phase-change RAM (PRAM), nanofloating gate memory (NFGM), polymer RAM (PoRAM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), and resistive RAM (RRAM), are known as non-volatile memory devices. Resistive memory devices can possess the non-volatile characteristics of flash memory and the high-speed characteristics of dynamic random access memory (DRAM).

[0004] Memory cells in resistive memory devices can have a resistance distribution based on programmed data. During read operations on data stored in the memory cells, data can be sensed by applying a constant current or voltage to the memory cell and reading the voltage that varies depending on the resistance of the memory cell. Both word lines and bit lines connected to the memory cells can have parasitic capacitive components, and capacitance affects sensing margin and read interference characteristics. On the other hand, in memory devices with a three-dimensional crossover structure, when vertically stacked first and second layers share bit lines, the capacitance of the word lines of the first and second layers may differ; therefore, the sensing margin and read interference characteristics of the first and second layers may differ. Summary of the Invention

[0005] The inventive concept provides a memory device and a method of operating the memory device that can increase sensing margin and / or reduce read interference.

[0006] According to one aspect of the inventive concept, a memory device is provided, the memory device comprising: a memory cell array including a plurality of memory cells in a region where a plurality of word lines and a plurality of bit lines intersect each other; a row decoder including a plurality of row switches corresponding to the plurality of word lines and configured to perform a selection operation on the plurality of word lines; a column decoder including a plurality of column switches corresponding to the plurality of bit lines and configured to perform a selection operation on the plurality of bit lines; and control logic configured to control a pre-charge operation performed on a selected word line connected to a selected memory cell during a word line pre-charge period in a data read operation, and to control a pre-charge operation performed on a selected bit line connected to the selected memory cell during a bit line pre-charge period after the word line pre-charge period, wherein the row switches connected to the selected word lines are weakly turned on during the bit line pre-charge period.

[0007] According to one aspect of the inventive concept, a memory device is provided, the memory device comprising: a memory cell array including a first layer and a second layer sharing a plurality of bit lines and stacked thereon, wherein each of the first layer and the second layer includes a plurality of memory cells in regions where the plurality of word lines and the plurality of bit lines intersect each other; a row decoder including a plurality of row switches corresponding to the plurality of word lines and configured to perform a selection operation on the plurality of word lines; a column decoder including a plurality of column switches corresponding to the plurality of bit lines and configured to perform a selection operation on the plurality of bit lines; and a word line precharge device configured to apply a word line precharge voltage to the memory cell array during a word line precharge period. The selected word line is selected by the row decoder; a bit line precharge device is configured to apply a bit line precharge voltage to the selected bit line selected by the column decoder during the bit line precharge period; and a comparator compares the voltage of the selected word line with a reference voltage and outputs a comparison result, wherein, when a data read operation is performed on the first memory cell of the first layer, a first word line selection signal of a first level is applied to the first row switch connected to the first memory cell during the word line precharge period to turn on the first row switch, and a first word line selection signal of a third level between a second level that turns off the first row switch and the first level is applied to the first row switch during the bit line precharge period.

[0008] According to one aspect of the inventive concept, a memory module is provided, the memory module comprising: a module board; a plurality of memory chips located on the module board; and a non-volatile memory located on the module board and communicating with the plurality of memory chips, each of the plurality of memory chips comprising: a memory cell array comprising a first layer and a second layer sharing a plurality of bit lines and stacked thereon, wherein each of the first layer and the second layer comprises a plurality of memory cells in a region where the plurality of word lines and the plurality of bit lines intersect each other; a line decoder comprising a plurality of line switches corresponding to the plurality of word lines and configured to perform selection operations on the plurality of word lines. The system includes a column decoder, comprising multiple column switches corresponding to the multiple bit lines and configured to perform selection operations on the multiple bit lines; and control logic configured to control precharge operations on the word lines and bit lines of the selected memory cell, wherein, when a read operation is performed on a first memory cell of the first layer, a weakly on first word line selection signal is applied to a first row switch connected to the first memory cell during the bit line precharge period, and wherein, when a read operation is performed on a second memory cell of the second layer, a cut-off second word line selection signal is applied to a second row switch connected to the second memory cell during the bit line precharge period.

[0009] According to one aspect of the inventive concept, a method of operating a memory device is provided, wherein the memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells disposed in regions where the plurality of word lines and the plurality of bit lines intersect each other, each of the plurality of memory cells including a variable resistor and a selection device, the method of operating comprising: precharging a selected word line connected to a selected memory cell among the plurality of memory cells during a first precharging period; precharging a selected bit line connected to the selected memory cell during a second precharging period, while using a row switch to weakly conduct the connection of the selected word line to a data line; connecting the selected word line to the data line; and sensing data of the selected memory cell based on the voltage of the data line.

[0010] According to one aspect of the inventive concept, a memory device is provided, the memory device comprising: a memory cell array including a first layer and a second layer that share a plurality of bit lines and are vertically stacked, wherein each of the first layer and the second layer includes a plurality of memory cells in a region where the plurality of word lines and the plurality of bit lines intersect each other; a row decoder including a plurality of row switches corresponding to the plurality of word lines and configured to perform a selection operation on the plurality of word lines; a column decoder including a plurality of column switches corresponding to the plurality of bit lines and configured to perform a selection operation on the plurality of bit lines; a read circuit configured to read data from a selected memory cell based on a voltage level of a selected word line connected to the selected memory cell among the plurality of memory cells; and control logic for controlling such that when a data read operation is performed on a first memory cell of the first layer, N (N is zero or a positive integer) of the plurality of unselected word lines of the first layer are floated, and when a data read operation is performed on a second memory cell of the second layer, M (M is a positive integer greater than N) of the plurality of unselected word lines of the second layer are floated. Attached Figure Description

[0011] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an example embodiment of the inventive concept;

[0013] Figure 2 This is a block diagram illustrating a memory device according to an example embodiment of the inventive concept;

[0014] Figure 3A and Figure 3B It is shown Figure 2 Circuit diagram of an example embodiment of a memory cell array;

[0015] Figure 4A It is shown Figure 2 A circuit diagram of an example embodiment of a memory cell array, and Figure 4B yes Figure 4A A perspective view of the memory cell array;

[0016] Figure 5A It is shown Figure 2 A circuit diagram of an example embodiment of a memory cell array, and Figure 5B yes Figure 5A A perspective view of the memory cell array;

[0017] Figure 6A It shows that it is aimed at Figure 3A The diagram illustrates the set write and reset write operations of the variable resistor device in the memory cell, and... Figure 6B This is a diagram showing the distribution of memory cells according to resistance when the memory cell is a single-level cell;

[0018] Figure 7 This is a flowchart illustrating a method for reading a memory device according to an example embodiment of the inventive concept;

[0019] Figure 8 This is a circuit diagram illustrating components for performing a read operation of a memory device according to an example embodiment of the inventive concept;

[0020] Figure 9 This is a diagram illustrating a method for reading a memory device according to an example embodiment of the inventive concept;

[0021] Figure 10 This is a flowchart illustrating a method for reading a memory device according to an example embodiment of the inventive concept;

[0022] Figure 11 A method for reading a memory device according to an example embodiment of the inventive concept is shown;

[0023] Figure 12A and Figure 12B A method for reading a memory device according to an example embodiment of the inventive concept is shown;

[0024] Figure 13 A method for reading a memory device according to an example embodiment of the inventive concept is shown;

[0025] Figure 14A , Figure 14B and Figure 14C A method for reading a memory device according to an example embodiment of the inventive concept is shown;

[0026] Figure 15 This is a circuit diagram illustrating a method for reading a memory device according to an exemplary embodiment of the inventive concept;

[0027] Figure 16A , Figure 16B and Figure 16C A method for reading a memory device according to an example embodiment of the inventive concept is shown;

[0028] Figure 17 This is a circuit diagram illustrating a method for reading a memory device according to an exemplary embodiment of the inventive concept;

[0029] Figure 18A and Figure 18B This is a diagram illustrating a method for reading a memory device according to an exemplary embodiment of the inventive concept;

[0030] Figure 19This is a diagram illustrating a method for reading a memory device according to an exemplary embodiment of the inventive concept;

[0031] Figure 20 This is a circuit diagram illustrating an example of compensating for leakage current during a data read operation;

[0032] Figure 21 This is a diagram illustrating an example of an embodiment of the inventive concept applied to a 3D memory device;

[0033] Figure 22 This is a block diagram illustrating an example of a memory device applied to an SSD system according to an embodiment of the inventive concept;

[0034] Figure 23 This is a block diagram illustrating examples of implementations of a memory system according to various embodiments of the inventive concept; and

[0035] Figure 24 This is a block diagram illustrating an example of a memory device used as a buffer for a controller according to an embodiment of the inventive concept. Detailed Implementation

[0036] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an example embodiment of the inventive concept. In some embodiments of the inventive concept, the memory device 200 may be referred to as a resistive memory device because it includes resistive memory cells. Alternatively, in embodiments of the inventive concept, the memory device 200 may include various other types of memory cells. Additionally, since the memory device 200 may be disposed in an area where multiple first signal lines and multiple second signal lines intersect each other, the memory device 200 may be referred to as a crosspoint memory device. For example, the memory device 200 may include multiple layers, and adjacent layers may be configured to share at least one signal line. In the following embodiments, it may be assumed that the memory device 200 is a resistive memory device.

[0038] Figure 1 The memory device 200 can be implemented in various forms. As an example, the memory device 200 can be a device that is implemented as a single memory chip. Alternatively, the memory device 200 can be defined as a device that includes multiple memory chips. For example, the memory device 200 can be a memory module in which multiple memory chips are mounted on a board. However, embodiments of the inventive concept are not limited thereto, and the memory device 200 can be implemented in various forms, such as a semiconductor package including one or more memory dies.

[0039] Reference Figure 1 The memory system 10 may include a memory controller 100 and a memory device 200. The memory device 200 may include a memory cell array 210, write / read circuitry 220, and / or control logic 230. Additionally, the memory controller 100 may include a processor, and under the control of the processor, the memory controller 100 may control various memory operations relating to the memory device 200 in a hardware-, software-, or combined manner.

[0040] The memory controller 100 can control the memory device 200 to read data stored in the memory device 200, or control the memory device 200 to write data to the memory device 200, in response to a write / read request from the host. For example, the memory controller 100 can provide the memory device 200 with an address ADDR, a command CMD, and / or a control signal CTRL, thereby controlling programming (or writing), reading, and erasing operations on the memory device 200. Additionally, data DATA to be written and read can be transferred and received between the memory controller 100 and the memory device 200.

[0041] Although not shown, the memory controller 100 may include RAM, a processing unit, a host interface, and a memory interface. The RAM may serve as operational memory for the processing unit. The processing unit may control the operation of the memory controller 100. The host interface may include a protocol for exchanging data between the host and the memory controller 100. The memory controller 100 may be configured to communicate with the host via at least one of various protocols, such as USB, MMC, PCI-E, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, SCSI, ESDI, and Integrated Drive Electronics (IDE).

[0042] The memory cell array 210 may include a plurality of memory cells disposed in regions where a plurality of first signal lines and a plurality of second signal lines intersect each other. In some embodiments, the first signal lines may be one of bit lines and word lines, and the second signal lines may be another of bit lines and word lines. Additionally, each of the plurality of memory cells may be a single-level cell (SLC) capable of storing one bit of data, or a multi-level cell (MLC) capable of storing at least two or more bits of data. Furthermore, the memory cells may have multiple resistance profiles depending on the number of bits to be stored in each memory cell. In some embodiments, when one bit of data is written to a memory cell, the memory cell may have two resistance profiles. When two bits of data are stored in a memory cell, the memory cell may have four resistance profiles.

[0043] The memory cell array 210 may include resistive memory cells, each comprising a variable resistance device. For example, when the variable resistance device comprises a phase-change material and its resistance changes with temperature, the resistive memory device may be a phase-change random access memory (PRAM). In another embodiment, when the variable resistance device comprises an upper electrode, a lower electrode, and a transition metal oxide between them, the resistive memory device may be a resistive RAM. In other embodiments, when the variable resistance device comprises an upper electrode of magnetic material, a lower electrode of magnetic material, and a dielectric material between them, the resistive memory device may be a resistive RAM.

[0044] The write / read circuit 220 can provide a constant voltage or current to a selected memory cell during data write and read operations targeting a selected memory cell among a plurality of memory cells by connecting a selected first signal line or a selected second signal line to the selected memory cell. For example, when performing a read operation, the write / read circuit 220 can provide a pre-charge voltage to the selected first signal line and / or the selected second signal line, and then can sense the voltage level of the selected first signal line or the voltage level of the selected second signal line.

[0045] Control logic 230 can perform storage operations such as data writing and data reading by controlling various components of the memory device 200. As an example, control logic 230 can generate control signals for controlling the levels of multiple voltages, the duration of application of the multiple voltages, the selection of multiple voltages, etc., wherein the multiple voltages can be applied to signal lines connected to the selected memory cell and / or circuitry for driving the signal lines (e.g., ...). Figure 2 Line decoder 240 in Figure 2 (such as the column decoder 250 and write / read circuit 220).

[0046] In a read operation of the memory cell array 210, a read voltage can be provided to the selected word line (hereinafter referred to as the word line) and the selected bit line (hereinafter referred to as the bit line) connected to the selected memory cell, respectively. As an example, a first precharge voltage can be provided to the word line and a second precharge voltage can be provided to the bit line, such that the voltage between the word line and the bit line can have a level difference corresponding to a predetermined or optionally desired set value. Furthermore, after the precharge operation for the word line and the bit line is completed, the level of the voltage to be detected from at least one of the word line and the bit line can vary depending on the programming state of the selected memory cell (e.g., a set state or a reset state).

[0047] As an example, when performing an operation to sense data using voltage detected from word lines, the level of the voltage detected from word lines can vary depending on the programming state of the selected memory cell. When the level of the voltage detected from word lines is greater than a predetermined or optionally desired reference level, data "0" can be sensed because the selected memory cell may be in a set state; when the level of the voltage detected from word lines is less than the predetermined or optionally desired reference level, data "1" can be sensed because the selected memory cell may be in a reset state. In various embodiments, memory device 200 can be implemented to sense data using voltage detected from bit lines. Optionally, memory device 200 can be implemented such that data "1" can be sensed when the selected memory cell is in a set state, and data "0" can be sensed when the selected memory cell is in a reset state.

[0048] In the read operation described above, word lines and bit lines may each have capacitive components (e.g., parasitic capacitors). For example, word lines and bit lines may have their own capacitive components, capacitive components due to adjacent lines, capacitive components due to memory cells connected to word lines and bit lines, and capacitive components due to peripheral circuitry (e.g., driver circuitry and sensing circuitry) connected to word lines and bit lines. These capacitive components of each of the word lines and bit lines affect sensing margin and read interference characteristics.

[0049] For example, when the capacitance of word lines and / or bit lines is large, a large current flows through the memory cell, thus increasing the temperature of the memory cell. This can lead to read interference. Furthermore, in read methods that sense data based on the voltage level of word lines or bit lines, the sensing margin decreases when the capacitance of the word lines or bit lines is small. Additionally, in memory devices with a vertical three-dimensional intersection structure, when the first and second vertically stacked layers share bit lines, the capacitance of the word lines in the first layer can differ from that in the second layer. Therefore, the sensing margin and / or read interference characteristics of the first layer can differ from those of the second layer.

[0050] However, according to example embodiments of the inventive concept, by compensating for the parasitic capacitance components of word lines or bit lines, or by compensating for the capacitance difference between the first and second layers, the sensing margin can be increased and read interference can be reduced.

[0051] In some embodiments, after the word lines and bit lines are precharged and then the word lines and data lines are shared by charge, data can be sensed based on the voltage of the data lines, thereby allowing data about the memory cell to be read. At this time, the word line selection switch (e.g., a word line selection transistor connected between the word line and the data line) can be weakly turned on during the bit line precharge period, thereby increasing the sensing margin by increasing the parasitic capacitance component of the word line. For example, the word line selection transistor connected to the word line can be turned off in response to a cutoff level control signal during the bit line precharge period, causing the word line to be floated. In the memory device 200 according to an embodiment of the inventive concept, the word line selection transistor connected to the word line can be weakly turned on in response to a weak on-level control signal to increase the sensing margin, thereby causing the word line to be pseudo-floating.

[0052] In some embodiments, the memory cell array 210 may include a vertically stacked first layer and a second layer. When a read operation is performed on a first memory cell located in the first layer, a first word line select transistor connected to the first memory cell via a first word line can be weakly turned on during the bit line precharge period, thus the first word line can be pseudo-floated. When a read operation is performed on a second memory cell located in the second layer, a second word line select transistor connected to the second memory cell via a second word line can be turned off during the bit line precharge period, thus the second word line can be floating, or the second word line can be pseudo-floated more strongly than the first word line. In other words, the level of the control signal to be applied to the second word line select transistor can be closer to the cutoff level than the level of the control signal to be applied to the first word line select transistor.

[0053] In some embodiments, the memory cell array 210 may include a vertically stacked first layer and a second layer. When the word line parasitic capacitance component of the second layer is greater than that of the first layer, unselected word lines can be biased based on a disable voltage during read operations on the first layer, and unselected word lines adjacent to the selected word line during the bit line precharge period can be floated during read operations on the second layer. Therefore, the read interference characteristics of the first layer can become the same as or similar to those of the second layer. Optionally, when performing read operations on the first and second layers, unselected word lines adjacent to the selected word line during the bit line precharge period can be floated, wherein the number of unselected word lines to be floated can differ between the first and second layers.

[0054] According to the example embodiments of the inventive concept described above, the sensing margin can be increased by increasing the capacitance of the word lines, and the sensing margin of the first layer can become the same as or similar to that of the second layer. Furthermore, since the capacitance difference between the word lines of the first and second layers can be compensated, the read interference characteristics of the first layer and the read interference characteristics of the second layer can become the same as or similar.

[0055] The memory controller 100 and the memory device 200 can be implemented as separate semiconductor devices. Alternatively, the memory controller 100 and the memory device 200 can be integrated into a single semiconductor device. For example, the memory controller 100 and the memory device 200 can be integrated into a single semiconductor device to construct a memory card. For example, the memory controller 100 and the memory device 200 can be integrated into a single semiconductor device and can be used to construct PC cards (PCMCIA), compact flash memory cards (CF), smart media cards (SM / SMC), memory sticks, multimedia cards (e.g., MMC, RS-MMC, micro MMC), SD cards (e.g., SD, mini SD, micro SD), and universal flash memory devices (UFS), etc.

[0056] Figure 2 This is a block diagram illustrating a memory device according to an example embodiment of the inventive concept.

[0057] Reference Figure 2 The memory device 200 may include a memory cell array 210, a write / read circuit 220, control logic 230, a row decoder 240, a column decoder 250, and / or a voltage generator 260. The write / read circuit 220 may include a write driver 221 and a sensing amplification unit 222.

[0058] The memory cell array 210 can be connected to multiple first signal lines and multiple second signal lines. Additionally, the memory cell array 210 can include multiple memory cells respectively disposed in regions where the multiple first signal lines and multiple second signal lines intersect each other. In the following description, the case where the multiple first signal lines are word lines WL and the multiple second signal lines are bit lines BL will be used as an example.

[0059] The write driver 221 can be selectively connected to the bit line BL and / or the word line WL and can provide write current to the selected memory cell. As a result, the write driver 221 can program the data DATA to be stored in the memory cell array 210.

[0060] The sensing amplification unit 222 can be selectively connected to the bit line BL and / or the word line WL and can read data written to the selected memory cell. For example, the sensing amplification unit 222 can detect the voltage from the word line WL connected to the selected memory cell and amplify it to output the read data DATA.

[0061] Control logic 230 can be based on... Figure 1 The memory controller 100 receives commands CMD, address ADDR, and control signal CTRL to write data to the memory cell array 210 or can output various control signals to read data from the memory cell array 210. As a result, the control logic 230 can control various operations in the memory device 200 in general.

[0062] Various control signals output from control logic 230 can be provided to write / read circuit 220, voltage generator 260, row decoder 240, and column decoder 250. For example, control logic 230 can provide operation selection signal CTRL_op to write / read circuit 220, voltage control signal CTRL_vol to voltage generator 260, row address X_ADDR to row decoder 240, and column address Y_ADDR to column decoder 250.

[0063] For example, when performing a read operation, control logic 230 can control the selection operations of word lines of row decoder 240 and bit lines of column decoder 250, as well as the sensing operation of sensing amplification unit 222, to read data from the selected memory cell. It can also control voltage generator 260 such that the voltages supplied to row decoder 240, column decoder 250, and sensing amplification unit 222 have predetermined or optionally desired voltage levels. Voltage generator 260 can generate various types of voltages for performing write, read, and erase operations on memory cell array 210 based on voltage control signal CTRL_vol. For example, voltage generator 260 can generate a first drive voltage V for driving multiple word lines WL. R and the second driving voltage V used to drive multiple bit lines BL C For example, when performing a read operation, voltage generator 260 can generate a first pre-charge voltage V. p1 Discharge voltage V dc And the on or off voltage of the switch of the line decoder 240 as the first drive voltage V R And it can generate a second pre-charge voltage V p2 Clamping voltage V CMP And the on or off voltage of the switch of the column decoder 250 as the second drive voltage V CAdditionally, voltage generator 260 can generate various voltages to be supplied to write / read circuit 220, such as set or reset write voltages to be supplied to write driver 221 and reference voltage Vref to be supplied to sense amplifier unit 222.

[0064] The row decoder 240 can be connected to the memory cell array 210 via multiple word lines WL and can activate a selected word line among the multiple word lines WL in response to a row address X_ADDR received from the control logic 230. For example, the row decoder 240 can control the voltage to be applied to the selected word lines among the multiple word lines WL in response to the row address X_ADDR, or it can control the connection relationship of the selected word lines. The row decoder 240 may include multiple row switches, and at least one row switch may be connected to each of the multiple word lines WL. By turning on or off the multiple row switches, the selected word line can be activated for write / read operations. In a read operation, the row decoder 240 can connect the selected word line to the sensing amplification unit 222 and can discharge the voltage V. dc Apply to unselected word lines.

[0065] Column decoder 250 can be connected to memory cell array 210 via multiple bit lines BL and can activate selected bit lines among the multiple bit lines BL in response to column address Y_ADDR received from control logic 230. For example, column decoder 250 can control the voltage to be applied to the selected bit lines among the multiple bit lines BL in response to column address Y_ADDR, or it can control the connection relationship of the selected bit lines. Column decoder 250 may include multiple column switches, and at least one column switch may be connected to each of the multiple bit lines BL. By turning on or off the multiple column switches, the selected bit lines can be activated for write / read operations.

[0066] Figure 3A and Figure 3B It is shown Figure 2 A circuit diagram of an example embodiment of a memory cell array. Figure 3A and Figure 3B This illustrates the case where the resistive memory cell is PRAM. Additionally, Figure 3A The memory cell array 210 shown can correspond to a cell block.

[0067] The memory cell array 210 may include a horizontally structured two-dimensional memory cell array, and may include multiple word lines WL1 to WLn, multiple bit lines BL1 to BLm, and multiple memory cells MC. The memory cell array may include multiple memory blocks. Each memory block may have multiple memory cells arranged in rows and columns. Here, the number of word lines WL, the number of bit lines BL, and the number of memory cells MC may vary depending on the embodiment. However, the inventive concept is not limited thereto, and in other embodiments, the memory cell array 210 may include a vertically structured three-dimensional memory cell array.

[0068] According to some embodiments, each of the plurality of memory cells MC may include a variable resistor device R and a switching device SW. Here, the variable resistor device R may be referred to as a variable resistance material and the switching device SW may be referred to as a selection device.

[0069] In some embodiments, the variable resistor R may be connected between one of the multiple bit lines BL1 to BLm and the switching device SW, and the switching device SW may be connected between the variable resistor R and one of the multiple word lines WL1 to WLn. However, the inventive concept is not limited thereto; the switching device SW may be connected between one of the multiple bit lines BL1 to BLm and the variable resistor R, and the variable resistor R may be connected between the switching device SW and one of the multiple word lines WL1 to WLn.

[0070] The switching device SW can be connected between any one of the multiple word lines WL1 to WLn and the variable resistor R, and the current supply to the variable resistor R can be controlled according to the voltage applied to the connected word lines and bit lines. The switching device SW can be implemented using a bidirectional threshold switch (OTS) material. However, the switching device SW is not limited to this, and in other embodiments, the switching device SW can be changed by another switchable device such as a unidirectional diode, a bidirectional diode, or a transistor.

[0071] A voltage can be applied to a variable resistor R in the memory cell MC via multiple word lines WL1 to WLn and multiple bit lines BL1 to BLm, allowing current to flow through the variable resistor R. For example, the variable resistor R may include a phase change material layer capable of reversibly changing between a first state and a second state. However, the variable resistor R is not limited to this and may include any variable resistor whose resistance value varies according to the applied voltage. For example, the selected memory cell MC can reversibly change the resistance of the variable resistor R between a first state and a second state based on the voltage applied to it.

[0072] Based on the resistance change of the variable resistor R, the memory cell MC can store digital information such as "0" or "1" and can also erase digital information from the memory cell MC. For example, data can be written to the memory cell MC in a high resistance state "0" and a low resistance state "1". Here, the write operation from the high resistance state "0" to the low resistance state "1" can be called a "set operation", and the write operation from the low resistance state "1" to the high resistance state "0" can be called a "reset operation". However, the memory cell MC according to the embodiment of the inventive concept is not limited to the digital information of the high resistance state "0" and the low resistance state "1" shown above, and can store various resistance states.

[0073] By selecting multiple word lines WL1 to WLn and multiple bit lines BL1 to BLm, any memory cell MC can be addressed, and the memory cell MC can be programmed by applying a predetermined or optionally desired signal (e.g., voltage or current) between the multiple word lines WL1 to WLn and the multiple bit lines BL1 to BLm. In some embodiments, the voltage can be measured through the selected word line among the multiple word lines WL1 to WLn, thereby allowing information about the resistance value of the variable resistor R of the selected memory cell MC to be read, i.e., the programmed data.

[0074] Reference Figure 3B The memory cell MC may include a variable resistor R and a switching device SW. The switching device SW may be implemented using various devices such as transistors and diodes. The variable resistor R may include a phase change film 11 (or a variable resistance layer) containing a mixture of germanium, antimony and tellurium (GST, Ge-Sb-Te), an upper electrode 12 formed on the phase change film 11, and a lower electrode 13 formed below the phase change film 11.

[0075] The upper electrode 12 and the lower electrode 13 may comprise various metals, metal oxides, or metal nitrides. The upper electrode 12 and the lower electrode 13 may comprise aluminum (Al), copper (Cu), titanium nitride (TiN), or titanium aluminum nitride (Ti). x Al y N z ), iridium (Ir), platinum (Pt), silver (Ag), gold (Au), polycrystalline silicon, tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), nickel (Ni), cobalt (Co), chromium (Cr), antimony (Sb), iron (Fe), molybdenum (Mo), palladium (Pd), tin (Sn), zirconium (Zr), zinc (Zn), iridium oxide (IrO2), strontium zirconate (SrZrO3), etc.

[0076] The phase change film 11 may include a bipolar resistive storage material or a unipolar resistive storage material. The bipolar resistive storage material can be programmed into a set or reset state depending on the polarity of the current, and perovskite materials can be used for bipolar resistive storage materials. On the other hand, the unipolar resistive storage material can be programmed into a set or reset state even when a current of the same polarity passes through it, and materials such as NiO... x or TiO x Transition metal oxides can be used in unipolar resistive storage materials.

[0077] GST materials can be programmed between an amorphous state with relatively high resistivity and a crystalline state with relatively low resistivity. GST materials can be programmed by heating them. The magnitude and duration of heating determine whether the GST material remains in an amorphous or crystalline state. High and low resistivity can be represented as programming values ​​of logic 0 or logic 1, respectively, and can be sensed by measuring the resistivity of the GST material. Conversely, high and low resistivity can be represented as programming values ​​of logic 1 or logic 0, respectively.

[0078] Figure 4A It is shown Figure 2 A circuit diagram of an example embodiment of a memory cell array, and Figure 4B yes Figure 4A A perspective view of the memory cell array.

[0079] Reference Figure 4A The memory cell array 210a may include word lines WL1 and WL2, which extend in a first direction (X direction) and are spaced apart from each other in a second direction (Y direction) perpendicular to the first direction. Additionally, the memory cell array 210a may include bit lines BL1, BL2, BL3, and BL4, which are spaced apart from word lines WL1 and WL2 in a third direction (Z direction) and extend in the second direction.

[0080] Memory cells MC can be located between bit lines BL1, BL2, BL3, BL4 and word lines WL1, WL2, respectively. For example, memory cells MC can be located at the intersection of bit lines BL1, BL2, BL3, BL4 and word lines WL1, WL2, and can include a variable resistor R for storing information and a switching device SW for selecting the memory cell MC. The switching device SW can be referred to as the switching device layer or the access device layer.

[0081] Memory cells MC can be arranged in the same structure in the third direction. For example, in a memory cell MC located between word line WL1 and bit line BL1, a switching device SW can be electrically connected to word line WL1, a variable resistor R can be connected to bit line BL1, and the variable resistor R and the switching device SW can be connected in series.

[0082] However, the inventive concept is not limited to this. For example, with Figure 4A Unlike other memory cells, the positions of the switching device SW and the variable resistor R can be changed within the memory cell MC. For example, in the memory cell MC, the variable resistor R can be connected to the word line WL1 and the switching device SW can be connected to the bit line BL1.

[0083] Reference Figure 4B The memory cell array 210a may include a first electrode line layer 110L, a second electrode line layer 120L, and a memory cell layer MCL on the substrate 101.

[0084] An interlayer insulating layer 105 may be disposed on the substrate 101. The interlayer insulating layer 105 may include an oxide such as silicon oxide or a nitride such as silicon nitride, and may be used to electrically decouple the first electrode line layer 110L from the substrate 101. In some embodiments of the memory cell array 210a, the interlayer insulating layer 105 is disposed on the substrate 101, but this is only one example. For example, in some embodiments of the memory cell array 210a, an integrated circuit layer may be disposed on the substrate 101, and memory cells may be disposed on such an integrated circuit layer. The integrated circuit layer may include, for example, peripheral circuitry for operating the memory cells and / or core circuitry for computation. For reference, a structure in which an integrated circuit layer including peripheral circuitry and / or core circuitry is disposed on the substrate and memory cells are disposed on the integrated circuit layer may be called a cell-on-periphery (COP) structure.

[0085] The first electrode line layer 110L may include a plurality of first electrode lines 110 extending parallel to each other in a first direction (X direction). The second electrode line layer 120L may include a plurality of second electrode lines 120 extending parallel to each other in a second direction (Y direction) intersecting the first direction. The first direction and the second direction may intersect each other perpendicularly.

[0086] The first electrode line 110 (or lower electrode) can correspond to Figure 4A The character line WL in the middle, and the second electrode line 120 (or upper electrode) can correspond to Figure 4A The bit line BL is in the middle. In addition, the first electrode line 110 can correspond to the bit line, and the second electrode line 120 can correspond to the word line.

[0087] The memory cell layer (MCL) may include a plurality of memory cells 140 spaced apart from each other in a first direction and a second direction. Figure 4A (MC in the diagram). As shown, the first electrode line 110 and the second electrode line 120 may intersect each other. The memory cell 140 may be disposed at the portion where the first electrode line 110 and the second electrode line 120 intersect between the first electrode line layer 110L and the second electrode line layer 120L.

[0088] Each memory cell 140 may include a lower electrode layer 141, a select device layer 143, an intermediate electrode layer 145, a heating electrode layer 147, a variable resistor layer 149, and / or an upper electrode layer 148. When positional relationships are not considered, the lower electrode layer 141 may be referred to as the first electrode layer, the intermediate electrode layer 145 and the heating electrode layer 147 may be referred to as the second electrode layer, and the upper electrode layer 148 may be referred to as the third electrode layer.

[0089] In some embodiments, the variable resistance layer 149 ( Figure 4A The variable resistance device R in the variable resistance layer 149 may include a phase change material that can reversibly change between an amorphous and a crystalline state depending on the heating time. For example, the variable resistance layer 149 may include a material whose phase can be reversibly changed by Joule heating generated by a voltage applied across the variable resistance layer 149, and whose resistance can change according to the phase change. For example, the phase change material may be in a high-resistance state in an amorphous phase and in a low-resistance state in a crystalline phase. Data can be stored in the variable resistance layer 149 by defining the high-resistance state as "0" and the low-resistance state as "1".

[0090] In some embodiments, the variable resistance layer 149 may comprise a chalcogenide material as a phase change material. For example, the variable resistance layer 149 may comprise Ge-Sb-Te (GST). For example, Ge-Sb-Te may comprise materials such as Ge2Sb2Te5, Ge2Sb2Te7, Ge1Sb2Te4, or Ge1Sb4Te7. The variable resistance layer 149 may comprise various phase change materials. However, the inventive concept is not limited thereto, and the variable resistance layer 149 may comprise various materials having resistance change characteristics.

[0091] Select device layer 143 ( Figure 3AThe SW in the text can be a current conditioning layer capable of controlling the flow of current. The selector layer 143 may include a material layer whose resistance varies depending on the magnitude of the voltage applied across it. For example, the selector layer 143 may include a bidirectional threshold switch (OTS) material. When a voltage less than a threshold voltage Vth is applied to the selector layer 143, the selector layer 143 can maintain a high-resistance state with almost no current flow, and when a voltage greater than the threshold voltage Vth is applied to the selector layer 143, the selector layer 143 can transition to a low-resistance state where current begins to flow. Additionally, when the current flowing through the selector layer 143 becomes less than the holding current, the selector layer 143 can change to a high-resistance state. In some embodiments, the selector layer 143 may include a chalcogenide switching material as the OTS material.

[0092] The heating electrode layer 147 may be configured to contact the variable resistance layer 149 between the intermediate electrode layer 145 and the variable resistance layer 149. The heating electrode layer 147 serves to heat the variable resistance layer 149 during set or reset operations. The heating electrode layer 147 may include a conductive material capable of generating sufficient heat to cause a phase change in the variable resistance layer 149 without reacting with it. For example, the heating electrode layer 147 may include a carbon-based conductive material.

[0093] The lower electrode layer 141, the intermediate electrode layer 145, and the upper electrode layer 148 may include conductive materials serving as current paths. For example, the lower electrode layer 141, the intermediate electrode layer 145, and the upper electrode layer 148 may each include a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the lower electrode layer 141 and the upper electrode layer 148 may be selectively formed. In other words, the lower electrode layer 141 and the upper electrode layer 148 may be omitted.

[0094] A first insulating layer 160a may be located between the first electrode lines 110, and a second insulating layer 160b may be located between the memory cells 140 of the memory cell layer MCL. Additionally, a third insulating layer 160c may be located between the second electrode lines 120. The first insulating layer 160a to the third insulating layer 160c may comprise insulating layers of the same material, or at least one of the first insulating layer 160a to the third insulating layer 160c may comprise insulating layers of different materials. The first insulating layer 160a to the third insulating layer 160c may comprise dielectric materials such as oxides or nitrides and may serve to electrically isolate the devices in each layer. An air gap (not shown) may be formed instead of the second insulating layer 160b. When an air gap is formed, an insulating pad (not shown) having a predetermined or optionally desired thickness may be formed between the air gap and the memory cell 140.

[0095] Figure 5AIt is shown Figure 2 A circuit diagram of an example embodiment of a memory cell array, and Figure 5B yes Figure 5A A perspective view of the memory cell array.

[0096] Reference Figure 5A The memory cell array 210b may include a vertically stacked first layer and a second layer, and the first layer and the second layer may share signal lines, for example, share... Figure 5A The common bit lines are BL1, BL2, BL3 and BL4.

[0097] The memory cell array 210b may include lower word lines WL11 and WL12 extending in a first direction (X direction) and spaced apart from each other in a second direction (Y direction) perpendicular to the first direction, and upper word lines WL21 and WL22 extending in the first direction (X direction) and spaced apart from each other above the lower word lines WL11 and WL12 in a third direction (Z direction) perpendicular to the first direction. Additionally, the memory cell array 210b may include common bit lines BL1, BL2, BL3, and BL4, which are spaced apart from each of the upper word lines WL21 and WL22 and the lower word lines WL11 and WL12 in the third direction and extend in the second direction.

[0098] The first memory cell MC1 and the second memory cell MC2 can be located between common bit lines BL1, BL2, BL3, and BL4 and lower word lines WL11 and WL12, and between common bit lines BL1, BL2, BL3, and BL4 and upper word lines WL21 and WL22, respectively. For example, the first memory cell MC1 can be located at the intersection of common bit lines BL1, BL2, BL3, and BL4 and lower word lines WL11 and WL12, and the second memory cell MC2 can be located at the intersection of common bit lines BL1, BL2, BL3, and BL4 and upper word lines WL21 and WL22. Lower word lines WL11 and WL12, multiple first memory cells MC1, and common bit lines BL1, BL2, BL3, and BL4 can constitute the first layer, and upper word lines WL21 and WL22, multiple second memory cells MC2, and common bit lines BL1, BL2, BL3, and BL4 can constitute the second layer. By selecting word lines WL11, WL12, WL21, and WL22, as well as common bit lines BL1, BL2, BL3, and BL4, any memory cell MC1 and MC2 can be addressed.

[0099] exist Figure 5A In the diagram, memory cell array 210b is shown as including a first layer and a second layer, but is not limited thereto. Memory cell array 210b may include three or more layers stacked vertically.

[0100] Reference Figure 5B The memory cell array 210b may include a first electrode line layer 110L, a first memory cell layer MCL1, a second electrode line layer 120L, a second memory cell layer MCL2, and / or a third electrode line layer 130L on the substrate 101. An interlayer insulating layer 105 may be disposed on the substrate 101.

[0101] The first memory cell layer MCL1 may include a plurality of first memory cells 140-1 spaced apart from each other in the first direction and the second direction. Figure 5A The second memory cell layer MCL2 may include a plurality of second memory cells 140-2 spaced apart from each other in the first and second directions. Figure 5A (MC2 in the diagram). As shown, the first electrode line 110 and the second electrode line 120 can intersect each other, and the second electrode line 120 and the third electrode line 130 can intersect each other. The first electrode line 110 can correspond to... Figure 5A The lower letter lines WL11 and WL12, and the second electrode line 120 can correspond to Figure 5A The bit lines BL1 to BL4 are shared between the first and second layers. Additionally, the third electrode line 130 can correspond to... Figure 5A The upper part of the character is WL21 and WL22.

[0102] The first memory unit 140-1 may be disposed at the intersection of the first electrode line 110 and the second electrode line 120 between the first electrode line layer 110L and the second electrode line layer 120L. The second memory unit 140-2 may be disposed at the intersection of the second electrode line 120 and the third electrode line 130 between the second electrode line layer 120L and the third electrode line layer 130L.

[0103] The first memory cell 140-1 and the second memory cell 140-2 may each include lower electrode layers 141-1 and 141-2, selection device layers 143-1 and 143-2, intermediate electrode layers 145-1 and 145-2, heating electrode layers 147-1 and 147-2, variable resistor layers 149-1 and 149-2, and upper electrode layers 148-1 and 148-2. Insulating layers 162-1, 162-2, and 163 may be located between the first memory cell 140-1 and the second memory cell 140-2. (Refer to...) Figure 4B The described memory cell 140 can be applied to a first memory cell 140-1 and / or a second memory cell 140-2. In some embodiments, the structure of the first memory cell 140-1 may be the same as or substantially the same as the structure of the second memory cell 140-2.

[0104] Figure 6AIt shows that it is aimed at Figure 3A The diagram illustrates the set write and reset write operations of the variable resistor device in the memory cell, and... Figure 6B This is a diagram showing the distribution of memory cells according to resistance when the memory cell is a single-level cell.

[0105] Reference Figure 6A When it will constitute Figure 3A When the phase change material of a variable resistor R is heated for a certain period of time to a temperature between its crystallization temperature (Tx) and melting point (Tm) and then gradually cooled, the phase change material can be in a crystalline state. This crystalline state can be called a "set state" and can be a state that can store data "1". On the other hand, if the phase change material is quenched after being heated to a temperature above its melting point (Tm), the phase change material can be in an amorphous state. This amorphous state can be called a "reset state" and can be a state that can store data "0". Therefore, data can be stored by supplying current to the variable resistor R, and data can be read by measuring the resistance value of the variable resistor R.

[0106] Reference Figure 6B The horizontal axis represents resistance, and the vertical axis represents the number of memory cells (MCs). When a memory cell (MC) is a single-level cell, it can be in one of two states: a low-resistance state (i.e., set state) or a high-resistance state (i.e., reset state).

[0107] Therefore, the operation of switching the memory cell MC from a low-resistance state to a high-resistance state can be referred to as a reset operation or a reset write operation. In some embodiments, a reset write operation can be used to write the data "0" into the memory cell MC. Conversely, the operation of switching the memory cell MC from a high-resistance state to a low-resistance state can be referred to as a set operation or a set write operation. In some embodiments, a set write operation can be used to write the data "1" into the memory cell MC.

[0108] Figure 7 This is a flowchart illustrating a method for reading a memory device according to an example embodiment of the inventive concept.

[0109] Reference Figure 7 The memory device can perform data read operations based on requests from an external host. For example, a memory controller included in the memory system can provide a read command to the memory device based on a request from the host. The memory device can receive the read command (S10) and can decode the address provided by the read command to determine the selected memory cell.

[0110] The memory device may precharge a first signal line connected to one end of the selected memory cell (S20). For example, the first signal line may be a word line, and a first precharge voltage may be applied to the word line. However, the inventive concept is not limited thereto, and the first signal line may be a bit line.

[0111] In operation S20, a first selection switch (e.g., a first selection transistor) connected to the first signal line can be turned on to connect the first signal line to the data line, and the first signal line and the data line can be precharged through a precharge path connected to the data line.

[0112] The memory device can precharge a second signal line connected to the other end of the selected memory cell (S30). For example, the second signal line can be a bit line, and a second precharge voltage can be applied to the bit line. However, the inventive concept is not limited thereto, and when the first signal line is a bit line, the second signal line can be a word line.

[0113] The second pre-charge voltage can be higher than the first pre-charge voltage, and the voltage difference between the first and second pre-charge voltages can be greater than the threshold voltage of the memory cell, such as the threshold voltage of a switching device. Therefore, current (hereinafter referred to as cell current) can flow through the memory cell and charge the first signal line, thereby increasing the voltage level of the first signal line. In some embodiments, since the amount of cell current can vary depending on the state of the memory cell (e.g., set or reset), the voltage level of the first signal line can change according to the state of the memory cell. For example, when the memory cell is in the set state, the voltage level of the first signal line can increase relatively because the resistance of the memory cell is small and the amount of cell current is large. On the other hand, when the memory cell is in the reset state, the voltage level of the first signal line can increase relatively little or not at all because the resistance of the memory cell is large and the amount of cell current is small.

[0114] The memory device may connect one of the first signal line and the second signal line to the data line (S40). For example, the memory device may connect the first signal line to the data line. By connecting the first signal line to the data line, charge sharing can be performed between the first signal line and the data line, and the voltage level of the first signal line and the voltage level of the data line can be the same. Therefore, when the memory cell is in the set state, the voltage level of the data line can be high, and when the memory cell is in the reset state, the voltage level of the data line can be low.

[0115] The memory device can sense data based on the voltage level of the data lines, that is, sense the data stored in the memory device (S50). The memory device can compare the voltage level of the data lines with a reference voltage and output the comparison result as data. In some embodiments, the reference voltage can be set to an intermediate level between the voltage level of the data lines when the memory cell is in a set state and the voltage level of the data lines when the memory cell is in a reset state. Therefore, by comparing the voltage level of the data lines with the reference voltage, a comparison result of 1 bit of data, such as 0 or 1, can be output. However, the inventive concept is not limited to this, and when the memory cell is a multi-level cell, the memory cell can have multiple states. In operation S50, the voltage level of the data lines can be determined based on the multiple states of the memory cell. The memory device can read multiple bits of data by comparing the voltage level of the data lines with multiple reference voltages.

[0116] In some embodiments, during operation S30, a first selection switch connected to the first signal line can be weakly turned on during at least a portion of the pre-charging period of the second signal line. For example, if the first signal line is a word line and the second signal line is a bit line, a word line selection transistor connected to the word line can be weakly turned on during the pre-charging period of the bit line, allowing leakage current to flow. The word line can be pseudo-floating. Therefore, the current flowing through the memory cell can charge the data line, thereby increasing the voltage level of the data line. Therefore, during operation S40, when the first signal line and the data line are connected, the amount of change in the voltage level of the first signal line can be reduced, thereby increasing the sensing margin. (Refer to...) Figures 8 to 1 4. This will be described in detail.

[0117] In some embodiments, during operation S30, at least a portion of the first signal line (i.e., the unselected first signal line adjacent to the selected first signal line) can be floated during the period when the second signal line is pre-charged. Therefore, the parasitic capacitance component of the first signal line can be reduced, thereby reducing the amount of current in the cell current and thus reducing read interference.

[0118] In some embodiments, in a memory cell array with a three-dimensional intersection structure, when the parasitic capacitance value of the first signal line of the second layer is greater than that of the first signal line of the first layer, the number of unselected first signal lines that can be floated in operation S30 when performing a read operation on a memory cell of the second layer can be greater than the number of unselected first signal lines that can be floated in operation S30 when performing a read operation on a memory cell of the first layer. Therefore, the difference between the parasitic capacitance values ​​of the first signal lines of the first layer and the parasitic capacitance values ​​of the first signal lines of the second layer can be compensated, thereby reducing the impact on read interference characteristics. This will be described in detail later with reference to Figures 16 to 18.

[0119] Figure 8 This is a circuit diagram illustrating a component for performing a read operation of a memory device according to an example embodiment of the inventive concept.

[0120] Reference Figure 8 The word line WL can be connected to one end of the memory cell MC, and the bit line BL can be connected to the other end of the memory cell MC. The row decoder 240 can be connected to the word line WL. For example, the row decoder 240 may include multiple row switches, such as a word line selection transistor TRx and a discharge transistor TR. wd For ease of description, Figure 8 The line decoder 240 is shown to include a word line selection transistor TRx and a discharge transistor TR. wd However, the line decoder 240 may include multiple word line selection transistors TRx and multiple discharge transistors TRx, which are respectively connected to multiple word lines. wd Additionally, the line decoder 240 may also include other switches and / or control devices.

[0121] The word line select transistor TRx can be turned on or off in response to the word line select signal LX. When the word line select transistor TRx is on, the word line WL can be connected to the sense amplifier unit 222 via the data line DL (or the global word line). When the word line select transistor TRx is implemented as an NMOS transistor, the word line select transistor TRx can be turned on when the word line select signal LX is high and can be turned off when the word line select signal LX is low.

[0122] Discharge transistor TR wd It can be turned on or off in response to the discharge enable signal WDE. When the discharge transistor TR... wd When turned on, the discharge voltage V dc (Or, the first prohibition voltage) can be applied to the word line WL. For example, the discharge voltage V dc It can be 0V (volts). When the discharge transistor TR... wd When implemented as a PMOS transistor, the discharge transistor TR wd It can be turned on when the discharge enable signal WDE is low, and turned off when the discharge enable signal WDE is high.

[0123] For example, in a read operation, when the word line selection transistor TRx connected to the selected word line is turned on, the discharge transistor TR connected to the selected word line... wd It can be cut off. The discharge transistor TR connected to the unselected word line. wd It can be turned on, and the word line selection transistor TRx connected to the unselected word line can be turned off.

[0124] Column decoder 250 can be connected to bit line BL. For example, column decoder 250 may include multiple column switches, such as bit line selection transistors TRy. For ease of description, Figure 8 The diagram shows a column decoder 250 including a bit line selection transistor TRy, but the column decoder 250 may include multiple bit line selection transistors TRy respectively connected to multiple bit lines BL. Additionally, the column decoder 250 may also include multiple discharge transistors connected to each of the multiple bit lines BL.

[0125] Bit line select transistor TRy can be connected to a control switch, such as clamp transistor TR. CMP Bit line precharge transistor TRb. Bit line precharge transistor TRb and clamping transistor TR CMP It can be understood as a component of the sensing amplification unit 222.

[0126] The bit line select transistor TRy can be turned on or off in response to the bit line select signal LY. For example, as shown, when the bit line select transistor TRy is implemented as a PMOS transistor, it can be turned on when the bit line select signal LY is low and turned off when the bit line select signal LY is high.

[0127] The bit line precharge transistor TRb can be turned on or off in response to the bit line precharge enable signal BPE. For example, when the bit line precharge transistor TRb is implemented as a PMOS, it can be turned on when BPE is low and turned off when BPE is high. The bit line precharge transistor TRb can be turned on to charge the second precharge voltage V. p2 Apply to the bit line BL. In some embodiments, clamp the transistor TR. CMP It can be controlled based on the clamping voltage V CMP Apply a predetermined or optionally desired voltage to the bit line BL.

[0128] The sensing amplification unit 222 may include a word line precharge transistor TR WP and sensing amplifier SA. Sensing amplifier unit 222 may also include bit line precharge transistor TRb and clamping transistor TR. CMP .

[0129] Word line precharge transistor TR WP It can be turned on or off in response to the word line precharge enable signal WPE. When the word line precharge transistor TR... WP When implemented as NMOS, the word line precharge transistor TR WPIt can be turned on when the word line precharge enable signal WPE is high, and the word line precharge transistor TR WP It can be turned off when the word line precharge enable signal WPE is low. Word line select transistor TRx and word line precharge transistor TR WP It can be turned on to charge the first pre-charge voltage V p1 Apply to word line WL.

[0130] The word line WL and bit line BL can each include parasitic capacitance components, and the parasitic capacitance component of the word line WL (e.g., word line capacitor C) A The parasitic capacitance component (not shown) of the bit line BL can be smaller than that of the word line BL. Therefore, the sense amplifier SA can be connected to a word line where the effect of the parasitic capacitance component is relatively low, and can sense the voltage level of the word line to read the data of the selected memory cell.

[0131] The sense amplifier SA compares the sensed voltage Vsen of the sense node SN (e.g., the voltage level of the data line DL, where the voltage level of the data line DL is the same as the voltage level of the word line WL) with the reference voltage Vref, and then outputs the comparison result as data DATA. In other words, the sense amplifier SA can act as a comparator. For example, when the memory cell MC is in the set state, the sensed voltage Vsen can be higher than the reference voltage Vref, and the sense amplifier SA can output "1" as data DATA. For example, when the memory cell MC is in the reset state, the sensed voltage Vsen can be lower than the reference voltage Vref, and the sense amplifier SA can output "0" as data DATA.

[0132] As referenced above Figure 5A and Figure 5B As described, in a memory cell array with a three-dimensional intersection structure, when the vertically stacked first and second layers share a bit line, the word line capacitor C of the first layer... A The word line capacitor C can be smaller than that of the second layer. A In other words, the word line capacitance of the first layer can be smaller than that of the second layer. When the word line capacitance C... A When the time is short, the sensing margin of the sensing amplifier SA will be reduced. On the other hand, when the word line capacitor C... A When the value is large, the read interference characteristics will deteriorate. As mentioned above, the word line capacitor C A This will affect sensing margin and readout interference characteristics. This is due to the word line capacitor C in the first layer. A The second layer of word line capacitor C A They can be different from each other, so the sensing margin and readout interference characteristics between the first layer and the second layer can be different.

[0133] However, according to the reference Figure 7 The described read method according to an example embodiment of the inventive concept can compensate for the reduction in sensing margin without increasing the word line capacitor C by weakly turning on the word line select transistor TRx during the pre-charge period of the bit line BL. A The capacitor can also compensate for the capacitance difference between the first and second layers. Additionally, when the word line capacitor C of the second layer... A The component is greater than the word line capacitor C of the first layer. A In the case of a component, when a read operation is performed on a memory cell of the second layer, at least a portion of the unselected word lines WL adjacent to the selected word line WL can be floated during the period when the bit line BL can be precharged, and when a read operation is performed on a memory cell of the first layer, the unselected word lines WL adjacent to the selected word line WL can be discharged by voltage V during the period when the bit line BL can be precharged. dc The bias, or the number of unselected word lines WL less than that in the second layer, can be floated, thus compensating for the capacitance difference between the first and second layers.

[0134] Figure 9 This is a diagram illustrating a method for reading a memory device according to an example embodiment of the inventive concept. Figure 10 This is a flowchart illustrating a method for reading a memory device according to an example embodiment of the inventive concept. It can be based on... Figure 8 The operation of the components of the memory device to perform Figure 9 and Figure 10 The method for reading memory devices. Therefore, reference will be made to... Figure 8 Describe them together.

[0135] Reference Figure 9 The horizontal axis represents time, and the vertical axis represents the voltage levels of the bit lines and word lines. The word line WL can be precharged with a first precharge voltage during the first precharge period T_P1 (e.g., the word line precharge period) (S11). The word line selection transistor TRx and the word line precharge transistor TR... WP It can be turned on to utilize the first pre-charge voltage V p1 The word line WL and data line DL are pre-charged. In some embodiments, a first pre-charge voltage V is applied. p1 It can be a negative voltage, and the voltage level of the word line WL can drop to the first pre-charge voltage V. p1 .

[0136] At this time, the bit line selection transistor TRy can be turned off, allowing the bit line BL to be in a floating state. When the memory cell MC is the selected memory cell, the discharge transistor TRy... wd It can maintain a closed state during read operations.

[0137] The bit line BL can be precharged with a second precharge voltage during the second precharge period T_P2 (e.g., the bit line precharge period), while the word line selection transistor TRx connected to the word line WL is weakly turned on (S12). The bit line selection transistor TRy and the bit line precharge transistor TRb can be turned on during the second precharge period T_P2 to apply the second precharge voltage V. p2 A bit line BL is applied. In some embodiments, the supply voltage can be applied via the bit line precharge transistor TRb, and the clamping transistor TRb... CMP The voltage level V of bit line BL can be... BL Maintain at the second pre-charge voltage V p2 .

[0138] The voltage level V of bit line BL BL It can be increased to the second pre-charge voltage V p2 At this time, when the voltage level V of bit line BL... BL The voltage level V of the word line WL WL When the difference between the two threshold voltages is equal to or greater than the threshold voltage Vth of the memory cell MC, the cell current can flow in the memory cell MC. When the memory cell MC is in the set state, the voltage level Vth of the word line WL is... WL_SET It can be increased. However, the voltage level V of the word line WL... WL_SET Voltage level V of bit line BL BL The difference between them can be equal to or greater than the disable voltage Vs (that is, the voltage level at which the cell current of the memory cell can be cut off). Therefore, when the memory cell MC is in the set state, the voltage level V of the word line WL is... WL_SET It can be increased to a certain voltage level, which is derived from the voltage level V of the bit line BL. BL Reduce the voltage level of the disable voltage Vs. On the other hand, when the memory cell MC is in the reset state, the voltage level V of the word line WL is reduced. WL_RST It can hardly increase or can increase very little.

[0139] Because the word line select transistor TRx is weakly turned on during the second precharge period T_P2, the word line WL can be pseudo-floating. As described above, the word line select transistor TRx can be turned on when the word line select signal LX is high, and the word line select transistor TRx can be turned off when the word line select signal LX is low. During the second precharge period T_P2, a weak turn-on signal (weak turn-on voltage) below high and above low can be provided to the word line select transistor TRx as the word line select signal LX. In the example embodiment, the weak turn-on signal can be a voltage having a level that reduces the threshold voltage of the word line select transistor TRx from a high level.

[0140] During the sensing period T_S, the word line selection transistor TRx can be turned on, connecting the word line WL and the data line DL to perform charge sharing (S13). Because of charge sharing, the voltage levels of the word line WL and the data line DL can be the same, and as... Figure 9 As shown, the voltage level V of word line WL WL_SET and V WL_RST This can be varied. When charge sharing is complete, data can be sensed based on the voltage level of the data line DL (e.g., the sensing voltage Vsen) (S14). The sensing amplifier SA can sense data by comparing the reference voltage Vref with the sensing voltage Vsen.

[0141] During charge sharing, specifically, when the memory cell MC is in the set state, the voltage level V of the word line WL is... WL_SET This can be reduced through charge sharing. If the reduction is significant, the sensing margin of the sensing amplifier SA will decrease. The sensing margin SM can be represented by Equation 1.

[0142] [Equation 1]

[0143] SM = Vsen_set - Vsen_reset = C A / (C A +C DL )×(V WL_SET -V WL_RST )

[0144] Among them, C DL The capacitor represents the data line; Vsen_set represents the sensed voltage (i.e., the data line voltage level) when the memory cell is in the set state; Vsen_set represents the sensed voltage level when the memory cell is in the reset state. WL_SET This represents the voltage level of the word line when the memory cell is in the set state, where V WL_SET It can have a voltage level that decreases from the threshold voltage Vth to the inhibit voltage Vs. WL_RST This represents the word line voltage level when the memory cell is in the reset state. Taking into account the leakage current flowing in the word line WL during the bit line precharge period (e.g., the current flowing into the word line through unselected memory cells connected to the same word line), V... WL_RST The amount of charge that can be charged into the word line WL during the bit line precharge period can be divided by the word line capacitor C. A The voltage level corresponding to the capacitor. Referring to Equation 1, it can be found that the sensing margin SM can be related to the word line capacitor C. A Proportional.

[0145] According to the read method of the memory device according to an exemplary embodiment of the inventive concept, the word line select transistor TRx can be weakly turned on during the second pre-charge period T_P2. Therefore, the data line DL can be charged through the leakage current of the word line select transistor TRx, thereby having the effect of increasing the word line capacitor C. A Same effect.

[0146] Therefore, the voltage level V of word line WL WL_SET The change in voltage level (i.e., the drop in voltage level when the memory cell is in the set state) can be less than the voltage level V of word line WL when the word line selection transistor TRx is turned off in the second precharge period T_P2, according to the read method of the comparative example. WL_SET The amount of change. Therefore, compared to the sensing margin SM' according to the comparative example, the sensing margin SM can be increased.

[0147] Figure 11 A method for reading a memory device according to an example embodiment of the inventive concept is shown. Figure 11 The levels of the word line select signal LX and the bit line select signal LY at each stage of a read operation are shown, and the voltage of the word line WL when the memory cell is in the set state is also shown.

[0148] Reference Figure 11 During standby operation from time t0 to time t1, the word line select signal LX can be low, and the bit line select signal LY can be high. Therefore, the word line select transistor TRx and the bit line select transistor TRy can be turned off. The word line WL can be floating or can have a voltage level of 0V.

[0149] Subsequently, the word line select signal LX can go high at time t1, and the word line WL can be based on the first pre-charge voltage V. p1 Precharged. First precharge voltage V p1 It can be a negative voltage. Therefore, the voltage level V of the word line WL. WL It can descend.

[0150] The bit line select signal LY can go low at time t2, and the bit line BL can be based on the second precharge voltage V. p2 Precharged. Second precharge voltage V p2 It can be higher than the first pre-charge voltage V p1And it can be a positive voltage. In this case, a weak on-level Vwo can be provided as the word line select signal LX. In other words, the word line select signal LX can have a weak on-level. The weak on-level Vwo can be higher than the off-level Voff of the word line select transistor TRx (i.e., the low level of the word line select signal LX) and lower than the on-level Von of the word line select transistor TRx (i.e., the high level of the word line select signal LX). The word line select transistor TRx can be weakly turned on based on the weak on-level word line select signal LX. The word line WL can be pseudo-floating.

[0151] For reference Figure 9 As described, when the difference between the voltage level of bit line BL and the voltage level of word line WL is greater than or equal to the threshold voltage of the memory cell, for example, at time t3, cell current can flow through the memory cell. Since the memory cell is in the set state, a larger amount of cell current can flow compared to the reset state, and because the cell current can... Figure 8 The character line WL capacitor C A Charging, therefore the voltage level V of word line WL. WL It can be increased. Because the word line select transistor TRx is weakly conducting, the leakage current of the word line select transistor TRx can be reduced. Figure 8 The capacitor C in the data line DL DL Charging allows the voltage level of the data line DL to increase. In other words, because the word line select transistor TRx can be weakly turned on, the capacitor C of the word line WL... A It can manifest as being enlarged.

[0152] Since the word line select signal LX can go high at time t4 and the word line select transistor TRx can be turned on, the word line WL can be connected to the data line DL. Charge sharing can be performed between the word line WL and the data line DL. Because the voltage level of the data line DL can be lower than the voltage level V of the word line WL... WL Therefore, the voltage level V of the word line WL WL The voltage level of the data line DL can be lowered and the voltage level of the word line WL can be increased, so the voltage levels of the data line DL can be the same.

[0153] Subsequently, data sensing can be performed from time t5 to time t6 (i.e., the data sensing period). As described above, the word line selection transistor TRx can be weakly turned on during the bit line precharge period (e.g., the period from time t2 to time t4), causing the voltage level V of the word line WL during the bit line precharge period to be lower than the precharge period. WL The drop can be greater than the word line WL voltage level V when the word line select transistor TRx is off. WL' The decrease in the amount of loss is reduced. Therefore, the sensing margin can be increased.

[0154] Figure 12A and Figure 12B A method for reading a memory device according to an example embodiment of the inventive concept is shown. Figure 12A and Figure 12B The reading method can be similar to Figure 11 The reading method. However, with Figure 11 Compared to the reading method, since the voltage level of the word line select signal LX can vary during the bit line precharge period, the following discussion will focus on their differences.

[0155] exist Figure 12A and Figure 12B In this context, the word line select signal can have a weak on-level Vwo during at least some periods of the bit line precharge period (e.g., from time t2 to time t5) and a cut-off level Voff for the remaining periods. Therefore, the word line select transistor TRx can be weakly on during some periods of the bit line precharge period and cut off for the remaining periods. This can be based on the word line capacitor C. A The capacitance is used to adjust the length of some time during which the word line select transistor TRx can be weakly turned on. For example, with the word line capacitor C... A As the capacitance increases, the length of some of the periods during which the word line selection transistor TRx is weakly turned on during the bit line precharge period can be reduced. For example... Figure 12A As shown, after the switching device of the memory cell is turned on at time t3, and then the voltage level of the word line WL increases, the word line selection transistor TRx can be turned off at time t4. However, the inventive concept is not limited to this, and as... Figure 12B As shown, the word line selection transistor TRx can be, for example... Figure 12B The deadline is t3, and time t3 is, for example... Figure 12B Before time t4, the voltage level of word line WL increases at time t4 by turning on the switching device of the memory cell.

[0156] Figure 13 A method for reading a memory device according to an example embodiment of the inventive concept is shown. Figure 13 The voltage levels of word line selection signals LX_L1 and LX_L2, bit line selection signals LY_L1 and LY_L2, and word lines WL_L1 and WL_L2 are shown in the data read operation of the first layer L1 and the data read operation of the second layer L2. In some embodiments, it is assumed that the selected memory cell of the first layer L1 and the selected memory cell of the second layer L2 are in the set state.

[0157] Reference Figure 13The levels of word line selection signals LX_L1 and LX_L2 can be applied differently in the data read operations of the first layer L1 and the second layer L2. In the following text, for ease of description, the word line WL_L1 of the first layer L1 will be referred to as the first word line, and the word line WL_L2 of the second layer L2 will be referred to as the second word line WL_L2. Furthermore, the word line capacitor of the first word line WL_L1 will be referred to as the first word line capacitor C. A1 And the word line capacitor of the second word line WL_L2 will be referred to as the second word line capacitor C. A2 .

[0158] In the first layer L1 data read operation, the word line select signal LX_L1 applied to the word line select transistor connected to the first word line WL_L1 can have a weak on level Vwo during the bit line precharge period. In the second layer L2 data read operation, the word line select signal LX_L2 applied to the word line select transistor connected to the second word line WL_L2 can have a cutoff level Voff during the bit line precharge period. In some embodiments, the second word line capacitor C A2 It can be greater than the first word line capacitor C. A1 .

[0159] As mentioned above, word line capacitor C A It can affect the sensing margin, therefore the word line capacitor C A The larger the value, the higher the sensing margin. This is especially true when considering a relatively small word line capacitor C. A When performing data read operations using the first layer L1, a weak on-level word line select signal LX_L1 (Vwo) can be applied to the word line select transistor during the bit line precharge period to weakly turn on the word line select transistor. Therefore, the first word line capacitor C A1 It can be increased. Therefore, the effect can be represented by the first word line capacitor C. A1 With the second word line capacitor C of the second layer L2 A2 The voltage levels of the first word line WL_L1 and the second word line WL_L2 during the sensing periods of the data read operation in the first layer L1 and the data read operation in the second layer L2, respectively, can be the same or similar. Therefore, the sensing margins of the first layer L1 and the second layer L2 can be the same or similar.

[0160] Figure 14A , Figure 14B and Figure 14C A method for reading a memory device according to an example embodiment of the inventive concept is shown. Figure 14A , Figure 14B and Figure 14CAn example is shown of providing word line selection signals LX_L1 and LX_L2 of different levels or waveforms to the first layer L1 and the second layer L2 during a read operation of the memory device.

[0161] Reference Figure 14A The levels of word line selection signals LX_L1 and LX_L2 can be applied differently in the data read operation of the first layer L1 and the data read operation of the second layer L2.

[0162] In the first layer L1 data read operation, the word line select signal LX_L1 applied to the word line select transistor connected to the first word line (i.e., the word line select signal LX_L1 applied to the first layer L1) can have a first weak conduction level Vwo1 during the bit line precharge period, and in the second layer L2 data read operation, the word line select signal LX_L2 applied to the word line select transistor connected to the second word line (i.e., the word line select signal LX_L2 applied to the second layer L2) can have a second weak conduction level Vwo2 during the bit line precharge period. The second weak conduction level Vwo2 can be lower than the first weak conduction level Vwo1. Therefore, the word line select transistor TRx of the first layer L1 and the word line select transistor TRx of the second layer L2 can be weakly turned on during the bit line precharge period. However, the amount of leakage current flowing through the word line select transistor TRx of the first layer L1 can be relatively greater than the amount of leakage current flowing through the word line select transistor TRx of the second layer L2. Therefore, the first word line capacitor C A1 It can be expressed as a capacitor C of the second word line. A2 The increase is relatively large, therefore, the effect can be expressed as the first word line capacitor C A1 With the second word line capacitor C A2 The same or similar. In other words, the voltage levels of the first word line WL_L1 and the second word line WL_L2 during the sensing periods of the data read operation of the first layer L1 and the data read operation of the second layer L2, respectively, can be the same or similar, so the sensing margins of the first layer L1 and the second layer L2 can be the same or similar.

[0163] Reference Figure 14BIn the data read operation of the first layer L1 and the data read operation of the second layer L2, each of the word line select signals LX_L1 and LX_L2 may have a weak on level Vwo during a portion of the bit line precharge period and a cutoff level Voff during the remainder of the bit line precharge period. In some embodiments, the period during which the word line select signal LX_L1 applied to the first layer L1 has a weak on level Vwo (e.g., a first weak on period Two1) may differ from the period during which the word line select signal LX_L2 applied to the second layer L2 has a weak on level Vwo2 (e.g., a second weak on period Two2). For example, the second weak on period Two2 may be shorter than the first weak on period Two1.

[0164] Reference Figure 14C In the data read operation of the first layer L1 and the data read operation of the second layer L2, each of the word line selection signals LX_L1 and LX_L2 may have a weak on level Vwo during a portion of the bit line precharge period and may have a cutoff level Voff during the remainder of the bit line precharge period.

[0165] At this time, during the data read operation of the first layer L1, the word line selection signal LX_L1 applied to the first layer L1 can have a first weak on-state level Vwo1 during the bit line precharge period, and during the data read operation of the second layer L2, the word line selection signal LX_L2 applied to the second layer L2 can have a second weak on-state level Vwo2 during the bit line precharge period. The first weak on-state level Vwo1 and the second weak on-state level Vwo2 can be different.

[0166] In an example embodiment, when the time period during which the word line selection signal LX_L1 applied to the first layer L1 maintains the first weak conduction level Vwo1 is the same as the time period during which the word line selection signal LX_L2 applied to the second layer L2 maintains the second weak conduction level Vwo2, the second weak conduction level Vwo2 can be lower than the first weak conduction level Vwo1. However, the inventive concept is not limited to this; the time period during which the word line selection signal LX_L1 applied to the first layer L1 maintains the first weak conduction level Vwo1 can be different from the time period during which the word line selection signal LX_L2 applied to the second layer L2 maintains the second weak conduction level Vwo2. Therefore, the first weak conduction level Vwo1 and the second weak conduction level Vwo2 can vary depending on the length of the time period.

[0167] Figure 15 This is a circuit diagram illustrating a method for reading a memory device according to an exemplary embodiment of the inventive concept. Figure 16A , Figure 16B and Figure 16C A method for reading a memory device according to an example embodiment of the inventive concept is shown. (Refer to...) Figure 15and Figures 16A to 16C Describes the method for reading based on the location of the selected memory cell.

[0168] Reference Figure 15 The sense amplifier SA can be connected to one of the word lines WL1 to WLn that is connected to the selected memory cell, and the voltage level of the word line can be compared with the reference voltage Vref, and then the data of the selected memory cell can be read.

[0169] For reference Figures 7 to 1 As described in section 4, after word line precharging, bit line precharging can be performed, and during the bit line precharging period, the row switches connected to the selected word line (e.g., word line selection transistors TRx1 to TRxn) can be weakly turned on in response to the corresponding weak on-level word line selection signals LX1 to LXn. Therefore, the sensing margin of the sensing amplifier SA can be increased.

[0170] The precharge voltage can be applied to the bit line via a driver DRV (or a column decoder connected to the bit line). For example, the driver DRV may include... Figure 8 Bit line precharge transistor TRb and clamp transistor TR CMP In some embodiments, the word line select signal LX can be applied differently depending on the distance between the driver for applying the pre-charge voltage to the bit line and the memory cell to be read (i.e., the selected memory cell). For example, the weak on-time and / or off-time of the word line select signal LX can be applied differently. This will be referred to... Figures 16A to 16C Describe it.

[0171] Reference Figure 16A The weak on level Vwo4 of the word line select signal LX when performing a read operation on a memory cell located far from the driver can be higher than the weak on level Vwo3 of the word line select signal LX when performing a read operation on a memory cell located near the driver.

[0172] For example, in Figure 15 In this context, the distance between the first memory unit MC1 and the driver can be less than the distance between the second memory unit MC2 and the driver. (Refer to...) Figure 16AIn the data read operation of the first memory cell MC1, the first word line select signal LX1 may have a third weak conduction level during the bit line precharge period, and in the data read operation of the second memory cell MC2, the nth word line select signal LXn may have a fourth weak conduction level during the bit line precharge period. In some embodiments, the fourth weak conduction level may be higher than the third weak conduction level. In other words, the word line select transistor TRx1 or TRxn may be weakly turned on during the bit line precharge period, and at this time, the nth word line select transistor TRxn, which is connected to the second memory cell MC2, which is located further away from the driver, may be more strongly turned on compared to the first word line select transistor TRx1 connected to the first memory cell MC1, which is located closer to the driver.

[0173] When word line selection transistors TRx1 to TRxn are weakly turned on during the bit line precharge period to increase the sensing margin, read interference characteristics can be considered. As the conduction level of the selected transistors increases, the read interference characteristics deteriorate. On the other hand, as the distance between the driver and the memory cell increases, the resistive component of the current path can increase and the cell current can decrease, resulting in good read interference characteristics. Therefore, as described above, by adjusting the conduction level of the word line selection transistors connected to the memory cell considering the distance between the memory cell and the driver, the sensing margin can be increased while maintaining the read interference characteristics of the memory cell at a constant level.

[0174] Reference Figure 16B In the data read operation of the first memory cell MC1 and the data read operation of the second memory cell MC2, each of the first word line select signal LX1 and the nth word line select signal LXn can have a weak on level Vwo during a portion of the bit line precharge period and a cutoff level Voff during the remainder of the bit line precharge period. Therefore, during the bit line precharge period, the first word line select transistor TRx1 and the nth word line select transistor TRxn can be weakly turned on and then turned off.

[0175] In some embodiments, the period during which the first word line selection signal LX1 has a weak conduction level Vwo (e.g., a third weak conduction period Two3) may differ from the period during which the second word line selection signal LX2 has a weak conduction level Vwo (e.g., a fourth weak conduction period Two4). For example, the fourth weak conduction period Two4 may be longer than the third weak conduction period Two3.

[0176] Reference Figure 16CIn the data read operation of the first memory cell MC1 and the data read operation of the second memory cell MC2, each of the first word line selection signal LX1 and the nth word line selection signal LXn may have a weak on level during a portion of the bit line precharge period and may have a cutoff level Voff during the remaining period of the bit line precharge period.

[0177] In some embodiments, during the data read operation of the first memory cell MC1, the first word line select signal LX1 may have a third weak conduction level Vwo3 during the bit line precharge period, and during the data read operation of the second memory cell MC2, the nth word line select signal LXn may have a fourth weak conduction level Vwo4 during the bit line precharge period. The third weak conduction level Vwo3 and the fourth weak conduction level Vwo4 may be different.

[0178] In some embodiments, when the duration for which the first word line selection signal LX1 maintains the third weak conduction level Vwo3 is the same as the duration for which the nth word line selection signal LXn maintains the fourth weak conduction level Vwo4, the fourth weak conduction level Vwo4 may be higher than the third weak conduction level Vwo3. However, the inventive concept is not limited thereto; the duration for which the first word line selection signal LX1 maintains the third weak conduction level Vwo3 may differ from the duration for which the nth word line selection signal LXn maintains the fourth weak conduction level Vwo4, and the third weak conduction level Vwo3 and the fourth weak conduction level Vwo4 may also vary according to the length of the duration.

[0179] Figure 17 This is a circuit diagram illustrating a method for reading a memory device according to an example embodiment of the inventive concept.

[0180] Reference Figure 17 When a data read operation is performed on the selected memory cell MC_sel, the selected word line connected to the selected memory cell MC_sel (e.g., the third word line WL3) can undergo voltage level changes depending on each operation (e.g., word line precharge operation, bit line precharge operation, and charge sharing operation). In some embodiments, unselected word lines adjacent to the selected word line (e.g., at least one word line adjacent to the selected word line from the first word line WL1, the second word line WL2, and the fourth word line WL4 to the nth word line WLn) can be floated. In some embodiments, the at least one word line can be floated during the bit line precharge period and can be biased by a discharge voltage (e.g., 0V) for the remaining period.

[0181] Refer to together Figure 8 When performing a read operation, the word line selection transistor TRx connected to the unselected word line can be turned off, and the discharge transistor TR... wd It can conduct, therefore the discharge voltage V dc(That is, the disable voltage Vinhx) can be applied to the unselected word line, thereby biasing the unselected word line to a predetermined or optionally desired disable level. In this case, according to an embodiment of the inventive concept, a discharge transistor TR connected to at least one unselected word line adjacent to the selected word line... wd The process can be terminated during the bit line precharge period, thereby allowing at least one unselected word line to be floated.

[0182] During a read operation, since at least one unselected word line adjacent to the selected word line is floated, the parasitic capacitance component caused by adjacent word lines in the parasitic capacitance component of word lines can be reduced.

[0183] In some embodiments, in a memory cell array with a three-dimensional crossover structure, when the word line capacitor components of the first layer and the second layer are different and the word line capacitor component of the second layer is greater than the word line capacitor component of the first layer, all unselected word lines can be biased to an inhibit level during a read operation for the first layer, and at least one unselected word line adjacent to the selected word line can be floated during a bit line precharge period during a read operation for the second layer.

[0184] In the example embodiment, during a read operation for the first layer, N unselected word lines (N is a positive integer) adjacent to the selected word line can be floated during the bit line precharge period, and during a read operation for the second layer, M unselected word lines (M is a positive integer greater than N) adjacent to the selected word line can be floated during the bit line precharge period.

[0185] Therefore, the parasitic capacitor component of the selected word line in the second layer can be reduced relatively more, and it can be seen that the capacitor component of the selected word line from the first layer and the second layer is the same, so the read interference characteristics can be the same.

[0186] In some embodiments, such as reference Figures 7 to 16C As described, the word line selection transistor connected to the selected word line can be weakly turned on in response to a control signal with a weak on level during the bit line precharge period.

[0187] In some embodiments, a first word line select transistor connected to the selected word line of the first layer may be weakly turned on during the bit line precharge period, and a second word line select transistor connected to the selected word line of the second layer may be turned off during the bit line precharge period. Optionally, the control signal applied to the first word line select transistor may be closer to the on level than the control signal applied to the second word line select transistor.

[0188] Figure 18A and Figure 18BThis is a diagram illustrating a method for reading a memory device according to an example embodiment of the inventive concept. The description will assume that the capacitance of the word line capacitor in the second layer L2 is greater than the capacitance of the word line capacitor in the first layer L1.

[0189] Reference Figure 18A When performing a read operation on the first layer (L1), a disable voltage Vinhx can be applied to the unselected word line Unsel_WL. For example, the disable voltage Vinhx can be 0V. The unselected word line Unsel_WL can be biased to 0V. When performing a read operation on the second layer (L2), the unselected word line Unsel_WL adjacent to the selected word line Sel_WL can be floated, and the remaining unselected word lines can be biased to 0V. Although Figure 18A This illustrates that each unselected character line closest to the selected character line in both directions is floating, but the inventive concept is not limited to this, such as... Figure 18B As shown, any two or more unselected word lines can be floated in both directions of the selected word lines. Additionally, as another example embodiment, unselected word lines adjacent to the selected word line in one direction can be floated.

[0190] Figure 19 This is a diagram illustrating a method for reading a memory device according to an example embodiment of the inventive concept.

[0191] Reference Figure 19 When a read operation is performed on the first layer L1 and when a read operation is performed on the second layer L2, the unselected word lines Unsel_WL adjacent to the selected word line Sel_WL can be floated, and the remaining unselected word lines can be biased to 0V. In some embodiments, the number of unselected word lines Unsel_WL to be floated when a read operation is performed on the second layer L2 can be greater than the number of unselected word lines Unsel_WL to be floated when a read operation is performed on the first layer L1.

[0192] Figure 20 This is a circuit diagram illustrating an example of compensating for leakage current during a data read operation.

[0193] According to the above embodiment, the word line WL can be floated during the data read process, and leakage current can flow into the floated word line WL due to various factors (e.g., multiple unselected memory cells connected to the word line), which will cause fluctuations in the voltage level of the word line WL. To compensate for this effect of leakage current, the leakage current can be released from the sensing node SN using a current source.

[0194] Reference Figure 20The compensation switch SW1 and the current source can be connected to the sensing node SN. Although an example of the compensation switch SW1 being implemented as an NMOS transistor is shown, the inventive concept is not limited thereto; the compensation switch SW1 can be implemented as a PMOS transistor, a transmission gate, or another type of switching device. The compensation switch SW1 can be controlled to turn on and off by a compensation control signal BC. The compensation switch SW1 can be turned on in response to a high-level compensation control signal BC during the bit line precharge period, and the current source can sink a predetermined or optionally desired compensation current. In some embodiments, the compensation current can be set to be the same as or similar to the leakage current flowing into the word line WL. Therefore, the leakage current can be compensated by the current source.

[0195] Figure 21 This is a diagram illustrating an example of an embodiment of the inventive concept applied to a 3D memory device. Figure 21 In the diagram, the memory cell array is shown as including a first layer and a second layer, but more layers can be provided in the memory cell array.

[0196] Reference Figure 21 The memory device 200a may include a peripheral layer 201a in which a peripheral region including peripheral circuitry is disposed, and a first layer 202a and a second layer 203a in which memory cells are disposed. Each of the first layer 202a and the second layer 203a may include a plurality of memory cells and word lines / bit lines connected to the plurality of memory cells. Additionally, although in Figure 21 An example of an outer layer 201a including a write driver / sensor amplifier (WD / SA) and control logic is shown, but various types of peripheral circuitry related to memory operations can be located in the outer layer. Additionally, the write driver / sensor amplifier can be shared by the first layer 202a and the second layer 203a.

[0197] As referenced above Figure 5A and Figure 5B As described, the first layer 202a and the second layer 203a can share at least one signal line in the 3D memory device. The first layer 202a and the second layer 203a can share a word line or a bit line. In the multiple layers of the stacked structure, the word lines and bit lines of the second layer 203a can have a larger capacitance component (or a larger load) than the word lines and bit lines of the first layer 202a. Furthermore, according to an example embodiment of the above-described inventive concept, during a data read operation, the word line selection signal applied to the word line selection transistor can be controlled differently in the first layer 202a and the second layer 203a. Additionally, according to an example embodiment of the above-described inventive concept, during a data read operation, the unselected word lines adjacent to the selected word line can be controlled differently in the first layer 202a and the second layer 203a.

[0198] Figure 22This is a block diagram illustrating an example of a memory device applied to an SSD system according to an embodiment of the inventive concept.

[0199] Reference Figure 22 The SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 can exchange signals SGL with the host 1100 via a signal connector and can receive power PWR via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and a plurality of non-volatile memory devices 1230, 1240, and 1250. At least one of the plurality of non-volatile memory devices 1230, 1240, and 1250 may be a resistive memory device, and the memory device according to the example embodiment of the inventive concept may be applied as one of the plurality of non-volatile memory devices 1230, 1240, and 1250.

[0200] SSD controller 1210 can be connected to multiple memory devices 1230, 1240 and 1250 through multiple channels Ch1 to Chn, so that data can be stored in or read from the multiple memory devices 1230, 1240 and 1250.

[0201] Figure 23 This is a block diagram illustrating implementations of a memory system according to various embodiments of the inventive concept. Figure 23 The image shows an example of a memory system 2000 including a memory module 2200, and the memory module 2200 may correspond to the memory device in the above embodiments or may include multiple memory devices in the above embodiments.

[0202] Reference Figure 23 The memory controller 2100 can control the overall operation of the memory system 2000. Although in Figure 23 Not shown, but the memory controller 2100 may also include various other components (such as a command / address generator, host I / F, and memory I / F) as components for controlling memory operations.

[0203] Memory module 2200 may include multiple memory chips mounted on a module board. For example, memory module 2200 may include first memory chips 2210_1 to Nth memory chips 2210_N. Furthermore, each of the first memory chips 2210_1 to Nth memory chips 2210_N may correspond to the memory device in the above embodiments; therefore, each of the first memory chips 2210_1 to Nth memory chips 2210_N may include control logic for performing various control operations related to data reading in the above embodiments. For example, in the data reading operation of the first memory chips 2210_1 to Nth memory chips 2210_N, the word line selection transistor may be weakly turned on during the bit line precharge period, and the voltage level of the word line selection signal applied to weakly turn on the word line selection transistor may be different in the first layer and the second layer. Additionally, unselected word lines adjacent to the selected word line may be floated during the bit line precharge period, and the number of floated unselected word lines in the first layer and the second layer may be different.

[0204] The memory module 2200 can be implemented as a single in-line memory module (SIMM) or a dual in-line memory module (DIMM). Furthermore, the memory module 2200 can correspond to various types of DIMMs, and various types of DIMMs such as FB-DIMM and LR-DIMM can be applied to the memory module 2200. Optionally, the memory module 2200 can correspond to a non-volatile DIMM (NVDIMM) in which non-volatile memory 2220 is installed to compensate for the problem of data loss in volatile memory during power failure.

[0205] Furthermore, as various types of modules, when the memory module 2200 includes a PRAM as a resistive memory, the memory module 2200 can be referred to as a P_DIMM. In addition to the above, embodiments of the inventive concept can also be applied to various types of modules. For example, since the memory module 2200 may include a crosspoint memory chip having resistive memory cells of the 3D type, the memory module 2200 can be referred to as a crosspoint DIMM or a 3D crosspoint DIMM.

[0206] When memory module 2200 corresponds to an NVDIMM, it can operate based on various specifications such as NVDIMM-N and NVDIMM-P. Therefore, the non-volatile memory 2220 can be used for data storage or as a buffer. Furthermore, each of the first memory chip 2210_1 to the Nth memory chip 2210_N can operate based on Double Data Rate (DDR) for transmitting and receiving data on both the rising and falling edges of the clock. Memory module 2200 can be installed in a DDR slot. For example, memory module 2200 can be installed in a DDR slot such as DDR4 or DDR5 to operate based on the corresponding specifications. Additionally, according to the above embodiments... Figure 1 The memory device 200 can be used to implement the non-volatile memory 2220 of the memory module 2200.

[0207] Figure 24 This is a block diagram illustrating an example of a memory device used as a buffer for a controller according to an embodiment of the inventive concept.

[0208] Reference Figure 24 The memory system 3000 may include a controller 3100 and a flash memory device 3200, and the flash memory device 3200 may include flash memory cells 3210 and control logic 3220. Additionally, the controller 3100 may include a flash translation layer (FTL) 3110 and a buffer 3120 for temporarily storing data DATA and metadata provided to the flash memory device 3200. The controller 3100 may control the flash memory device 3200 to read data stored in the flash memory cells 3210 or to program data into the flash memory cells 3210 in response to write / read requests from the host. Specifically, the controller 3100 may control programming, reading, and erasing operations on the flash memory device 3200 by providing the flash memory device 3200 with an address ADDR, a command CMD, and a control signal CTRL.

[0209] Buffer 3120 may include a memory device according to the above embodiments, and therefore buffer 3120 may include a resistive memory device. Additionally, according to the above embodiments, data sensing operations can be performed based on pseudo-float operations of word lines and / or bit lines when temporarily storing and retrieving data DATA and metadata from the resistive memory device.

[0210] The controller 3100, and any other elements described above (e.g., memory controller 100, write / read circuitry 220, control logic 230, etc.), may include processing circuitry (such as hardware including logic circuitry), hardware / software combinations (such as a processor executing software), or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0211] In the above embodiments, the memory device is described as including resistive memory; however, embodiments of the inventive concept are not necessarily limited thereto. As an example, embodiments of the inventive concept can be applied to various types of memory devices that perform data sensing based on pre-charge operations on word lines and / or bit lines. For example, embodiments of the inventive concept can be applied to various types of volatile and non-volatile memories such as DRAM, mobile DRAM, SRAM, or flash memory devices.

[0212] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device comprising: an array of memory cells including a plurality of memory cells in a region where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including a plurality of row switches corresponding to the plurality of word lines and configured to perform a selection operation on the plurality of word lines; a column decoder including a plurality of column switches corresponding to the plurality of bit lines and configured to perform a selection operation on the plurality of bit lines; and control logic configured to control a pre-charge operation performed on a selected word line connected to a selected memory cell in a word line pre-charge period in a data read operation, and to control a pre-charge operation performed on a selected bit line connected to the selected memory cell in a bit line pre-charge period after the word line pre-charge period; wherein the row switch connected to the selected word line is weakly turned on in the bit line pre-charge period in response to a control signal at a weak turn-on level, wherein the control signal at the weak turn-on level is applied to the row switch in the bit line pre-charge period, wherein the weak turn-on level is a level between a turn-on level for turning on the row switch and an off level for turning off the row switch.

2. The memory device of claim 1, further comprising a sense amplifier connected to the selected word line to detect data of the selected memory cell by comparing a voltage of the selected word line to a reference voltage.

3. The memory device of claim 1, wherein the row switch is turned on to pre-charge the selected word line in the word line pre-charge period, and the row switch is weakly turned on in the bit line pre-charge period such that the selected word line is pseudo floated.

4. The memory device of claim 1, wherein the row switch includes a transistor including a drain terminal connected to the selected word line, a gate terminal to which the control signal is applied, and a source terminal connected to a data line, and the weak turn-on level of the control signal is lower than the turn-on level and higher than the off level. the array of memory cells each include a plurality of memory cells and each include a first tier and a second tier stacked vertically, and 5. The memory device of claim 1, wherein, wherein when a read operation is performed on a first memory cell of the first tier, a control signal at a first level is applied to a first row switch connected to the first memory cell in the bit line pre-charge period, and when a read operation is performed on a second memory cell of the second tier, a control signal at a second level is applied to a second row switch connected to the second memory cell in the bit line pre-charge period, and the first level and the second level are different.

6. The memory device of claim 5, wherein the first level is a level between the turn-on level and the off level, and the second level is the off level. the first level and the second level are levels between the turn-on level and the off level.

7. The memory device of claim 5, wherein, the first tier and the second tier share the plurality of bit lines.

8. The memory device of claim 5, wherein, each of the first memory cell of the first tier and the second memory cell of the second tier includes a selector device tier and a variable resistance layer stacked on the selector device tier.

9. The memory device of claim 5, wherein, 10. The memory device of claim 5, wherein ​ The first memory cell of the first layer includes a first selector device layer stacked on a first word line, a first variable resistance layer stacked on the first selector device layer, and a bit line stacked on the first variable resistance layer, and The second memory cell of the second layer includes a second selector device layer stacked on the bit line, a second variable resistance layer stacked on the second selector device layer, and a second word line stacked on the second variable resistance layer.

11. The memory device of claim 1, wherein, The plurality of memory cells includes a first memory cell and a second memory cell positioned farther from the column decoder than the first memory cell, and wherein, when a read operation is performed on the first memory cell, a third level of a control signal is applied to a first row switch connected to the first memory cell in a bit line pre-charge period, and when a read operation is performed on the second memory cell, a fourth level of a control signal is applied to a second row switch connected to the second memory cell in the bit line pre-charge period, and the third level and the fourth level are different.

12. The memory device of claim 11, wherein, The third level and the fourth level are levels between an on level and an off level, and wherein the fourth level is higher than the third level.

13. The memory device of claim 1, further comprising a compensation switch and a current source connected to a selected word line, wherein, when the compensation switch is turned on in the bit line pre-charge period and the current source is electrically connected to the selected word line, a leakage current generated in the selected word line is compensated.

14. The memory device of claim 1, wherein, Each of the plurality of memory cells includes a variable resistance device including a phase change material.

15. A memory device, the memory device comprising: an array of memory cells including a first layer and a second layer stacked and sharing a plurality of bit lines, wherein each of the first layer and the second layer includes a plurality of memory cells located in an area where a plurality of word lines and the plurality of bit lines cross each other; a row decoder including a plurality of row switches corresponding to the plurality of word lines and configured to perform a selection operation on the plurality of word lines; a column decoder including a plurality of column switches corresponding to the plurality of bit lines and configured to perform a selection operation on the plurality of bit lines; a word line pre-charge device configured to apply a word line pre-charge voltage to a selected word line selected by the row decoder in a word line pre-charge period; a bit line pre-charge device configured to apply a bit line pre-charge voltage to a selected bit line selected by the column decoder in a bit line pre-charge period; and a comparator comparing a voltage of the selected word line with a reference voltage and outputting a comparison result, wherein, when a data read operation is performed on a first memory cell of the first layer, a first word line selection signal of a first level is applied to a first row switch connected to the first memory cell to turn on the first row switch in the word line pre-charge period, and a first word line selection signal of a third level between a second level for turning off the first row switch and the first level is applied to the first row switch in the bit line pre-charge period.

16. The memory device of claim 15, wherein, When a data read operation is performed on the second memory cell of the second tier, a second word line select signal at a first level is applied to the second row switch connected to the second memory cell in a word line pre-charge period, and a second word line select signal at a second level is applied to the second row switch in a bit line pre-charge period.

17. The memory device of claim 16, wherein, When a data read operation is performed on the first memory cell, a first word line connected between the first memory cell and the first row switch is pseudo-floated in a bit line pre-charge period, and When a data read operation is performed on the second memory cell, a second word line connected between the second memory cell and the second row switch is floated in a bit line pre-charge period.

18. The memory device of claim 17, wherein, When a data read operation is performed on the first memory cell, an inhibit voltage is applied to unselected word lines of the first tier in a bit line pre-charge period, and When a data read operation is performed on the second memory cell, at least one unselected word line among the unselected word lines of the second tier is floated in a bit line pre-charge period.

19. A memory module, the memory module comprising: a module board; a plurality of memory chips located on the module board; and a non-volatile memory located on the module board and in communication with the plurality of memory chips, each of the plurality of memory chips comprising: an array of memory cells including a first tier and a second tier stacked and sharing a plurality of bit lines, wherein each of the first tier and the second tier includes a plurality of memory cells located in an area where a plurality of word lines and the plurality of bit lines cross each other; a row decoder including a plurality of row switches corresponding to the plurality of word lines and configured to perform a selection operation on the plurality of word lines; a column decoder including a plurality of column switches corresponding to the plurality of bit lines and configured to perform a selection operation on the plurality of bit lines; and control logic configured to control a pre-charge operation of word lines and bit lines of a selected memory cell, wherein, when a read operation is performed on a first memory cell of the first tier, a first word line select signal at a weak-on level is applied to a first row switch connected to the first memory cell in a bit line pre-charge period, wherein the weak-on level is a level between an on level for turning on the first row switch and an off level for turning off the first row switch, and wherein, when a read operation is performed on a second memory cell of the second tier, a second word line select signal at an off level is applied to a second row switch connected to the second memory cell in a bit line pre-charge period.

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