Chip fuses with high breaking capacity

Abstract

A high interrupting capability chip fuse includes a bottom insulating layer, a first intermediate insulating layer, a second intermediate insulating layer, and a top insulating layer arranged in that order in a stacked arrangement; a fusible element disposed between the first intermediate insulating layer and the second intermediate insulating layer and extending between electrically conductive first and second terminals, the first and second terminals being at opposite longitudinal ends of the bottom insulating layer, the first intermediate insulating layer, the second intermediate insulating layer, and the top insulating layer; wherein the first intermediate insulating layer and the second intermediate insulating layer are formed of a porous ceramic.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 906,024, filed on September 25, 2019, the entirety of which is incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of circuit protection devices, and more specifically to a chip fuse having a porous inner layer adapted to absorb energy from a fusible element that has been fused. Background Technology

[0004] Surface mount fuses (often also called "solid" fuses) typically consist of a fusible element that extends between two conductive end caps and is sandwiched between two or more layers of dielectric material (e.g., ceramic). When the fusible element of a surface mount fuse melts or otherwise breaks under an overcurrent condition, an electric arc can sometimes propagate between the separated parts of the fusible element. The arc can rapidly heat the surrounding air and ambient particles and may cause a small explosion within the surface mount fuse. In some cases, the explosion can damage the dielectric layers and cause the surface mount fuse to break, potentially damaging surrounding components. The likelihood of breakage is generally proportional to the severity of the overcurrent condition. The maximum current a surface mount fuse can break without breaking is called its "breaking capacity." It is generally desirable to maximize the breaking capacity of a surface mount fuse without significantly increasing its size or form factor.

[0005] In light of these and other considerations, the improvements of the present invention can be useful. Summary of the Invention

[0006] The present invention is provided in a simplified form to introduce some conceptual options, which will be further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0007] A high breaking capacity patch fuse according to a non-limiting embodiment of the present disclosure may include: a bottom insulating layer, a first intermediate insulating layer, a second intermediate insulating layer, and a top insulating layer (which are arranged in a stacked manner in the above order); a fusible element disposed between the first intermediate insulating layer and the second intermediate insulating layer and extending between a conductive first terminal and a second terminal, the first terminal and the second terminal being located at opposite longitudinal ends of the bottom insulating layer, the first intermediate insulating layer, the second intermediate insulating layer, and the top insulating layer; wherein the first intermediate insulating layer and the second intermediate insulating layer are formed of porous ceramic.

[0008] A method for forming a patch fuse with high breaking capacity according to a non-limiting embodiment of the present disclosure may include: providing a bottom insulating layer, a first intermediate insulating layer, a second intermediate insulating layer, and a top insulating layer (which are arranged in a stacked manner in the order described above); and disposing a fusible element between the first intermediate insulating layer and the second intermediate insulating layer, the fusible element extending between a conductive first terminal and a second terminal, the first terminal and the second terminal being located at opposite longitudinal ends of the bottom insulating layer, the first intermediate insulating layer, the second intermediate insulating layer, and the top insulating layer; wherein the first intermediate insulating layer and the second intermediate insulating layer are formed of porous ceramic. Attached Figure Description

[0009] As an example, various embodiments of the disclosed system will now be described with reference to the accompanying drawings, in which:

[0010] Figure 1A This is a perspective view illustrating a patch fuse with high breaking capacity according to an exemplary embodiment of the present disclosure;

[0011] Figure 1B It is shown Figure 1A The diagram shows a cross-sectional view of a patch fuse with high breaking capacity. Detailed Implementation

[0012] A high breaking capacity surface mount fuse according to the present disclosure will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the high breaking capacity surface mount fuse are presented. However, it will be understood that the high breaking capacity surface mount fuse described below can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will convey certain exemplary aspects of a high breaking capacity surface mount fuse to those skilled in the art.

[0013] Reference Figure 1A and Figure 1BA perspective view and a cross-sectional side view of a high-breaking-capacity patch fuse 10 (hereinafter referred to as "fuse 10") according to an exemplary non-limiting embodiment of the present disclosure are presented. Fuse 10 may include a bottom insulating layer 12, a first intermediate insulating layer 14, a second intermediate insulating layer 16, and a top insulating layer 18, which are arranged in a stacked manner in the order described above. Layers 12-18 may be bonded planarly to each other, such as using epoxy resin or other electrically insulating adhesives or fasteners. Although fuse 10 presented and described herein has only two intermediate insulating layers (first intermediate insulating layer 14 and second intermediate insulating layer 16), it is contemplated that fuse 10 may be provided with additional intermediate insulating layers without departing from the scope of the invention. For example, fuse 10 may be provided with a third intermediate insulating layer disposed between the bottom insulating layer 12 and the first intermediate insulating layer 14, and / or a fourth intermediate insulating layer disposed between the top insulating layer 18 and the second intermediate insulating layer 16. The present disclosure is not limited thereto.

[0014] The fuse 10 may further include a fusible element 20 disposed between (e.g., sandwiched between) a first intermediate insulating layer 14 and a second intermediate insulating layer 16 and extending between conductive first terminals 22 and second terminals 24 located at opposite longitudinal ends of layers 12-18. The fusible element 20 may be formed of a conductive material including, but not limited to, tin or copper, and may be formed as a conductive core, wire, strip, metal chain, spiral wound wire, film, etc., deposited on a substrate. The fusible element 20 may be configured to melt and separate upon occurrence of a predetermined fault condition in the fuse 10 (e.g., an overcurrent condition in which a current exceeding a predetermined maximum current (i.e., the "rated value" of the fuse 10) flows through the fusible element 20). As will be understood by those skilled in the art, the size, shape, construction, and material of the fusible element 20 may contribute to the rated value of the fuse 10.

[0015] The bottom insulating layer 12 and top insulating layer 18 of the fuse 10 can be formed of any suitable dielectric material and are generally non-porous, wherein the dielectric material includes, but is not limited to, FR-4, glass, ceramics (e.g., low-temperature co-fired ceramics), etc. The first intermediate insulating layer 14 and the second intermediate insulating layer 16 of the fuse 10 can be formed of porous ceramics (e.g., low-temperature co-fired ceramics) in which a plurality of hollow pores 26 are formed. The porous ceramics of the first intermediate insulating layer 14 and the second intermediate insulating layer 16 can be made by incorporating particles or microparticles of one or more temporary (fugitive) materials (e.g., carbon, corn starch, etc.) into the ceramic prior to firing / curing. During firing / curing, the microparticles of the temporary material can be burned off, thereby leaving hollow pores 26 within the ceramic. This disclosure is not limited thereto.

[0016] In various embodiments, the porosity of the first intermediate insulating layer 14 and the second intermediate insulating layer 16 may be greater than the porosity of the bottom insulating layer 12 and the top insulating layer 18 of the fuse 10. In a particular embodiment, the porosity of the first intermediate insulating layer 14 and the second intermediate insulating layer 16 may be 25% greater than the porosity of the bottom insulating layer 12 and the top insulating layer 18 of the fuse 10. In another embodiment, the porosity of the first intermediate insulating layer 14 and the second intermediate insulating layer 16 may be 50% greater than the porosity of the bottom insulating layer 12 and the top insulating layer 18 of the fuse 10. In another embodiment, the porosity of the first intermediate insulating layer 14 and the second intermediate insulating layer 16 may be 75% greater than the porosity of the bottom insulating layer 12 and the top insulating layer 18 of the fuse 10. In yet another embodiment, the porosity of the first intermediate insulating layer 14 and the second intermediate insulating layer 16 may be 100% greater than the porosity of the bottom insulating layer 12 and the top insulating layer 18 of the fuse 10. This disclosure is not limited thereto.

[0017] During operation of fuse 10, if an overcurrent condition causes the fusible element 20 to melt and explode, the first intermediate insulation layer 14 and the second intermediate insulation layer 16, which are relatively weaker and more porous than the bottom insulation layer 12 and the top insulation layer 18 and are therefore more prone to breakage, will fracture due to the presence of holes 26 and can absorb the energy of the explosion (e.g., in the manner of a crash buffer in a car), thereby preventing a large amount of energy from the explosion from being transferred to the bottom insulation layer 12 and the top insulation layer 18. Furthermore, the vaporized material of the molten fusible element 20 can be rapidly cleared into the holes 26 of the fractured first intermediate insulation layer 14 and the second intermediate insulation layer 16, thereby preventing such vaporized material from feeding and prolonging the arc between the separated parts of the fusible element 20. Therefore, the risk of fuse 10 rupture is mitigated by the fracture of the first intermediate insulation layer 14 and the second intermediate insulation layer 16, and thus the breaking capacity of the fuse 10 of this disclosure can be relatively greater compared to the breaking capacity of a patch fuse without the porous first intermediate insulation layer 14 and the second intermediate insulation layer 16.

[0018] As used herein, elements or steps described in the singular and beginning with the word "a" or "an" should be understood to not exclude multiple elements or steps unless such exclusion is explicitly stated. Furthermore, references to "one embodiment" in this disclosure are not intended to be construed as excluding the existence of other embodiments that also include the described features.

[0019] Although this disclosure references certain embodiments, various modifications, alterations, and changes can be made to the described embodiments without departing from the scope and range of this disclosure as defined by the appended claims. Therefore, it is intended that this disclosure is not limited to the described embodiments, but has the full scope defined by the language of the appended claims and their equivalents.

Claims

1. A high interrupting capability chip fuse comprising: a bottom insulating layer, a first intermediate insulating layer, a second intermediate insulating layer, and a top insulating layer arranged in a stack; and a fusible element disposed between the first and second intermediate insulating layers and extending between electrically conductive first and second terminals, the first and second terminals being located at opposite longitudinal ends of the bottom, first, second, and top insulating layers, the first and second intermediate insulating layers extending continuously from the electrically conductive first terminal to the electrically conductive second terminal and completely shielding the fusible element from the bottom and top insulating layers; wherein each of the first and second intermediate insulating layers is formed from a single unitary ceramic layer having a plurality of hollow voids encased therein that weaken the first and second intermediate insulating layers to fracture upon the fusible element melting and exploding.

2. The high breaking capacity surface mount fuse of claim 1, wherein, The fusible element is one of: an electrically conductive core, wire, ribbon, metal chain, film deposited on a substrate.

3. The high interrupting capability surface mount fuse of claim 1, wherein, The first and second intermediate insulating layers have a porosity greater than the bottom and top insulating layers.

4. The high interrupting capability surface mount fuse of claim 3 wherein, The first and second intermediate insulating layers have a porosity at least 25% greater than the bottom and top insulating layers.

5. The high interrupting capability surface mount fuse of claim 3 wherein, The first and second intermediate insulating layers have a porosity at least 50% greater than the bottom and top insulating layers.

6. The high interrupting capability surface mount fuse of claim 3 wherein, The first and second intermediate insulating layers have a porosity at least 75% greater than the bottom and top insulating layers.

7. The high interrupting capability surface mount fuse of claim 3 wherein, The first and second intermediate insulating layers have a porosity at least 100% greater than the bottom and top insulating layers.

8. The high interrupting capability surface mount fuse of claim 1, wherein, The bottom and top insulating layers are formed from one of: FR-4, glass, and ceramic.

9. The high interrupting capability surface mount fuse of claim 1, wherein, The bottom, first, second, and top insulating layers are flatly joined to one another with an electrically conductive insulating adhesive.

10. A method of forming a high interrupting capability chip fuse comprising: providing a bottom insulating layer, a first intermediate insulating layer, a second intermediate insulating layer, and a top insulating layer arranged in a stack; and disposing a fusible element between the first and second intermediate insulating layers, the fusible element extending between electrically conductive first and second terminals, the first and second terminals being located at opposite longitudinal ends of the bottom, first, second, and top insulating layers, the first and second intermediate insulating layers extending continuously from the electrically conductive first terminal to the electrically conductive second terminal and completely shielding the fusible element from the bottom and top insulating layers. wherein each of the first and second intermediate insulating layers is formed of a single unitary ceramic layer having a plurality of hollow voids encased therein that weaken the first and second intermediate insulating layers to break upon the fusible element melting and exploding.

11. The method of claim 10, wherein, The fusible element is one of: a conductive core, wire, ribbon, metal chain, film deposited on a substrate.

12. The method of claim 10, wherein, The first and second intermediate insulating layers have a porosity greater than the bottom and top insulating layers.

13. The method of claim 12, wherein, The first and second intermediate insulating layers have a porosity at least 25% greater than the bottom and top insulating layers.

14. The method of claim 12, wherein, The first and second intermediate insulating layers have a porosity at least 50% greater than the bottom and top insulating layers.

15. The method of claim 12, wherein, The first and second intermediate insulating layers have a porosity at least 75% greater than the bottom and top insulating layers.

16. The method of claim 12, wherein, The first and second intermediate insulating layers have a porosity at least 100% greater than the bottom and top insulating layers.

17. The method of claim 10, wherein, The bottom and top insulating layers are formed of one of: FR-4, glass, and ceramic.

18. The method of claim 10, further comprising: The single unitary ceramic layer having the plurality of hollow voids encased therein is formed by mixing microparticles of one or more fugitive materials into a ceramic and then firing the ceramic to burn out the microparticles of the one or more fugitive materials, leaving the plurality of hollow voids within the ceramic.

19. The method of claim 18, wherein, The fugitive material includes at least one of: carbon and corn starch.

20. The method of claim 10, further comprising: The bottom, first intermediate, second intermediate, and top insulating layers are joined to one another flatly with a conductive insulating adhesive. The first and second intermediate insulating layers have a porosity at least 25% greater than the bottom and top insulating layers.

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