Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device is provided. According to one embodiment, the method includes forming a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material on a substrate; forming a semiconductor cap layer on the first fin and the second fin; and annealing the semiconductor cap layer at a first temperature while exposing at least a portion of the semiconductor cap layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor technology, and more particularly to a method for manufacturing a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. During IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while feature size (i.e., the smallest component that can be formed using a manufacturing process) has decreased. This process miniaturization has generally yielded benefits by increasing production efficiency and reducing associated costs. However, this miniaturization has also been accompanied by increased complexity in the design and manufacture of the devices that incorporate these ICs, and achieving these advances requires similar developments in device manufacturing.

[0003] As IC device geometries continue to shrink, defects that were previously insignificant to the performance of conventional large-scale devices can now significantly impact device performance. For example, p-type fully strained channel technology has been developed to improve hole mobility within p-type transistors. A silicon cap layer can be formed over the p-type fully strained channel to prevent undesirable oxidation of the semiconductor material in the p-type channel. It has been observed that a high density of interface trapped charges can exist at the interface between the silicon cap layer and the p-type fully strained channel, leading to leakage current and increased channel resistance. Therefore, while conventional p-type fully strained channel devices are adequate for their intended purpose, they are not satisfactory in all respects. Summary of the Invention

[0004] A method for manufacturing a semiconductor device includes: forming a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material on a substrate; forming a semiconductor cap layer on the first fin and the second fin; and annealing the semiconductor cap layer at a first temperature while exposing at least a portion of the semiconductor cap layer.

[0005] A method for manufacturing a semiconductor device includes: forming a first fin including silicon and germanium on a substrate; forming a second fin including silicon on the substrate; forming a silicon cap layer on the first fin and the second fin; performing a first anneal at a first temperature and a first pressure while exposing at least a portion of the silicon cap layer; forming source / drain features on the source / drain regions of the first fin and the second fin; forming a gate structure above the channel region of the first fin and the second fin; and after forming the gate structure, performing a second anneal at a second temperature and a second pressure while not exposing any portion of the silicon cap layer.

[0006] A method for manufacturing a semiconductor device includes: forming a first fin including silicon and germanium on a substrate; forming a second fin including silicon on the substrate; forming a silicon cap layer above the first fin and the second fin, and immediately after forming the silicon cap layer, performing a first annealing at a temperature between approximately 800°C and 1050°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A flow chart illustrating a method for fabricating a semiconductor device on a workpiece according to some embodiments is shown.

[0008] Figure 2-Figure 12 The working components according to some embodiments are shown in FIG. Figure 1 Schematic diagram of partial cross-sections of different steps in the method.

[0009] Description of reference numerals:

[0010] 100: Method

[0011] 102, 104m, 106, 108, 110, 112, 114, 116A, 116B, 118: Blocks

[0012] 200: Working parts

[0013] 202: Base

[0014] 202N: n-well

[0015] 202P: p-well

[0016] 204: Second semiconductor material

[0017] 206: First semiconductor material

[0018] 208: Silicon top layer

[0019] 210: First hard mask layer

[0020] 211: Hard mask

[0021] 212: Second hard mask layer

[0022] 214: Lining

[0023] 216: p-type fin

[0024] 216A: First fin

[0025] 216B, 218B: adjacent fins

[0026] 218: n-type fin

[0027] 218A: Second fin

[0028] 219: Dielectric Materials

[0029] 220: Isolation Structure

[0030] 222: Silicon cap layer

[0031] 224: Interface layer

[0032] 226, 228: Source / drain features

[0033] 230: Gate spacer

[0034] 232: Interlayer dielectric (ILD) layer

[0035] 234: Metal Gate Stack

[0036] 236: Silicide layer

[0037] 238, 240: Source / drain contact electrodes

[0038] 300: Annealing process / post-silicon cover annealing (PSA) process

[0039] 400: High pressure annealing (HPA) process DETAILED DESCRIPTION

[0040] The following disclosure provides many different embodiments or examples for implementing the different characteristic components of the present invention. The following disclosure describes specific examples of each component and its arrangement in order to simplify the disclosure. Of course, these are merely examples and are not intended to define the present invention. For example, if the following disclosure describes forming a first characteristic component on or above a second characteristic component, it means that it includes an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which additional characteristic components can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the disclosure will repeat numbers and / or text in each different example. The repetition is for the purpose of simplicity and clarity, rather than to specify the relationship between the different embodiments and / or configurations being discussed.

[0041] Furthermore, in the subsequent descriptions herein, forming a feature on, connecting to, and / or coupling to another feature may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features are inserted between the features so that the features are not in direct contact. In addition, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above," "above," "below," "below," "upward," "downward," "below," "top," "bottom," and their derivatives (e.g., "horizontal," "downward," "upward," etc.) are used to facilitate descriptions of the relationship between one feature and another in the embodiments herein. Spatially relative terms are intended to encompass different orientations of a device having a feature. Furthermore, when "about," "approximately," etc. are used to describe a value or range of values, such terms are intended to encompass values ​​within a reasonable range including the stated value, such as + / - 10% of the stated value, or any other value understood by a person of ordinary skill in the art. For example, the term "approximately 5 nm" encompasses a range from 4.5 nm to 5.5 nm.

[0042] As IC device sizes shrink, the short channel effect (SCE) hinders further scaling of planar field effect transistors (FETs). Various multi-gate devices have been proposed to enhance gate control and prevent the short channel effect. One example of these multi-gate devices is the fin-shaped field effect transistor (FinFET). Improved FinFETs have been proposed over the years. For example, the mobility of charge carriers (i.e., electrons in n-type devices and holes in p-type devices) can be increased by forming a FinFET with a strained channel. The materials used in the strained channel may be different for p-type field effect transistors (PFETs) and n-type field effect transistors (NFETs). By way of example and not limitation, electron mobility in NFETs can be enhanced by using a fully strained silicon / carbon-doped silicon (Si / Si:C) channel, while hole mobility in PFETs can be enhanced by using a fully strained silicon germanium (SiGe) channel. Epitaxial growth can be used to form fully strained silicon / carbon-doped silicon (Si / Si:C) channels and fully strained silicon germanium (SiGe) channels.

[0043] A fully strained epitaxial channel can be formed from an epitaxial layer atop a silicon (Si) fin. The fabrication process for a fully strained channel requires numerous lithography, etching, pretreatment, annealing, and growth steps. To further strain the p-type channel and prevent unwanted oxidation of the germanium, a silicon capping layer can be formed on the active component to cover the fully strained p-type channel. The properties of the silicon capping layer have been observed to affect semiconductor device performance. When the silicon capping layer lacks crystallinity, it may oxidize too quickly and may not adequately prevent oxidation of the germanium contained within the p-type channel. Furthermore, when the silicon capping layer contains defects at its interface with the p-type channel, it may increase the density of interface trap charges (DITs), leading to leakage current, reduced carrier mobility, and increased channel resistance. For example, compared to an n-type fully strained channel (NFSC) (using Si, Si:C, or a combination thereof), a p-type fully strained channel (PFSC) is susceptible to defects resulting from a large lattice mismatch between Si and SiGe.

[0044] Figure 1 A flow chart of a method 100 for fabricating a semiconductor device on a workpiece 200 is shown. Figure 1 Will refer to Figure 2-Figure 12 (which shows a partial cross-sectional schematic diagram of the working component 200 at different steps in different embodiments of the method 100 according to the embodiment of the present invention) for illustration. Additional steps may be provided before, during, and after the method 100, and for other embodiments of the method 100, some of the steps described may be moved, replaced, or eliminated. Figure 2-Figure 12 The working part 200 shown in FIG. 1 is provided with other features. Figure 2-Figure 12In other embodiments of the illustrated working unit 200, some of the features described below may be replaced, modified, or eliminated. Because a semiconductor device is formed from the working unit 200 after the manufacturing process is completed, for convenience, the working unit 200 is sometimes referred to as a semiconductor device 200 in the embodiments herein. The semiconductor device 200 may be included in a microprocessor, memory, and / or other integrated circuit (IC) devices. In some embodiments, the semiconductor device 200 is part of an IC chip, a system on a chip (SoC), or a portion thereof, and includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0045] Reference Figure 1 、 Figure 2 and Figure 3 The method 100 includes block 102, wherein a first fin 216A having a first semiconductor material 206 and a second fin 218A having a second semiconductor material 204 are disposed on a substrate 202. Figure 2, which shows substrate 202 including an n-type well region (n-well) 202N and a p-type well region (p-well) 202P. Substrate 202 may include silicon. Alternatively or additionally, substrate 202 may include another elemental semiconductor (e.g., germanium), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (e.g., silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP), or a combination thereof. In some embodiments, substrate 202 includes one or more Group III-V materials, one or more Group II-IV materials, or a combination thereof. In some embodiments, substrate 202 is a semiconductor-on-insulator (SIO) substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate can be manufactured by separation by implantation of oxygen (SIMOX), wafer bonding and / or other suitable methods. Figure 2 In the illustrated embodiment, substrate 202 is substantially composed of silicon. The n-well 202N includes an n-type dopant, such as phosphorus, arsenic, other n-type dopant, or a combination thereof. The p-well 202P includes a p-type dopant, such as boron, indium, other p-type dopant, or a combination thereof. The n-well 202N and the p-well 202P can be formed directly on and / or within the substrate 202 by ion implantation, diffusion, and / or other suitable doping processes.

[0046] After forming the n-well 202N and the p-well 202P, a film layer comprising a first semiconductor material 206 and a film layer comprising a second semiconductor material 204 are formed on the workpiece 200. The film layer comprising the second semiconductor material 204 is first epitaxially grown on the substrate 202. A portion of the film layer comprising the second semiconductor material 204 is removed to form a recess, and then a film layer comprising the first semiconductor material 206 is epitaxially grown to fill the recess. In some embodiments, the film layer comprising the second semiconductor material 204 is not grown directly from the substrate 202. In those embodiments, a seed layer (not shown) may be formed on the substrate 202, and then the film layer comprising the second semiconductor material 204 is formed on the seed layer. In some embodiments, the second semiconductor material 204 may comprise silicon, carbon, or a combination thereof. In some embodiments, the first semiconductor material 206 may comprise silicon, germanium, or a combination thereof. In some cases where the first semiconductor material 206 comprises silicon and germanium, the germanium content of the first semiconductor material 206 may be between 20% and 80%. For illustrative purposes, the following example assumes that the second semiconductor material 204 is formed from silicon. The film layer comprising the second semiconductor material 204 is epitaxially grown to a thickness between about 50 nm and about 100 nm using a raw material gas such as silane (SiH4), silicon tetrachloride (SiCl4), trichlorosilane (TCS), or dichlorosilane (SiH2Cl2 or DCS (dichlorosilane)). Hydrogen (H2) may be used as a reaction gas to reduce the above raw material gases. Depending on the gas used, the deposition temperature during the epitaxial layer formation may be in the range of about 700°C to 1250°C. For example, a raw material gas with fewer chlorine atoms (e.g., DCS) may require a lower formation temperature than a raw material gas with more chlorine atoms (e.g., SiCl4 or TCS). The aforementioned ranges and types of gases are provided as examples only and are not intended to be limiting. In order to form recesses in the film layer comprising the second semiconductor material 204, a hard mask formed of a dielectric material may be formed thereon. The hard mask may be formed of silicon oxide or silicon nitride. A photolithography process is then performed to pattern the hard mask. An etching process is then performed using the patterned hard mask as an etch mask to etch a recess within the film layer comprising the second semiconductor material 204. The etching process can be a dry etching process or a wet etching process using an appropriate etching chemistry. In some embodiments, the etching process to form the recess does not remove all of the second semiconductor material 204 at the bottom of the recess, so that the thickness of the second semiconductor material 204 at the bottom can serve as a seed layer for the first semiconductor material 206 that fills the recess. A film layer comprising the first semiconductor material 206 is then formed to fill the recess within the film layer comprising the second semiconductor material 204.According to some embodiments, the film layer having the first semiconductor material 206 is epitaxially grown at a temperature between approximately 550° C. and 700° C. using a precursor gas (e.g., SiH 4 , Si 2 H 6 , SiH 2 Cl 2 , GeH 4 , HCl, or a combination thereof) and a reactant gas (e.g., H 2 , N 2 , or Ar, or a combination thereof).

[0047] After epitaxially growing the first semiconductor material 206 to fill the recess in the film layer having the second semiconductor material 204, a planarization process (e.g., chemical mechanical polishing (CMP)) may be performed to planarize the upper surfaces of the first semiconductor material 206 and the second semiconductor material 204 so that they are coplanar. In some embodiments, after the planarization process, the first semiconductor material 206 has a thickness of approximately 45 nm to 70 nm. Thereafter, a silicon top layer 208 is epitaxially grown on the planarized upper surfaces of the first semiconductor material 206 and the second semiconductor material 204 to a thickness of approximately 1.5 nm to 5 nm. In some embodiments, the deposited silicon top layer 208 may be trimmed by etching back or grinding to reduce the thickness to approximately 0.5 nm to 4 nm.

[0048] In order to form Figure 3 The first fin 216A and the second fin 218A shown in FIG. 2 may deposit a hard mask 211 ( Figure 2 ) on the silicon top layer 208. The hard mask 211 can be a single layer or multiple layers. Figure 2In the illustrated embodiment, the hard mask 211 is a multi-layer mask including a first hard mask layer 210 and a second hard mask layer 212. The first hard mask layer 210 and the second hard mask layer 212 have different compositions. In some embodiments, the first hard mask layer 210 is formed of silicon oxide, and the second hard mask layer 212 is formed of silicon nitride. In some embodiments, a combination of deposition, photolithography, and / or etching processes are performed to define the first fin 216A and the second fin 218A above the substrate 202. For example, forming the first fin 216A and the second fin 218A includes performing a photolithography process to form a patterned photoresist layer on the hard mask 211; and performing an etching process to transfer the pattern defined in the patterned photoresist layer to the hard mask 211. The photolithography process may include forming a photoresist layer on the hard mask 211, performing a pre-exposure bake process, performing an exposure process using a mask, a post-exposure bake process, and a development process. During the exposure process, the photoresist layer is exposed to radiation energy (e.g., ultraviolet (UV), deep ultraviolet (DUV), or extreme ultraviolet (EUV) light), wherein the photomask blocks, transmits, and / or reflects the radiation, depending on the mask pattern and / or the type of the photomask (e.g., a binary photomask, a phase-shift photomask, or an EUV photomask), such that an image is projected onto the photoresist layer corresponding to the mask pattern. Because the photoresist layer is sensitive to radiation energy, the exposed portion of the photoresist layer undergoes a chemical change during the development process, depending on the properties of the photoresist layer and the properties of the developer used in the development process, and the exposed (or unexposed) portion of the photoresist layer is dissolved during the development process. After the development process, the patterned photoresist layer includes a photoresist pattern corresponding to the photomask. The etching process uses the patterned photoresist layer as an etching mask to remove portions of the hard mask 211. The etching process may include a dry etching process (e.g., a reactive ion etching (RIE) process), a wet etching process, other suitable etching processes, or a combination thereof. After the etching process, the patterned photoresist layer is removed from the substrate 202 , for example, by a photoresist stripping process.Alternatively, the first fin 216A and the second fin 218A are formed by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process, a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) SADP process, other double patterning processes, or a combination thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, other triple patterning processes, or a combination thereof), other multiple patterning processes (e.g., a self-aligned quadruple patterning (SAQP) process), or a combination thereof. In some embodiments, directed self-assembly (DSA) technology is performed while forming the first fin 216A and the second fin 218A. Furthermore, in some embodiments, the exposure process may be maskless lithography, electron beam (e-beam) writing, ion beam writing, and / or nanoimprinting technology to pattern the photoresist layer and / or other film layers.

[0049] exist Figure 3 In some of the illustrated embodiments, semiconductor device 200 includes a dual-fin transistor, with two fins formed above each of n-well 202N and p-well 202P. In these embodiments, a first fin 216A and an adjacent fin 216B are formed above n-well 202N, and a second fin 218A and an adjacent fin 218B are formed above p-well 202P. The first fin 216A and the adjacent fin 216B may be collectively referred to as p-type fins 216, and the second fin 218A and the adjacent fin 218B may be collectively referred to as n-type fins 218. The p-type fin 216 serves as a p-type active region for forming a p-type transistor with a p-type fully strained channel. The n-type fin 218 serves as an n-type active region for forming an n-type transistor with an n-type channel or a strained n-type channel. However, the embodiments herein are not to be construed as limiting. Those skilled in the art will appreciate that the methods and devices disclosed in the embodiments herein can be readily applied to semiconductor devices having a single fin or multi-fin transistors (ie, each transistor having more than three fins).

[0050] Now please refer to Figure 1 and Figure 4 Method 100 includes block 104, where a liner 214 is formed over the first fin 216A and the second fin 218A. The liner 214 is used to provide structural support to the first fin 216A and the second fin 218A during subsequent processing. In some embodiments, the liner 214 may be formed of silicon nitride to a thickness of approximately 0.5 nm to 3 nm. In some embodiments, the liner 214 may be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0051] Please refer to Figure 1 、 Figure 5 and Figure 6 , the method 100 includes block 106, wherein an isolation structure (isolation feature) 220 is located between the first fin 216A and the second fin 218A. Figure 5 In some embodiments shown, a dielectric material 219 is first blanket deposited on the workpiece 200 to fill the space between the p-type fin 216 and the n-type fin 218. The dielectric material 219 may include silicon oxide, silicon oxynitride, other suitable isolation materials, or a combination thereof, and may be deposited by a chemical vapor deposition (CVD) or spin-on-glass (SOG) process. A planarization process (e.g., a CMP process) is then performed until the hard mask layer 211 is removed. Now refer to Figure 6 , and then the planarized dielectric material 219 is etched back to form an isolation structure 220. Figure 6 As shown, the first semiconductor material 206 and the second semiconductor material 204 of the first fin 216A and the second semiconductor material 204 of the second fin 218A are exposed and rise above the isolation structure 220. Figure 6In the illustrated embodiment, the isolation structure 220 is a shallow trench isolation (STI) structure and may be referred to as an STI structure 220. However, embodiments with other types of isolation structures (e.g., deep trench isolation (DTI) structures and local oxidation of silicon (LOCOS) structures) are also contemplated, as long as such embodiments do not preclude the formation of a semiconductor device having a strained channel. In some embodiments, the etch back of the dielectric material 219 also removes the liner 214 without substantially etching the isolation structure 220, the first semiconductor material 206, and the second semiconductor material 204. In some other embodiments, a separate etching process is performed to selectively remove the liner 214. In embodiments where the liner 214 is formed of silicon nitride, the separate etching process is used to selectively etch the silicon nitride.

[0052] Please refer to Figure 1 and Figure 7 , method 100 includes block 108, in which a silicon capping layer 222 is formed over the first fin 216A and the second fin 218A. The silicon capping layer 222 may be deposited using a suitable deposition technique such as atomic layer deposition (ALD) or epitaxial growth. In some embodiments, the silicon capping layer 222 may be epitaxially grown to a thickness between about 0.5 nm and about 5 nm using a feed gas such as silane (SiH4), silicon tetrachloride (SiCl4), trichlorosilane (TCS), or dichlorosilane (SiH2Cl2 or DCS). Hydrogen (H2) may be used as a reaction gas to reduce the above-mentioned feed gas. Depending on the gas used, the deposition temperature during the epitaxial layer formation may be in the range of about 380° C. to 1250° C. For example, a feed gas with fewer chlorine atoms (e.g., DCS) may require a lower formation temperature than a feed gas with more chlorine atoms (e.g., SiCl4 or TCS). In some other embodiments, ALD can be used to form the silicon cap layer 222 to a similar thickness, approximately in the range of 0.5 nm to 5 nm, using similar gaseous precursors. The primary difference between ALD and epitaxial growth is that alternating self-limiting monolayers are formed in the former, while this is not required in the latter. Other differences may include reactor type and process conditions. In some embodiments, the silicon cap layer 222 is first formed to a first thickness and then etched back to a smaller second thickness, approximately in the range of 0.5 nm to 5 nm.

[0053] Please refer to Figure 1 and Figure 8Method 100 includes block 110 , in which the silicon capping layer 222 undergoes an annealing process 300 to crystallize the silicon capping layer 222 . In some embodiments, the annealing process 300 in block 110 performs radiative heating at a first temperature (T1) between approximately 800° C. and 1050° C. The disclosed temperature range is critical for the annealing process 300 in block 110 . When the first temperature (T1) of the annealing process 300 is below 800° C., little or no silicon reflow occurs to improve the crystallinity of the silicon capping layer and reduce the interface trapped charge density between the silicon capping layer 222 and the first semiconductor layer 206 . When the first temperature (T1) of the annealing process 300 is above 1050° C., damage to the p-type fin 216 (including the first fin 216A) and the n-type fin 218 (including the second fin 218A) may occur. The annealing process 300 in block 110 may be performed at a first pressure (P1) (approximately between 0.001 atmospheres (atm) and 1.1 atm). It has been observed that when the annealing pressure of the annealing process 300 is much lower than 1 atm (e.g., 0.02 atm), a limited amount of oxygen may be required to control the reflow of the silicon capping layer 222. Because low pressure and oxygen deficiency increase the diffusivity of silicon in the silicon capping layer 222, the limited amount of oxygen can prevent excessive silicon reflow (which results in a non-uniform thickness of the silicon capping layer 222). When the first pressure (P1) of the annealing process 300 is 1 atm or approximately 1 atm (e.g., 1.02 atm), the limited amount of oxygen is not required. The annealing process 300 in block 110 may be performed in an atmosphere containing only nitrogen gas that is substantially free of oxygen. When the first pressure (P1) in block 110 is significantly less than 1 atm, the gas atmosphere includes nitrogen and oxygen, with the oxygen content being between approximately 0.01% and 0.05%, such as approximately 0.025%. When the first pressure (P1) of annealing process 300 is at or about 1 atm, the gas atmosphere includes only nitrogen. In some embodiments, when the first pressure (P1) of annealing process 300 is at or about 1 atm, one or more purging operations may be required to intentionally remove oxygen from the gas atmosphere. Because annealing process 300 is performed after forming silicon cap layer 222, annealing process 300 may be referred to as a post-silicon-capanneal (PSA) process 300. It has been observed that the post silicon cap annealing (PSA) process 300 can effectively reduce the density of interface trap charge (DIT) at the interface between the silicon cap layer 222 and the first semiconductor material 206 and improve the crystallinity of the silicon cap layer 222 .Transmission electron microscope (TEM) images show that a sharper interface between the silicon cap layer 222 and the first semiconductor material 206 is formed through the post-silicon cap annealing (PSA) process 300. Because the post-silicon cap annealing (PSA) in block 110 reduces lattice defects and dislocations at the interface, the interface trapped charge density (DIT) is reduced. Since the oxidation rate of silicon decreases with crystallinity, improving the crystallinity of the silicon cap layer 222 slows the oxidation rate and provides better protection for the first semiconductor layer 206 from unwanted oxidation.

[0054] Because the post-silicon cap anneal (PSA) in block 110 is performed before forming the source / drain features, metal gate stack, and other metal-containing contact features, the post-silicon cap anneal (PSA) at the relatively high first temperature Tl (i.e., between approximately 800°C and 1050°C) does not pose any risk of exceeding the thermal budget or causing thermal damage to the above-mentioned structures.

[0055] Please refer to Figure 1 and Figure 9 Method 100 includes block 112, where an interfacial layer 224 is deposited on the silicon capping layer 222. In some embodiments, the interfacial layer 224 comprises silicon oxide and is deposited on the silicon capping layer 222 using a suitable deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). In some embodiments, an annealing process may be performed to anneal the deposited interfacial layer 224 to reduce defects and improve the quality of the interfacial layer 224.

[0056] Now please refer to Figure 1 and Figure 10 , method 100 includes block 114, in which source / drain features 226, 228 and a metal gate stack 234 are formed. The metal gate stack 234 can be formed using a gate-first process or a gate-last process. The latter will be described below as an example, but the former is entirely foreseeable. In the gate-last process, a dummy gate stack (not shown) can first be formed above the p-type fin 216 and the n-type fin 218, so that the dummy gate stack surrounds each of the p-type fin 216 and the n-type fin 218 and engages with its upper surface and side surfaces. In some embodiments, the dummy gate stack may include polysilicon and may be formed on the interface layer 224 (such as Figure 9). After forming the dummy gate stack, gate spacers 230 may be deposited on the dummy gate stack. A dielectric layer (not shown) is then deposited on the working component 200 to cover the dummy gate stack, the p-type fin 216, and the n-type fin 218, and then planarized to form a flush top surface. In some embodiments, a photolithography process may then be performed to sequentially expose and recess the source / drain regions of the p-type fin 216 and the n-type fin 218 to form p-type source / drain features 226 and n-type source / drain features. Epitaxial source / drain features may then be disposed within the recessed source / drain regions of the p-type fin 216 and the n-type fin 218. The epitaxial growth process may be performed using CVD deposition techniques (e.g., vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. In some embodiments, the p-type epitaxial source / drain features 226 may be formed from silicon germanium doped with a p-type dopant (e.g., boron). The n-type epitaxial source / drain features 228 may be formed from silicon or Si:C doped with an n-type dopant (e.g., phosphorus). In some embodiments, an annealing process is performed to activate the dopants within the epitaxial source / drain features 226 and 228 of the semiconductor device 200. According to some embodiments, after depositing the epitaxial source / drain features 226 and 228, a contact etch stop layer (CESL) (not shown) may be deposited on the p-type source / drain features 226 and the n-type source / drain features 228. The contact etch stop layer (CESL) may be formed of silicon nitride or silicon carbonitride. Thereafter, an interlayer dielectric layer (ILD) 232 may be deposited on the workpiece 200 to cover the p-type source / drain features 226 and the n-type source / drain features 228. The interlayer dielectric (ILD) layer 232 may be formed of silicon oxide, silicon nitride, silicon oxynitride, an oxide formed from TEOS, PSG, BPSG, a low-k dielectric material, other suitable dielectric materials, or combinations thereof. Exemplary low-k dielectric materials include FSG, carbon-doped silicon oxide, (Applied Materials, Santa Clara, California), Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, other low-k dielectric materials, or combinations thereof. In some embodiments, the interlayer dielectric (ILD) layer 232 may be formed by flowable CVD (FCVD) or spin coating. For ease of illustration, Figure 10 The inter-layer dielectric (ILD) layer 232 is transparent to show the gate spacers 230 .

[0057] A suitable process (e.g., a CMP process) is used to planarize the interlayer dielectric (ILD) layer 232 until the dummy gate stack is exposed. In the example gate-last process described in the embodiments of this document, a gate replacement operation step is then performed to replace the dummy gate with a metal gate stack 234. First, the dummy gate stack and / or a portion of the interface layer 224 are removed to form a gate trench. Then, a metal gate stack 234 is deposited in the gate trench. In some embodiments, the metal gate stack 234 may include a gate electrode having a gate dielectric layer located above the gate dielectric layer. In some embodiments, the gate dielectric layer may include a silicon oxide layer and a high-k dielectric layer. The silicon oxide layer may be the remaining interface layer 224, or may be re-formed when all or most of the interface layer 224 is removed. The high-k dielectric layer is formed of a dielectric material having a high dielectric constant, which may be greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include hafnium, aluminum, zirconium, lanthanum, tantalum, titanium, yttrium, oxygen, nitrogen, other suitable components, or combinations thereof. In some embodiments, the high-k dielectric layer may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, HfO2-Al2O3, TiO2, Ta2O5, La2O3, Y2O3, other suitable high-k dielectric materials, or combinations thereof. The gate electrode comprises a conductive material. In some embodiments, the gate electrode comprises multiple layers, such as one or more capping layers, work function layers, glue / barrier layers, and / or metal fill (or bulk) layers. The capping layer comprises a material that prevents or eliminates diffusion and / or reaction of components between the gate dielectric and other film layers of the gate electrode. In some embodiments, the capping layer includes a metal and nitrogen, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (W2N), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or a combination thereof. The work function layer includes a conductive material tuned to have a desired work function (e.g., n-type work function or p-type work function), such as an n-type work function material and / or a p-type work function material. P-type work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other p-type work function materials, or a combination thereof. N-type work function materials include Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, TiAlN, other n-type work function materials, or a combination thereof. The glue / barrier layer may include a material that promotes adhesion between adjacent film layers (e.g., the work function layer and the metal fill layer) and / or a material that blocks and / or reduces diffusion between gate layers (e.g., the work function layer and the metal fill layer). For example, the glue / barrier layer includes a metal (e.g., W, Al, Ta, Ti, Ni, Cu, Co, other suitable metals, or combinations thereof), a metal oxide, a metal nitride (e.g., TiN), or combinations thereof.The metal filling layer may include a suitable conductive material, such as Al, W, and / or Cu. Note that when viewed along the X direction, the metal gate stack 234 is hidden behind the gate spacer 230 .

[0058] Now please refer to Figure 1 and Figure 11 , method 100 includes block 116A, where a high pressure anneal (HPA) process 400 is performed on the workpiece 200. In some embodiments, the HPA process 400 may be performed after forming the source / drain features 226, 228 and the metal gate stack 234 in block 114. In some other embodiments, method 100 may alternatively include block 116B (instead of block 116A), where the HPA process 400 is performed after block 118 (described below). IC manufacturing processes are generally categorized into three categories: front-end-of-line (FEOL), middle-end-of-line (MEOL), and back-end-of-line (BEOL). The front-end-of-line (FEOL) generally encompasses processes associated with manufacturing IC devices (e.g., transistors). For example, front-end-of-line (FEOL) processes may include the formation of active regions, isolation features, gate structures, and source / drain features. Middle-of-line (MEOL) processes typically include processes associated with fabricating contacts to conductive features (or regions) of an IC device, such as contacts to gate structures and / or source / drain features. Back-end-of-line (BEOL) processes typically include processes associated with fabricating multilayer interconnect (MLI) features that interconnect IC features fabricated during the FEOL and MEOL processes. In view of the above-mentioned IC manufacturing process flow, the post-silicon cap annealing (PSA) process 300 in block 110 occurs in the front-end-of-line (FEOL) stage or is a front-end-of-line (FEOL) process; the high-pressure annealing (HPA) process 400 in block 116A occurs in the middle-end-of-line (MEOL) stage or is a middle-end-of-line (MEOL) process; and the high-pressure annealing (HPA) process 400 in block 116B occurs in the back-end-of-line (BEOL) stage or is a back-end-of-line (BEOL) process.

[0059] In block 116A or block 116B, a high pressure anneal (HPA) process 400 may be performed using convection heating in a gas atmosphere including hydrogen at a second temperature (T2) between about 350° C. and about 450° C., a second pressure (P2) between about 10 atm and about 20 atm. Compared to the parameters used for the post-silicon cap anneal (PSA) process 300, the second temperature (T2) of the HPA process 400 is lower than the first temperature (T1) of the post-silicon cap anneal (PSA) process 300, and the second pressure (P2) of the HPA process 400 is greater than the first pressure (P1) of the post-silicon cap anneal (PSA) process 300. The elevated second pressure (P2) is necessary to drive hydrogen from structures adjacent to the channel region into the channel region. Compared to the PSA process 300 , the second temperature ( T2 ) of the HPA process 400 may not exceed 450° C. to avoid reflow or damage to metal-containing structures formed in the back-end-of-line (BEOL) or middle-of-line (MEOL) stages.

[0060] Please refer to Figure 1 and Figure 12 , method 100 includes block 118, where further processing is performed. As described above, this further processing includes forming an additional inter-layer dielectric (ILD) layer and contact features formed in the additional inter-layer dielectric (ILD) layer. Examples of contact features may include contact features to a metal gate stack (e.g., Figure 10 The gate contact electrode of the metal gate stack 234 in the embodiment of the present invention, the ... Figure 10 The source / drain contact electrodes 238 and 240 of the p-type source / drain feature 226 and the n-type source / drain feature 228 in FIG. The gate contact via couples the gate contact electrode to the upper conductive layer, and the source / drain contact via couples the source / drain contact electrode to the upper conductive layer or the conductive rail structure connected to various source / drain / gate contact electrodes. For ease of explanation, Figure 12 Only source / drain contact electrodes 238 and 240 are shown. In some embodiments, the contact features may include a barrier layer, a liner layer, and a metal fill layer. The barrier layer may be formed of Ta, TaN, TaC, Ti, TiN, TiC, or other suitable materials that can prevent oxygen diffusion. The liner layer may be formed of a suitable metal, metal nitride, or metal carbide, such as Co, CoN, and RuN. The metal fill layer may be formed of any suitable conductive material, such as W, Ni, Ta, Ti, Al, Cu, Co, TaN, TiN, Ru, and / or other suitable conductive materials. The contact features are used to route and / or distribute signals (e.g., timing signals, voltage signals, and / or ground signals) between devices in the semiconductor device 200.

[0061] exist Figure 12 In some embodiments shown, a silicide layer 236 may be formed over the recessed p-type source / drain features 226 and n-type source / drain features 228. In some embodiments, the silicide layer 236 is formed by depositing a metal layer over the p-type source / drain features 226 and n-type source / drain features 228. The metal layer may include any material suitable for promoting silicide formation, such as nickel, platinum, palladium, vanadium, titanium, cobalt, tantalum, ytterbium, zirconium, other suitable metals, or combinations thereof. The semiconductor device 200 is then heated (e.g., performing an annealing process) to react components of the p-type source / drain features 226 and n-type source / drain features 228 (e.g., silicon and / or germanium) with the metal. Consequently, the silicide layer includes the metal as well as components of the p-type source / drain features 226 and n-type source / drain features 228 (e.g., silicon and / or germanium). In some embodiments, the silicide layer 236 includes nickel silicide, titanium silicide, or cobalt silicide. Any unreacted metal (eg, remaining portion of the metal layer) may be selectively removed by any suitable process, such as an etching process. Figure 12 Shown in Figure 1

[0046] Operation steps at block 116B As described above, a high pressure annealing (HPA) process 400 may be performed after the operations at block 118 are performed to form the contact features comprising metal.

[0062] The methods of the embodiments herein provide numerous advantages. A post-silicon cap anneal (PSA) process performed after forming the silicon cap layer but before forming the metal gate stack and contact features can include a high annealing temperature to crystallize the silicon cap layer and reduce the interface trapped charge density (DIT) caused by forming the silicon cap layer without causing reflow or damaging the metal gate stack and contact features. A high-pressure anneal (HPA) process performed during the middle-of-line (MEOL) or back-end-of-line (BEOL) stages can include a high pressure to drive hydrogen into the channel region and reduce the interface trapped charge density (DIT) caused by processes performed after the post-silicon cap anneal (PSA) process. The two-stage reduction of interface trapped charge density (DIT) in the embodiments herein suppresses interface trapped charge density (DIT), reduces low-field scattering, increases hole mobility, reduces subthreshold swing, and reduces channel resistance. In some embodiments, when a post-silicon cap anneal (PSA) process is performed in addition to a high-pressure anneal (HPA) process, the channel resistance within a p-type fully strained channel (e.g., the channel region formed within the p-type fin 216) can be reduced by approximately 5% to approximately 10%. Experimental data demonstrates that this reduction in channel resistance is independent of channel length. In some embodiments, a 5% to approximately 10% reduction in channel resistance has been observed to result in an approximately 5% to approximately 10% increase in hole mobility.

[0063] Embodiments herein provide embodiments of methods for manufacturing semiconductor devices. In one embodiment, a method for manufacturing a semiconductor device is provided. The method includes forming a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material on a substrate; forming a semiconductor cap layer on the first fin and the second fin; and annealing the semiconductor cap layer at a first temperature while exposing at least a portion of the semiconductor cap layer.

[0064] In some embodiments, the first fin includes a p-type channel region, the second fin includes an n-type channel region, the first semiconductor material includes germanium, and the second semiconductor material includes silicon. In some embodiments, the semiconductor cap is substantially composed of silicon. In some embodiments, the first temperature is greater than 800°C. In some embodiments, the first temperature is approximately between 800°C and 1050°C. In some embodiments, forming the semiconductor cap layer includes depositing silicon using atomic layer deposition (ALD). In some embodiments, forming the semiconductor cap layer includes epitaxially growing silicon over the first fin and the second fin. In some examples, annealing the semiconductor cap layer increases the crystallinity of the semiconductor cap layer.

[0065] In another embodiment, a method for fabricating a semiconductor device is provided. The method includes forming a first fin comprising silicon and germanium on a substrate; forming a second fin comprising silicon on the substrate; forming a silicon capping layer on the first fin and the second fin; performing a first anneal at a first temperature and a first pressure while exposing at least a portion of the silicon capping layer; forming source / drain features on the source / drain regions of the first fin and the second fin; forming a gate structure above the channel region of the first fin and the second fin; and performing a second anneal at a second temperature and a second pressure after forming the gate structure while not exposing any portion of the silicon capping layer.

[0066] In some embodiments, the first temperature is greater than the second temperature, and the second pressure is greater than the first pressure. In some embodiments, the germanium content in the first fin is approximately between 20% and 60%. In some embodiments, forming the silicon cap layer includes depositing silicon using atomic layer deposition (ALD). In some embodiments, forming the silicon cap layer includes epitaxially growing silicon above the first fin and the second fin. In some embodiments, the first temperature is approximately between 800°C and 1050°C, and the first pressure is approximately between 0.01 atmospheres (atm) and 1.1atm. In some embodiments, the second temperature is approximately between 350°C and 450°C, and the second pressure is approximately between 10 atmospheres (atm) and 20atm. In some embodiments, the gate structure includes a high-k dielectric layer, a work function layer, and a metal fill layer.

[0067] In another embodiment, a method for manufacturing a semiconductor device is provided. The method includes forming a first fin comprising silicon and germanium on a substrate; forming a second fin comprising silicon on the substrate; forming a silicon capping layer over the first fin and the second fin; and performing a first anneal at a temperature between approximately 800° C. and 1050° C. immediately after forming the silicon capping layer.

[0068] In some embodiments, forming the silicon capping layer includes depositing silicon using atomic layer deposition (ALD). In some embodiments, forming the silicon capping layer includes epitaxially growing silicon over the first and second fins. In some embodiments, the method further includes forming a gate structure over the channel regions of the first and second fins; and performing a second anneal at a temperature between approximately 350°C and 450°C after forming the gate structure.

[0069] The above briefly describes the features of several embodiments of the present invention, so that those skilled in the art can more easily understand the types of the present disclosure. Anyone skilled in the art should understand that this disclosure can be easily used as a basis for modification or design of other processes or structures to achieve the same purposes and / or obtain the same advantages as the embodiments described herein. Anyone skilled in the art will also understand that structures equivalent to the above do not depart from the spirit and scope of protection of the present disclosure, and that changes, substitutions, and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material on a substrate; forming a semiconductor cap layer on the first fin and the second fin; performing a first annealing on the semiconductor cap layer at a first temperature and a first pressure while exposing at least a portion of the semiconductor cap layer, wherein the annealing of the semiconductor cap layer increases the crystallinity of the semiconductor cap layer; forming a gate structure above the channel regions of the first fin and the second fin; as well as After forming the gate structure, a second annealing is performed at a second pressure greater than the first pressure, wherein the second annealing is performed in a gas atmosphere including hydrogen. 2 . The method for fabricating a semiconductor device according to claim 1 , wherein the first fin comprises a p-type channel region, wherein the second fin comprises an n-type channel region, wherein the first semiconductor material comprises germanium, and wherein the second semiconductor material comprises silicon.

3. The method for manufacturing a semiconductor device as claimed in claim 1, wherein the semiconductor cap is substantially composed of silicon. 4 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first temperature is greater than 800° C. 5 . The method for manufacturing a semiconductor device as claimed in claim 1 , wherein the first temperature is between 800° C. and 1050° C. The method for manufacturing a semiconductor device as claimed in claim 1 , wherein forming the semiconductor cap layer comprises depositing silicon using atomic layer deposition. 7 . The method for fabricating a semiconductor device as claimed in claim 1 , wherein forming the semiconductor cap layer comprises epitaxially growing silicon on the first fin and the second fin.

8. A method for manufacturing a semiconductor device, comprising: forming a first fin comprising silicon and germanium on a substrate; forming a second fin comprising silicon on the substrate; forming a silicon cap layer on the first fin and the second fin; Performing a first annealing at a first temperature and a first pressure while exposing at least a portion of the silicon cap layer, wherein the first annealing increases the crystallinity of the silicon cap layer; forming source / drain features on the source / drain regions of the first fin and the second fin; A gate structure is formed above the channel region of the first fin and the second fin; and after forming the gate structure, a second anneal is performed at a second temperature and a second pressure greater than the first pressure while no portion of the silicon cap layer is exposed, wherein the second anneal is performed in a gas atmosphere including hydrogen. 9 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the first temperature is greater than the second temperature. 10 . The method for manufacturing a semiconductor device according to claim 8 , wherein a germanium content in the first fin is between 20% and 60%. 11 . The method for manufacturing a semiconductor device according to claim 8 , wherein forming the silicon cap layer comprises depositing silicon using atomic layer deposition. 12 . The method for fabricating a semiconductor device according to claim 8 , wherein forming the silicon cap layer comprises epitaxially growing silicon on the first fin and the second fin. 13 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the first temperature is between 800° C. and 1050° C., and wherein the first pressure is between 0.01 atmospheres and 1.1 atmospheres. 14 . The method for manufacturing a semiconductor device according to claim 8 , wherein the second temperature is between 350° C. and 450° C., and wherein the second pressure is between 10 atmospheres and 20 atmospheres. 15 . The method for manufacturing a semiconductor device as claimed in claim 8 , wherein the gate structure comprises a high-k dielectric layer, a work function layer, and a metal filling layer.

16. A method for manufacturing a semiconductor device, comprising: forming a first fin comprising silicon and germanium on a substrate; forming a second fin comprising silicon on the substrate; forming a silicon cap layer over the first fin and the second fin; as well as After forming the silicon cap layer, performing a first annealing at a temperature between 800° C. and 1050° C. and a first pressure, wherein the first annealing increases the crystallinity of the silicon cap layer; forming a gate structure above the channel regions of the first fin and the second fin; as well as After forming the gate structure, a second annealing is performed at a second pressure greater than the first pressure, wherein the second annealing is performed in a gas atmosphere including hydrogen. 17 . The method for manufacturing a semiconductor device according to claim 16 , wherein forming the silicon capping layer comprises depositing silicon using atomic layer deposition. 18 . The method for fabricating a semiconductor device according to claim 16 , wherein forming the silicon cap layer comprises epitaxially growing silicon on the first fin and the second fin.

19. The method for manufacturing a semiconductor device according to claim 16, wherein a second annealing is performed at a temperature between 350°C and 450°C.

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