Semiconductor device

Abstract

A semiconductor device is provided. The semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes a first valley region and a second valley region spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first valley region and the second valley region are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench exposing at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley region.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2019-0118149, filed with the Korean Intellectual Property Office on September 25, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present inventive concept relates to a semiconductor device and a method of manufacturing a semiconductor device. Background Art

[0003] In view of the technological advancements of electronic devices and the recent trend of miniaturization of electronic devices, semiconductor chips with high integration density and low power consumption have attracted increasing attention. Accordingly, the feature size of semiconductor devices has been continuously reduced to meet these requirements.

[0004] Since the feature size of semiconductor devices has been reduced, various studies have been conducted on ways to stably connect wirings. Summary of the Invention

[0005] Exemplary embodiments of the present inventive concept provide a semiconductor device that improves performance and reliability.

[0006] Exemplary embodiments of the present inventive concept also provide a method of manufacturing a semiconductor device that improves performance and reliability.

[0007] However, the exemplary embodiments of the present inventive concept are not limited to the exemplary embodiments set forth herein. The above and other exemplary embodiments of the present inventive concept will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to an exemplary embodiment of the present inventive concept, a semiconductor device includes a first interlayer insulating film disposed on a substrate and having a first trench. A first lower conductive pattern fills the first trench and includes a first valley region and a second valley region spaced apart from each other in a first direction parallel to an upper surface of the substrate. The first valley region and the second valley region are recessed toward the substrate. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench exposing at least a portion of the first lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper filling film disposed on the upper barrier film. The upper conductive pattern at least partially fills the first valley region.

[0009] According to an exemplary embodiment of the inventive concept, a semiconductor device includes a lower conductive pattern including a lower barrier film defining a trench for a fill film and a lower fill film disposed on the lower barrier film in the trench for the fill film. The lower conductive pattern has a top surface having a first width in a first direction parallel to an upper surface of a substrate. An upper conductive pattern is disposed on the lower conductive pattern. The upper conductive pattern is connected to the lower conductive pattern and includes an upper barrier film and an upper fill film disposed on the upper barrier film. A bottom surface of the upper conductive pattern has a second width in the first direction. The second width is greater than or equal to the first width. The upper barrier film covers a portion of sidewalls of the lower barrier film defining the trench for the fill film.

[0010] According to the foregoing and other exemplary embodiments of the inventive concept, a semiconductor device includes a first interlayer insulating film disposed on a substrate and including a first trench. A lower conductive pattern is disposed in the first trench and includes a lower barrier film. A lower liner is disposed on the lower barrier film. A lower fill film is disposed on the lower liner. A second interlayer insulating film is disposed on the first interlayer insulating film and includes a second trench exposing at least a portion of a top surface of the lower conductive pattern. An upper conductive pattern fills the second trench and includes an upper barrier film and an upper fill film disposed on the upper barrier film. The lower conductive pattern further includes a valley region defined by the lower barrier film, the lower liner, and the lower fill film and extending in a thickness direction of the substrate. The upper conductive pattern fills the valley region.

[0011] According to the foregoing and other exemplary embodiments of the inventive concept, a method of manufacturing a semiconductor device includes forming a lower conductive pattern in a first interlayer insulating film, the lower conductive pattern including a valley region extending in a thickness direction of the first interlayer insulating film. Forming a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film including a trench exposing at least a partial portion of a top surface of the lower conductive pattern. Forming an upper barrier film along sidewalls of the trench and a surface of the valley region. Forming an upper fill film on the upper barrier film.

[0012] Other features and other embodiments will be apparent from the following detailed description, the drawings, and the claims. Description of Drawings

[0013] The above and other embodiments and features of the present disclosure will become more apparent by describing exemplary embodiments of the present disclosure in detail with reference to the drawings, in which:

[0014] Figure 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0015] Figure 2 is an enlarged cross-sectional view of a portion P of a semiconductor device according to an exemplary embodiment of the inventive concept Figure 1 of;

[0016] Figure 3It is an enlarged cross-sectional view of part P of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0017] Figure 4 It is an enlarged cross-sectional view of part P of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0018] Figure 5 It is an enlarged cross-sectional view of part P of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0019] Figure 6 It is an enlarged cross-sectional view of part P of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0020] Figure 7 It is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0021] Figure 8 It is according to an exemplary embodiment of the inventive concept Figure 7 of an enlarged cross-sectional view of part P of the semiconductor device;

[0022] Figure 9 It is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0023] Figure 10 It is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0024] Figure 11 It is according to an exemplary embodiment of the inventive concept Figure 10 of an enlarged cross-sectional view of part P of the semiconductor device;

[0025] Figure 12 It is an enlarged cross-sectional view of part P of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0026] Figure 13 It is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0027] Figure 14 and Figure 15 It is an enlarged cross-sectional view of part P of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0028] Figure 16 It is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept;

[0029] Figure 17 and Figure 18 It is according to an exemplary embodiment of the inventive concept Figure 16 of an enlarged cross-sectional view of part Q of the semiconductor device;

[0030] Figure 19 is a magnified cross-sectional view of a part Q of a semiconductor device according to an exemplary embodiment of the inventive concept Figure 16 ;

[0031] Figure 20 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept

[0032] Figure 21 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept

[0033] Figure 22 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept

[0034] Figure 23 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept

[0035] Figure 24 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept; and

[0036] Figures 25 to 29 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept DETAILED DESCRIPTION

[0037] Figure 1 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept Figure 2 is according to an exemplary embodiment of the inventive concept Figure 1 a magnified cross-sectional view of a part P of a semiconductor device

[0038] Referring to Figure 1 and Figure 2 a semiconductor device may include a first lower conductive pattern 200_1, a second lower conductive pattern 200_2, and an upper conductive pattern 300

[0039] The semiconductor device includes a substrate 100. In an exemplary embodiment, the substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In another exemplary embodiment, the substrate 100 may be a silicon substrate, or may include at least one material selected from silicon germanium, silicon-germanium-on-insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, and gallium antimonide. However, the exemplary embodiments of the inventive concept are not limited thereto

[0040] The substrate 100 may further include a conductive pattern. In an exemplary embodiment, the conductive pattern may be a metal wiring, a contact, a conductive pad, a gate electrode and a source / drain of a transistor, or a diode. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, the substrate 100 may include a transistor formed in a front-end-of-line (FEOL) process or a contact or contact wiring formed in a middle-of-line process. In addition, the substrate 100 may include a connection wiring formed in a back-end-of-line (BEOL) process.

[0041] The interlayer insulating film 110 may be disposed on the substrate 100 (e.g., in a second direction D2 which is a thickness direction of the substrate 100). For example, as Figure 1 shown in the exemplary embodiment, a lower surface of the interlayer insulating film 110 may be in direct contact with an upper surface of the substrate 100. The interlayer insulating film 110 may include at least one lower pattern trench 200t.

[0042] In an exemplary embodiment, the interlayer insulating film 110 may include at least one compound selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. For example, the interlayer insulating film 110 may include a low-k material to reduce the occurrence of a coupling phenomenon between adjacent conductive patterns. The low-k material may be a material having a sufficient amount of carbon and hydrogen, such as SiCOH for example.

[0043] Since the low-k material contains carbon, the dielectric constant of the low-k material may be further reduced. In an exemplary embodiment, the low-k material may include pores or cavities filled with a gas or air to further reduce the dielectric constant of the low-k material.

[0044] In an exemplary embodiment, the low-k material may include at least one compound selected from tetraethyl orthosilicate fluoride (FTEOS), hydrogen silsesquioxane (HSQ), benzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexaethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditert-butoxysilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (tonen silazen), fluorided silicate glass (FSG), polyimide nanofoam, polypropylene oxide, carbon-doped silica (CDO), organosilicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, and combinations thereof. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0045] The first lower conductive pattern 200_1 and the second lower conductive pattern 200_2 may be disposed on the substrate 100 and may be spaced apart from each other in a first direction D1 parallel to the upper surface of the substrate 100 and intersecting a second direction D2. The first lower conductive pattern 200_1 and the second lower conductive pattern 200_2 may be disposed in the lower interlayer insulating film 110.

[0046] The first lower conductive pattern 200_1 and the second lower conductive pattern 200_2 may fill the lower pattern trench 200t.

[0047] The first lower conductive pattern 200_1 may be connected to the upper conductive pattern 300. As Figure 1 shown in the exemplary embodiment of, the second lower conductive pattern 200_2 may not be connected to the upper conductive pattern 300. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, at least one second lower conductive pattern 200_2 may be connected to a conductive pattern spaced apart from the upper conductive pattern 300 in a third direction D3 in the upper interlayer insulating film 130, the third direction D3 being parallel to the upper surface of the substrate and intersecting the first direction D1 and the second direction D2.

[0048] Both the first lower conductive pattern 200_1 and the second lower conductive pattern 200_2 may include a lower barrier film 210 and a lower filling film 220. The lower filling film 220 may be disposed on the lower barrier film 210.

[0049] The lower barrier film 210 may extend along the sidewalls and bottom of each lower pattern trench 200t. The lower barrier film 210 may define a filling film trench 210t in the lower pattern trench 200t.

[0050] The lower filling film 220 may fill the lower pattern trench 200t in which the lower barrier film 210 is formed. The lower filling film 220 may at least partially fill the filling film trench 210t.

[0051] As Figure 1 shown in the exemplary embodiment of, the second lower conductive pattern 200_2 may further include, for example, in the second direction D2, a covering film 230 disposed on the upper surface of the lower filling film 220. In the exemplary embodiment, the first lower conductive pattern 200_1 may not include the covering film 230 in the portion where it is connected to the upper conductive pattern 300. However, the first lower conductive pattern 200_1 may include the covering film 230 in the portion where it is not connected to the upper conductive pattern 300. Although Figure 1The exemplary embodiment illustrated shows the covering film 230 formed on the upper surface of the underfill film 220 in each second lower conductive pattern 200_2, but the exemplary embodiment of the inventive concept is not limited thereto. For example, in another exemplary embodiment, the covering film 230 may also be formed on at least one sidewall and / or bottom surface of the under-barrier film 210 in each second lower conductive pattern 200_2.

[0052] In an exemplary embodiment, the under-barrier film 210 may include at least one material selected from tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boride (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), and rhodium (Rh). However, the exemplary embodiment of the inventive concept is not limited thereto. For example, the under-barrier film 210 may include Ta.

[0053] The underfill film 220 may include at least one material selected from aluminum (Al), Cu, W, and Co. However, the exemplary embodiment of the inventive concept is not limited thereto. In an embodiment where the underfill film 220 includes Cu, the underfill film 220 may further include at least one material selected from carbon (C), Ag, Co, Ta, indium (In), tin (Sn), zinc (Zn), manganese (Mn), titanium (Ti), magnesium (Mg), chromium (Cr), germanium (Ge), strontium (Sr), platinum (Pt), Al, and Zr.

[0054] In an exemplary embodiment, the covering film 230 may include at least one of Co, Ru, and Mn. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0055] Hereinafter, reference will be made to Figure 2 describe the shape of the first lower conductive pattern 200_1. The shape of the second lower conductive pattern 200_2 is substantially the same as the shape of the first lower conductive pattern 200_1, and thus, its detailed description will be omitted.

[0056] Referring to Figure 2 , the first lower conductive pattern 200_1 may include a first valley region 200Va and a second valley region 200Vb. The first valley region 200Va and the second valley region 200Vb may be spaced apart from each other in the first direction D1.

[0057] The first valley region 200Va and the second valley region 200Vb may be regions recessed toward the substrate 100. The first valley region 200Va and the second valley region 200Vb may be recessed regions formed in the first lower conductive pattern 200_1 and may have a recessed shape.

[0058] The first valley region 200Va and the second valley region 200Vb may be formed on the top surface 200us of the first lower conductive pattern 200_1 (such as the top surface of the underfill film 220). For example, the first valley region 200Va and the second valley region 200Vb may extend in the thickness direction of the lower interlayer insulating film 110 (e.g., in the second direction D2). The first valley region 200Va and the second valley region 200Vb may be recessed regions extending in the second direction D2.

[0059] The lower barrier film 210 may include a bottom portion 210b and a first sidewall portion 210sa and a second sidewall portion 210sb. The bottom portion 210b (e.g., substantially in the first direction D1) extends along the bottom of the lower pattern trench 200t and corresponds to the first lower conductive pattern 200_1. The first sidewall portion 210sa and the second sidewall portion 210sb extend along the sidewalls of the lower pattern trench 200t corresponding to the first lower conductive pattern 200_1 and are spaced apart from each other in the first direction D1. The first sidewall portion 210sa and the second sidewall portion 210sb may extend substantially in the second direction D2 along the sidewalls of the lower pattern trench 200t corresponding to the first lower conductive pattern 200_1.

[0060] The first sidewall portion 210sa and the second sidewall portion 210sb extend from the bottom portion 210b. The fill film trench 210t corresponding to the first lower conductive pattern 200_1 may be defined by the first sidewall portion 210sa, the second sidewall portion 210sb, and the bottom portion 210b.

[0061] As Figure 2 shown in the exemplary embodiment of, the top surface of the underfill film 220 may bulge upward (e.g., in the second direction D2). As a result, the height (e.g., the distance from the upper surface of the substrate 100 in the second direction D2) of the side edge portion of the top surface of the underfill film 220 (e.g., the side edge in the first direction D1) may be lower than the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210. For example, as Figure 2 shown in the exemplary embodiment of, the side edge portion of the underfill film 220 may not cover the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 (which define the sidewalls of the fill film trench 210t corresponding to the first lower conductive pattern 200_1).

[0062] The first valley region 200Va and the second valley region 200Vb may be defined by a height difference between a side edge portion of the top surface of the lower barrier film 210 and an upper portion of the lower filling film 220. The first valley region 200Va and the second valley region 200Vb may be regions between the top surface of the lower filling film 220 and first and second side wall portions of the lower barrier film 210 that are not covered by the lower filling film 220.

[0063] For example, as Figure 2 shown in the exemplary embodiment of, the first valley region 200Va and the second valley region 200Vb may have a substantially triangular cross-sectional shape. However, in other exemplary embodiments, the top surface of the lower filling film 220 may have a shape other than the Figures 1 to 2 upwardly convex shape shown in the exemplary embodiment of, and the recessed regions forming the first valley region 200Va and the second valley region 200Vb may have various different shapes defined by the lower filling film 220 and the lower barrier film 210.

[0064] The first lower conductive pattern 200_1 may include a curved (e.g., upwardly convex along the second direction D2) top surface 200us. For example, the top surface 200us of the first lower conductive pattern 200_1 may include a first valley portion 200us_1, a second valley portion 200us_2, a first protruding portion 200us_3, a second protruding portion 200us_4, and a valley connection portion 200us_5 connecting the first valley portion 200us_1 and the second valley portion 200us_2.

[0065] The first protruding portion 200us_3 may include the top surface of the first side wall portion 210sa of the lower barrier film 210, and the second protruding portion 200us_4 may include the top surface of the second side wall portion 210sb of the lower barrier film 210. The first valley portion 200us_1 may include a side edge (e.g., left edge) of the top surface of the lower filling film 220 and a portion of the first side wall portion 210sa of the adjacent lower barrier film 210 that is not covered by the lower filling film 220. The second valley portion 200us_2 may include the other side edge (e.g., right edge) of the top surface of the lower filling film 220 and a portion of the second side wall portion 210sb of the adjacent lower barrier film 210 that is not covered by the lower filling film 220. The valley connection portion 200us_5 may include the top surface of the lower filling film 220 that extends (e.g., in the first direction D1) between the first valley portion 200us_1 and the second valley portion 200us_2. In the exemplary embodiment, the valley connection portion 200us_5 may be substantially flat. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0066] The first valley portion 200us_1 and the second valley portion 200us_2 may be defined by the lower fill film 220 and the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 that are not covered by the lower fill film 220. The valley connection portion 200us_5 may be defined by the upper portion of the lower fill film 220 (e.g., in the first direction D1) that extends between the first valley portion 200us_1 and the second valley portion 200us_2.

[0067] The first valley region 200Va may be defined by the first valley portion 200us_1 of the top surface 200us of the first lower conductive pattern 200_1. The second valley region 200Vb may be defined by the second valley portion 200us_2 of the top surface 200us of the first lower conductive pattern 200_1.

[0068] For example, the upper surface of the first valley region 200Va may extend (e.g., in the first direction D1) between the uppermost portion (e.g., in the second direction D2) of the first sidewall portion 210sa of the lower barrier film 210 that defines the fill film trench 210t corresponding to the first lower conductive pattern 200_1 and the uppermost portion (e.g., in the second direction D2) of the lower fill film 220. The bottom of the first valley region 200Va may correspond to the region where the upper portion of the first sidewall portion 210sa of the lower barrier film 210 and the side edge of the top surface of the lower fill film 220 meet.

[0069] The first valley region 200Va may have a first depth d1 (e.g., the length in the second direction D2) relative to the top surface of the first lower conductive pattern 200_1 (e.g., the uppermost portion of the lower fill film 220), and the second valley region 200Vb may have a second depth d2 relative to the uppermost portion of the lower fill film 220. As Figure 2 shown in the exemplary embodiment of, the first depth d1 may be the same as the second depth d2. However, in other exemplary embodiments of the inventive concept, the first depth d1 and the second depth d2 may be different from each other.

[0070] The first sidewall portion 210sa of the lower barrier film 210 may have a first height h1 (e.g., the length in the second direction D2) relative to the bottom of the lower pattern trench 200t corresponding to the first lower conductive pattern 200_1, and the second sidewall portion 210sb of the lower barrier film 210 may have a second height h2 (e.g., the length in the second direction D2) relative to the bottom of the lower pattern trench 200t corresponding to the first lower conductive pattern 200_1. As Figure 2 shown in the exemplary embodiment of, the first height h1 may be the same as the second height h2. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0071] Similar to the first lower conductive pattern 200_1, the second lower conductive pattern 200_2 may each include a first valley region 200Va and a second valley region 200Vb spaced apart from each other in the first direction D1. The depth of the first valley region 200Va of the second lower conductive pattern 200_2 (e.g., the length from the top surface to the bottom surface in the second direction D2) may be the same as or different from the depth of the second valley region 200Vb of the second lower conductive pattern 200_2.

[0072] An etch stop film 120 may be disposed on the lower interlayer insulating film 110. The etch stop film 120 may cover the top surface of the lower interlayer insulating film 110 and the top surface of the second lower conductive pattern 200_2. For example, as Figure 1 shown in the exemplary embodiment of, the lower surface of the etch stop film 120 may be in direct contact with the upper surface of the covering film 230 of the second lower conductive pattern 200_2 and the upper surface of the lower interlayer insulating film 110.

[0073] In an exemplary embodiment, the etch stop film 120 may include, for example, a silicon-based insulating material. The etch stop film 120 may include a silicon-based insulating material film. For example, the etch stop film 120 may include at least one compound selected from silicon nitride (SiN), silicon carbonitride (SiCN), silicon boron nitride (SiBN), silicon carbonate (SiCO), silicon oxynitride (SiON), silicon oxide (SiO), and silicon oxycarbonitride (SiOCN). However, the exemplary embodiments of the inventive concept are not limited thereto. In this specification, the term "silicon oxycarbonitride" only means that the corresponding material contains silicon (Si), carbon (C), and oxygen (O), and does not necessarily represent any specific ratio of Si, C, and O in the corresponding material.

[0074] The first valley region 200Va and / or the second valley region 200Vb of the second lower conductive pattern 200_2 may be filled with an insulating material.

[0075] For example, as Figures 1 to 2 shown in the exemplary embodiment of, both the first valley region 200Va and the second valley region 200Vb of the second lower conductive pattern 200_2 are filled with an insulating material. The etch stop film 120 may fill the first valley region 200Va and the second valley region 200Vb of the second lower conductive pattern 200_2. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0076] An upper interlayer insulating film 130 may be disposed on the etch stop film 120. For example, as Figures 1 to 2 shown in the exemplary embodiment of, the lower portion of the upper interlayer insulating film 130 may be in direct contact with the upper portion of the etch stop film 120. The upper interlayer insulating film 130 may include an upper pattern trench 300t. The upper pattern trench 300t may extend into the etch stop film 120. For example, asFigure 1 As shown in an exemplary embodiment, the upper pattern trench 300t may extend through the etch stop film 120.

[0077] The upper pattern trench 300t may expose at least a portion of the first lower conductive pattern 200_1. The upper pattern trench 300t may include a first upper via trench 301t and an upper wiring trench 305t. At least a partial portion of the first lower conductive pattern 200_1 may be exposed by the first upper via trench 301t.

[0078] In an exemplary embodiment, the upper interlayer insulating film 130 may include at least one compound selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0079] The upper conductive pattern 300 may be disposed in the upper interlayer insulating film 130. As Figure 1 shown in an exemplary embodiment, the upper conductive pattern 300 may fill the upper pattern trench 300t. The upper conductive pattern 300 may be connected to the first lower conductive pattern 200_1.

[0080] The upper conductive pattern 300 may include an upper barrier film 310 and an upper fill film 320. The upper fill film 320 may be disposed on the upper barrier film 310.

[0081] The upper barrier film 310 may extend along the sidewalls and bottom of the upper pattern trench 300t. The upper barrier film 310 may extend along the sidewalls of the first upper via trench 301t and along the sidewalls and bottom of the upper wiring trench 305t. A portion of the upper barrier film 310 may extend along the top surface 200us of the first lower conductive pattern 200_1. The upper fill film 320 may fill the upper pattern trench 300t in which the upper barrier film 310 is formed.

[0082] The upper conductive pattern 300 may include a first upper via 301 that fills the first upper via trench 301t and an upper connection wiring 305 that fills the upper wiring trench 305t.

[0083] In an exemplary embodiment, the upper barrier film 310 may include at least one material selected from Ta, TaN, Ti, TiN, Ru, Co, Ni, NiB, W, WN, WCN, Zr, ZrN, V, VN, Nb, NbN, Pt, Ir, and Rh. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0084] In an exemplary embodiment, the upper fill film 320 may include at least one material selected from Al, Cu, W, and Co. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0085] In Figure 1In the exemplary embodiment shown, the cover film 230 is not formed on the upper fill film 320. However, the exemplary embodiments of the inventive concept are not limited thereto. In addition, in Figure 1 In the exemplary embodiment shown, a valley region is not formed between the upper fill film 320 and the upper barrier film 310. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in an alternative embodiment, similar to the first lower conductive pattern 200_1 and the second lower conductive pattern 200_2, the upper conductive pattern 300 may include at least one valley region.

[0086] In Figure 1 In the exemplary embodiment shown, the upper fill film 320 included in the first upper via 301 and the upper fill film 320 included in the upper connection wiring 305 are directly connected to each other. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the upper barrier film 310 may be disposed between the upper fill film 320 included in the first upper via 301 and the upper fill film 320 included in the upper connection wiring 305.

[0087] The upper conductive pattern 300 may fill at least one of the first valley region 200Va and the second valley region 200Vb of the first lower conductive pattern 200_1. For example, as Figures 1 to 2 shown in the exemplary embodiment of

[0088] In an exemplary embodiment, the upper barrier film 310 may completely fill at least one of the first valley region 200Va and the second valley region 200Vb of the first lower conductive pattern 200_1. For example, as Figures 1 to 2 shown in the exemplary embodiment of

[0089] In this specification, the expression "one element completely fills another element" means that in a cross-sectional view (e.g., when viewed from the third direction D3), one element completely fills another element.

[0090] Since the upper barrier film 310 completely fills the first valley regions 200Va and 200Vb of the first lower conductive pattern 200_1, the lowest level of the upper filling film 320 provided on the upper barrier film 310 (e.g., the distance from the upper surface of the substrate 100 in the second direction D2) can be higher than the highest level of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210. For example, the upper barrier film 310 can be provided between the lowest level of the upper filling film 320 and the highest level of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 in the second direction D2.

[0091] The upper conductive pattern 300 can cover the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 (which define the sidewalls of the filling film trench 210t corresponding to the first lower conductive pattern 200_1). For example, the upper barrier film 310 can cover portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 (which define the sidewalls of the filling film trench 210t corresponding to the first lower conductive pattern 200_1).

[0092] The first valley region 200Va and the second valley region 200Vb of the first lower conductive pattern 200_1 can be defined by the top surface of the lower filling film 220 and the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 that are not covered by the lower filling film 220. As Figures 1 to 2 shown in the exemplary embodiment, the upper barrier film 310 can cover the first valley region 200Va and the second valley region 200Vb. The first valley portion 200us_1 and the second valley portion 200us_2 of the top surface 200us of the first lower conductive pattern 200_1 can be defined by the top surface of the lower filling film 220 and the portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 that are covered by the upper barrier film 310. The first valley region 200Va and the second valley region 200Vb of the first lower conductive pattern 200_1 can be the region between the side edges of the top surface of the lower filling film 220 and the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 that are covered by the upper barrier film 310.

[0093] The bottom surface of the upper conductive pattern 300 can be the bottom surface 301bs of the first upper via 301 and the portion of the upper barrier film 310 that extends within the first valley region 200Va and the second valley region 200Vb. As Figure 2As shown in the exemplary embodiment of, the width W1 of the top surface 200us of the first lower conductive pattern 200_1 (e.g., the length in the first direction D1) may be smaller than the width W2 of the bottom surface 301bs of the upper conductive pattern 300 (e.g., the length in the first direction D1).

[0094] As Figure 1 shown in the exemplary embodiment of, in a cross-sectional view, the bottom surface 301bs of the upper conductive pattern 300 may completely cover the top surface 200us of the first lower conductive pattern 200_1 (e.g., in the first direction D1).

[0095] Figure 3 is an enlarged cross-sectional view of a part P of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 4 is an enlarged cross-sectional view of a part P of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 5 is an enlarged cross-sectional view of a part P of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 6 is an enlarged cross-sectional view of a part P of a semiconductor device according to an exemplary embodiment of the inventive concept. For convenience, hereinafter, the description will mainly focus on the differences from the semiconductor device of Figure 1 and Figure 2 to describe the semiconductor device of Figures 3 to 6 the semiconductor device.

[0096] Figures 3 to 6 is an enlarged cross-sectional view of a part corresponding to part P of a semiconductor device according to some exemplary embodiments of the inventive concept and Figure 1 the semiconductor device.

[0097] Referring to Figure 3 , the first depth d1 of the first valley region 200Va may be different from the second depth d2 of the second valley region 200Vb.

[0098] For example, the height of the upper part of the first sidewall portion 210sa of the lower barrier film 210 that is not covered by the lower filling film 220 (e.g., the length in the second direction D2) may be different from the height of the upper part of the second sidewall portion 210sb of the lower barrier film 210 that is not covered by the lower filling film 220.

[0099] For example, the height of the upper part of the first sidewall portion 210sa of the lower barrier film 210 that is covered by the upper barrier film 310 (e.g., the length in the second direction D2) may be different from the height of the upper part of the second sidewall portion 210sb of the lower barrier film 210 that is covered by the upper barrier film 310. As Figure 3 shown in the exemplary embodiment of, the second depth d2 of the second valley region 200Vb may be greater than the first depth d1 of the first valley region 200Va. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0100] Figure 3 An exemplary embodiment of [the relevant content] shows the upper barrier film 310 completely filling the second valley region 200Vb. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, depending on the second depth d2 of the second valley region 200Vb and the thickness of the upper barrier film 310, the second valley region 200Vb may be only partially filled with the upper barrier film 310, and the second valley region 200Vb may also be filled with the upper filling film 320.

[0101] As Figure 4 shown in an exemplary embodiment of [the relevant content], the first height h1 (e.g., the length in the second direction D2) of the first sidewall portion 210sa of the lower barrier film 210 may be different from the second height h2 of the second sidewall portion 210sb of the lower barrier film 210.

[0102] However, the depth of the first valley region 200Va may be the same as the depth of the second valley region 200Vb.

[0103] The height of the upper part of the first sidewall portion 210sa of the lower barrier film 210 that is not covered by the lower filling film 220 may be different from the height of the upper part of the second sidewall portion 210sb of the lower barrier film 210 that is not covered by the lower filling film 220.

[0104] Referring to Figure 5 an exemplary embodiment of [the relevant content], the width W1 (e.g., the length in the first direction D1) of the top surface 200us of the first lower conductive pattern 200_1 may be the same as the width W2 (e.g., the length in the first direction D1) of the bottom surface 301bs of the upper conductive pattern 300.

[0105] In Figure 5 the exemplary embodiment shown, the first upper via 301 of the upper conductive pattern 300 may be arranged to be aligned with the first lower conductive pattern 200_1. For example, the sidewalls forming the first upper via 301 and the first sidewall portion 210sa and the second sidewall portion 210sb of the first lower conductive pattern 200_1 may be aligned in the second direction D2.

[0106] Referring to Figure 6 an exemplary embodiment of [the relevant content], the top surface 200us of the first lower conductive pattern 200_1 may not include the valley connection portion 200us_5.

[0107] The first valley portion 200us_1 of the top surface 200us of the first lower conductive pattern 200_1 may be directly connected to the second valley portion 200us_2 of the top surface 200us. In this embodiment, the top surface of the lower filling film 220 may be substantially curved and may not be flat. Therefore, the curved surface of the top surface of the lower filling film 220 may form a part of the first valley portion 200us_1 and a part of the second valley portion 200us_2 of the top surface 200us, and the uppermost surface of the top surface 200us of the first lower conductive pattern 200_1 may form a common edge of the first valley portion 200us_1 and the second valley portion 200us_2.

[0108] Figure 7 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 8 is according to an exemplary embodiment of the inventive concept Figure 7 of a semiconductor device of portion P of the enlarged cross-sectional view. Hereinafter will mainly focus on the Figure 1 and Figure 2 of the semiconductor device differences to describe Figure 7 and Figure 8 of the semiconductor device.

[0109] Referring to Figure 7 and Figure 8 , each of the first lower conductive pattern 200_1 and the second lower conductive pattern 200_2 may further include a lower liner 240. The upper conductive pattern 300 may further include an upper liner 330.

[0110] The lower liner 240 may be disposed between the lower barrier film 210 and the lower filling film 220. The lower liner 240 may be disposed on the lower barrier film 210. For example, the lower liner 240 may be formed along a partial portion of the contour of the lower barrier film 210.

[0111] The lower liner 240 may extend along a part of the sidewall of each filling film trench 210t and the bottom of each filling film trench 210t. The lower liner 240 may not cover the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210.

[0112] Referring to Figure 8 , the first valley region 200Va and the second valley region 200Vb of the first lower conductive pattern 200_1 may be defined by the side edge of the lower filling film 220, the lower barrier film 210, and the lower liner 240. The first valley region 200Va and the second valley region 200Vb may be defined by the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 that are not covered by the lower liner 240, the top surface of the lower liner 240, and the side edge (e.g., in the first direction D1) of the top surface of the lower filling film 220.

[0113] The first valley portion 200us_1 of the top surface 200us of the first lower conductive pattern 200_1 may include the left edge of the top surface of the lower filling film 220, the left top surface of the lower liner 240, and the upper portion of the first sidewall portion 210sa of the lower barrier film 210 that is not covered by the lower liner 240. The second valley portion 200us_2 of the top surface 200us of the first lower conductive pattern 200_1 may include the right edge of the top surface of the lower filling film 220, the right top surface of the lower liner 240, and the upper portion of the second sidewall portion 210sb of the lower barrier film 210 that is not covered by the lower liner 240.

[0114] The uppermost portion of the lower liner 240 (e.g., in the second direction D2) may be lower than the uppermost portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210. The uppermost portion of the lower liner 240 may be lower than the uppermost portion of the lower filling film 220.

[0115] The bottom portions of the first valley region 200Va and the second valley region 200Vb may be defined by the lower liner 240 (such as the uppermost portion of the lower liner 240).

[0116] The upper liner 330 may be disposed between the upper barrier film 310 and the upper filling film 320. The upper liner 330 may be disposed on the upper barrier film 310. The upper liner 330 may be formed along the contour of the upper barrier film 310. For example, the upper liner 330 may cover the bottom surface and the sidewall surface of the upper barrier film 310.

[0117] In an exemplary embodiment, the lower liner 240 and the upper liner 330 may include at least one material selected from Co, Ru, and Mn. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0118] Figure 9 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Hereinafter, the focus will be mainly on the differences from the Figure 1 and Figure 2 semiconductor device to describe the Figure 9 exemplary embodiment of the semiconductor device.

[0119] Referring to Figure 9 the exemplary embodiment, at least one of the first valley region 200Va and the second valley region 200Vb of each second lower conductive pattern 200_2 may include a wiring void 200ag.

[0120] For example, as Figure 9As shown in the exemplary embodiment, the first valley region 200Va and the second valley region 200Vb may both include a wiring gap 200ag. The wiring gap 200ag may be formed in each of the first valley region 200Va and the second valley region 200Vb. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0121] One or more wiring gaps 200ag may be defined between the lower surface of the etch stop film 120 and the top surface of the side edge of each second lower conductive pattern 200_2.

[0122] In an alternative embodiment, the first valley region 200Va may be filled with an insulating material, and the wiring gap 200ag may be formed only in the second valley region 200Vb. In another exemplary embodiment, the second valley region 200Vb may be filled with an insulating material, and the wiring gap 200ag may be formed only in the first valley region 200Va.

[0123] Figure 10 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 11 is according to an exemplary embodiment of the inventive concept Figure 10 of the semiconductor device of part P. In the following, the focus will be mainly on the differences from Figure 1 and Figure 2 of the semiconductor device to describe Figure 10 and Figure 11 of the semiconductor device.

[0124] Referring to Figure 10 and Figure 11 , the upper barrier film 310 may extend along the contour of the top surface 200us of the first lower conductive pattern 200_1.

[0125] For example, as Figures 10 to 11 shown in the exemplary embodiment, the upper barrier film 310 may extend along the contours of the first protruding portion 200us_3, the first valley portion 200us_1, the valley connection portion 200us_5, the second valley portion 200us_2, and the second protruding portion 200us_4 of the top surface of the first lower conductive pattern 200_1.

[0126] The first valley region 200Va and / or the second valley region 200Vb of the first lower conductive pattern 200_1 that remain unfilled by the upper barrier film 310 may be filled with the upper filling film 320. For example, as Figures 10 to 11As shown in the exemplary embodiment, the upper barrier film 310 may each have a recessed portion extending below the height of the top surfaces of the first protruding portion 200us_3 and the second protruding portion 200us_4. The upper filling film 320 may fill the recessed portions in the upper barrier film 310 to fill the portions of the first valley region 200Va and the second valley region 200Vb that remain unfilled by the upper barrier film 310.

[0127] Figure 12 is an enlarged cross-sectional view of a part P of a semiconductor device according to an exemplary embodiment of the inventive concept. Hereinafter, the description will mainly focus on the differences from the Figure 10 and Figure 11 semiconductor device to describe Figure 12 the semiconductor device.

[0128] Referring to Figure 12 , the upper barrier film 310 may extend along local portions of the first valley portions 200us_1 and the second valley portions 200us_2 of the top surface of the first lower conductive pattern 200_1.

[0129] For example, the upper barrier film 310 may be formed along the upper portions of the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210. The upper barrier film 310 may be formed on the first valley portions 200us_1 and the second valley portions 200us_2 defined by the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 and the side edges of the top surface of the lower filling film 220.

[0130] However, the upper barrier film 310 may not extend along the top surface of the lower filling film 220. For example, as Figure 12 shown in the exemplary embodiment, the upper barrier film 310 may not be formed on at least local portions of the first valley portions 200us_1 and the second valley portions 200us_2, and may not be formed on the valley connection portion 200us_5. For example, the portions of the upper barrier film 310 formed along the first sidewall portion 210sa and the second sidewall portion 210sb of the lower barrier film 210 may be disposed on the side edges of the top surface of the lower filling film 220. However, as Figure 12 shown in the exemplary embodiment, the upper barrier film 310 may not cover the portions of the first valley portions 200us_1 and the second valley portions 200us_2 defined by the lower filling film 220. For example, the upper barrier film 310 may not cover the local portions of the side edges of the first valley portions 200us_1 and the second valley portions 200us_2 defined by the lower filling film 220 that are away from the first sidewall portion 210sa and the second sidewall portion 210sb, and the relatively flat valley connection portion 200us_5 defined by the lower filling film 220.

[0131] In an exemplary embodiment, before forming the upper barrier film 310, a surface treatment may be performed on the top surface of the lower filling film 220. As a result, the upper barrier film 310 may not be formed on the top surface of the lower filling film 220.

[0132] Figure 13 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 14 and Figure 15 is according to an exemplary embodiment of the inventive concept Figure 13 of a semiconductor device of portion P. Hereinafter, the description will mainly focus on the differences from Figure 1 and Figure 2 of the semiconductor device to describe Figures 13 to 15 of the semiconductor device.

[0133] Referring to Figures 13 to 15 , the upper conductive pattern 300 may fill the first valley region 200Va of the first lower conductive pattern 200_1. However, the upper conductive pattern 300 may not fill the second valley region 200Vb of the first lower conductive pattern 200_1.

[0134] For example, the bottom surface 301bs of the upper conductive pattern 300 may only cover a partial portion of the top surface 200us of the first lower conductive pattern 200_1.

[0135] As Figure 13 shown in the exemplary embodiment of, the covering film 230 may be formed on a portion of the lower filling film 220 not covered by the bottom surface 301bs of the upper conductive pattern 300. However, the exemplary embodiment of the inventive concept is not limited thereto.

[0136] As Figure 14 shown in the exemplary embodiment of, the second valley region 200Vb may be filled with an insulating material. For example, a portion of the etch stop film 120 may be formed in the second valley region 200Vb. As Figure 14 shown in the exemplary embodiment of, the etch stop film 120 may be disposed on the covering film 230. For example, the lower surface of the etch stop film 120 may be in direct contact with the upper surface of the covering film 230.

[0137] Referring to Figure 15 the exemplary embodiment shown in, a wiring void 200ag may be formed in the second valley region 200Vb. The wiring void 200ag may be defined between the etch stop film 120 and the covering film 230 disposed on the side edge defining the second valley region 200Vb on the top surface 200us of the first lower conductive pattern 200_1.

[0138] For example, the width W1 of the top surface 200us of the first lower conductive pattern 200_1 (e.g., the length in the first direction D1) may be greater than the width W2 of the bottom surface 301bs of the upper conductive pattern 300. However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, the width W1 may be the same as the width W2. In another exemplary embodiment, the width W1 may be smaller than the width W2.

[0139] Figure 16 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 17 and Figure 18 is according to an exemplary embodiment of the inventive concept Figure 16 of a semiconductor device of part Q. In the following, the description will mainly focus on the differences between Figure 1 and Figure 2 of the semiconductor device to describe Figures 16 to 18 of the semiconductor device.

[0140] Referring to Figures 16 to 18 , the etch stop film 120 may include a first sub-etch stop film 121 and a second sub-etch stop film 122.

[0141] The second sub-etch stop film 122 may be disposed on the first sub-etch stop film 121. For example, the lower surface of the second sub-etch stop film 122 may be in direct contact with the upper surface of the first sub-etch stop film 121. The first sub-etch stop film 121 may be disposed (e.g., in the second direction D2) between the second sub-etch stop film 122 and the lower interlayer insulating film 110.

[0142] In an exemplary embodiment, the first sub-etch stop film 121 may include a metal-containing insulating material. Thus, the etch stop film 120 may include a metal. For example, in an exemplary embodiment, the first sub-etch stop film 121 may include an Al-containing insulating material. The first sub-etch stop film 121 may include at least one compound selected from aluminum oxide (AlO), aluminum nitride (AlN), and aluminum oxycarbide (AlOC). However, the exemplary embodiments of the inventive concept are not limited thereto.

[0143] In this specification, the term "aluminum oxycarbide" only means that the corresponding material contains Al, O, and C, and does not necessarily represent any specific ratio of Al, O, and C in the corresponding material.

[0144] In an exemplary embodiment, the second sub-etch stop film 122 may include a Si-based insulating material. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0145] As Figure 17As shown in the exemplary embodiment of, the etch stop film 120 may include a pit pattern 120dp. The pit pattern 120dp may be formed at a portion defining a sidewall of the upper pattern trench 300t. Specifically, the pit pattern 120dp may be formed at a portion defining a sidewall of the first upper via trench 301t. For example, as Figure 17 As shown in the exemplary embodiment of, the pit pattern 120dp may be formed on a bottom portion of a sidewall of the upper pattern trench 300t. The pit pattern 120dp may be a portion recessed into the etch stop film 120. The pit pattern 120dp may be a portion extending in the first direction D1.

[0146] The pit pattern 120dp may be formed on a portion of the sidewall of the first upper via trench 301t defined by the first sub-etch stop film 121. For example, as Figure 17 As shown in the exemplary embodiment of, the pit pattern 120dp may be formed on two portions of the sidewall of the first upper via trench 301t defined by the first sub-etch stop film 121. However, the exemplary embodiment of the inventive concept is not limited thereto, and the pit pattern 120dp may be formed only on one sidewall of the first upper via trench 301t in other exemplary embodiments. In the exemplary embodiment, since wet etching has isotropic etching characteristics, the pit pattern 120dp may be formed while removing the first sub-etch stop film 121 by wet etching.

[0147] The upper barrier film 310 may fill at least a portion of each pit pattern 120dp. Referring to Figure 17 the exemplary embodiment shown in, the upper barrier film 310 may be formed along the contour of the pit pattern 120dp. The unfilled portion of the pit pattern 120dp may be filled with the upper fill film 320. Accordingly, in these exemplary embodiments, the width (e.g., the length in the first direction D1) of the upper fill film 320 at the same level as the first sub-etch stop film 121 may be wider than the width of the upper fill film 320 at the same level as the second sub-etch stop film 122. Referring to Figure 18 the exemplary embodiment shown in, the upper barrier film 310 may completely fill the pit pattern 120dp. Figure 17 or Figure 18 The cross-sectional structure shown in the exemplary embodiment of may be obtained according to the thickness of the first sub-etch stop film 121 and the degree of etching of the first sub-etch stop film 121.

[0148] Figure 19 is an enlarged cross-sectional view of a portion Q of a semiconductor device according to an exemplary embodiment of the inventive concept. Hereinafter, the description will mainly focus on the differences from the Figures 16 to 18 semiconductor device to describe the Figure 19 semiconductor device.

[0149] Referring to Figure 19 an exemplary embodiment of

[0150] , the etch stop film 120 may further include a third sub-etch stop film 123. Figure 19 The third sub-etch stop film 123 may be disposed on the second sub-etch stop film 122. For example, as shown in an exemplary embodiment of

[0151] , the lower surface of the third sub-etch stop film 123 may be in direct contact with the upper surface of the second sub-etch stop film 122. In an exemplary embodiment, the third sub-etch stop film 123 may include an insulating material containing a metal. Accordingly, the third sub-etch stop film 123 may include a metal. For example, the third sub-etch stop film 123 may include an insulating material containing Al. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0152] Figure 20 FIG. is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 21 FIG. is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 22 FIG. is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Hereinafter, the description will mainly focus on the differences from the exemplary embodiments of the semiconductor device shown in Figure 1 and Figure 2 to describe the semiconductor device shown in the exemplary embodiments of Figures 20 to 22 FIG.

[0153] Referring to Figure 20 , the upper barrier film 310 may be conformally formed along the upper pattern trench 300t. However, the lower barrier film 210 may not be conformally formed along the lower pattern trench 200t.

[0154] For example, the thickness (e.g., the length in the second direction D2) of the portion of the upper barrier film 310 at the bottom of the upper wiring trench 305t and extending substantially along the first direction D1 may be substantially the same as the thickness (e.g., the length in the first direction D1) of the portion of the upper barrier film 310 on the sidewall of the upper wiring trench 305t.

[0155] However, the thickness t11 (e.g., the length in the second direction D2) of the portion of the lower barrier film 210 at the bottom of each lower pattern trench 200t may be greater than the thickness t12 (e.g., the length in the first direction D1) of the portion of the lower barrier film 210 on the sidewall of each lower pattern trench 200t.

[0156] For example, in an exemplary embodiment, the upper barrier film 310 may be formed by a deposition method having excellent step coverage, and the lower barrier film 210 may be formed by a deposition method having poor step coverage.

[0157] Referring to Figure 21 the exemplary embodiment shown in, the lower barrier film 210 may be conformally formed along the lower pattern trench 200t. However, the upper barrier film 310 may not be conformally formed along the upper pattern trench 300t.

[0158] For example, the thickness t21 (e.g., the length in the second direction D2) of the portion of the upper barrier film 310 at the bottom of the upper wiring trench 305t may be greater than the thickness t22 (e.g., the length in the first direction D1) of the portion of the upper barrier film 310 on the sidewall of the upper wiring trench 305t.

[0159] However, as Figure 21 shown in the exemplary embodiment of, the thickness of the portion of the lower barrier film 210 at the bottom of each lower pattern trench 200t may be substantially the same as the thickness of the portion of the lower barrier film 210 on the sidewall of each lower pattern trench 200t.

[0160] In an exemplary embodiment, the lower barrier film 210 may be formed by a deposition method having excellent step coverage, and the upper barrier film 310 may be formed by a deposition method having poor step coverage.

[0161] However, the exemplary embodiments of the inventive concept are not limited thereto. For example, in another exemplary embodiment, both the upper barrier film 310 and the lower barrier film 210 may not be conformally formed along the upper pattern trench 300t and the lower pattern trench 200t, respectively.

[0162] Referring to Figure 22 the exemplary embodiment of, each first lower conductive pattern 200_1 may include a covering film 230.

[0163] The covering film 230 may be disposed (e.g., in the second direction D2) between the upper conductive pattern 300 and the upper surface of the lower filling film 220.

[0164] Figure 23 is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept. Figure 24It is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the inventive concept.

[0165] Referring to Figure 23 the exemplary embodiment of , the upper conductive pattern 300 may further include a second upper via 302 spaced apart from the first upper via 301 in the first direction D1.

[0166] The second upper via 302 may fill the second upper via trench 302t. The second upper via 302 may be connected to the second lower conductive pattern 200_2.

[0167] As Figure 23 shown in the exemplary embodiment of , the bottom of the second upper via 302 may completely cover the top surface of the second lower conductive pattern 200_2. However, the exemplary embodiment of the inventive concept is not limited thereto. For example, in another exemplary embodiment, the second upper via 302 may only cover a partial portion of the top surface of the second lower conductive pattern 200_2.

[0168] Referring to Figure 24 the exemplary embodiment of , the upper conductive pattern 300 may not include upper connection wirings (such as Figure 1 the upper connection wiring 305 shown in the exemplary embodiment of ).

[0169] In Figure 24 the exemplary embodiment shown in , the upper conductive pattern 300 may only include the first upper via 301.

[0170] Figures 25 to 29 It is a cross-sectional view showing a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0171] Referring to Figure 25 the exemplary embodiment shown in , the first lower conductive pattern 200_1 and the second lower conductive pattern 200_2 may be formed in the lower interlayer insulating film 110 on the substrate 100.

[0172] Each of the first lower conductive pattern 200_1 and the second lower conductive pattern 200_2 may include a lower barrier film 210 formed along the lower pattern trench 200t and a lower filling film 220 formed on the lower barrier film 210. A covering film 230 may be formed along the top surface of the lower filling film 220.

[0173] Each of the first lower conductive pattern 200_1 and the second lower conductive pattern 200_2 may include a first valley region 200Va and a second valley region 200Vb extending in the thickness direction of the lower interlayer insulating film 110 (e.g., in the second direction D2).

[0174] Referring to Figure 26In an exemplary embodiment, an etch stop film 120 and an upper interlayer insulating film 130 may be sequentially formed on the lower interlayer insulating film 110 (e.g., along the second direction D2).

[0175] An upper pattern trench 300t exposing at least a partial portion of the first lower conductive pattern 200_1 may be formed in the etch stop film 120 and the upper interlayer insulating film 130. The capping film 230 formed on the lower fill film 220 of the first lower conductive pattern 200_1 may be etched and removed. The upper pattern trench 300t may include a first upper via trench 301t and an upper wiring trench 305t.

[0176] Referring to Figure 27 In an exemplary embodiment, a preliminary upper barrier film 310p may be formed along the sidewalls of the upper pattern trench 300t and the first valley regions 200Va and 200Vb of the first lower conductive pattern 200_1.

[0177] The preliminary upper barrier film 310p may be formed on the sidewalls of the first upper via trench 301t, the sidewalls and bottom of the upper wiring trench 305t, and the surfaces of the first valley regions 200Va and 200Vb of the first lower conductive pattern 200_1. As shown in Figure 27 In the exemplary embodiment, the preliminary upper barrier film 310p may completely fill the first valley regions 200Va and 200Vb of the first lower conductive pattern 200_1. However, the exemplary embodiments of the inventive concept are not limited thereto.

[0178] In an exemplary embodiment, the preliminary upper barrier film 310p may be formed by atomic layer deposition (ALD).

[0179] Referring to Figure 28 In an exemplary embodiment, the preliminary upper barrier film 310p may be densified (e.g., the density of the preliminary upper barrier film 310p may be increased) through a densification process 50. As a result, the preliminary upper barrier film 310p may form an upper barrier film 310.

[0180] For example, in an exemplary embodiment, physical vapor deposition (PVD) may be used for the densification process 50. PVD using a process gas may improve the quality of the preliminary upper barrier film 310p. For example, almost no additional barrier film is formed on the preliminary upper barrier film 310p through PVD. However, the exemplary embodiments of the inventive concept are not limited thereto, and the densification process 50 may be performed through various different methods.

[0181] Referring to Figure 29 In an exemplary embodiment, an upper fill film 320 filling the upper pattern trench 300t may be formed on the upper barrier film 310.

[0182] Summarizing the detailed description of the exemplary embodiments of the inventive concept, those skilled in the art will understand that many variations and modifications can be made to the exemplary embodiments without departing in essence from the principles of the inventive concept. Therefore, the disclosed exemplary embodiments of the inventive concept are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A semiconductor device, the semiconductor device comprising: A first interlayer insulating film disposed on a substrate and including a first trench; A first lower conductive pattern filling the first trench and including a first valley region and a second valley region spaced apart from each other in a first direction parallel to the upper surface of the substrate, the first valley region and the second valley region being recessed toward the substrate; A second interlayer insulating film disposed on the first interlayer insulating film and including a second trench exposing at least a part of the first lower conductive pattern; And An upper conductive pattern filling the second trench and including an upper barrier film and an upper filling film disposed on the upper barrier film, Wherein the upper conductive pattern at least partially fills the first valley region, Wherein the first lower conductive pattern includes a lower barrier film and a lower filling film disposed on the lower barrier film, and The first valley region and the second valley region are defined by the upper surface of the lower filling film and the portions of the inner surfaces of the sidewall portions of the lower barrier film not covered by the lower filling film, Wherein the upper barrier film extends along the sidewalls of the second trench and covers the portions of the inner surfaces of the sidewall portions of the lower barrier film not covered by the lower filling film and the top surface of the lower barrier film.

2. The semiconductor device according to claim 1, wherein, The upper conductive pattern also at least partially fills the second valley region.

3. The semiconductor device according to claim 2, wherein, The upper barrier film completely fills at least one of the first valley region and the second valley region.

4. The semiconductor device according to claim 2, wherein, The top surface of the first lower conductive pattern includes a first valley portion and a second valley portion respectively defining the first valley region and the second valley region, and The upper barrier film extends along all surfaces of the first valley portion and the second valley portion.

5. The semiconductor device according to claim 2, wherein, The top surface of the first lower conductive pattern includes a first valley portion and a second valley portion respectively defining the first valley region and the second valley region, and The upper barrier film extends along local portions of the surfaces of the first valley portion and the second valley portion.

6. The semiconductor device according to claim 1, wherein, The depth of the first valley region is the same as the depth of the second valley region.

7. The semiconductor device according to claim 1, wherein, The first lower conductive pattern further includes a lower liner disposed between the lower barrier film and the lower filling film, and The bottom portions of the first valley region and the second valley region are defined by the lower liner.

8. The semiconductor device according to claim 1, wherein, The second valley region is filled with an insulating material.

9. The semiconductor device according to claim 1, wherein, The second valley region includes a wiring void.

10. The semiconductor device according to claim 1, the semiconductor device further comprising: A second lower conductive pattern disposed in the first interlayer insulating film and spaced apart from the first lower conductive pattern in the first direction, Wherein the second lower conductive pattern includes a third valley region and a fourth valley region spaced apart from each other in the first direction, and Wherein at least one of the third valley region and the fourth valley region is filled with an insulating material.

11. The semiconductor device according to claim 1, the semiconductor device further comprising: A second lower conductive pattern disposed in the first interlayer insulating film and spaced apart from the first lower conductive pattern in the first direction, Wherein the second lower conductive pattern includes a third valley region and a fourth valley region spaced apart from each other in the first direction, and Wherein at least one of the third valley region and the fourth valley region includes a wiring void.

12. A semiconductor device, the semiconductor device comprising: A lower conductive pattern, comprising a lower barrier film forming a filled film trench and a lower filling film disposed on the lower barrier film in the filled film trench, the lower conductive pattern having a top surface with a first width in a first direction parallel to the upper surface of the substrate; and an upper conductive pattern, disposed on the lower conductive pattern, the upper conductive pattern being connected to the lower conductive pattern and comprising an upper barrier film and an upper filling film disposed on the upper barrier film, wherein, the bottom surface of the upper conductive pattern has a second width in the first direction, wherein, the second width is greater than or equal to the first width, and the upper barrier film directly covers a sidewall portion of the lower barrier film, and the sidewall portion of the lower barrier film forms an inner sidewall of the filled film trench, wherein, the lower conductive pattern includes a first valley portion and a second valley portion spaced apart from each other in the first direction, and the first valley portion and the second valley portion are defined by the upper surface of the lower filling film and the inner surface of the sidewall portion of the lower barrier film not covered by the lower filling film, wherein, the upper barrier film covers the inner surface of the sidewall portion of the lower barrier film not covered by the lower filling film and the top surface of the lower barrier film.

13. The semiconductor device according to claim 12, wherein, the first valley portion and the second valley portion are included in the top surface of the lower conductive pattern.

14. The semiconductor device according to claim 13, wherein, the first valley portion defines a first valley region extending in a second direction intersecting the first direction, the second valley portion defines a second valley region extending in the second direction, and the first valley region and the second valley region are spaced apart from each other in the first direction.

15. The semiconductor device according to claim 12, wherein, the lower conductive pattern further includes a lower liner disposed between the lower barrier film and the lower filling film, and the uppermost portion of the lower liner is lower than the uppermost portion of the lower barrier film and the uppermost portion of the lower filling film.

16. A semiconductor device, the semiconductor device comprising: a first interlayer insulating film, disposed on a substrate and including a first trench; a lower conductive pattern, disposed in the first trench and including a lower barrier film, a lower liner disposed on the lower barrier film, and a lower filling film disposed on the lower liner; a second interlayer insulating film, disposed on the first interlayer insulating film and including a second trench exposing at least a portion of the top surface of the lower conductive pattern; and an upper conductive pattern, filling the second trench and including an upper barrier film and an upper filling film disposed on the upper barrier film, wherein, the lower conductive pattern further includes a valley region defined by the lower barrier film, the lower liner, and the lower filling film and extending in the thickness direction of the substrate, and wherein, the upper conductive pattern fills the valley region, wherein, the valley region is defined by the upper surface of the lower filling film and the inner surface of the sidewall portion of the lower barrier film not covered by the lower filling film, wherein, the upper barrier film extends along the sidewall of the second trench and covers the inner surface of the sidewall portion of the lower barrier film not covered by the lower filling film and the top surface of the lower barrier film.

17. The semiconductor device according to claim 16, wherein, The width of the top surface of the lower conductive pattern is less than or equal to the width of the bottom surface of the upper conductive pattern.

18. The semiconductor device according to claim 16, wherein, The lowermost portion of the upper filling film is higher than the uppermost portion of the lower barrier film.

19. The semiconductor device according to claim 16, wherein, the lower barrier film includes tantalum, the lower liner includes cobalt, and The lower filling film includes copper.

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