Package-on-package semiconductor packaging

Abstract

A package-on-package (POP) type semiconductor package is provided, the POP type semiconductor package including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is located, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and an alignment mark. The POP type semiconductor package may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment mark may be used to identify the upper package, and the alignment mark may be on the lower package below and near the outer boundary of the upper package.

Description

Technical Field

[0001] The inventive concept relates to semiconductor packages, and more particularly, to package-on-package (POP) type semiconductor packages. Background Art

[0002] Due to the rapid development of the electronics industry and user demand, electronic devices are becoming smaller and lighter. Therefore, highly integrated semiconductor chips, as core components of electronic devices, are becoming more and more popular. In addition, with the widespread use of mobile products, small multifunctional electronic devices are becoming more and more popular. Therefore, a POP-type semiconductor package has been proposed, in which an upper package with different functions is stacked on a lower package. Summary of the Invention

[0003] The inventive concept is directed to providing a package-on-package (POP) type semiconductor package in which misalignment between a lower package and an upper package can be detected.

[0004] According to some embodiments of the inventive concept, a package-on-package (POP) type semiconductor package is provided, comprising: a lower package including a lower package substrate in which a lower semiconductor chip is located, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and an alignment mark, the lower package having a first size; an upper package including an upper package substrate mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and an upper semiconductor chip on the upper package substrate, the upper package having a second size smaller than the first size. The alignment mark can be used to identify the upper package, and the alignment mark can be on the lower package below and near the outer boundary of the upper package. The alignment mark can indicate the outline of the upper package, and the alignment mark can be below and adjacent to the outline of the upper package.

[0005] According to some embodiments of the present invention, a POP-type semiconductor package is provided, comprising: a lower package including a lower package substrate having a lower semiconductor chip therein, an upper redistribution structure on the lower package substrate and the lower semiconductor chip and including an upper redistribution insulating layer and an upper redistribution layer, and an alignment mark, the lower package having a first size; and an upper package including an upper package substrate mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and an upper semiconductor chip on the upper package substrate, the upper package having a second size smaller than the first size. The alignment mark can be used to identify the upper package, and the alignment mark can be below and near the outer boundary of the upper package in the upper redistribution structure and can be at the same level as the upper redistribution layer. The alignment mark can indicate the outline of the upper package, and the alignment mark can be below and adjacent to the outline of the upper package.

[0006] According to some embodiments of the inventive concept, a POP-type semiconductor package is provided, comprising: a lower package including a lower package substrate with a lower semiconductor chip therein, an upper redistribution structure on the lower semiconductor package substrate and the lower semiconductor chip, and an alignment mark, the lower package having a first size; an upper package including an upper package substrate mounted on and electrically connected to the upper redistribution structure of the lower package, and an upper semiconductor chip on the upper package substrate, the upper package having a second size smaller than the first size; and a cover layer on the upper redistribution structure. The alignment mark can be used to identify the upper package, and the alignment mark can be on the upper redistribution structure below and near the outer boundary of the upper package and at the same level as the cover layer. The alignment mark can indicate the outline of the upper package, and the alignment mark can be below and adjacent to the outline of the upper package. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Some embodiments of the inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a schematic plan view of a package-on-package (POP) type semiconductor package according to some embodiments of the inventive concept;

[0009] Figure 2 yes Figure 1 An enlarged view of a portion A of the lower package;

[0010] Figure 3 It is a POP type semiconductor package that can be Figure 1 a sectional view taken along line III-III;

[0011] Figure 4 is a schematic cross-sectional view of a POP type semiconductor package according to some embodiments of the inventive concept;

[0012] Figure 5 is a schematic cross-sectional view of a POP type semiconductor package according to some embodiments of the inventive concept;

[0013] Figures 6 to 9 is a schematic plan view of a POP type semiconductor package according to some embodiments of the inventive concept;

[0014] Figure 10 is a schematic plan view of a POP type semiconductor package according to some embodiments of the inventive concept;

[0015] Figure 11 yes Figure 10 An enlarged view of part B of the lower package;

[0016] Figure 12 and Figure 13is a schematic plan view of a POP type semiconductor package according to some embodiments of the inventive concept;

[0017] Figures 14 to 18 is a schematic cross-sectional view illustrating a method of manufacturing a POP type semiconductor package according to some embodiments of the inventive concept;

[0018] Figure 19 is a block diagram of a POP type semiconductor package according to some embodiments of the inventive concept; and

[0019] Figure 20 is a schematic block diagram of a POP type semiconductor package according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0020] Hereinafter, some example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0021] In the drawings, the same elements may be assigned the same reference numerals and may not be described redundantly or repeatedly herein. Figure 1 is a schematic plan view of a package-on-package (POP) type semiconductor package according to some embodiments of the inventive concept. Figure 2 yes Figure 1 To simplify the explanation, the enlarged view of the lower package part A is shown. Figure 2 The upper package is not shown.

[0022] In detail, Figure 1 and Figure 2 The XY plane of the semiconductor package 200 is shown, and the XY plane is parallel to Figure 3 A surface of the lower package substrate 205, for example, the second surface 205b.

[0023] For ease of explanation, Figure 1 and Figure 2 , parts of components that overlap each other are also shown. Figure 1 and Figure 2 The semiconductor package 200 may not show all of its components, but may show only some components to illustrate the inventive concept. Figure 2 FIG. 2 is a top plan view of the lower package 200B. Figure 2 , reference numeral 204 may refer to a boundary line where an upper package 200T is mounted. The semiconductor package 200 includes a lower package 200B and an upper package 200T on the lower package 200B.

[0024] The lower package 200B may have a first size W1. The first size W1 may refer to length or width. The upper package 200T may have a second size W2 smaller than the first size W1. The second size W2 may refer to length or width. The first size W1 may be the size of the lower package substrate or the size of the lower redistribution structure described later. Figure 1 and Figure 2 As shown, upper redistribution structures 203 a and 203 b including an upper redistribution insulating layer 203 b and an upper redistribution layer 203 a may be provided on the lower package 200B.

[0025] In other words, the lower package 200B may include the upper redistribution structures 203a and 203b. Therefore, the lower package 200B may be a fan-out package including the upper redistribution structures 203a and 203b outside the lower semiconductor chip as described below.

[0026] In addition, the lower package 200B can be a panel-level package manufactured at the panel level or a wafer-level package manufactured at the wafer level. The lower package 200B can be collectively referred to as a fan-out panel-level package (FOPLP) or a fan-out wafer-level package (FOWLP). The upper redistribution layer 203a can be, for example, a metal layer.

[0027] although Figure 2 The upper redistribution insulating layer 203b is shown as being provided only on a portion of the lower package 200B, but in some embodiments, the upper redistribution insulating layer 203b may be provided on the entire surface of the lower package 200B. The upper redistribution insulating layer 203b may be, for example, a transparent organic layer. The upper redistribution insulating layer 203b may be, for example, a photoimageable dielectric (PID) layer. The grid pattern (e.g. Figure 2 The MP, or mesh pattern) 130 may be provided on the lower package 200B.

[0028] like Figure 2 As shown, the MP 130 may include a plurality of quadrilateral insulating patterns 130 a and a metal layer 130 b located between the plurality of insulating patterns 130 a .

[0029] The MP 130 may suppress or restrict lifting or distortion of the metal layer 130b by controlling thermal expansion of the metal layer 130b on the lower package 200B. A plurality of MPs 130 may be provided on an upper region of the lower package 200B.

[0030] The MP 130 may be provided on a portion on which the upper package 200T is mounted or on a portion on which the upper package 200T is not mounted. The metal layer 130b and the upper redistribution layer 203a of the MP 130 may be formed of the same material. An upper redistribution pad portion 294b, which may be connected to the upper package 200T, may be provided on the lower package 200B. The upper redistribution pad portion 294b may be positioned at the same level as the upper redistribution layer 203a, as described below. The lower package 200B may include an alignment mark 150. In some embodiments, the alignment mark 150 may be provided on the lower package 200B below and near the outer boundary of the upper package 200T.

[0031] although Figure 1 The alignment mark 150 is shown provided on the lower package 200B below the corner portion of the upper package 200T, but the alignment mark 150 may be provided at a boundary between the lower package 200B and the upper package 200T on the lower package 200B. The alignment mark 150 may include an upper portion of the lower package 200B that does not overlap with the upper package 200T.

[0032] The alignment mark 150 can be provided to identify the upper package 200T using, for example, a visual camera when or after stacking (or mounting) the upper package 200T. When the upper package 200T is mounted on the lower package 200B, the alignment mark 150 can be in the form of a solid pattern that can be identified by the visual camera. In some embodiments, the alignment mark 150 can be used to identify or detect the outline of the upper package 200T, thereby detecting misalignment of the upper package 200T. Therefore, the alignment mark 150 can indicate the outline of the upper package 200T.

[0033] A solid pattern may refer to a non-empty pattern having a certain area. The alignment mark 150 may be referred to as an alignment pattern for accurately aligning the upper package 200T on the lower package 200B. The alignment mark 150 may be an identification pattern that can be identified by a visual camera. The alignment mark 150 may be positioned on the upper portion of the lower package 200B exposed by the upper package 200T. In some embodiments, each alignment mark 150 may include a portion that does not overlap with the upper package 200T, such as Figure 1 shown.

[0034] One of the alignment marks 150 may be positioned under one of the corner portions of the upper package 200T. When the upper package 200T has a quadrilateral shape, at least two of the alignment marks 150 may be positioned under two opposite corner portions of the upper package 200T, respectively. In some embodiments, as Figure 1 As shown, the four alignment marks 150 may be respectively located under all quadrilateral corner portions of the upper package 200T.

[0035] The alignment mark 150 may have various forms or shapes and may be, for example, Figure 1 As described herein, the POP type semiconductor package 200 may include an alignment mark 150 formed on the lower package 200B without overlapping the upper package 200T.

[0036] The alignment mark 150 can be used to accurately measure or identify the boundary portion of the upper package 200T by a visual camera. Therefore, in the POP type semiconductor package 200 of the inventive concept, it is possible to detect misalignment between the lower package 200B and the upper package 200T by photographing the upper package 200T and using the alignment mark 150 to identify the upper package 200T.

[0037] Therefore, in the POP type semiconductor package 200 of the inventive concept, the upper package 200T may be accurately aligned on the lower package 200B.

[0038] Figure 3 is a cross-sectional view of a POP type semiconductor package according to some embodiments of the inventive concept. Figure 3 It can be a POP type semiconductor package along Figure 1 A cross-sectional view taken along line III-III.

[0039] Figure 3 The semiconductor package 200 may not show all of its components, but only shows some components to illustrate the inventive concept.

[0040] Figure 3 The cross-sectional view is taken along a horizontal direction (eg, X direction or Y direction) perpendicular to the Z-axis direction. The Z-axis direction may be perpendicular to an XY plane parallel to the second surface 205b of the lower package substrate 205. The semiconductor package 200 may include a lower package 200B and an upper package 200T.

[0041] The semiconductor package 200 may be a POP-type package in which an upper package 200T is attached to a lower package 200B. The upper package 200T may be attached to the lower package 200B such that the active surface (e.g., the lower surface) of the upper semiconductor chip 231 faces the lower package 200B. The lower package 200B may be a fan-out panel-level package (FOPLP) or a fan-out wafer-level package (FOWLP).

[0042] The lower package 200B may be a fan-out package including a lower redistribution structure 201 and an upper redistribution structure 203 outside a lower semiconductor chip 210. The lower package 200B may be a panel-level package or a wafer-level package including a lower package substrate 205. The lower package 200B may include the lower package substrate 205 and a lower semiconductor chip 210 within the lower package substrate 205. In some embodiments, the lower semiconductor chip 210 may be buried within the lower package substrate 205.

[0043] The lower package substrate 205 may be, for example, a printed circuit board. The lower package substrate 205 may be, for example, a semiconductor substrate. Here, an example in which the lower package substrate 205 is a printed circuit board will be described. The semiconductor substrate constituting the lower semiconductor chip 210 or the lower package substrate 205 may include, for example, silicon (Si).

[0044] The semiconductor substrate constituting the lower semiconductor chip 210 may include, for example, a semiconductor element such as germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate constituting the lower semiconductor chip 210 may have, for example, a silicon-on-insulator (SOI) structure.

[0045] For example, the semiconductor substrate constituting the lower semiconductor chip 210 may include a buried oxide (BOX) layer. In some embodiments, the semiconductor substrate constituting the lower semiconductor chip 210 may include a conductive region, such as a well containing impurities. Impurities may be contained in the well by a doping process. In some embodiments, the semiconductor substrate constituting the lower semiconductor chip 210 may include various types of isolation structures, such as a shallow trench isolation (STI) structure. The lower semiconductor chip 210 may include an active surface 210 a and an inactive surface 210 b opposite to the active surface 210 a.

[0046] In the lower semiconductor chip 210, various types of individual devices (not shown) may be provided on the active surface 210a. The various types of individual devices may include various types of microelectronic devices, for example, metal oxide semiconductor field effect transistors (MOSFETs) (such as complementary metal insulator semiconductor (CMOS) transistors), large-scale integration (LSI) systems, image sensors such as CMOS image sensors (CIS), microelectromechanical systems (MEMS), active devices, passive devices, etc. The lower semiconductor chip 210 may include a chip pad 211 on the active surface 210a.

[0047] The chip pad 211 may be electrically connected to one or more individual devices of the lower semiconductor chip 210. The lower semiconductor chip 210 may include a central processing unit (CPU), a microprocessor unit (MPU), a graphics processing unit (GPU), or an application processor (AP). The lower semiconductor chip 210 may be a controller chip for controlling the upper semiconductor chip 231, which will be described later. The lower package substrate 205 may be, for example, a multilayer printed circuit board on which a plurality of interconnection layers 238 are stacked.

[0048] The plurality of interconnect layers 238 may be electrically connected to one another. The lower package substrate 205 may include a lower package substrate body 205bd. The lower package substrate body 205bd may be formed of, for example, at least one material selected from phenolic resin, epoxy resin, and polyimide. For example, the lower package substrate body 205bd may include at least one material selected from flame retardant 4 (FR4), tetrafunctional epoxy resin, polyphenylene ether, epoxy / polyphenylene ether, bismaleimide triazine (BT), polyamide staple fiber mat (thermount), cyanate ester, polyimide, and liquid crystal polymer.

[0049] First and second connection pads 207 a and 207 b may be provided near the first and second surfaces 205 a and 205 b of the lower package substrate 205 , respectively.

[0050] An interconnection layer 238 may be provided in the lower package substrate 205 to connect the first and second connection pads 207a, 207b with the conductive path 240 that passes through the lower package substrate body 205bd. In some embodiments, an interconnection pattern (or interconnection layer) may be further provided on both surfaces of the lower package substrate body 205bd to connect the first and second connection pads 207a, 207b, and the conductive path 240. The first and second connection pads 207a, 207b, and the interconnection layer 238 may each be, for example, a metal layer.

[0051] The first connection pad 207a, the second connection pad 207b, and the interconnect layer 238 can be formed of, for example, electrolytically deposited (ED) copper foil, rolled annealed (RA) copper foil, stainless steel foil, aluminum foil, ultra-thin copper foil, sputtered copper, copper alloy, etc. The conductive path 240 can be formed of, for example, copper, nickel, stainless steel, or beryllium copper. The lower package substrate 205 may include a cavity 205H that penetrates the lower package substrate body 205bd. In some embodiments, the cavity 205H may extend through the lower package substrate body 205bd.

[0052] The lower semiconductor chip 210 may be in the cavity 205H of the lower package substrate 205. The horizontal cross-sectional area of ​​the cavity 205H may be greater than the horizontal cross-sectional area of ​​the lower semiconductor chip 210. The depth of the cavity 205H, that is, the thickness of the lower package substrate 205 in the Z direction, may be equal to or greater than the thickness of the lower semiconductor chip 210 in the Z direction. The lower semiconductor chip 210 may be in the cavity 205H so as to be spaced apart from the inner side surface of the cavity 205H of the lower package substrate 205. In some embodiments, the lower semiconductor chip 210 may be spaced apart from the side surface of the lower package substrate 205 that defines the cavity 205H.

[0053] Therefore, a lower molding layer 213 may be provided on the lower semiconductor chip 210 and the lower package substrate 205 to surround the lower semiconductor chip 210 in the cavity 205H. The lower molding layer 213 may be provided on the second surface 205b of the lower package substrate 205. The second connection pad 207b may be covered with the lower molding layer 213. The chip pad 211 of the lower semiconductor chip 210 and the first connection pad 207a of the lower package substrate 205 may be at substantially the same level. In some embodiments, as Figure 3 As shown, the surface of the chip pad 211 adjacent to the first surface 205a of the lower package substrate 205 and the surface of the first connection pad 207a may be coplanar with each other. Figure 3 As shown, the surface of the chip pad 211 and the surface of the first connection pad 207a adjacent to the first surface 205a of the lower package substrate 205 can be coplanar with the first surface 205a of the lower package substrate 205. As used herein, "element A covers element B" (or similar language) means that element A extends over element B, but does not necessarily mean that element A completely covers the surface of element B.

[0054] The lower redistribution structure 201 may be provided on the active surface 210a of the lower semiconductor chip 210 and the first surface 205a of the lower package substrate 205. The lower redistribution structure 201 may include a plurality of layers, including a lower redistribution layer 201a and a lower redistribution insulating layer 201b.

[0055] The lower redistribution layer 201a may be a multilayer structure in which a plurality of redistribution patterns or interconnect layers are stacked. The lower redistribution insulating layer 201b may be a multilayer structure in which a plurality of insulating layers are stacked. In some embodiments, the lower redistribution layer 201a may be a metal layer formed of a material such as copper, nickel, stainless steel, or beryllium copper. A first capping layer 293 may be provided below the lower redistribution structure 201.

[0056] A first cover layer 293 may be provided to protect the lower redistribution structure 201. The first cover layer 293 may expose a portion of the lower redistribution pad portion 294a connected to the lower redistribution layer 201a. A first external connection pad 291a may be provided on the portion of the lower redistribution pad portion 294a exposed by the first cover layer 293.

[0057] Due to the formation of the first cover layer 293, the first external connection pad 291a can be finely formed. The first cover layer 293 can be formed of, for example, a hydrocarbon ring compound containing a filler. The filler can be, for example, a SiO2 filler. The first cover layer 293 can be, for example, an Ajinomoto build-up film (ABF). The first cover layer 293 can be thicker than the lower redistribution pad portion 294a and the first external connection pad 291a. The external connection terminals 290 can be attached to the first external connection pads 291a, respectively.

[0058] The external connection terminals 290 may be, for example, solder balls or bumps. The external connection terminals 290 may electrically connect the semiconductor package 200 to an external device. The upper redistribution structure 203 may be positioned on the lower package substrate 205 and the lower semiconductor chip 210 .

[0059] The upper redistribution structure 203 may include multiple layers. The upper redistribution structure 203 may include an upper redistribution layer 203a and an upper redistribution insulating layer 203b. The upper redistribution layer 203a may be an interconnect pattern that is horizontally connected to each other. The upper redistribution layer 203a may pass through the lower mold layer 213 and may be connected to the second connection pad 207b. The upper redistribution layer 203a may be a metal layer formed of a material such as copper, nickel, stainless steel, or beryllium copper.

[0060] The upper redistribution insulating layer 203b may be, for example, a transparent organic layer. The upper redistribution insulating layer 203b may be, for example, a photoimageable dielectric (PID) layer. The upper redistribution insulating layer 203b may include, for example, epoxy resin or polyimide. In some embodiments, the upper redistribution insulating layer 203b may be formed by applying and curing a redistribution material. The alignment mark 150 may be included in the upper redistribution insulating layer 203b constituting the upper redistribution structure 203.

[0061] The alignment mark 150 may be positioned at the same level as the upper redistribution layer 203a. The alignment mark 150 may be located below and near the outer boundary of the upper package 200T. When or after stacking the upper package 200T, the alignment mark 150 may be provided to accurately identify or detect the outline of the upper package 200T using a visual camera. In some embodiments, the alignment mark 150 may be formed of the same material as the upper redistribution layer 203a. Each of the alignment mark 150 and the upper redistribution layer 203a may include a lower surface facing the lower package substrate 205 and an upper surface opposite to the lower surface. In some embodiments, the upper surface of the alignment mark 150 may be coplanar with the upper surface of the upper redistribution layer 203a, as shown in FIG. Figure 3 shown.

[0062] The alignment marks 150 can be manufactured using the same manufacturing process as the upper redistribution layer 203a. The alignment marks 150 can be located on the upper portion of the lower package 200B that is exposed by the upper package 200T (i.e., does not overlap with the upper package 200T) and below the corner portions of the upper package 200T. Therefore, when the upper package 200T is mounted on the lower package 200B, the alignment marks 150 can be used as recognition patterns for recognizing the outline of the upper package 200T, for example, using a visual camera.

[0063] References here Figure 1 and Figure 2 The alignment mark 150 is described, and thus a detailed description thereof will be omitted here. In the semiconductor package 200, the alignment mark 150 may be used to accurately identify or detect the outline of the upper package 200T by photographing the upper package 200T with a vision camera.

[0064] Therefore, in the semiconductor package 200, misalignment between the lower package 200B and the upper package 200T can be detected. As a result, in the POP-type semiconductor package 200 of the inventive concept, the upper package 200T can be accurately aligned on the lower package 200B. In the semiconductor package 200 according to some embodiments of the inventive concept, when the upper package 200T is accurately aligned on the lower package 200B, the package connection terminal 292 can be directly connected to the upper redistribution pad portion 294b of the upper redistribution structure 203.

[0065] An upper redistribution pad portion 294b may be provided on a portion of the upper redistribution layer 203a. The package connection terminal 292 may be, for example, a solder ball or a bump.

[0066] The package connection terminals 292 may electrically connect the lower package 200B to the upper package 200T. The upper package 200T may be attached to the lower package 200B via the package connection terminals 292 between the upper package 200T and the lower package 200B. The upper package 200T may include an upper semiconductor chip 231 attached to an upper package substrate 251.

[0067] The upper package substrate 251 and the upper semiconductor chip 231 may be electrically connected to each other through bonding wires or bumps. Figure 3 , the upper semiconductor chip 231 may be connected to the upper package substrate 251 by using bumps (not shown). The upper semiconductor chip 231 may be, for example, a memory semiconductor chip.

[0068] The memory semiconductor chip may be, for example, a volatile memory semiconductor chip such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory semiconductor chip such as a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). The upper semiconductor chip 231 may be any semiconductor chip, without being limited to the examples listed here.

[0069] For example, the upper semiconductor chip 231 may include a plurality of memory semiconductor chips. In some embodiments, the upper package 200T may further include a controller chip for controlling the upper semiconductor chip 231. The upper package 200T may include an upper molding layer 255 surrounding at least a portion of the upper semiconductor chip 231. In some embodiments, the upper molding layer 255 may completely surround the upper semiconductor chip 231, but the inventive concept is not limited thereto. In some embodiments, the upper molding layer 255 may extend only over a portion of the upper semiconductor chip 231.

[0070] The upper molding layer 255 can be formed of, for example, epoxy molding compound (EMC). The upper molding layer 255 is shown as covering the non-active surface (e.g., the upper surface) of the upper semiconductor chip 231, but is not limited thereto. As described herein, the semiconductor package 200 can be a POP type, in which the upper package 200T is attached to the lower package 200B to be electrically connected to the lower package 200B via the package connection terminals 292.

[0071] In addition, in the POP type semiconductor package 200 of the inventive concept, misalignment between the lower package 200B and the upper package 200T may be detected by photographing the upper package 200T with a vision camera and recognizing the upper package 200T using the alignment mark 150 .

[0072] Therefore, in the POP type semiconductor package 200 of the inventive concept, the upper package 200T may be accurately aligned on the lower package 200B.

[0073] Figure 4 is a schematic cross-sectional view of a POP type semiconductor package according to some embodiments of the inventive concept.

[0074] Figure 4 The semiconductor package 300 and Figures 1 to 3 The semiconductor package 200 is similar to the semiconductor package 200 , but a second cover layer 190 is further provided on the upper redistribution structure 203 , and the alignment mark 150 a is provided on the same level as the cover layer 190 .

[0075] Figure 4 of and Figures 1 to 3 Similar or identical parts may be briefly described or may not be described.

[0076] Figure 4 The semiconductor package 300 may not show all of its components, but only shows some components to illustrate the inventive concept. The semiconductor package 300 may be a POP type package in which an upper package 200T' is attached to a lower package 200B'.

[0077] The lower package 200B′ may be a fan-out panel level package (FOPLP) or a fan-out wafer level package (FOWLP). The lower package 200B′ may include a lower semiconductor chip 210 in (eg, buried in) a lower package substrate 205 .

[0078] The lower package substrate 205 may be, for example, a printed circuit board. The lower package substrate 205 may be, for example, a semiconductor substrate. Here, an example in which the lower package substrate 205 is a printed circuit board will be described. The lower semiconductor chip 210 may include an active surface 210 a and an inactive surface 210 b opposite to the active surface 210 a.

[0079] The lower semiconductor chip 210 may include a chip pad 211 on the active surface 210a. The chip pad 211 may be electrically connected to one or more individual devices included in the lower semiconductor chip 210. The lower package substrate 205 may include a lower package substrate body 205bd.

[0080] The lower package substrate body 205bd may be formed of, for example, at least one material selected from phenolic resin, epoxy resin, and polyimide. A conductive path 240 penetrating the lower package substrate body 205bd may be formed in the lower package substrate 205.

[0081] The conductive path 240 may be a metal layer formed of, for example, copper, nickel, stainless steel, or beryllium copper.The lower package substrate 205 may include a cavity 205H penetrating or extending through the lower package substrate body 205bd.

[0082] The lower semiconductor chip 210 may be provided in the cavity 205H of the lower package substrate 205. Figure 3 In some embodiments, the lower semiconductor chip 210 may directly contact the side surface of the lower package substrate body 205bd, which defines the following: Figure 4 The cavity 205H is shown. A lower redistribution structure 201 may be provided on the active surface 210 a of the lower semiconductor chip 210 and the first surface 205 a of the lower package substrate 205 .

[0083] The lower redistribution structure 201 may include a lower redistribution layer 201a and a lower redistribution insulating layer 201b. The lower redistribution layer 201a may include a redistribution pattern. Figure 3 Unlike the embodiment, the first external connection pad 291a can be formed directly below the lower redistribution structure 201 without an intermediate first cover layer (eg, Figure 3 The first covering layer 293 in the embodiment of the present invention.

[0084] The first external connection pad 291 a may be connected to the lower redistribution layer 201 a . The external connection terminal 290 may be attached to the first external connection pad 291 a . The upper redistribution structure 203 may be positioned on the lower package substrate 205 and the lower semiconductor chip 210 .

[0085] The upper redistribution structure 203 includes an upper redistribution layer 203 a and an upper redistribution insulating layer 203 b . The upper redistribution layer 203 a may include a redistribution pattern. A second capping layer 190 and a second external connection pad 291 b may be provided on the upper redistribution structure 203 .

[0086] The second external connection pad 291b may be electrically connected to the upper redistribution layer 203a. When the second cover layer 190 is provided, the second external connection pad 291b may be formed more precisely. In some embodiments, the second cover layer 190 may be formed of the same material as the upper redistribution insulation layer 203b.

[0087] For example, the second cover layer 190 may be a transparent organic layer. The second cover layer 190 may be, for example, a photoimageable dielectric (PID) layer. The alignment mark 150a may be formed on the upper redistribution structure 203 at the same level as the second cover layer 190. In some embodiments, the lower surface of each alignment mark 150a and the upper surface of the upper redistribution structure 203 may be coplanar with each other, such as Figure 4 shown.

[0088] The alignment mark 150a may be positioned on the upper redistribution structure 203 at the same level as the second cover layer 190 and below and near the outer boundary of the upper package 200T'. The alignment mark 150a may be performed with Figures 1 to 3 The alignment mark 150 has the same function.

[0089] That is, when the upper package 200T' is stacked on the lower package 200B' or thereafter, an alignment mark 150a may be provided to identify the outline of the upper package 200T'. In some embodiments, the alignment mark 150a may be formed of the same material as the upper redistribution layer 203a, such as a metal layer. The alignment mark 150a may be located on the upper portion of the lower package 200B' exposed by the upper package 200T' and below the corner portion of the upper package 200T'. In some embodiments, one of the corner portions of the upper package 200T' may overlap with a first portion of one of the alignment marks 150a, and one of the corner portions of the upper package 200T' may not overlap with a second portion of one of the alignment marks 150a, as shown in FIG. Figure 4 As used herein, "element A overlaps element B" (or similar language) means that there is at least one line extending in the Z-axis direction that intersects both element A and element B.

[0090] Already referenced Figures 1 to 3 The alignment mark 150 is described, so its detailed description will be omitted here. In the semiconductor package 300, misalignment between the lower package 200B' and the upper package 200T' can be detected by photographing the upper package 200T' and by using the alignment mark 150a for identifying the upper package 200T'.

[0091] When no misalignment occurs between the lower package 200B′ and the upper package 200T′, the package connection terminals 292 may be directly connected to the second external connection pads 291 b of the upper redistribution structure 203 . The upper package 200T′ may be mounted on the package connection terminals 292 .

[0092] The upper package 200T' may be attached to the lower package 200B' via the package connection terminals 292 between the upper package 200T' and the lower package 200B'. The upper package 200T' may include an upper semiconductor chip 231 attached to an upper package substrate 251. The upper semiconductor chip 231 may include a first upper semiconductor chip 231a and a second upper semiconductor chip 231b.

[0093] The first upper semiconductor chip 231a and the second upper semiconductor chip 231b may be connected to the upper package substrate 251 via bonding wires 233. The upper semiconductor chip 231 may include a memory chip and / or a controller chip. The upper package 200T' may include an upper molding layer 255 surrounding at least a portion of the upper semiconductor chip 231. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0094] The upper molding layer 255 can be formed of, for example, epoxy molding compound (EMC). The upper molding layer 255 is shown as covering the non-active surface (e.g., upper surface) of the upper semiconductor chip 231, but the inventive concept is not limited thereto. In some embodiments, the upper molding layer 255 may not cover the non-active surface (e.g., upper surface) of the upper semiconductor chip 231. As described herein, the semiconductor package 300 can be a POP type, wherein the upper package 200T' is attached to the lower package 200B' to be electrically connected to the lower package 200B' via the package connection terminals 292.

[0095] In addition, in the POP type semiconductor package 300 of the inventive concept, misalignment between the lower package 200B′ and the upper package 200T′ may be detected using the alignment mark 150 a .

[0096] Figure 5 is a schematic cross-sectional view of a POP type semiconductor package according to some embodiments of the inventive concept.

[0097] Figure 5 The semiconductor package 400 may be similar to Figure 4 The semiconductor package 300 is similar to the semiconductor package 300 , but the plurality of first lower semiconductor chips 210 - 1 and the second lower semiconductor chips 210 - 2 are in the lower package substrate 205 (eg, buried in the lower package substrate 205 ).

[0098] Figure 5 of and Figures 1 to 3 Portions similar to or identical to those of 4 may be briefly described or may not be described. The semiconductor package 400 may be a POP type package in which an upper package 200T′ is attached to a lower package 200B″.

[0099] The lower package 200B″ may include a first lower semiconductor chip 210-1 and a second lower semiconductor chip 210-2 in a lower package substrate 205 (e.g., buried in the lower package substrate 205) to be separated from each other. The lower package substrate 205 may be, for example, a printed circuit board. The first lower semiconductor chip 210-1 and the second lower semiconductor chip 210-2 may be positioned in a first area A1 and a second area A2 of the lower package substrate 205, respectively.

[0100] The first lower semiconductor chip 210-1 may include an active surface 210a-1 and an inactive surface 210b-1 opposite to the active surface 210a-1. The first lower semiconductor chip 210-1 may include a chip pad 211-1 on the active surface 210a-1. The second lower semiconductor chip 210-2 may include an active surface 210a-2 and an inactive surface 210b-2 opposite to the active surface 210a-2.

[0101] The second lower semiconductor chip 210 - 1 may include a chip pad 211 - 2 on the active surface 210 a - 2 . A conductive via 240 penetrating the lower package substrate body 205 bd may be provided in the lower package substrate 205 .

[0102] A conductive path 240 may be provided between the first lower semiconductor chip 210-1 and the second lower semiconductor chip 210-2. The lower package substrate 205 may include a first cavity 205H1 and a second cavity 205H2, which may penetrate or extend through the lower package substrate body 205bd. The first lower semiconductor chip 210-1 may be provided in the first cavity 205H1 of the lower package substrate 205. The second lower semiconductor chip 210-2 may be provided in the second cavity 205H2 of the lower package substrate 205. The first lower semiconductor chip 210-1 and the second lower semiconductor chip 210-2 may contact the inner surface of the first cavity 205H1 and the inner surface of the second cavity 205H2, respectively. In some embodiments, the first lower semiconductor chip 210-1 may directly contact the side surface of the lower package substrate body 205bd defining the first cavity 205H1, and the second lower semiconductor chip 210-2 may directly contact the side surface of the lower package substrate body 205bd defining the second cavity 205H2. Figure 5 shown.

[0103] The lower redistribution structure 201 may be provided on the active surface 210a-1 of the first lower semiconductor chip 210-1, the active surface 210a-2 of the second lower semiconductor chip 210-2, and the first surface 205a of the second lower package substrate 205. The lower redistribution structure 201 may include a lower redistribution layer 201a and a lower redistribution insulating layer 201b.

[0104] The first external connection pads 291a and the external connection terminals 290 may be attached to a lower portion of the lower redistribution structure 201. The upper redistribution structure 203 may be positioned on the lower package substrate 205 and the first and second lower semiconductor chips 210-1 and 210-2.

[0105] The upper redistribution structure 203 may include an upper redistribution layer 203a and an upper redistribution insulating layer 203b. A second cover layer 190 and a second external connection pad 291b may be provided on the upper redistribution structure 203. An alignment mark 150a may be formed on the upper redistribution structure 203 at the same level as the second cover layer 190. The alignment mark 150a may be positioned on the upper redistribution structure 203 at the same level as the second cover layer 190 and below and near the outer boundary of the upper package 200T'.

[0106] The alignment mark 150a may be performed with Figures 1 to 4 The alignment marks 150 and 150a have the same function. Figures 1 to 4 The alignment marks 150 and 105a are described, so their detailed description will be omitted here. The package connection terminal 292 can be directly connected to the second external connection pad 291b of the upper redistribution structure 203. The upper package 200T' can be mounted on the package connection terminal 292. As described herein, the semiconductor package 400 of the inventive concept may include a first lower semiconductor chip 210-1 and a second lower semiconductor chip 210-2.

[0107] Each of the first lower semiconductor chip 210-1 and the second lower semiconductor chip 210-2 may include, for example, a central processing unit (CPU), a microprocessor unit (MPU), a graphics processing unit (GPU), or an application processor (AP). The second lower semiconductor chip 210-2 may be, for example, a power management chip.

[0108] In some embodiments, the first lower semiconductor chip 210-1 or the second lower semiconductor chip 210-2 may be a controller chip for controlling the upper semiconductor chip 231. As described herein, when a plurality of lower semiconductor chips are included in the lower package substrate 205, various functions may be performed in the semiconductor package 400. In addition, in the semiconductor package 400 of the inventive concept, the alignment mark 150a may be used to detect misalignment between the lower package 200B″ and the upper package 200T′.

[0109] Therefore, in the semiconductor package 400 , the upper package 200T′ can be accurately aligned on the lower package 200B″.

[0110] Figures 6 to 9 is a schematic plan view of a POP type semiconductor package according to some embodiments of the inventive concept.

[0111] Figures 6 to 9 The semiconductor packages 200-1, 200-2, 200-3 and 200-4 may be similar to Figures 1 to 31 , but the arrangement of the alignment marks 150 - 1 , 150 - 2 , 150 - 3 , and 150 - 4 may be different.

[0112] Figures 6 to 9 The arrangement of the alignment marks 150-1, 150-2, 150-3 and 150-4 may be applied to Figure 4 and Figure 5 Arrangement of the alignment mark 150a.

[0113] Figures 6 to 9 of and Figures 1 to 3 Parts similar or identical to those of the semiconductor packages 200 - 1 , 200 - 2 , 200 - 3 , and 200 - 4 each include a lower package 200B and an upper package 200T on the lower package 200B.

[0114] Semiconductor packages 200-1, 200-2, 200-3, and 200-4 may each include a grid pattern 130 and an upper redistribution layer 203a. In semiconductor packages 200-1, 200-2, 200-3, and 200-4, alignment marks 150-1, 150-2, 150-3, and 150-4 are positioned on lower package 200B below and near the outer boundary of upper package 200T.

[0115] The alignment marks 150-1, 150-2, 150-3, and 150-4 may be formed in, for example, a quadrilateral shape. Figure 6 In the semiconductor package 200-1 of FIG. 1 , two opposing alignment marks 150-1 may be provided on the lower package 200B at the lower left corner and the upper right corner among the corners of the upper package 200T. In some embodiments, the two alignment marks 150-1 may be on the lower package 200B and adjacent to the opposite corners of the upper package 200T, such as Figure 6 shown.

[0116] In some embodiments, Figure 7 In the semiconductor package 200 - 2 of FIG. 1 , three alignment marks 150 - 2 may be provided on the lower package 200B at an upper left corner, a lower left corner, and an upper right corner among corners of the upper package 200T.

[0117] In some embodiments, Figure 8 In the semiconductor package 200 - 3 of FIG. 1 , three alignment marks 150 - 3 may be provided on the lower package 200B at an upper left corner, a lower right corner, and an upper right corner among corners of the upper package 200T.

[0118] In some embodiments, Figure 9In the semiconductor package 200 - 4 of FIG. 1 , two alignment marks 150 - 4 may be provided on the lower package 200B at an upper left corner and a lower right corner among corners of the upper package 200T.

[0119] As described herein, in the semiconductor packages 200-1, 200-2, 200-3, and 200-4, when the upper package 200T has a quadrilateral shape, the alignment marks 150-1, 150-2, 150-3, and 150-4 may be located under at least two opposite corner portions among the corner portions of the quadrilateral of the upper package 200T.

[0120] Figure 10 is a schematic plan view of a POP type semiconductor package according to some embodiments of the inventive concept. Figure 11 yes Figure 10 An enlarged view of part B of the lower package. Figure 11 The upper package is not shown.

[0121] Figure 10 and Figure 11 The semiconductor package 200-5 may be similar to Figures 1 to 3 The semiconductor package 200 may include an alignment mark 150 - 5 having a different shape.

[0122] Figure 10 and Figure 11 The shape of the alignment mark 150-5 can also be applied to Figure 4 and Figure 5 In some embodiments, Figure 4 and Figure 5 The alignment mark 150a may have a Figure 10 and Figure 11 The shapes of the alignment marks 150 - 5 are similar or identical to each other.

[0123] Figure 10 and Figure 11 of and Figures 1 to 3 Portions similar to or identical to those of the semiconductor package 200 may be briefly described or may not be described. The semiconductor package 200 includes a lower package 200B and an upper package 200T on the lower package 200B.

[0124] The semiconductor package 200 - 5 may include a grid pattern 130 and an upper redistribution layer 203 a . In the semiconductor package 200 - 5 , an alignment mark 150 - 5 is positioned on the lower package 200B below and near an outer boundary of the upper package 200T.

[0125] The alignment mark 150-5 may be formed in a clip shape (or L-shaped form). The shape of the portion of the alignment mark 150-5 on the lower package 200B that is covered by (eg, overlapped with) the upper package 200T is not limited. The portion of the alignment mark 150-5 that is covered by the upper package 200T may have the same shape as the lower package 200B. Figure 10 and Figure 11 The shapes shown are different from various shapes.

[0126] In other words, when the upper package 200T is mounted on the lower package 200B, when the alignment mark 150-5 is exposed, the alignment mark 150-5 can have various shapes. In this case, in the semiconductor package 200-5, the alignment mark 150-5 can be used to detect misalignment between the lower package 200B and the upper package 200T. In some embodiments, the portion of the alignment mark 150-5 that does not overlap with the upper package 200T after the upper package 200T is mounted can have various shapes, and these portions of the alignment mark 150-5 can be used to detect misalignment between the lower package 200B and the upper package 200T.

[0127] Therefore, in the semiconductor package 200 - 5 , the upper package 200T can be accurately aligned on the lower package 200B.

[0128] Figure 12 and Figure 13 is a schematic plan view of a POP type semiconductor package according to some embodiments of the inventive concept.

[0129] Figure 12 and Figure 13 The semiconductor packages 200-6 and 200-7 may be similar to Figures 1 to 3 The semiconductor package 200 may include alignment marks 150 - 6 and 150 - 7 having different shapes.

[0130] Figure 12 and Figure 13 The shapes of the alignment marks 150-6 and 150-7 can also be applied to Figure 4 and Figure 5 In some embodiments, Figure 4 and Figure 5 The alignment mark 150a may have a Figure 12 and Figure 13 The shapes of the alignment marks 150 - 6 and 150 - 7 are the same shape.

[0131] Figure 12 and Figure 13 of and Figures 1 to 3Portions similar or identical to those of the semiconductor packages 200 - 6 and 200 - 7 may each include a lower package 200B and an upper package 200T on the lower package 200B.

[0132] The semiconductor packages 200-6 and 200-7 may each include a grid pattern 130 and an upper redistribution layer 203a. In the semiconductor packages 200-6 and 200-7, alignment marks 150-6 and 150-7 are positioned on the lower package 200B below and near the outer boundary of the upper package 200T.

[0133] Figure 12 The alignment mark 150 - 6 may have a circular shape.

[0134] In some embodiments, alignment marks 150 - 6 may be provided at all corners of the upper package 200T on the top of the lower package 200B. Figure 13 The alignment mark 150 - 7 may have a triangular shape.

[0135] In some embodiments, the alignment mark 150-7 may be formed at all corners of the upper package 200T on the lower package 200B. The shape of the portion of the alignment marks 150-6 and 150-7 on the lower package 200B that is blocked by (e.g., overlapped with) the upper package 200T is not limited. In some embodiments, the portion of the alignment marks 150-6 and 150-7 that overlaps the upper package 200T may have the same shape as the lower package 200B. Figure 13 The shapes shown are different shapes.

[0136] In other words, when the upper package 200T is mounted on the lower package 200B, when the alignment marks 150-6 and 150-7 are exposed, the alignment marks 150-6 and 150-7 can have various shapes. In this case, in the semiconductor packages 200-6 and 200-7, the alignment marks 150-6 and 150-7 can be used to detect misalignment between the lower package 200B and the upper package 200T. In some embodiments, the portions of the alignment marks 150-6 and 150-7 that do not overlap with the upper package 200T after the upper package 200T is mounted can have various shapes, and these portions of the alignment marks 150-6 and 150-7 can be used to detect misalignment between the lower package 200B and the upper package 200T.

[0137] In addition, in the semiconductor packages 200 - 6 and 200 - 7 , the upper package 200T may be accurately aligned on the lower package 200B by using the alignment marks 150 - 6 and 150 - 7 .

[0138] In some embodiments, each of the alignment marks (e.g., 150, 150a, and 150-1 to 150-7) according to some embodiments of the inventive concept includes a first portion that overlaps with an upper package (e.g., 200T and 200T) and a second portion that does not overlap with the upper package, and the first portions of the alignment marks may have the same shape, and the second portions of the alignment marks may have the same shape. For example, the first portion of the alignment mark 150-7 has a rectangular shape, and the second portion of the alignment mark 150-7 has a shape of two triangles connected to each other, as shown in FIG. Figure 13 shown.

[0139] Figures 14 to 18 is a schematic cross-sectional view illustrating a method of manufacturing a POP type semiconductor package according to some embodiments of the inventive concept.

[0140] Specifically, in Figures 14 to 18 In the description Figure 4 A method for manufacturing a semiconductor package 300 is provided.

[0141] Figures 14 to 18 The manufacturing method can be applied to Figures 1 to 3 The method for manufacturing the semiconductor package 200 is shown in FIG. Figure 14 , a lower package substrate 205 having a cavity 205H in which the lower semiconductor chip 210 is to be accommodated may be provided.

[0142] A lower semiconductor chip 210 may be provided in the cavity 205H. The lower semiconductor chip 210 may include an active surface 210a and an inactive surface 210b opposite to the active surface 210a. A die pad 211 may be formed on the active surface 210a. A fixing member 295 may be provided on one surface of the lower package substrate 205 to fix the lower semiconductor chip 210.

[0143] The fixing member 295 may be in the form of a film or a support plate.The lower package substrate 205 may include a lower package substrate body 205bd.

[0144] A conductive path 240 may be provided in the lower package substrate body 205bd. The conductive path 240 may be formed before or after providing the lower semiconductor chip 210. Figure 15 , after removing the fixing member 295 , a lower redistribution structure 201 may be formed on the exposed first surface of the lower package substrate 205 and the surface of the lower semiconductor chip 210 .

[0145] Although an example in which the lower redistribution structure 201 is formed first is described herein, an upper redistribution structure 203 to be described later may be formed before forming the lower redistribution structure 201. A lower redistribution insulating layer 201b may be formed to form the lower redistribution structure 201.

[0146] The redistribution insulating layer 201b may be patterned to serve as a mold. Subsequently, a seed metal layer may be formed in the patterned redistribution insulating layer 201b, and the lower redistribution layer 201a may be formed by a plating method such as electroplating, chemical plating, or immersion plating. This process may be performed once or multiple times as necessary.

[0147] Since the method of forming the lower redistribution structure 201 is well known to those skilled in the art, a detailed description thereof will be omitted here. Figure 16 , you can refer to Figure 15 In the same manner as described above, the upper redistribution structure 203 is formed on the second surface 205 b which is the opposite surface of the lower package substrate 205 .

[0148] The upper redistribution structure 203 may include an upper redistribution layer 203a and an upper redistribution insulating layer 203b. The method of forming the upper redistribution structure 203 has been described with reference to Figure 16 A second capping layer 190 may be formed on the upper redistribution structure 203 .

[0149] The second cover layer 190 may be, for example, a transparent organic layer. The second cover layer 190 may be, for example, a photoimageable dielectric (PID) layer. After the second cover layer 190 is patterned to form a plurality of contact holes exposing the upper redistribution layer 203a, alignment marks 150a and second external connection pads 291b may be formed in the contact holes. The second external connection pads 291b may be formed at locations electrically connected to the upper redistribution layer 203a.

[0150] The alignment mark 150a may be formed at or adjacent to a boundary portion (eg, an outline) of an upper package to be mounted later. The alignment mark 150a may not be electrically connected to the upper redistribution layer 203a. Figure 17 and Figure 18 , the upper package 200T' may be provided on the lower package 200B', such as Figure 17 shown.

[0151] In the upper package 200T', the upper semiconductor chip 231 is mounted on the upper package substrate 251 via bonding wires 233. The upper package 200T' can be connected to Figure 4 The upper package 200T' is similar or substantially the same as that of FIG. 1 , and therefore a detailed description thereof may be omitted here. Figure 18 As shown, the upper package 200T' is mounted on the lower package 200B'.

[0152] After the upper package 200T' is mounted, the misalignment between the lower package 200B' and the upper package 200T' can be detected by photographing the alignment mark 150 on the lower package 200B' using, for example, a vision camera 299. Thereafter, when no misalignment occurs between the lower package 200B' and the upper package 200T', the upper package 200T' and the lower package 200B' can be heated to be pressed toward each other to obtain the alignment. Figure 4 A POP type semiconductor package 300 is shown.

[0153] Figure 19 is a block diagram of a POP type semiconductor package according to some embodiments of the inventive concept.

[0154] According to some embodiments of the inventive concept, the semiconductor package 1000 may correspond to a POP-type semiconductor package (eg, 200 , 300 , or 400 ).

[0155] The semiconductor package 1000 may include a controller chip 1020, a first memory chip (or a first storage device) 1041, a second memory chip 1045, and a memory controller 1043. The semiconductor package 1000 may also include a power management integrated circuit (PMIC) or a power management chip 1022 to supply an operating voltage to the controller chip 1020, the first memory chip 1041, the second memory chip 1045, and the memory controller 1043.

[0156] The operating voltages applied to the components may be designed to be the same or different. According to some embodiments of the inventive concepts described herein, the lower package 1030 including the controller chip 1020 and the power management chip 1022 may be a lower package 200B, 200B′, or 200B″.

[0157] According to some embodiments of the inventive concepts described herein, the upper package 1040 including the first memory chip 1041 , the second memory chip 1045 , and the memory controller 1043 may be an upper package 200T or 200T′. The semiconductor package 1000 may be implemented to be included in, for example, a personal computer (PC) or a mobile device.

[0158] The mobile device may be implemented as, for example, a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a personal navigation device or a portable navigation device (PND), a handheld game console, a mobile Internet device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a drone. The controller chip 1020 may control the operation of each of the first memory chip 1041, the second memory chip 1045, and the memory controller 1043.

[0159] For example, the controller chip 1020 may be implemented as, for example, an integrated circuit (IC), a system on chip (SoC), an application processor (AP), a mobile AP, a chipset, or a group of chips. For example, the controller chip 20 may include a central processing unit (CPU), a graphics processing unit (GPU), and / or a modem. In some embodiments, the controller chip 1020 may perform the functions of a modem and the functions of an AP. The memory controller 1043 may control the second memory chip 1045 under the control of the controller chip 1020.

[0160] The first memory chip 1041 may be implemented as, for example, a volatile memory device. The volatile memory device may be implemented as, for example, a random access memory (RAM), a dynamic RAM (DRAM), or a static RAM (SRAM), but the inventive concept is not limited thereto. The second memory chip 1045 may be implemented as, for example, a storage memory device. The storage memory device may be implemented as, for example, a non-volatile memory device. The storage memory device may be implemented as, for example, a flash memory-based memory device, but the inventive concept is not limited thereto.

[0161] The second memory chip 1045 can be implemented as, for example, a NAND-type flash memory device. The NAND-type flash memory device may include a two-dimensional (2D) memory cell array or a three-dimensional (3D) memory cell array. The 2D memory cell array or the 3D memory cell array may include a plurality of memory cells, and each of the plurality of memory cells may store 1 bit of information or 2 bits or more information. When the second memory chip 1045 is implemented as a flash memory-based memory device, the memory controller 1043 may use (or support) a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, or a universal flash memory (UFS) interface, but the inventive concept is not limited thereto.

[0162] Figure 20 is a schematic block diagram of a POP type semiconductor package according to some embodiments of the inventive concept.

[0163] The semiconductor package 1100 may include a micro processing unit 1110 , a memory 1120 , an interface 1130 , a graphic processing unit 1140 , a functional block 1150 , and a bus 1160 connecting these components to one another.

[0164] In some embodiments, semiconductor package 1100 may include both micro-processing unit 1110 and graphics processing unit 1140, or may include only one of micro-processing unit 1110 and graphics processing unit 1140. Micro-processing unit 1110 may include, for example, a core and an L2 cache.

[0165] For example, the microprocessing unit 1110 may include multiple cores. The cores in the multicore may have the same or different performance. In addition, the cores in the multicore may be activated at the same time or at different times. The memory 1120 may store the results of processing performed by the functional block 1150 under the control of the microprocessing unit 1110. For example, in the microprocessing unit 1110, when the content stored in the L2 cache is refreshed, the content may be stored in the memory 1120. The interface 1130 may be connected to an external device. For example, the interface 1130 may be connected to a camera, an LCD, a speaker, etc. The graphics processing unit 1140 may perform graphics functions.

[0166] For example, the graphics processing unit 1140 may implement a video codec or process 3D graphics. The functional blocks 1150 may perform various functions. For example, when the semiconductor package 1100 is an application processor (AP) used in a mobile device, some of the functional blocks 1150 may perform communication functions. The semiconductor package 1100 may be a semiconductor package (e.g., 200, 300, or 400) according to some embodiments of the inventive concepts described herein.

[0167] The microprocessing unit 1110 and / or the graphics processing unit 1140 may be the lower package 200B, 200B′ or 200B″ described herein. The memory 1120 may be the upper package 200T or 200T′ described herein. The interface 1130 and the functional block 1150 may correspond to parts of the lower package 200B, 200B′ or 200B″ described herein.

[0168] While the inventive concept has been particularly shown and described with reference to certain example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.

[0169] This application claims priority from Korean Patent Application No. 10-2019-0112368 filed on September 10, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Claims

1. A package-on-package (POP) type semiconductor package, comprising: a lower package having a first size and comprising a lower package substrate, an upper redistribution structure, a lower semiconductor chip, and an alignment mark, wherein the lower semiconductor chip is located in the lower package substrate, and the upper redistribution structure extends over the lower package substrate and the lower semiconductor chip; as well as an upper package having a second size smaller than the first size and comprising an upper package substrate and an upper semiconductor chip, wherein the upper package substrate is mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip is on the upper package substrate, wherein the alignment mark indicates an outline of the upper package, and the alignment mark is below and adjacent to the outline of the upper package, Each of the alignment marks includes a first portion overlapping with the upper package and a second portion not overlapping with the upper package.

2. The package-on-package type semiconductor package according to claim 1, wherein The lower package substrate includes a cavity extending through a body of the lower package substrate, and the lower semiconductor chip is in the cavity of the body of the lower package substrate.

3. The package-on-package type semiconductor package according to claim 1, wherein The upper redistribution structure includes an upper redistribution layer and an upper redistribution insulating layer, and The upper redistribution insulating layer is a transparent organic layer.

4. The package-on-package type semiconductor package according to claim 3, wherein The alignment mark is in the upper redistribution insulating layer and at the same level as the upper redistribution layer, and the alignment mark includes a same material as that of the upper redistribution layer.

5. The package-on-package type semiconductor package according to claim 1, wherein The upper package has a quadrilateral shape, and Each of the alignment marks is below and adjacent to a corresponding one of two opposing corner portions of the upper package.

6. The package-on-package type semiconductor package according to claim 1, wherein Each of the alignment marks is a solid pattern recognizable by a vision camera.

7. The package-on-package type semiconductor package according to claim 1, wherein The lower semiconductor chip includes a first lower semiconductor chip and a second lower semiconductor chip, and the first lower semiconductor chip and the second lower semiconductor chip are in the lower package substrate and spaced apart from each other.

8. The package-on-package type semiconductor package according to claim 1, wherein The alignment mark is between the lower package substrate and the upper package substrate.

9. The package-on-package type semiconductor package according to claim 8, wherein: The second portions of the alignment marks have the same shape.

10. The package-on-package type semiconductor package according to claim 9, wherein: The first portions of the alignment marks have the same shape.

11. A package-on-package (POP) type semiconductor package, comprising: a lower package comprising a lower package substrate, an upper redistribution structure, and an alignment mark, wherein the lower package substrate includes a lower semiconductor chip therein and has a first size, and the upper redistribution structure extends over the lower package substrate and the lower semiconductor chip and comprises an upper redistribution insulating layer and an upper redistribution layer; as well as an upper package having a second size smaller than the first size and comprising an upper package substrate and an upper semiconductor chip, wherein the upper package substrate is mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip is on the upper package substrate, wherein the alignment mark indicates an outline of the upper package and is below and adjacent to the outline of the upper package, and The alignment mark is in the upper redistribution structure and is at the same level as the upper redistribution layer, Each of the alignment marks includes a first portion overlapping with the upper package and a second portion not overlapping with the upper package.

12. The package-on-package type semiconductor package according to claim 11, wherein The lower package substrate includes a cavity extending through a body of the lower package substrate, and The lower semiconductor chip is in the cavity of the body of the lower package substrate.

13. The package-on-package type semiconductor package according to claim 12, further comprising a lower molding layer on the lower semiconductor chip and the lower package and in the cavity of the body of the lower package substrate, wherein the lower molding layer is between the lower semiconductor chip and the body of the lower package substrate.

14. The package-on-package type semiconductor package according to claim 13, wherein The second portions of the alignment marks have the same shape.

15. The package-on-package type semiconductor package according to claim 11, wherein The upper redistribution insulating layer is a transparent organic layer, and The alignment key is in the upper redistribution insulating layer and includes a same material as that of the upper redistribution layer.

16. The package-on-package type semiconductor package according to claim 11, wherein The lower package includes an upper portion that does not overlap with the upper package, and each of the alignment marks is a solid pattern and is on the upper portion of the lower package, and the solid pattern is recognizable by a vision camera, and The alignment mark includes two alignment marks respectively below and adjacent to two opposite corner portions of the upper package.

17. A package-on-package (POP) type semiconductor package, comprising: a lower package having a first size and comprising a lower package substrate, an upper redistribution structure, and an alignment mark, wherein the lower package substrate comprises a lower semiconductor chip therein, and the upper redistribution structure is on the lower package substrate and the lower semiconductor chip; an upper package having a second size smaller than the first size and comprising an upper package substrate and an upper semiconductor chip, wherein the upper package substrate is mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip is on the upper package substrate; as well as a cover layer extending over the upper redistribution structure, wherein the alignment mark indicates an outline of the upper package and is below and adjacent to the outline of the upper package, and The alignment mark is on the upper redistribution structure and is at the same level as the cover layer, Each of the alignment marks includes a first portion overlapping with the upper package and a second portion not overlapping with the upper package.

18. The package-on-package type semiconductor package according to claim 17, wherein Each of the alignment marks includes a solid pattern recognizable by a vision camera.

19. The package-on-package type semiconductor package according to claim 17, wherein The alignment mark includes two alignment marks respectively below and adjacent to two opposite corner portions of the upper package.

20. The package-on-package type semiconductor package according to claim 17, wherein The second portions of the alignment marks have the same shape.

Images