Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a first region, a second region, a third region, and a fourth region. The first region includes a first portion of an N well and a plurality of P-type transistors formed above the first portion of the N well. The first region extends in a first direction. The second region includes a first portion of a P well and a plurality of N-type transistors formed above the first portion of the P well. The second region extends in the first direction. The third region includes a second portion of the P well. The fourth region includes a second portion of the N well. The first region and the second region are disposed between the third region and the fourth region. Embodiments of the invention relate to a method of manufacturing a semiconductor device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. IC design and material technology has progressed to the point where chips can now be made with feature sizes below 100 nanometers. In the past, such small features were only available to designers of custom chips, but advances in complementary metal-oxide-semiconductor (CMOS) design and fabrication have made it possible for high-volume producers of ICs to implement such small features in high-density chip designs.

[0003] However, such scaling has increased the complexity of processing and manufacturing ICs, which in turn increases the cost of manufacturing, and reduces margins. For example, scaling down P-well and N-well pickup regions also scales down the size of the pickup regions. The smaller size of the P-well and N-well pickup regions can cause punchthrough effects and / or inter-well implant dose compensation, which can cause problems such as latchup. As a result, device performance can be reduced, and / or device failure can occur.

[0004] Therefore, while existing semiconductor devices have generally been adequate for their intended purposes, they have not been entirely satisfactory in every aspect. SUMMARY

[0005] Embodiments of the present invention provide a semiconductor device, comprising: a first region comprising a first portion of an N-well and a plurality of P-type transistors formed above the first portion of the N-well, wherein the first region extends in a first direction; a second region comprising a first portion of a P-well and a plurality of N-type transistors formed above the first portion of the P-well, wherein the second region extends in the first direction and shares a first boundary with the first region, and wherein the first boundary extends in the first direction; a third region comprising a second portion of the P-well, wherein the third region shares a second boundary with the first region and the second region, and wherein the second boundary extends in a second direction different from the first direction; and a fourth region comprising a second portion of the N-well, wherein the fourth region shares a third boundary with the first region and the second region, wherein the third boundary extends in the second direction, and wherein the first region and the second region are disposed between the third region and the fourth region.

[0006] Another embodiment of the invention provides a semiconductor device, comprising: a plurality of first regions each extending in a first direction, wherein a first region comprises a P-type transistor; a plurality of second regions each extending in the first direction, wherein a second region comprises an N-type transistor, and wherein the first regions and the second regions are interleaved with each other in a second direction perpendicular to the first direction; a continuous P-well pickup region disposed at a first side of the first regions and the second regions; and a continuous N-well pickup region disposed at a second side of the first regions and the second regions.

[0007] Yet another embodiment of the invention provides a method of manufacturing a semiconductor device, comprising: receiving an integrated circuit (IC) layout design comprising a plurality of N-type field effect transistor regions, a plurality of P-type field effect transistor regions, a plurality of N-well pickup regions, and a plurality of P-well pickup regions, wherein, according to the received integrated circuit layout design: each of the N-type field effect transistor regions and the P-type field effect transistor regions extends in a first direction, the N-type field effect transistor regions are interleaved with the P-type field effect transistor regions in a second direction different from the first direction, the N-well pickup regions are respectively aligned with the P-type field effect transistor regions, the P-well pickup regions are respectively aligned with the N-type field effect transistor regions, and the N-well pickup regions are interleaved with the P-well pickup regions in the second direction; and modifying the received integrated circuit layout design to generate a modified integrated circuit layout design at least in part by: replacing a first subset of the N-well pickup regions and a first subset of the P-well pickup regions with a continuous P-well pickup region; and replacing a second subset of the N-well pickup regions and a second subset of the P-well pickup regions with a continuous N-well pickup region. BRIEF DESCRIPTION OF DRAWINGS

[0008] Various aspects of the present invention can be best understood with reference to the following detailed description when considered in connection with the accompanying drawings. It should be emphasized that various components are not necessarily drawn to scale. In fact, the dimensions of the various components can be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the accompanying drawings illustrate only typical embodiments of the present invention and therefore should not be considered to narrow its scope as the present invention can be equally well suited for other embodiments.

[0009] FIG. 1A is a perspective view of an IC device in the form of a FinFET in accordance with various aspects of the present invention.

[0010] FIG. 1B is a planar top view of an IC device in the form of a FinFET in accordance with various aspects of the present invention.

[0011] FIG. 1C is a perspective view of an IC device in the form of a GAA device according to aspects of the present application.

[0012] FIGS. 2-3 is a plan top view of a portion of an IC device according to aspects of the present application.

[0013] FIGS. 4-5 is a cross-sectional side view of a portion of an IC device according to aspects of the present application.

[0014] FIG. 6 is a top view of a portion of an IC layout design according to aspects of the present application.

[0015] FIG. 7 is a circuit schematic of an SRAM cell according to aspects of the present application.

[0016] FIG. 8 is a block diagram of a manufacturing system according to aspects of the present application.

[0017] FIG. 9 is a flowchart illustrating a method of manufacturing a semiconductor device according to aspects of the present application.

[0018] FIGS. 10A-10D illustrates one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present application. FIG. 10A is a cross-sectional view along the X direction (source-drain direction), FIG. 10B is a cross-sectional view along the Y direction (gate direction) corresponding to FIG. 10A Y1-Y1 of FIG. 10C is a cross-sectional view along the Y direction (gate direction) corresponding to FIG. 10A Y2-Y2 of FIG. 10D is a cross-sectional view along the Y direction (gate direction) corresponding to FIG. 10A Y3-Y3 of

[0019] FIGS. 11A-11D illustrates one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present application. FIG. 11A is a cross-sectional view along the X direction (source-drain direction), FIG. 11B is a cross-sectional view along the Y direction (gate direction) corresponding to FIG. 11A Y1-Y1 of FIG. 11C is a cross-sectional view along the Y direction (gate direction) corresponding to FIG. 11A Y2-Y2 of FIG. 11D is a cross-sectional view along the Y direction (gate direction) corresponding to FIG. 11A Y3-Y3 of

[0020] FIGS. 12A-12D illustrates one of the various stages of manufacturing a semiconductor FET device according to embodiments of the present application. FIG. 12A is a cross-sectional view along the X direction (source-drain direction), FIG. 12B is a cross-sectional view along the Y direction (gate direction) corresponding toFIG. 12A a cross-sectional view of Y1-Y1 of FIG. 12C corresponding to FIG. 12A a cross-sectional view of Y2-Y2 of FIG. 12D corresponding to FIG. 12A a cross-sectional view of Y3-Y3 of

[0021] FIGS. 13A-13D shows one of the various stages in the manufacture of a semiconductor FET device according to an embodiment of the application. FIG. 13A is a cross-sectional view along the X direction (source-drain direction), FIG. 13B corresponding to FIG. 13A a cross-sectional view of Y1-Y1 of FIG. 13C corresponding to FIG. 13A a cross-sectional view of Y2-Y2 of FIG. 13D corresponding to FIG. 13A a cross-sectional view of Y3-Y3 of

[0022] FIGS. 14A-14D shows one of the various stages in the manufacture of a semiconductor FET device according to an embodiment of the application. FIG. 14A is a cross-sectional view along the X direction (source-drain direction), FIG. 14B corresponding to FIG. 14A a cross-sectional view of Y1-Y1 of FIG. 14C corresponding to FIG. 14A a cross-sectional view of Y2-Y2 of FIG. 14D corresponding to FIG. 14A a cross-sectional view of Y3-Y3 of

[0023] FIGS. 15A-15D shows one of the various stages in the manufacture of a semiconductor FET device according to an embodiment of the application. FIG. 15A is a cross-sectional view along the X direction (source-drain direction), FIG. 15B corresponding to FIG. 15A a cross-sectional view of Y1-Y1 of FIG. 15C corresponding to FIG. 15A a cross-sectional view of Y2-Y2 of FIG. 15D corresponding to FIG. 15A a cross-sectional view of Y3-Y3 of

[0024] FIGS. 16A-16D shows one of the various stages in the manufacture of a semiconductor FET device according to an embodiment of the application. FIG. 16A is a cross-sectional view along the X direction (source-drain direction), FIG. 16B corresponding to FIG. 16A a cross-sectional view of Y1-Y1 of FIG. 16C corresponding to FIG. 16A a cross-sectional view of Y2-Y2 of FIG. 16D corresponding to FIG. 16Aa cross-sectional view of Y3-Y3 of FIG. 1.

[0025] FIGS. 17A-17D shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present application. FIG. 17A is a cross-sectional view along the X direction (source-drain direction), FIG. 17B is a cross-sectional view of Y1-Y1 of FIG. 1, FIG. 17A is a cross-sectional view of Y2-Y2 of FIG. 1, and FIG. 17C is a cross-sectional view of Y3-Y3 of FIG. 1. FIG. 17A FIG. 17D shows a cross-sectional view of Y3-Y3 of FIG. 1. FIG. 17A

[0026] FIGS. 18A-18D shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present application. FIG. 18A is a cross-sectional view along the X direction (source-drain direction), FIG. 18B is a cross-sectional view of Y1-Y1 of FIG. 1, FIG. 18A is a cross-sectional view of Y2-Y2 of FIG. 1, and FIG. 18C is a cross-sectional view of Y3-Y3 of FIG. 1. FIG. 18A FIG. 18D shows a cross-sectional view of Y3-Y3 of FIG. 1. FIG. 18A

[0027] FIGS. 19A-19D shows one of the various stages of manufacturing a semiconductor FET device according to an embodiment of the present application. FIG. 19A is a cross-sectional view along the X direction (source-drain direction), FIG. 19B is a cross-sectional view of Y1-Y1 of FIG. 1, FIG. 19A is a cross-sectional view of Y2-Y2 of FIG. 1, and FIG. 19C is a cross-sectional view of Y3-Y3 of FIG. 1. FIG. 19A FIG. 19D shows a cross-sectional view of Y3-Y3 of FIG. 1. FIG. 19A DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application in any way. For example, the formation of a first component (e.g. a layer, region, or substrate) over or on a second component (e.g. a layer, region, or substrate) can include embodiments in which one or more additional components are formed intervening the first and second components, such that the first component and second component can not be in direct contact. Further, references to such drawings are not intended to be limiting since the application can be applied to other drawing configurations. The repeated use of references to the direction "vertical", "horizontal", "top", "bottom", "left", and "right" is for convenience of description only and is not intended to limit the present application or its application or uses. Relative terms should not be construed as limiting the scope of the application in any way. ​​​​​​

[0029] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0030] Furthermore, when using terms such as "about," "approximately," etc., to describe numbers or ranges of numbers, the term is intended to cover numbers within a reasonable range that includes the number, such as + / - 10% of the number as described, or other values ​​as understood by those skilled in the art. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0031] This invention generally relates to semiconductor devices, and more specifically to field-effect transistors (FETs) such as three-dimensional fin-wire FETs (FinFETs) or multi-channel gate-all-around (GAA) devices, or even planar FETs. One aspect of the invention relates to reconfiguring N-well and P-well pickup regions such that a first plurality of small, staggered N-well and P-well pickup regions are reconfigured into a much larger, continuous N-well pickup region, and a second plurality of small, staggered N-well and P-well pickup regions are reconfigured into a much larger, continuous P-well pickup region. As a result, as discussed in more detail below, device yield, reliability, and / or performance can be improved.

[0032] FIG. 1A and FIG. 1B Three-dimensional perspective and top view of a portion of an integrated circuit (IC) device 90 are shown, respectively. The IC device 90 may be an intermediate device manufactured during the processing of an IC or a portion thereof, which may include static random access memory (SRAM) and / or other logic circuitry, passive components (such as resistors, capacitors, and inductors), and active components (such as p-type FETs (PFETs), n-type FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells). Unless otherwise stated, the invention is not limited to any particular number of devices or device regions, nor to any particular device configuration. For example, although the shown IC device 90 is a three-dimensional FinFET device, the concepts of the invention can also be applied to GAA devices, or even planar FET devices.

[0033] refer to FIG. 1AThe IC device 90 includes a substrate 110. The substrate 110 can include elemental (single element) semiconductors such as silicon, germanium, and / or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 can be a single layer of material with a uniform composition. Alternatively, the substrate 110 can include multiple layers of material with similar or different compositions suitable for IC device fabrication. In one example, the substrate 110 can be a silicon-on-insulator (SOI) substrate with a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 110 can include conductive layers, semiconductor layers, dielectric layers, other layers, or combinations thereof. Various doped regions such as source / drain regions can be formed in or on the substrate 110. The doped regions can be doped with n-type dopants such as phosphorus or arsenic and / or p-type dopants such as boron, depending on design requirements. The doped regions can be formed on the substrate 110 directly in a p-well structure, in an n-well structure, in a dual-well structure, or using a raised structure. The doped regions can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0034] A three-dimensional active region 120 is formed on the substrate 110. The active region 120 is an elongated fin-like structure that protrudes upward beyond the substrate 110. As such, the active region 120 can be interchangeably referred to as a fin structure 120 or as a fin structure 120 hereinafter. The fin structure 120 can be fabricated using suitable processes including photolithography and etching processes. The photolithography process can include forming a photoresist layer on the substrate 110, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form mask elements (not shown) including the photoresist. The mask elements are then used to etch a recess in the substrate 110, leaving the fin structure 120 on the substrate 110. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 can be formed by a double patterning or multiple patterning process. Generally, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns with, for example, a pitch that is less than obtainable using a single direct photolithography. As an example, a layer can be formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned layer using a self-alignment process. The layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 120.

[0035] The IC device 90 also includes source / drain components 122 formed above the fin structures 120. The source / drain components 122 can include epitaxial layers grown epitaxially on the fin structures 120. As device sizes continue to shrink, these source / drain components 122 can merge together, even though they are intended to remain separate. As discussed in more detail below, this is a problem that the present invention overcomes.

[0036] The IC device 90 also includes isolation structures 130 formed above the substrate 110. The isolation structures 130 electrically isolate various components of the IC device 90. The isolation structures 130 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable materials. In some embodiments, the isolation structures 130 can include shallow trench isolation (STI) components. In one embodiment, the isolation structures 130 are formed by etching trenches in the substrate 110 during formation of the fin structures 120. The trenches can then be filled with the isolation materials described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, can also be implemented as the isolation structures 130. Optionally, the isolation structures 130 can include multiple layers of structures, e.g., with one or more layers of thermal oxide spacers.

[0037] The IC device 90 also includes gate structures 140 formed above the fin structures 120 in the channel regions of each fin 120 and joined with the fin structures 120 on three sides. The gate structures 140 can be pseudo-gate structures (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or they can be HKMG structures including a high-k gate dielectric and a metal gate electrode, where the HKMG structures are formed by replacing the pseudo-gate structures. Although not shown here, the gate structures 140 can include additional layers of material, such as an interface layer, a capping layer, other suitable layers, or combinations thereof, located above the fin structures 120.

[0038] Reference is made to FIG. 1B The plurality of fin structures 120 are oriented longitudinally along an X-direction, and the plurality of gate structures 140 are oriented longitudinally along a Y-direction, i.e., generally perpendicular to the fin structures 120. In many embodiments, the IC device 90 includes additional components, such as gate spacers disposed along the sidewalls of the gate structures 140, a hardmask layer disposed above the gate structures 140, and many other components.

[0039] As discussed above, various aspects of the present invention discussed below can be applicable to multi-channel devices, such as gate-all-around (GAA) devices. FIG. 1C A three-dimensional perspective view of an example GAA device 150 is shown. For consistency and clarity, FIG. 1C and FIGS. 1A-1BSimilar components in the figures will be labeled the same. For example, the active regions such as fin structures 120 rise vertically up in the Z-direction out of the substrate 110. The isolation structures 130 provide electrical isolation between the fin structures 120. The gate structures 140 are located above the fin structures 120 and above the isolation structures 130. The mask 155 is located above the gate structures 140, and the gate spacers 160 are located on the sidewalls of the gate structures 140. A cap layer 165 is formed above the fin structures 120 to protect the fin structures 120 from oxidation during formation of the isolation structures 130.

[0040] A plurality of nanostructures 170 are disposed above each of the fin structures 120. The nanostructures 170 can comprise nanosheets, nanotubes, or nanowires, or some other type of nanostructure that extends horizontally in the X-direction. Portions of the nanostructures 170 below the gate structures 140 can function as channels for the GAA devices 150. Dielectric interior spacers 175 can be disposed between the nanostructures 170. Furthermore, although not shown for simplicity reasons, each of the nanostructures 170 can be circumferentially wrapped by a gate dielectric and a gate electrode. In the illustrated embodiment, portions of the nanostructures 170 outside of the gate structures 140 can function as source / drain components for the GAA devices 150. However, in some embodiments, a continuous source / drain component can be epitaxially grown above portions of the fin structures 120 outside of the gate structures 140. Regardless, conductive source / drain contacts 180 can be formed above the source / drain components to provide electrical connections to the source / drain components. An interlayer dielectric (ILD) 185 is formed above the isolation structures 130 and around the gate structures 140 and the source / drain contacts 180.

[0041] Further details regarding GAA device fabrication are disclosed in U.S. Patent No. 10,164,012, issued December 25, 2018, entitled “Semiconductor Device and Method of Manufacturing the Same,” and in U.S. Patent No. 10,361,278, issued July 23, 2019, entitled “Method of Manufacturing Semiconductor Device and Semiconductor Device,” and in U.S. Patent No. 9,887,269, issued February 6, 2018, entitled “Multi-Gate Device and Method of Manufacturing the Same,” the entire disclosures of each of which are hereby incorporated by reference. To the extent the present disclosure relates to fin structures or FinFET devices, such discussion can equally apply to GAA devices.

[0042] GAA device fabrication is described below with reference to U.S. Patent No. 10,361,278, issued July 23, 2019, entitled “Method of Manufacturing Semiconductor Device and Semiconductor Device.”

[0043] FIGS. 10A-10D To FIGS. 19A-19DVarious stages of fabricating a semiconductor FET device according to embodiments of the present application are shown. In FIGS. 10A-19D , Figure "A" is a cross-sectional view along the X direction (source-drain direction), Figure "B" is a cross-sectional view of Y1-Y1 corresponding to the respective Figure "A", Figure "C" is a cross-sectional view of Y2-Y2 corresponding to the respective Figure "A", and Figure "D" is a cross-sectional view of Y3-Y3 corresponding to the respective Figure "A". It should be understood that additional operations can be provided before, during, and after the processes shown, and that some of the operations described below can be replaced or eliminated, for a FIGS. 10A-19D additional embodiments of the method. The order of the operations / processes can be interchanged.

[0044] FIGS. 10A-10D A structure after forming a pseudo-gate structure over the fin structure with the first semiconductor layer 20 and the second semiconductor layer 25 alternately stacked is shown.

[0045] Next, as shown in FIGS. 11A-11D , by using one or more photolithography and etching operations, the stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25 is etched away at the S / D regions, thereby forming S / D spaces 27. In some embodiments, the substrate 10 (or the bottom of the fin structure 11) is also partially etched.

[0046] Further, as shown in FIGS. 12A-12D , the first semiconductor layer 20 is laterally etched within the S / D spaces 27 along the X direction, thereby forming cavities 22. In some embodiments, the etching amount of the first semiconductor layer 20 is in a range of about 2 nm to about 10 nm. When the first semiconductor layer 20 is Ge or SiGe and the second semiconductor layer 25 is Si, the first semiconductor layer 20 can be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine o-phenanthroline (EDP), or potassium hydroxide (KOH) solution.

[0047] In other embodiments, as shown in FIGS. 13A-13D , by selecting an appropriate crystal orientation of the first semiconductor layer 20 and an etchant, the etched surface of the lateral end portion of the first semiconductor layer 20 has a quadrilateral cavity 23 defined by (111) facets. As shown in FIG. 13A , the cross-section of the cavity 23 along the X direction has a V-shape (or an open triangle).

[0048] In the following figures, fabrication operations after forming FIGS. 12A-12D the structure shown are explained. However, the same operations can be applied to the structure shown in FIGS. 13A-13D .

[0049] As shown in FIGS. 14A-14DAs shown, a first insulating layer 33 is conformally formed on the lateral ends of the first semiconductor layer 20 and the second semiconductor layer 25 in the S / D spacing 27. The first insulating layer 33 comprises one of silicon nitride (SiN) and silicon oxide (SiO2) and has a thickness in the range of about 0.5 nm to about 3.0 nm. In other embodiments, the first insulating layer 33 has a thickness in the range of about 1.0 nm to about 2.0 nm. The first insulating layer 33 can be formed by ALD or any other suitable method. By conformally forming the first insulating layer 33, the size of the cavity 22 is reduced.

[0050] like FIGS. 15A-15D As shown, after the formation of the first insulating layer 33, an etching operation is performed to partially remove the first insulating layer. Through this etching, the first insulating layer 33 is substantially retained within the cavity 22 due to the small volume of the cavity. Typically, plasma dry etching etches layers in wide and flat areas faster than in concave portions (e.g., holes, grooves, and / or slits). Therefore, the first insulating layer 33 can remain inside the cavity 22. In some embodiments, one or more additional insulating layers are formed on the first insulating layer 33, and then an etching operation is performed.

[0051] Subsequently, as FIGS. 16A-16D As shown, an S / D epitaxial layer 50 is formed within the S / D spacing. The source / drain epitaxial layer 50 comprises one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or Si, SiGe, and Ge for p-channel FETs. For p-channel FETs, boron (B) may also be included in the source / drain. The source / drain epitaxial layer 50 is formed using epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy (MBE). FIGS. 16A-16D As shown, the source / drain epitaxial layer 50 is formed to contact the second semiconductor layer 25, and is formed such that an air gap 37 is formed between the S / D epitaxial layer 50 and the first insulating layer 33.

[0052] Then, as FIGS. 17A-17D As shown, an interlayer dielectric (ILD) layer 70 is formed above the S / D epitaxial layer 50. Materials used for the ILD layer 70 include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials such as polymers can be used for the ILD layer 70. After forming the ILD layer 70, a planarization operation such as CMP is performed to expose the top of the sacrificial gate electrode layer 42.

[0053] Then, the sacrificial gate electrode layer 42 and the sacrificial gate dielectric layer 41 are removed. During the removal of the sacrificial gate structure, the ILD layer 70 protects the S / D epitaxial layer 50. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer 42 is polysilicon and the ILD layer 70 is silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 42. The sacrificial gate dielectric layer 41 is then removed using plasma dry etching and / or wet etching.

[0054] like FIGS. 18A-18D As shown, after removing the sacrificial gate structure, the first semiconductor layer 20 is removed to form the wiring of the second semiconductor layer 25. As described above, the first semiconductor layer 20 can be removed or etched using an etchant that selectively etches the first semiconductor layer 20 relative to the second semiconductor layer 25. FIGS. 18A-18D As shown, due to the formation of the first insulating layer 33, the etching of the first semiconductor layer 20 stops at the first insulating layer 33. In other words, the first insulating layer 33 serves as an etch stop layer for etching the first semiconductor layer 20.

[0055] like FIGS. 19A-19D As shown, after the semiconductor wiring of the second semiconductor layer 25 is formed, a gate dielectric layer 82 is formed around each channel layer (the wiring of the second semiconductor layer 25), and a gate electrode layer 84 is formed on the gate dielectric layer 82.

[0056] In certain embodiments, the gate dielectric layer 82 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 82 includes an interface layer (not shown) formed between the channel layer and the dielectric material.

[0057] The gate dielectric layer 82 can be formed by CVD, ALD, or any suitable method. In one embodiment, a highly conformal deposition process such as ALD is used to form the gate dielectric layer 82 to ensure that the gate dielectric layer formed around each channel layer has a uniform thickness. In one embodiment, the thickness of the gate dielectric layer 82 is in the range of about 1 nm to about 6 nm.

[0058] A gate electrode layer 84 is formed over the gate dielectric layer 82 to surround each of the channel layers. The gate electrode 84 includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof.

[0059] The gate electrode layer 84 can be formed by CVD, ALD, electroplating, or other suitable methods. The gate electrode layer is also deposited over the upper surface of the ILD layer 70. The gate dielectric layer and the gate electrode layer formed over the ILD layer 70 are then planarized by using, for example, CMP until the top surface of the ILD layer 70 is exposed. In some embodiments, after the planarization operation, the gate electrode layer 84 is recessed, and a cap insulating layer (not shown, also referred to as a protective insulating layer) is formed over the recessed gate electrode (layer) 84. The cap insulating layer includes one or more layers of silicon nitride-based material, such as SiN. The cap insulating layer can be formed by depositing an insulating material and then performing a planarization operation.

[0060] In certain embodiments of the present application, one or more work function adjustment layers (not shown) can be sandwiched between the gate dielectric layer 82 and the gate electrode 84. The work function adjustment layer is made of conductive material, such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or multiple layers of two or more of these materials. For n-channel FETs, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the work function adjustment layer, and for p-channel FETs, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co are used as the work function adjustment layer. The work function adjustment layer can be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable processes. Furthermore, the work function adjustment layer can be formed separately for n-channel FETs and p-channel FETs that can use different metal layers.

[0061] Subsequently, a contact hole is formed in the ILD layer 70 by using dry etching, thereby exposing an upper portion of the S / D epitaxial layer 50. In some embodiments, a silicide layer is formed over the S / D epitaxial layer 50. The silicide layer includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. Subsequently, a conductive contact layer 72 is formed in the contact hole. The conductive contact layer 72 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN. Further, a conductive contact plug 75 is formed on the conductive contact layer 72. The conductive contact plug 75 includes one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN, and TaN.

[0062] It should be appreciated that the GAA FETs undergo further CMOS processes to form various components, such as contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc.

[0063] FIG. 2 is a simplified schematic partial top view of an IC device 200 in accordance with various aspects of the present disclosure. For simplicity and clarity, FIG. 2 The top view of shows various N-wells and P-wells of the IC device 200, but does not show other microelectronic components of the IC device 200, such as fin structures (or active regions), gate structures, contacts, vias, or metal lines.

[0064] The IC device 200 includes a plurality of PFET regions and a plurality of NFET regions, such as PFET regions 210, 211, 212, and 213, and NFET regions 220, 221, 222, and 223. Each of the PFET regions 210-213 includes an N-well. For example, the PFET region 210 includes an N-well 240A, the PFET region 211 includes an N-well 240B, the PFET region 212 includes an N-well 240C, and the PFET region 213 includes an N-well 240D. Each of the NFET regions 220-223 includes a P-well. For example, the NFET region 220 includes a P-well 250A, the NFET region 221 includes a P-well 250B, the NFET region 222 includes a P-well 250C, and the NFET region 223 includes a P-well 250D. In some embodiments, the N-wells 240A-240D and the P-wells 250A-250D can correspond to doped portions of the substrate 110 shown. Although not shown for simplicity, it should be appreciated that P-type source / drain components can be formed over the N-wells 240A-240D in the PFET regions 210-213, and N-type source / drain components can be formed over the P-wells 250A-250D in the NFET regions 220-223. FIG. 1A The N-wells 240A-240D and the P-wells 250A-250D can correspond to doped portions of the substrate 110 shown. Although not shown for simplicity, it should be appreciated that P-type source / drain components can be formed over the N-wells 240A-240D in the PFET regions 210-213, and N-type source / drain components can be formed over the P-wells 250A-250D in the NFET regions 220-223.

[0065] Each of the N-wells 240A-240D (and therefore PFET regions 210-213) has a dimension 270 measured in the X direction, and each of the P-wells 250A-250D (and therefore NFET regions 220-223) has a dimension 271 measured in the X direction. In some embodiments, each of dimensions 270 and 271 may be in the range of about 50 micrometers to about 500 micrometers. Each of the N-wells 240A-240D also has a dimension 280 measured in the Y direction, and each of the P-wells 250A-250D has a dimension 281 measured in the Y direction. In some embodiments, each of dimensions 280 and 281 may be in the range of about 0.5 micrometers to about 5 micrometers. Since dimensions 270 and 271 are substantially larger than dimensions 280 and 281 (e.g., greater than 10 times, or even 100 times), it can be said that each of the N-wells 240A-240D and the P-wells 250A-250D is oriented in the X direction, or each extends in the X direction.

[0066] In some embodiments, dimension 270 may have substantially the same value as dimension 271, and dimension 280 may have substantially the same value as dimension 281. In other words, the dimensions of N-wells 240A-240D may be the same as those of P-wells 250A-250D, or the dimensions of PFET regions 210-213 may be the same as those of NFET regions 220-223. However, it should be understood that in other embodiments, depending on design needs and / or manufacturing requirements, the dimensions of N-wells 240A-240D and P-wells 250A-250D (and therefore PFET regions 210-213 and NFET regions 220-223) may differ.

[0067] like FIG. 2 As shown, N-wells 240A-240B intersect with P-wells 250A-250B in the Y direction, which is perpendicular to the X direction. For example, N-wells 240A and P-wells 250A share boundary 290, P-wells 250A and N-wells 240B share boundary 291, and N-wells 240B and P-wells 250B share boundary 292, where boundaries 290-292 extend in the X direction. Similarly, N-wells 240C-240D intersect with P-wells 250C-250D in the Y direction.

[0068] It should be understood that the IC device 200 may include a plurality of additional N-wells and P-wells interleaved in the Y direction, but these additional N-wells and P-wells are not specifically shown herein due to space constraints. Since N-wells 240A-240D correspond to PFET regions 210-213 respectively, and P-wells 250A-250D correspond to NFET regions 220-223 respectively, it can also be said that each of the PFET regions 210-213 and the NFET regions 220-223 extends in the X direction and interleaves with each other in the Y direction.

[0069] PFET regions 210-213 and NFET regions 220-223 are regions of IC device 200 that form functional transistors. In some embodiments, these functional transistors include transistors for various devices such as inverters, flip-flops, multiplexers, etc. As building blocks, transistors from PFET regions 210-213 and NFET regions 220-223 can be used to form IC devices such as SRAM devices, ring oscillators, radio frequency (RF) devices, etc.

[0070] IC device 200 also includes a plurality of N-well pickup regions and a plurality of P-well pickup regions. For example, FIG. 2 N-well pickup region 300 and P-well pickup region 310 are shown. N-well pickup region 300 includes N-well 240E, and P-well pickup region 310 includes P-well 250E. In some embodiments, N-well 240E is connected to N-wells 240A-240D, and P-well 250E is connected to P-wells 250A-250D. In other words, N-well 240E and N-wells 240A-240D are different parts of the same N-well, and P-well 250E and P-wells 250A-250D are different parts of the same P-well. Although not shown in FIG. 3 for simplicity, it should be understood that dummy transistors can be formed in N-well pickup region 300 and P-well pickup region 310. FIG. 2

[0071] N-well pickup region 300 and P-well pickup region 310 are regions of IC device 200 that are reserved or configured for applying predetermined bias voltages. For example, in some embodiments, N-well pickup region 300 can be electrically connected to a power supply or voltage rail such as Vdd (or Vcc), and P-well pickup region 310 can be electrically connected to electrical ground (or Vss). In other words, N-well 240E can be electrically coupled to a power supply or voltage rail via dummy transistors in N-well pickup region 300, and P-well 250E can be electrically coupled to electrical ground via dummy transistors in P-well pickup region 310. And since N-well 240E is part of the same N-well as N-wells 240A-240D, and P-well 250E is part of the same P-well as P-wells 250A-250D, functional transistors of PFET regions 210-213 and NFET regions 220-223 can be properly electrically biased.

[0072] Unlike conventional IC devices in which N-well pickup regions and P-well pickup regions are composed of multiple small N-wells and P-wells interleaved with each other (e.g., in a similar manner to the interleaving of N-wells 240A-240B and P-wells 250A-250B), N-well pickup region 300 here corresponds to a much larger and continuous N-well 240E, and P-well pickup region 310 here corresponds to a much larger and continuous P-well 250E.​

[0073] like FIG. 2 As shown, each of the N-well pickup region 300 and the P-well pickup region 310 spans multiple PFET regions and NFET regions. For example, the N-well pickup region 300 has a boundary 335 extending in the Y direction, and this boundary 335 coincides with the boundary 340 of the PFET region 210, the boundary 341 of the NFET region 220, the boundary 342 of the PFET region 211, and the boundary 343 of the NFET region 211. Similarly, the P-well pickup region 310 has a boundary 350 also extending in the Y direction, and this boundary 350 coincides with the boundary 360 of the PFET region 211, the boundary 361 of the NFET region 220, the boundary 362 of the PFET region 211, and the boundary 363 of the NFET region 211. Thus, the N-well pickup region 300 and the P-well pickup region 310 are substantially (in the Y direction) longer than the PFET regions 210-213 and the NFET regions 220-223. This is important, as will be discussed in more detail below.

[0074] N-well 240E (and therefore N-well pickup area 300) has a dimension 320 measured in the X direction and a dimension 321 measured in the Y direction, and P-well 250E (and therefore P-well pickup area 310) has a dimension 330 measured in the X direction and a dimension 331 measured in the Y direction. Each of dimensions 320 and 330 is substantially smaller than each of dimensions 270 and 271, for example, by a factor of 100. In some embodiments, the ratio of dimension 320 (or dimension 330) to dimension 270 (or dimension 271) is in the range of about 1:10 to about 1:10000. Meanwhile, each of dimensions 321 and 331 is substantially larger than each of dimensions 280 and 281, for example, by at least a factor of four. In some embodiments, the ratio of dimension 321 (or dimension 331) to dimension 280 (or dimension 281) is in the range of about 10:1 to about 10000:1. In other words, each of the well-pickup regions 300 and 310 is substantially narrower (in the X direction) than each of the PFET 210-213 and NFET regions 220-223, and longer (in the Y direction) than each of the PFET 210-213 and NFET regions 220-223. These ranges and ratios are not randomly chosen but are specifically configured to ensure that the N-well-pickup regions 300 and 310 are large enough to be less likely to suffer from undesirable via effects (discussed in more detail below), but not so large as to take up excessive chip area, which is very valuable and would otherwise be used to implement functional transistors in the NFET and PFET regions.

[0075] It should be appreciated that in some embodiments, dimensions 320 and 321 can be equal to each other, but in other embodiments, they can be different. The same is true for dimensions 330 and 331. In other words, in some embodiments, the dimensions of N-well 240E and P-well 250E (and thus N-well pickup region 300 and P-well pickup region 310) can be the same, or in other embodiments, their dimensions can be different. Regardless of how N-well 240E and P-well 250E respectively adjust their dimensions, one unique physical feature of the present invention is that each of N-well 240E and P-well 250E spans multiple N-wells of the PFET region and multiple P-wells of the NFET region, rather than being interleaved with each other in the Y direction. Such a configuration improves device performance and / or reliability.

[0076] In more detail, conventional IC devices have significantly smaller N-well and P-well pickup regions that can be aligned with the PFET region and NFET region, respectively. As such, conventional IC devices can have multiple small N-well and P-well pickup regions that are interleaved with each other in the Y direction in a similar manner as the interleaved PFET and NFET regions. In older technology eras, this was not a significant issue. However, as device dimensions continue to shrink, for example, in 7 nanometer technology nodes or smaller (i.e., less than 7 nanometer technology nodes), the smaller and smaller dimensions of the N-well and P-well pickup regions can present significant challenges.

[0077] One issue is excessive inter-well implant dose compensation. This refers to P-type dopants in the P-well leaking into the N-well through the N / P boundary, and / or N-type dopants in the N-well leaking into the P-well through the N / P boundary. In older technology eras, larger device dimensions meant there were not as many N / P boundaries between the N-well and P-well pickup regions, so there were fewer opportunities for inter-well implant dose compensation. Even if inter-well implant dose compensation did occur, the leaked dopants can have only affected a small portion of the other oppositely doped well. However, since the N-well and P-well pickup regions are also scaled down in certain IC devices fabricated in 7 nanometer (or smaller) technology nodes, while still being interleaved with each other, the number of N / P boundaries increases, thereby creating more opportunities for inter-well implant dose compensation. Worse, the smaller footprint of the N-well and P-well pickup regions means that the leaked dopants will have a greater negative impact on the other well. The fact that well implants are typically deep exacerbates the problem, for example, the depth (in the Z direction) of the wells can range from about 100 nanometers to about 1000 nanometers. The greater the depth of the N-well and P-well, the more likely it is that undesirable inter-well implant dose compensation will occur. FIG. 1A

[0078] ​Another problem faced by conventional IC devices fabricated in 7 nanometer or smaller nodes is the injection hole effect. In this regard, the N-well of the N-well pickup region and the P-well of the P-well pickup region are typically formed by first forming a layer of a patterned photoresist layer over the substrate. The patterned photoresist layer includes openings that define the locations of the wells to be formed. Thereafter, an ion implantation process can be performed to implant dopants into the substrate through the openings while using the patterned photoresist layer as an implantation mask. As device fabrication has progressed to 7 nanometer technology nodes or higher, the smaller openings (and correspondingly larger opening aspect ratios) can make it more difficult for dopants to be implanted into their desired locations in the substrate. For example, dopants can be bombarded into the sidewalls of the openings of the photoresist layer instead of into the substrate as intended. This will cause the dose of the doped well to deviate from target. In other words, the well can not reach the intended dose or dopant concentration level.

[0079] Due to the inter-well implant dose compensation and / or the injection hole effect problems that occur in conventional 7 nanometer technology node IC devices, the contact resistance of the well can increase, and / or the bias of the well can be poor. This can cause problems for the IC device, such as latch-up problems, which can cause the IC device to leak current and / or burn out prematurely, or suffer performance degradation.

[0080] In contrast, the present invention overcomes the problems of conventional IC devices fabricated using 7 nanometer or smaller process nodes because the present invention implements a relatively "large" N-well 240E and P-well 250E in the well pickup regions instead of having multiple small, interleaved N-wells and P-wells in the well pickup regions. As a result, the size of the N-well 240E is several times larger (e.g., at least four times larger) than the size of a small N-well implemented in a conventional IC device fabricated using the same technology node (i.e., compare the 7 nanometer technology node of the present invention to the 7 nanometer technology node of a conventional device in order to make an accurate "apple-to-apple" comparison. Likewise, the size of the P-well 250E is several times larger (e.g., at least four times larger) than the size of a small P-well implemented in a conventional IC device fabricated using the same technology node.

[0081] Due to their much larger size (which translates into larger photoresist openings), the N-well 240E and P-well 250E are much less susceptible to the injection hole effect discussed above. In addition, the elimination of the interleaved configuration of the N-wells and P-wells in the N-well pickup region 300 and P-well pickup region 310 also translates into the elimination (or at least a significant reduction) of the N / P boundaries in the N-well pickup region 300 and P-well pickup region 310. Thus, the present invention also significantly improves the inter-well implant dose compensation problem. These improvements can result in a reduction in contact resistance, a reduced likelihood of latch-up problems, and / or other improvements in device performance and / or reliability.

[0082] Due to space limitations, FIG. 2Only one N-well pickup region 300 and one P-well pickup region 310 are shown. However, it should be understood that the IC device may include multiple additional N-well pickup regions and P-well pickup regions that are similar to (or identical to) N-well pickup region 300 and P-well pickup region 310. The same applies to PFET regions 210-213 and NFET regions 220-223. For example, the configuration of PFET regions 210-213, NFET regions 220-223, N-well pickup region 300, and P-well pickup region 310 may be repeated multiple times in the X and / or Y directions.

[0083] FIG. 3 This is another simplified schematic partial top view of an IC device 200 according to various aspects of the present invention. FIG. 2 compared to, FIG. 3 Several other microelectronic components of the IC device 200 are shown to provide greater clarity. For example, FIG. 3 Multiple active regions 400-407 are shown, which are formed in N-wells or P-wells (in FIG. 1A As shown in the Z direction, each extends in the X direction. In the case of FinFET, the active regions 400-407 include fin structures, such as... FIG. 1A and FIG. 1B The fin structure 120. In the case of a multi-channel GAA device, the active region 400-407 includes the fin structure 120 and nanostructures formed above the fin structure, such as... FIG. 1C Nanostructures 170 (e.g., nanosheets, nanotubes, nanowires, etc.). It should be understood that... FIG. 3 The number and location of active regions shown are merely examples and are not intended to be limiting. Similar active regions may be formed in PFET regions 212-213 and NFET regions 222-223, as well as in N-well pickup region 300, but these active regions are not specifically shown herein for simplicity.

[0084] FIG. 3 Multiple gate structures 410-413 are also shown, formed above the active regions 400-407 and each extending in the Y direction. For example, the gate structures 410-413 can be implemented as follows: FIGS. 1A-1Cgate structures 410 and 411 are formed in the P-well pickup region 310 and are dummy gate structures. The gate structures 412 and 413 are formed in the PFET region 210 and are functional gate structures. In other words, while the transistors (including active regions and gate structures) in the PFET regions 210-213 and the NFET regions 220-223 are functional transistors that are part of the circuit, the transistors in the P-well pickup region 310 and the N-well pickup region 300 are dummy transistors that are not part of the circuit, except to provide an electrical path between the P-well 250E (or the N-well 240E) and a power supply or electrical ground. It will be appreciated that the number and location of the gate structures (dummy or non-dummy) shown in FIG. 4 are examples only and are not intended to be limiting. Similar gate structures can be formed in the PFET regions 212-213 and the NFET regions 222-223, as well as in the N-well pickup region 300, but these gate structures are not specifically shown herein for simplicity reasons. FIG. 3

[0085] FIG. 3 Also shown are a plurality of conductive contacts formed in the P-well pickup region 310. For simplicity, only three such conductive contacts 420-422 are labeled in FIG. 4. These conductive contacts, such as the conductive contacts 420-422, can be formed over the dummy source / drain of the dummy transistors located in the P-well pickup region 310 (in the Z-direction shown). In a top view, the conductive contacts 420-422 are located between the active regions 400-401 and between the dummy gate structures 410-411. The conductive contacts 420-422 provide an electrical connection between the P-well 250E and a metal line formed in the multilayer interconnect structure above the conductive contacts 420-422. Thus, the conductive contacts 420-422 provide an electrical connection to the P-well 250E. The conductive contacts 420-422 can also be referred to as P-well pickup contacts. It will be appreciated that a plurality of conductive contacts similar to the conductive contacts 420-422 can be formed in the N-well pickup region 300 to provide an electrical connection to the N-well 240E, but these conductive contacts in the N-well pickup region 300 are not specifically shown herein for simplicity reasons. In addition, similar contacts can be formed in the PFET regions 210-213 and the NFET regions 220-223 to provide an electrical connection to the functional transistors in these regions, but these contacts are also not specifically shown herein for simplicity reasons. FIG. 3 FIG. 1A

[0086] FIG. 4 is a simplified schematic partial cross-sectional side view of an IC device 200 according to an embodiment of the present application. FIG. 4 The cross-sectional view of FIG. 4 is taken along the line FIG. 3 ​​​The illustrated cut line A-A' (extending in the X direction) intercepts the cross-sectional view. Thus, FIG. 4 The cross-sectional view can be referred to as an X-Z cross-sectional view. FIG. 4 Cross-sections of PFET regions 210 and 212, N-well pickup region 300, and P-well pickup region 310 are shown.

[0087] As FIG. 4 illustrated, IC device 200 includes a substrate 110, which in some embodiments can be doped with P-type dopants. P-well 250E and N-wells 240A, 240E, and 240C are formed above substrate 110. As discussed above, N-wells 240A, 240E, and 240C can be part of the same N-well, but for clarity are shown in FIG. 4 dashed lines to illustrate their pseudo "boundaries." These "boundaries" can not be visible in an actually manufactured IC device.

[0088] Also as discussed above, one or more pseudo transistors 500 are formed above N-well 240E in N-well pickup region 300, and one or more pseudo transistors 510 are formed above P-well 250E in P-well pickup region 310. These pseudo transistors 500 and 510 can include pseudo fins, pseudo source / drain, pseudo gate structures, as discussed above in connection with FIG. 3 It is noted that in some embodiments, the conductive contacts 420-422 discussed above in FIG. 3 may also be considered part of the pseudo transistors 500 and 510. Pseudo transistors 500 and 510 can be used to provide electrical connections to N-well pickup region 300 and P-well pickup region 310. For example, in some embodiments, pseudo transistors 500 can be used to electrically bias N-well 240E to a power supply or voltage rail (such as Vdd (or Vcc)), and pseudo transistors 510 can be used to electrically bias P-well 250E to electrical ground, or vice versa in other embodiments. For simplicity, although details of pseudo transistors 500 and 510 are not shown here, it should be understood that FinFET or GAA devices can be used to implement these pseudo transistors 500 and 510.

[0089] A plurality of functional transistors 520 and 530 are also formed in PFET regions 210 and 212, respectively. Functional transistors 520 and 530 include functional active regions, functional source / drain, and functional gate structures, which form transistors that are building blocks of operational circuitry. In some embodiments, electrical interconnects such as vias, contacts, or metal lines can also be considered part of functional transistors 520 and 530. For simplicity, details of functional transistors 520 and 530 are not shown here, but it should be understood that FinFET or GAA devices can be used to implement these functional transistors 520 and 530.

[0090] FIG. 5 is another simplified schematic partial cross-sectional side view of the IC device 200 according to embodiments of the application. FIG. 5 The cross-sectional view of FIG. 3 is taken along the cut line B-B’ (extending in the Y direction) shown. Thus, FIG. 5 The cross-sectional view of FIG. 5 The cross-section of the P-well pickup region 310 is shown because the PFET regions 210 and 212 and the N-well pickup region 300 are outside of the cut line B-B’.

[0091] As shown in FIG. 5 P-well 250E is formed as a continuous P-well above the substrate 110. As discussed above, this is a significant difference from conventional devices in which the well pickup region would have multiple small, interleaved P-wells and N-wells, rather than a long continuous P-well (or a continuous N-well if the cross-section is taken above or on the N-well pickup region 300). The interleaved P-wells and N-wells create many N / P boundaries at locations where dopant diffusion can occur (e.g., well-to-well implant dose compensation). In addition, the small size of the P-wells and N-wells can be related to implant hole effects. As a result, the configuration of conventional devices can cause improper biasing of the P-wells and N-wells, which in turn can cause latching and other problems.

[0092] Instead, the present application prevents the problems associated with conventional IC devices by changing the configuration of the P-well and N-well pickup regions to substantially reduce or eliminate interleaved small P-wells and N-wells in the well pickup regions. The now significantly larger P-wells (such as P-well 250E) and N-wells (such as N-well 240E) in the well pickup regions do not suffer from the problems associated with many N / P boundaries, thereby reducing or preventing diffusion of dopants across such N / P boundaries. The larger size of the P-wells and N-wells herein also means that implant hole effects are less pronounced, which means that the P-wells and N-wells are also more properly biased. As a result, problems such as latching are significantly reduced.

[0093] FIG. 6 A process 600 is shown in which a received IC layout design is modified according to embodiments of the application. For example, FIG. 6A top view of a portion of a received IC layout design 610 is shown. The received IC layout design 610 can be generated by an IC design house, for example. The received IC layout design 610 can include a plurality of NFET regions and PFET regions each extending in an X direction and interleaved with each other in a Y direction. Functional transistors are formed in the NFET regions and PFET regions. The received IC layout also includes a plurality of N-well pickup regions and a plurality of P-well pickup regions. The N-well pickup regions and P-well pickup regions are aligned with the PFET regions and NFET regions, respectively, in the X direction, and they are interleaved with each other in the Y direction in the same way that the NFET regions and PFET regions are interleaved with each other. This configuration can be undesirable for reasons discussed above, as interleaved N-well and P-well pickup regions can cause problems such as latching.

[0094] According to embodiments of the present application, an IC layout modification process 600 is performed on the received IC layout design 610 to generate a modified IC layout design 620. As shown, FIG. 6 the interleaved N-well and P-well pickup regions of the received IC layout design 610 are converted into a single continuous N-well pickup region and a single continuous P-well pickup region. The N-well pickup region spans multiple NFET and PFET regions in the Y direction, and the same is true for the P-well pickup region. As discussed above, this design helps to reduce well-to-well implant dose compensation and mitigate problems caused by implant window effects. The modified IC layout design 620 can then be used to manufacture an IC device.

[0095] The IC device 200 can be implemented in various IC applications, including memory devices such as static random access memory (SRAM) devices. In this regard, FIG. 7 An example circuit schematic of a single-port SRAM cell (e.g., a 1-bit SRAM cell) 800 is shown. The single-port SRAM cell 800 includes pull-up transistors PU1, PU2; pull-down transistors PD1, PD2; and pass-gate transistors PG1, PG2. As shown in the circuit diagram, the transistors PU1 and PU2 are p-type transistors, and the transistors PG1, PG2, PD1, and PD2 are n-type transistors. According to various aspects of the present application, the PG1, PG2, PD1, and PD2 transistors are implemented with thinner spacers than the PU1 and PU2 transistors. Since the SRAM cell 800 includes six transistors in the illustrated embodiment, it can also be referred to as a 6T SRAM cell.

[0096] The drains of pull-up transistor PU1 and pull-down transistor PD1 are coupled together, and the drains of pull-up transistor PU2 and pull-down transistor PD2 are coupled together. Transistors PU1 and PD1 are cross-coupled with transistors PU2 and PD2 to form a first data latch. The gates of transistors PU2 and PD2 are coupled together and to the drains of transistors PU1 and PD1 to form a first storage node SN1, and the gates of transistors PU1 and PD1 are coupled together and to the drains of transistors PU2 and PD2 to form a complementary first storage node SNB1. The sources of pull-up transistors PU1 and PU2 are coupled to a supply voltage Vcc (also referred to as Vdd), and the sources of pull-down transistors PD1 and PD2 are coupled to a voltage Vss, which in some embodiments can be electrically ground.

[0097] The first storage node SN1 of the first data latch is coupled to a bit line BL through a pass gate transistor PG1, and the complementary first storage node SNB1 is coupled to a complementary bit line BLB through a pass gate transistor PG2. The first storage node N1 and the complementary first storage node SNB1 are complementary nodes that are normally at opposite logic levels (logic high or logic low). The gates of pass gate transistors PG1 and PG2 are coupled to a word line WL. FinFET devices and / or GAA devices can be used to implement the SRAM devices (such as SRAM cell 800). In some embodiments, the transistors PU1, PU2, PD1, PD2, PG1, and PG2 are implemented using functional transistors of IC device 200 (e.g., transistors 520 and 530 of FIG. 5). FIG. 4

[0098] FIG. 8 An integrated circuit manufacturing system 900 is shown in accordance with an embodiment of the present application. Manufacturing system 900 includes a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916,..., N connected through a communications network 918. Network 918 can be a single network, or can be a variety of different networks (such as an intranet and the Internet), and can include both wired and wireless communication channels at the same time.

[0099] ​In embodiments, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer monitoring a product of interest; entity 906 represents an engineer, such as a process engineer controlling a process and associated recipe, or a facility engineer monitoring or adjusting conditions and settings of a processing tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool for performing a lithography process to define gate spacers for an SRAM device; entity 912 represents a virtual metrology module associated with processing tool 910; entity 914 represents an advanced process control module associated with processing tool 910 and additionally other processing tools; and entity 916 represents a sampling module associated with processing tool 910.

[0100] Each entity can interact with other entities and can provide integrated circuit manufacturing, process control, and / or computing capabilities to receive and / or provide such capabilities from / to other entities. Each entity can also include one or more computer systems for performing computations and executing automation. For example, the advanced process control module of entity 914 can include multiple computer hardware having software instructions encoded therein. The computer hardware can include hard disk drives, flash drives, CD-ROMs, RAM memory, display devices (e.g., monitors), input / output devices (e.g., mouse and keyboard). The software instructions can be written in any appropriate programming language and can be designed to perform specific tasks.

[0101] The integrated circuit manufacturing system 900 is capable of interactions between entities for integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In embodiments, the advanced process control includes adjusting processing conditions, settings, and / or recipes of one processing tool applicable to a related wafer according to metrology results.

[0102] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of a subset of processed wafers according to an optimal sampling field / point determined based on various characteristics of process quality and / or product quality.

[0103] One of the capabilities provided by the IC manufacturing system 900 can enable collaboration and information access in areas such as design, engineering and process, metrology and advanced process control. Another capability provided by the IC manufacturing system 900 can integrate systems between facilities, such as between metrology tools and processing tools. This integration enables facilities to coordinate their activities. For example, integrating metrology tools and processing tools can enable manufacturing information to be more efficiently merged into manufacturing processes or APC modules, and can enable on-line or in-situ measurement of wafer data by metrology tools integrated in related processing tools.

[0104] FIG. 9 is a flowchart illustrating a method 1000 of manufacturing a semiconductor device according to an embodiment of the present application. The method 1000 includes a step 1010 to receive an integrated circuit (IC) layout design including a plurality of PFET regions, NFET regions, N-well pickup regions, and P-well pickup regions. According to the received IC layout design, each of the PFET regions and the NFET regions extends in a first direction, the PFET regions are interleaved with the NFET regions in a second direction different from the first direction, the N-well pickup regions are respectively aligned with the PFET regions, the P-well pickup regions are respectively aligned with the NFET regions, and the N-well pickup regions are interleaved with the P-well pickup regions in the second direction.

[0105] The method 1000 includes a step 1020 to modify the received IC layout design at least in part by: replacing a first subset of the N-well pickup regions and a first subset of the P-well pickup regions with a continuous P-well pickup region; and replacing a second subset of the N-well pickup regions and a second subset of the P-well pickup regions with a continuous N-well pickup region.

[0106] The method 1000 includes a step 1030 to manufacture an IC device based on the modified IC layout design. In some embodiments, the step 1030 includes implementing a plurality of dummy transistors in the continuous N-well pickup region and the continuous P-well pickup region. In some embodiments, the step 1030 includes electrically biasing the continuous N-well pickup region or the continuous P-well pickup region to a voltage source or electrical ground at least in part using the dummy transistors. In some embodiments, the step 1030 includes manufacturing a multi-channel gate-all-around (GAA) device.

[0107] It should be appreciated that the method 1000 can include other steps performed before, during, or after the steps 1010-1030. These additional steps are not discussed in detail here for the sake of brevity.

[0108] The advanced lithography processes, methods, and materials described above can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between components, for which the above disclosure is well suited. Additionally, spacers, also known as mandrels, used to form the fins of a FinFET can be processed in accordance with the above disclosure. It will also be appreciated that various aspects of the invention discussed above can be applicable to multi-channel devices, such as gate-all-around (GAA) devices. To the extent that the invention relates to fin structures or FinFET devices, such discussion can equally apply to GAA devices.

[0109] In summary, the present invention configures (or reconfigures) the layout of the N-well pickup region and the P-well pickup region of an IC device such that they are not interleaved with each other. Rather, the N-well pickup region and the P-well pickup region of the IC device of the present invention extend contiguously without interleaving with each other. The N-well pickup region and the P-well pickup region of the IC device of the present invention are also much larger in size than their counterparts in conventional IC devices. In some embodiments, the IC device of the present invention is fabricated in a 7-nanometer technology node or smaller.

[0110] The present invention can provide advantages over conventional devices. However, it is to be understood that not all advantages are discussed, different embodiments can provide different advantages, and no particular advantage is necessary for any embodiment. One advantage is that undesired well-to-well implant dose compensation is reduced. For example, the fact that the N-well and P-well pickup regions are not interleaved with each other eliminates N / P boundaries that can exist between them if they were interleaved. Eliminating these N / P boundaries means that dopants will not diffuse into oppositely doped wells, which would have reduced resistance. Another advantage is that undesired hole effects are also mitigated. For example, because the N-well and P-well pickup regions are now much larger, the aspect ratio of the photoresist layer (used to define the N-well and P-well of the pickup regions) is smaller than in conventional devices, and the openings themselves are much wider / larger. As a result, it is less likely that the implanted dopants will be bombarded into the photoresist walls. This allows the correct dose of dopants to be implanted into the substrate to properly form the doped wells. For these reasons, the IC device of the present invention can have improved performance and / or reliability, such as reduced likelihood of latch-up or burn-out. Aspects of the present invention are particularly beneficial for newer technology nodes, such as 7-nanometer technology nodes or below, because the small geometry of these technology nodes means that well-to-well implant dose compensation and / or implant hole effect problems will be more prominent if they are not addressed by the implementation of embodiments of the present invention. Other advantages can include compatibility with existing manufacturing processes, including FinFET and GAA processes, and ease of implementation and low cost.

[0111] The advanced lithography processes, methods, and materials described above can be used in many applications, including fin field effect transistors (FinFETs). For example, fins can be patterned to produce relatively tight spacing between components, for which the above disclosure is well suited. In addition, spacers, also known as mandrels, used to form fins for FinFETs can be processed according to the above disclosure.

[0112] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a first region including a first portion of an N well and a plurality of P-type transistors formed above the first portion of the N well. The first region extends in a first direction. The semiconductor device includes a second region including a first portion of a P well and a plurality of N-type transistors formed above the first portion of the P well. The second region extends in the first direction and shares a first boundary with the first region, and wherein the first boundary extends in the first direction. The semiconductor device includes a third region including a second portion of the P well. The third region shares a second boundary with the first region and the second region. The second boundary extends in a second direction different from the first direction. The semiconductor device includes a fourth region including a second portion of the N well. The fourth region shares a third boundary with the first region and the second region. The third boundary extends in the second direction, and wherein the first region and the second region are disposed between the third region and the fourth region.

[0113] In the above semiconductor device, wherein: the third region includes one or more P well pickup contacts; and the fourth region includes one or more N well pickup contacts.

[0114] In the above semiconductor device, wherein: the third region includes one or more P well pickup contacts; and the fourth region includes one or more N well pickup contacts, each of the one or more P well pickup contacts or the one or more N well pickup contacts is electrically coupled to a voltage source.

[0115] In the above semiconductor device, wherein: the third region includes one or more P well pickup contacts; and the fourth region includes one or more N well pickup contacts, each of the one or more P well pickup contacts or the one or more N well pickup contacts is electrically coupled to a voltage source.

[0116] In the above semiconductor device, wherein: the P-type transistors of the first region and the N-type transistors of the second region are functional transistors; and each of the third region and the fourth region includes a plurality of dummy transistors.

[0117] In the above semiconductor device, wherein: the first region has a first size measured in the first direction; the second region has a second size measured in the first direction; the third region has a third size measured in the first direction; the fourth region has a fourth size measured in the first direction; and each of the first size and the second size is greater than the third size or the fourth size.

[0118] In the above semiconductor device, wherein: the first region has a first size measured in the first direction; the second region has a second size measured in the first direction; the third region has a third size measured in the first direction; the fourth region has a fourth size measured in the first direction; and each of the first size and the second size is greater than the third size or the fourth size; the first size is equal to the second size; and the third size is equal to the fourth size.

[0119] In the above semiconductor device, wherein: the first region has a first size measured in the first direction; the second region has a second size measured in the first direction; the third region has a third size measured in the first direction; the fourth region has a fourth size measured in the first direction; and each of the first size and the second size is greater than the third size or the fourth size; the first region has a fifth size measured in the second direction; the second region has a sixth size measured in the second direction; the third region has a seventh size measured in the second direction; the fourth region has an eighth size measured in the second direction; and each of the seventh size and the eighth size is greater than the fifth size or the sixth size.

[0120] In the above semiconductor device, wherein: the first region has a first size measured in the first direction; the second region has a second size measured in the first direction; the third region has a third size measured in the first direction; the fourth region has a fourth size measured in the first direction; and each of the first size and the second size is greater than the third size or the fourth size; the first region has a fifth size measured in the second direction; the second region has a sixth size measured in the second direction; the third region has a seventh size measured in the second direction; the fourth region has an eighth size measured in the second direction; and each of the seventh size and the eighth size is greater than the fifth size or the sixth size; the fifth size is equal to the sixth size; and the seventh size is equal to the eighth size.

[0121] In the above semiconductor device, further comprising: a fifth region including a third portion of the N well and a plurality of additional P-type transistors formed above the third portion of the N well, wherein the fifth region extends in the first direction; and a sixth region including a third portion of the P well and a plurality of additional N-type transistors formed above the third portion of the P well, wherein the sixth region extends in the first direction; wherein: the fifth region is disposed between the second region and the sixth region; the fifth region and the sixth region are disposed between the third region and the fourth region; the fifth region and the first region have the same size; and the sixth region and the second region have the same size.

[0122] In the above semiconductor device, wherein the P-type transistors and the N-type transistors comprise multi-channel gate-all-around (GAA) transistors or fin field effect transistors.

[0123] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a plurality of first regions each extending in a first direction. The first regions include P-type transistors. The semiconductor device includes a plurality of second regions each extending in the first direction. The second regions include N-type transistors, and wherein the first regions and the second regions are interleaved with each other in a second direction perpendicular to the first direction. The semiconductor device includes a continuous P well pickup region disposed on a first side of the first regions and the second regions. The semiconductor device includes a continuous N well pickup region disposed on a second side of the first regions and the second regions.

[0124] In the above semiconductor device, wherein: each of the first regions and the continuous N well pickup region are formed above a same N well; and each of the second regions and the continuous P well pickup region are formed above a same P well.

[0125] In the above semiconductor device, wherein each of the continuous P well pickup region and the continuous N well pickup region includes a plurality of dummy transistors.

[0126] In the above semiconductor device, wherein each of the continuous P well pickup region and the continuous N well pickup region includes a plurality of dummy transistors, the P well in the continuous P well pickup region or the N well in the continuous N well pickup region is electrically connected to a voltage rail or electrical ground through at least some of the dummy transistors.

[0127] In the above semiconductor device, wherein each of the contiguous P-well pickup region and the contiguous N-well pickup region includes a plurality of dummy transistors, the P-well in the contiguous P-well pickup region or the N-well in the contiguous N-well pickup region is electrically connected to a voltage rail or electrical ground through at least some of the dummy transistors, the P-type transistors and the N-type transistors are transistors manufactured using a 7 nanometer technology node or a technology node smaller than the 7 nanometer technology node.

[0128] Another aspect of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes receiving an integrated circuit (IC) layout design, the integrated circuit (IC) layout design including a plurality of NFET regions, a plurality of PFET regions, a plurality of N-well pickup regions, and a plurality of P-well pickup regions. From the received IC layout design: each of the NFET regions and the PFET regions extends in a first direction, the NFET regions are interleaved with the PFET regions in a second direction different from the first direction, the N-well pickup regions are respectively aligned with the PFET regions, the P-well pickup regions are respectively aligned with the NFET regions, and the N-well pickup regions are interleaved with the P-well pickup regions in the second direction. The method includes modifying the received IC layout design to generate a modified IC layout design at least in part by: replacing a first subset of the N-well pickup regions and a first subset of the P-well pickup regions with a contiguous P-well pickup region; and replacing a second subset of the N-well pickup regions and a second subset of the P-well pickup regions with a contiguous N-well pickup region.

[0129] In the above method, further including: manufacturing an integrated circuit device based on the modified integrated circuit layout design.

[0130] In the above method, further including: manufacturing an integrated circuit device based on the modified integrated circuit layout design, wherein manufacturing the integrated circuit device includes: implementing a plurality of dummy transistors in the contiguous N-well pickup region and the contiguous P-well pickup region; and electrically biasing the contiguous N-well pickup region or the contiguous P-well pickup region to a power supply or electrical ground at least in part using the dummy transistors.

[0131] In the above method, further including: manufacturing an integrated circuit device based on the modified integrated circuit layout design, wherein manufacturing the integrated circuit device includes manufacturing a multi-channel gate-all-around (GAA) device.

[0132] The foregoing outlines features of several embodiments so that those skilled in the art can better understand the detailed description that follows. Those skilled in the art should appreciate that they can readily use the present application as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the application, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present application. For example, different resistances of the conductors can be achieved by implementing different thicknesses of the bit line and word line conductors. However, other techniques for varying the resistance of the metal conductors can also be utilized.

Claims

1. A semiconductor device comprising: a first region comprising a first portion of an N-well and a plurality of P-type transistors formed above the first portion of the N-well, wherein the first region extends in a first direction; a second region comprising a first portion of a P-well and a plurality of N-type transistors formed above the first portion of the P-well, wherein the second region extends in the first direction and shares a first boundary with the first region, and wherein the first boundary extends in the first direction; a third region comprising a second portion of the P-well, wherein the third region includes a second boundary between the third region and the first and second regions, portions of the boundaries of the first and second regions adjacent to the third region overlap the second boundary, and wherein the second boundary extends in a second direction different from the first direction and a length of the second boundary in the second direction is greater than a sum of a length of the first region in the second direction and a length of the second region in the second direction; and a fourth region comprising a second portion of the N-well, wherein the fourth region includes a third boundary between the fourth region and the first and second regions, portions of the boundaries of the first and second regions adjacent to the fourth region overlap the third boundary, wherein the third boundary extends in the second direction, a length of the third boundary in the second direction is equal to a length of the second boundary in the second direction, and wherein the first and second regions are disposed between the third and fourth regions, a first active region formed above the second portion of the N-well and the first portion of the N-well and continuously extending in the first direction from the second portion of the N-well to the first portion of the N-well, a second active region formed above the second portion of the P-well and the first portion of the P-well and continuously extending in the first direction from the second portion of the P-well to the first portion of the P-well, wherein each of the third and fourth regions comprises a dummy transistor.

2. The semiconductor device of claim 1, wherein: the third region comprises one or more P-well pickup contacts; and the fourth region comprises one or more N-well pickup contacts.

3. The semiconductor device of claim 2, wherein, each of the one or more P-well pickup contacts or the one or more N-well pickup contacts is electrically coupled to a voltage source.

4. The semiconductor device of claim 2, wherein, each of the one or more P-well pickup contacts or the one or more N-well pickup contacts is electrically coupled to electrical ground.

5. The semiconductor device of claim 1, wherein: the P-type transistors of the first region and the N-type transistors of the second region are functional transistors; and each of the third and fourth regions comprises a plurality of dummy transistors.

6. The semiconductor device of claim 1, wherein: the first region has a first dimension measured in the first direction; the second region has a second dimension measured in the first direction; and the second dimension is greater than the first dimension. the second region has a second dimension measured in the first direction; the third region has a third dimension measured in the first direction; the fourth region has a fourth dimension measured in the first direction; and each of the first dimension and the second dimension is greater than the third dimension or the fourth dimension.

7. The semiconductor device of claim 6, wherein: the first dimension is equal to the second dimension; and the third dimension is equal to the fourth dimension.

8. The semiconductor device of claim 6, wherein: the first region has a fifth dimension measured in the second direction; the second region has a sixth dimension measured in the second direction; the third region has a seventh dimension measured in the second direction; the fourth region has an eighth dimension measured in the second direction; and each of the seventh dimension and the eighth dimension is greater than the fifth dimension or the sixth dimension.

9. The semiconductor device of claim 8, wherein: the fifth dimension is equal to the sixth dimension; and the seventh dimension is equal to the eighth dimension.

10. The semiconductor device of claim 1, further comprising: a fifth region comprising a third portion of the N-well and a plurality of additional P-type transistors formed above the third portion of the N-well, wherein the fifth region extends in the first direction; and a sixth region comprising a third portion of the P-well and a plurality of additional N-type transistors formed above the third portion of the P-well, wherein the sixth region extends in the first direction; wherein: the fifth region is disposed between the second region and the sixth region; the fifth region and the sixth region are disposed between the third region and the fourth region; the fifth region and the first region have the same dimension; and the sixth region and the second region have the same dimension.

11. The semiconductor device of claim 1, wherein, the P-type transistors and the N-type transistors comprise multi-channel gate-all-around (GAA) transistors or fin field effect transistors.

12. A semiconductor device, comprising: a plurality of first regions each extending in a first direction, wherein the first regions comprise P-type transistors; a plurality of second regions each extending in the first direction, wherein the second regions comprise N-type transistors, and wherein the first regions and the second regions are interleaved with each other in a second direction perpendicular to the first direction; a continuous P-well pickup region disposed on a first side of the first regions and the second regions, wherein a length of the continuous P-well pickup region in the second direction is greater than or equal to a sum of lengths of the first regions and the second regions in the second direction, and each of the second regions and the continuous P-well pickup region is formed above a same P-well; and a plurality of first regions each extending in a first direction, wherein the first regions comprise P-type transistors; a plurality of second regions each extending in the first direction, wherein the second regions comprise N-type transistors, and wherein the first regions and the second regions are interleaved with each other in a second direction perpendicular to the first direction; a continuous P-well pickup region disposed on a first side of the first regions and the second regions, wherein a length of the continuous P-well pickup region in the second direction is greater than or equal to a sum of lengths of the first regions and the second regions in the second direction, and each of the second regions and the continuous P-well pickup region is formed above a same P-well; and a continuous N-well pickup region disposed on a second side of the first region and the second region, wherein a length of the continuous N-well pickup region is equal to a length of the continuous P-well pickup region, and each of the first region and the continuous N-well pickup region is formed over a same N-well, a plurality of first active regions each formed over each of the plurality of first regions and the continuous N-well pickup region and extending in the first direction from each of the plurality of first regions to the continuous N-well pickup region, a plurality of second active regions each formed over each of the plurality of second regions and the continuous P-well pickup region and extending in the first direction from each of the plurality of second regions to the continuous P-well pickup region, wherein each of the continuous P-well pickup region and the continuous N-well pickup region includes a plurality of dummy transistors.

13. The semiconductor device of claim 12, wherein: the P-type transistors and the N-type transistors comprise multi-channel gate-all-around (GAA) transistors or fin field effect transistors.

14. The semiconductor device of claim 12, wherein, the continuous N-well pickup region is connected to the first region, and the continuous P-well pickup region is connected to the second region.

15. The semiconductor device of claim 12, wherein, the P-well in the continuous P-well pickup region or the N-well in the continuous N-well pickup region is electrically connected to a voltage rail or electrical ground through at least some of the dummy transistors.

16. The semiconductor device of claim 15, wherein, the P-type transistors and the N-type transistors are transistors fabricated using a 7 nanometer technology node or a technology node smaller than the 7 nanometer technology node.

17. A method of fabricating a semiconductor device, comprising: receiving an integrated circuit (IC) layout design including a plurality of N-type field effect transistor regions, a plurality of P-type field effect transistor regions, a plurality of N-well pickup regions, and a plurality of P-well pickup regions, wherein, according to the received integrated circuit layout design: each of the N-type field effect transistor regions and the P-type field effect transistor regions extends in a first direction, the N-type field effect transistor regions are interleaved with the P-type field effect transistor regions in a second direction different from the first direction, the N-well pickup regions are respectively aligned with the P-type field effect transistor regions, the P-well pickup regions are respectively aligned with the N-type field effect transistor regions, and the N-well pickup regions are interleaved with the P-well pickup regions in the second direction; and modifying the received integrated circuit layout design to generate a modified integrated circuit layout design at least in part by: replacing a first subset of the N-well pickup regions and a first subset of the P-well pickup regions with a continuous P-well pickup region, wherein a length of the continuous P-well pickup region in the second direction is greater than or equal to a sum of lengths of the N-type field effect transistor regions and the P-type field effect transistor regions in the second direction; and replacing a second subset of the N-well pickup regions and a second subset of the P-well pickup regions with a continuous N-well pickup region, wherein a length of the continuous N-well pickup region in the second direction is greater than or equal to the sum of the lengths of the N-type field effect transistor regions and the P-type field effect transistor regions in the second direction. replacing the second subset of the N-well pickup regions and the second subset of the P-well pickup regions with continuous N-well pickup regions and continuous P-well pickup regions, wherein a length of the continuous N-well pickup regions is equal to a length of the continuous P-well pickup regions, wherein the modified integrated circuit layout design includes regions including a plurality of dummy transistors in the continuous N-well pickup regions and the continuous P-well pickup regions, respectively, and a first active region extends from the N-type field effect transistor region to the continuous N-well pickup regions in the first direction and a second active region extends from the P-type field effect transistor region to the continuous P-well pickup regions in the first direction.

18. The method of claim 17, further comprising: manufacturing an integrated circuit device based on the modified integrated circuit layout design.

19. The method of claim 18, wherein, manufacturing the integrated circuit device includes: implementing the plurality of dummy transistors in the continuous N-well pickup regions and the continuous P-well pickup regions; and electrically biasing the continuous N-well pickup regions or the continuous P-well pickup regions to a power supply or electrical ground using at least in part the dummy transistors.

20. The method of claim 18, wherein, manufacturing the integrated circuit device includes manufacturing a multi-channel gate-all-around (GAA) device.

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