Vertical semiconductor device

Abstract

A vertical semiconductor device is provided, which includes a substrate, a cell array region and a pad region formed on the substrate, and gate patterns and corresponding insulating layers. The gate patterns are stacked in a vertical direction perpendicular to an upper surface of the substrate. Each of the gate patterns extends in a first direction parallel to the upper surface of the substrate over the cell array region and the pad region of the substrate. The gate patterns include pads respectively located at edge portions of the gate patterns in the first direction. The corresponding insulating layers are located between the gate patterns adjacent in the vertical direction. The gate patterns and the insulating layers on the pad region serve as a pad structure including a first step structure having a step shape, a second step structure having a step shape and disposed below the first step structure, a flat surface portion located between the first and second step structures, and a dummy step structure formed on the flat surface portion. The dummy step structure is spaced apart from each of the first and second step structures.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2019-0118949, filed on September 26, 2019, with the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The example embodiments relate to vertical semiconductor devices. More specifically, the example embodiments relate to vertical NAND (VNAND) flash memory devices. Background Technology

[0004] In VNAND flash memory devices, the gate pattern of each memory cell extends horizontally, and the edge portions of the gate pattern can be used as pad structures with a stepped shape. To form the pad structure, a molding structure can first be formed on a substrate. The molding structure can include a stepped structure and a flat surface portion. The flat surface portion can have a relatively wide flat surface, and the stepped structure can be formed above and below the flat surface portion, respectively. After forming the molding structure, the width of the pattern included in the molding structure can be measured. However, obtaining an accurate measurement of the width of the pattern included in the molding structure is not easy. Summary of the Invention

[0005] An example embodiment provides a vertical semiconductor device.

[0006] According to an example embodiment, a vertical semiconductor device includes: a substrate; a cell array region including memory cells formed on the substrate; a pad region formed on the substrate, wherein contact plugs electrically connecting the memory cells are formed in the pad region. The vertical semiconductor device further includes: gate patterns stacked in a vertical direction perpendicular to the upper surface of the substrate, each gate pattern extending in the cell array region and the pad region along a first direction parallel to the upper surface of the substrate, and each gate pattern including a pad disposed in the pad region and at an edge portion of the respective gate pattern in the first direction; an insulating layer located between adjacent gate patterns in the vertical direction; and a channel structure located in the cell array region and extending through the gate patterns along the vertical direction. The gate pattern and the insulating layer located on the pad area serve as a pad structure, and the pad structure includes a first stepped structure having a stepped shape, a second stepped structure having a stepped shape and disposed below the first stepped structure, a flat surface portion located between the first stepped structure and the second stepped structure, and a dummy stepped structure formed on the flat surface portion, wherein the second stepped structure is spaced apart from the first stepped structure in the first direction.

[0007] According to an example embodiment, a vertical semiconductor device includes: a substrate; a cell array region and a pad region formed on the substrate; gate patterns stacked in a vertical direction perpendicular to an upper surface of the substrate, each gate pattern extending over the cell array region and the pad region of the substrate in a first direction parallel to the upper surface of the substrate, and the gate pattern including pads located at edge portions of the gate pattern in the first direction; an insulating layer located between adjacent gate patterns in the vertical direction; a channel structure located on the cell array region and extending through the gate patterns, the channel structure extending along the vertical direction; and contact pins extending along the vertical direction and contacting the upper surfaces of the pads respectively. The gate pattern and the insulating layer located on the pad region serve as a pad structure, and the pad structure includes a first stepped structure having a stepped shape and including the pad, a second stepped structure disposed below the first stepped structure, a flat surface portion located between the first stepped structure and the second stepped structure, and a dummy stepped structure formed on the flat surface portion, the second stepped structure having a stepped shape and including the pad; and the dummy stepped structure extends to the outermost opposite end of the pad structure in a second direction perpendicular to the first direction.

[0008] According to an example embodiment, a vertical semiconductor device includes a substrate, a cell array region and a pad region formed on the substrate, a gate pattern, and a corresponding insulating layer. The gate patterns may be stacked in a vertical direction perpendicular to the upper surface of the substrate. Each gate pattern may extend over the cell array region and the pad region of the substrate in a first direction parallel to the upper surface of the substrate. The gate pattern may include pads located at edge portions of the gate pattern in the first direction. The corresponding insulating layer may be located between adjacent gate patterns in the vertical direction. The gate pattern and the insulating layer located on the pad region may serve as a pad structure, and the pad structure may include a first stepped structure having a stepped shape, a second stepped structure having a stepped shape and disposed below the first stepped structure, a flat surface portion located between the first stepped structure and the second stepped structure, and a dummy stepped structure formed on the flat surface portion. The dummy stepped structure may be spaced apart from each of the first stepped structure and the second stepped structure. Attached Figure Description

[0009] The exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 52These represent non-limiting example embodiments as described herein.

[0010] Figures 1 to 29 These are top views, cross-sectional views, and perspective views illustrating a method of manufacturing a vertical storage device according to an example embodiment;

[0011] Figures 30 to 37 Cross-sectional view, top view and perspective view of a method for manufacturing a vertical storage device according to an example embodiment;

[0012] Figures 38 to 46 A top view, a cross-sectional view, and a perspective view illustrating a method for manufacturing a vertical storage device according to an example embodiment; and

[0013] Figures 47 to 52 These are top and perspective views illustrating a method for manufacturing a vertical storage device according to an example embodiment. Detailed Implementation

[0014] In the following text, a direction substantially perpendicular to the upper surface of the substrate will be described as a vertical direction. Two directions substantially parallel to the upper surface of the substrate and intersecting each other will be described as a first direction and a second direction, and may be described as horizontal directions. In an example embodiment, the first and second directions may be substantially perpendicular to each other. However, it should be noted that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. Unless the context otherwise indicates, these terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion, for example, as a naming convention. Therefore, without departing from the teachings of the invention, a first element, first component, first region, first layer, or first portion discussed in one part of the specification may be referred to as a second element, second component, second region, second layer, or second portion in another part of the specification or in the claims. In addition, in certain cases, even if the terms "first" or "second" are not used in the specification, the terms may still be referred to as "first" or "second" in the claims to distinguish different claimed elements from each other.

[0015] Figures 1 to 29 These are top views, cross-sectional views, and perspective views illustrating a method for manufacturing a vertical storage device according to an example embodiment. Specifically, Figure 1 , Figure 6 , Figure 7 and Figure 17 It is a top view. Figure 2 , Figure 3 , Figure 16 , Figures 18 to 23 and Figures 26 to 28It is a cross-sectional view. Figure 4 , Figure 5 , Figures 8 to 15 , Figure 24 , Figure 25 and Figure 29 It is a perspective view.

[0016] Figure 6 , Figure 7 and Figure 17 yes Figure 1 A top view of region X. Figure 4 , Figure 5 , Figures 8 to 15 , Figure 24 , Figure 25 and Figure 29 yes Figure 1 A perspective view of region X. Figure 3 , Figures 18 to 20 , Figure 22 as well as Figure 26 and Figure 28 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 21 and Figure 23 It is along Figure 1 A cross-sectional view taken from line B-B'. Figure 27 It is along Figure 1 The cross-sectional view taken from line C-C'. Figure 16 Is Figure 1 A cross-sectional view taken from region X along a line extending in the first direction.

[0017] Reference Figure 1 The substrate 600 may include a first region I and a second region II. The second region II may be adjacent to the opposite side of the first region I in a first direction.

[0018] The substrate 600 may include semiconductor materials such as silicon, germanium, or silicon-germanium, or III-V compounds such as GaP, GaAs, GaSb, etc., or may be formed from semiconductor materials such as silicon, germanium, or silicon-germanium, or III-V compounds such as GaP, GaAs, GaSb, etc. In some example embodiments, the substrate 600 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0019] In the example embodiment, a first region I of the substrate 600 is a cell array region in which memory cells are formed, and a second region II of the substrate 600 is a pad region in which contact pins electrically connected to the memory cells are formed. The second region II can extend from the first region I along a first direction, and thus the second region II can be referred to as an extension region or a word line extension region.

[0020] In an example embodiment, the vertical memory device may have a cell-on-periphery (COP) structure. For example, peripheral circuitry for driving the memory cells may be formed below the memory cells. Therefore, the circuit pattern region for forming the peripheral circuitry, as well as the cell array region and pad region, may be vertically stacked on the substrate 600, and the peripheral circuitry may be referred to as the circuit pattern or the lower circuit pattern.

[0021] However, the present invention is not limited thereto; the vertical memory device may not have a COP structure, and the substrate 600 may further include a peripheral circuit region that at least partially surrounds the second region II. Circuit patterns may be formed on the peripheral circuit region.

[0022] Figure 1 Region X shown is part of the second region II of substrate 600. In the example embodiment, multiple regions X may be provided along the second direction.

[0023] Reference Figure 2 The circuit pattern can be formed on the substrate 600, and the first lower insulating intermediate layer 660 and the second lower insulating intermediate layer 730 can be sequentially formed on the substrate 600 to cover the circuit pattern.

[0024] First, a device isolation process can be performed on substrate 600 to form a field region on which isolation pattern 610 is formed, or an active region on which isolation pattern is formed. Isolation pattern 610 may include oxide.

[0025] The circuit pattern may include transistors, lower contact pins, lower wiring, lower vias, etc. For example, the transistor may include a lower gate structure 650 located on the substrate 600 and a first impurity region 605 adjacent to the lower gate structure 650 on the upper part of the active region of the substrate 600. The lower gate structure 650 may include a lower gate insulating pattern 620, a lower gate pattern 630, and a lower gate mask 640 stacked in sequence.

[0026] A first lower insulating interlayer 660 may be formed on the substrate 600 to cover the transistor. A lower contact 670 may pass through the first lower insulating interlayer 660 and may contact the first impurity region 605 or the lower gate pattern 630. A first lower wiring 680 may be formed on the first lower insulating interlayer 660 to contact the upper surface of the lower contact 670. A first lower pass 690, a second lower wiring 700, a second lower pass 710, and a third lower wiring 720 may be sequentially stacked on the first lower wiring 680.

[0027] To avoid the complexity of the accompanying drawings, the circuit pattern on substrate 600 will not be shown in the following text.

[0028] Reference Figure 3A base pattern 100 can be formed on the second lower insulating intermediate layer 730, and insulating patterns (not shown) can be formed between portions of the base pattern 100. Insulating layers 110 and sacrificial layers 120 can be stacked alternately and repeatedly on the base pattern 100 and the insulating patterns. In this case, insulating layer 110 can be formed on the uppermost portion of the stack.

[0029] The substrate pattern 100 may include, for example, a semiconductor material such as silicon, or may be formed from, for example, a semiconductor material such as silicon. The insulating layer 110 may include, for example, an oxide such as silicon oxide, or may be formed from, for example, an oxide such as silicon oxide. The sacrificial layer 120 may include a material that has etch selectivity relative to the insulating layer 110. The sacrificial layer 120 may include, for example, a nitride such as silicon nitride, or may be formed from, for example, a nitride such as silicon nitride.

[0030] In the following text, to avoid the complexity of the accompanying drawings, the insulating layer 110 will not be shown in any perspective views; instead, only the sacrificial layer 120 will be shown. The etching process for the sacrificial layer 120 can be performed not only on the sacrificial layer 120 but also on the insulating layer 110. Each insulating layer 110 can form a pair with a sacrificial layer 120 located directly below it, and for ease of explanation, the insulating layer 110 will not be shown when the etching process is described with reference to the perspective views.

[0031] Reference Figure 4 A first photoresist pattern (not shown) can be formed on the uppermost sacrificial layer 120 to cover the edge portions (also described as ends) of the first region I and the second region II of the substrate 600 adjacent to the first region I. The uppermost sacrificial layer 120 can be etched using an etching process employing an etching mask to form the first sacrificial pattern 122. The first sacrificial pattern 122 can extend along the boundary of the first region I. For example, the first sacrificial pattern 122 can extend along the boundary of the first region I in a second direction.

[0032] Additionally, a second-level sacrificial layer 120, counting from the top level, can be exposed on a second region II adjacent to the sidewall of the first sacrificial pattern 122 (hereinafter, the nth level counting from the top level will be simply referred to as the nth level).

[0033] However, Figure 4 Only a portion of the second region II of the substrate 600, such as region X, is shown; therefore, only a portion of the first sacrificial pattern 122 is shown. Hereinafter, the sacrificial pattern formed by etching the sacrificial layer 120 may be described with respect to the shape within region X.

[0034] The method for forming the stepped molding structure can be described below. In the process for forming the stepped molding structure, the sacrificial layer 120 on the first region I of the substrate 600 is continuously covered by a photoresist pattern. Therefore, the sacrificial layer 120 on the first region I of the substrate 600 may not be etched and is therefore not described. In some embodiments, the sacrificial pattern 122 covers the entire first region I of the substrate 600 along a first direction and extends slightly into a second region II of the substrate 600 located at the opposite end of the first region I.

[0035] After the first sacrificial pattern 122 is formed, the first photoresist pattern can be removed by an ashing process and / or a stripping process.

[0036] Reference Figures 5 to 7 Second to fifth photoresist patterns 142, 144, 146 and 148 can be formed on the first sacrificial pattern 122 and the exposed sacrificial layer 120 at the second level.

[0037] The second photoresist pattern 142 can cover the first sacrificial pattern 122, and the length of the second photoresist pattern 142 in the first direction can be greater than the length of the first sacrificial pattern 122 in the first direction.

[0038] The third photoresist pattern 144 may cover a portion of the sacrificial layer 120 located in region X and may be spaced apart from the second photoresist pattern 142 in a first direction. In a top view, the third photoresist pattern 144 may have a quadrilateral shape. The third photoresist pattern 144 may be formed on a portion of a subsequently formed first stepped structure.

[0039] The fifth photoresist pattern 148 may cover a portion of the sacrificial layer 120 located in region X and may be spaced apart from the third photoresist pattern 144 in a first direction. In a top view, the fifth photoresist pattern 148 may have a quadrilateral shape. The fifth photoresist pattern 148 may be formed on a portion of a subsequently formed second stepped structure.

[0040] In an example embodiment, the first stepped structure formed on the upper level and the second stepped structure formed on the lower level may include steps of the same size and shape. In this case, although not shown in the perspective view, it is... Figure 6As shown, the width of the third photoresist pattern 144 used to form the first step structure in the second direction can be smaller than the width of the fifth photoresist pattern 148 used to form the second step structure in the second direction. The number of etching processes used to form the second step structure can be greater than the number of etching processes used to form the first step structure. Therefore, if the widths of the third photoresist pattern 144 and the fifth photoresist pattern 148 are substantially the same, the first step structure can have a relatively large width in the second direction.

[0041] Additionally, although not shown in the perspective view, as Figure 6 As shown, the third photoresist pattern 144 and the fifth photoresist pattern 148 can have trapezoidal shapes instead of rectangular shapes. For example, as the distance from the first region I increases, the width of each of the third photoresist pattern 144 and the fifth photoresist pattern 148 in the second direction can increase. When forming each of the first and second stepped structures, the number of etching processes can increase with the increase of the distance from the first region I to a portion of each of the first and second stepped structures. Therefore, the third photoresist pattern 144 and the fifth photoresist pattern 148 can have the shapes described above. However, in each perspective view, to avoid the complexity of the figures, and also when a rectangular shape is used, the third photoresist pattern 144 and the fifth photoresist pattern 148 are shown to have the same rectangular shape.

[0042] The portion between the third photoresist pattern 144 and the fifth photoresist pattern 148 can be a flat surface portion Y between the first stepped structure and the second stepped structure. For example, the flat surface can be formed from the top surface of a sacrificial layer 120. In an example embodiment, the width of the flat surface portion Y in the first direction can be approximately 15 μm to 40 μm.

[0043] A fourth photoresist pattern 146 can be formed on a flat surface portion between the third photoresist pattern 144 and the fifth photoresist pattern 148. The fourth photoresist pattern 146 can be spaced apart from the third photoresist pattern 144 and the fifth photoresist pattern 148 in a first direction. The fourth photoresist pattern 146 can extend along a second direction to have a line shape parallel to the boundary of the first region I. However, Figure 6 Only region X of substrate 600 is shown, so the fourth photoresist pattern 146 can be shown as having a strip shape. The fourth photoresist pattern 146 can be disposed on a portion of a dummy stepped structure formed later.

[0044] The exposed sacrificial layer 120 can be etched using the second to fifth photoresist patterns 142, 144, 146, and 148 as etch masks. For example, the sacrificial layer 120 at the second level can be etched.

[0045] Therefore, a first sacrificial pattern 122 can be further formed at the second layer, thus the first sacrificial pattern can include two layers. A second sacrificial pattern 124 can be formed to be spaced apart from the first sacrificial pattern 122 in the first direction, and in a top view, the second sacrificial pattern 124 can have a quadrilateral shape. A fourth sacrificial pattern 128 can be formed to be spaced apart from the second sacrificial pattern 124 in the first direction, and in a top view, the fourth sacrificial pattern 128 can have a quadrilateral shape. A third sacrificial pattern 126 can be formed between the second sacrificial pattern 124 and the fourth sacrificial pattern 128. The third sacrificial pattern 126 can have the shape of a line extending along a second direction (e.g., it can extend longitudinally along the second direction such that its length in the second direction is greater than its width in the first direction).

[0046] In some example embodiments, such as Figure 7 As shown, multiple second sacrificial patterns 124 and fourth sacrificial patterns 128 spaced apart from each other in the first direction can be alternately formed. A third sacrificial pattern 126 can be formed between the second sacrificial patterns 124 and the fourth sacrificial patterns 128. In this case, more stepped structures and dummy stepped structures can be formed by subsequent processes.

[0047] Reference Figure 8 A first trimming process can be performed to reduce the area of ​​the second to fifth photoresist patterns 142, 144, 146 and 148, and the reduced second to fifth photoresist patterns 142, 144, 146 and 148 can be used as etching masks to etch the first to fourth sacrificial patterns 122, 124, 126 and 128 and the sacrificial layer 120 at the third level.

[0048] Therefore, the length of the first sacrificial pattern 122 in the first direction can be reduced in the second layer, and the first sacrificial pattern 122 can be further formed in the third layer. Therefore, the first sacrificial pattern 122 can include three layers. The areas of the second sacrificial patterns 124 and 128 in the second layer can be reduced, and the second sacrificial patterns 124 and 128 can be further formed in the third layer. Therefore, both the second sacrificial patterns 124 and 128 can include two layers. The area of ​​the third sacrificial pattern 126 in the second layer can be reduced, and the third sacrificial pattern 126 can be further formed in the third layer. Therefore, the third sacrificial pattern 126 can include two layers.

[0049] Reference Figure 9 It can perform a second trimming process and an etching process.

[0050] For example, after reducing the area of ​​the second to fifth photoresist patterns 142, 144, 146, and 148, the reduced second to fifth photoresist patterns 142, 144, 146, and 148 can be used as etching masks to etch the first to fourth sacrificial patterns 122, 124, 126, and 128, as well as the sacrificial layer 120 at the fourth level. Therefore, the upper surface of the sacrificial layer at the fifth level can be exposed.

[0051] Therefore, the first sacrificial pattern 122 may include four layers, and the edge portion of the first sacrificial pattern 122 in the first direction may be a stepped shape with four layers.

[0052] The second sacrificial pattern 124 and the fourth sacrificial pattern 128 may each include three layers, and the edge portions of each of the second sacrificial pattern 124 and the fourth sacrificial pattern 128 in the first and second directions may each have a stepped shape with three layers. The number of layers included in each of the second sacrificial pattern 124 and the fourth sacrificial pattern 128 can determine the number of steps in the second direction of each subsequently formed stepped structure. For example, the number of layers included in each of the second sacrificial pattern 124 and the fourth sacrificial pattern 128 may be one less than the number of steps in the second direction of each subsequently formed stepped structure.

[0053] The third sacrificial pattern 126 may include three layers, and the edge portion of the third sacrificial pattern 126 in the first direction may have a stepped shape. However, the third sacrificial pattern 126 may not include steps in the second direction. That is, the opposing sidewalls of the third sacrificial pattern 126 may have a stepped shape only in the direction perpendicular to the boundary of the first region I (i.e., in the first direction).

[0054] In some example embodiments, the first through fourth sacrificial patterns 122, 124, 126, and 128 may each include more or fewer layers. For example, the number of layers (e.g., the number of steps) included in each of the first through fourth sacrificial patterns 122, 124, 126, and 128 may be controlled by the number of photoresist pattern finishing processes and the number of etching processes.

[0055] In the following text, the first to fourth sacrificial patterns formed by the finishing and etching processes of the second to fifth photoresist patterns 142, 144, 146, and 148 can be referred to as the initial first sacrificial patterns to the initial fourth sacrificial patterns, respectively. That is, Figure 9 The first to fourth sacrifice patterns shown can be referred to as the initial first sacrifice pattern to the initial fourth sacrifice pattern, respectively.

[0056] Reference Figure 10A sixth photoresist pattern 152 can be formed on the fifth-level sacrificial layer 120, covering the portion of the first sacrificial pattern 122 and the second sacrificial pattern 124 adjacent to the first sacrificial pattern 122.

[0057] Subsequently, the sixth photoresist pattern 152 can be used as an etching mask to etch the second to fourth sacrificial patterns 124, 126 and 128 and the fifth to eighth sacrificial layers 120.

[0058] Therefore, the third sacrificial pattern 126 and the fourth sacrificial pattern 128, which are not covered by the sixth photoresist pattern 152, can be etched and transferred onto the ninth-level sacrificial layer. Thus, the third sacrificial pattern 126 and the fourth sacrificial pattern 128 can be formed on the ninth-level sacrificial layer.

[0059] The portion of the second sacrificial pattern 124 not covered by the sixth photoresist pattern 152 can be etched and transferred onto the ninth-level sacrificial layer. The portion of the second sacrificial pattern 124 covered by the sixth photoresist pattern 152 can be left unetched and retained.

[0060] In an example embodiment, during the etching process, the number of sacrificial layers etched may be one more than the number of layers included in each of the initial second to initial fourth sacrificial patterns 124, 126, and 128. For example, because each of the initial second to initial fourth sacrificial patterns 124, 126, and 128 includes three layers from the second to the fourth level, the four layers below each of the initial second to initial fourth sacrificial patterns 124, 126, and 128 (e.g., sacrificial layers 120 at the fifth to eighth levels) can be etched.

[0061] Thus, although four layers of sacrificial layers 120 are etched using an etching process with the sixth photoresist pattern 152, the inventive concept is not limited thereto. More or fewer layers of sacrificial layers 120 can be etched using the etching process.

[0062] Reference Figure 11 and Figure 12 A first trimming process can be performed to reduce the area of ​​the sixth photoresist pattern 152, thereby further exposing a portion of the second sacrificial pattern 124.

[0063] The reduced sixth photoresist pattern 152 can be used as an etching mask to etch the second to fourth sacrificial patterns 124, 126, and 128, as well as the sacrificial layers 120 at the ninth to twelfth levels. The third sacrificial pattern 126 and the fourth sacrificial pattern 128 can be etched and thus transferred onto the sacrificial layer 120 at the thirteenth level. The third sacrificial pattern 126 and the fourth sacrificial pattern 128 can be formed on the sacrificial layer at the thirteenth level.

[0064] The portion of the second sacrificial pattern 124 not covered by the sixth photoresist pattern 152 can be etched and transferred onto the sacrificial layer 120 at the thirteenth level. The portion of the second sacrificial pattern 124 covered by the sixth photoresist pattern 152 can be left unetched and retained.

[0065] Subsequently, the trimming of the sixth photoresist pattern 152 and the etching of the exposed sacrificial pattern and sacrificial layer can be repeatedly performed.

[0066] When performing a trimming of the photoresist pattern and etching of the exposed sacrificial pattern and sacrificial layer, a step in the second sacrificial pattern 124 in the first direction can be further formed. Additionally, four steps in the second direction of the second sacrificial pattern 124 can be formed from the initial step of the second sacrificial pattern 124. Thus, the trimming and etching processes can be performed once or more.

[0067] Figure 11 The structure formed by performing a total of three etching processes and two finishing processes is shown. Figure 12 The structure formed by performing a total of five etching processes and four finishing processes is shown.

[0068] like Figure 12 As shown, a first step structure S1 can be formed on the sacrificial layer 120 at the 25th layer by performing a trimming and etching process. Hereinafter, the pattern included in the first step structure S1 is referred to as the fifth sacrificial pattern 124a. After forming the first step structure S1, the sixth photoresist pattern 152 can be removed. The pattern formed on a single layer can be referred to herein as a layer pattern.

[0069] The first stepped structure S1 may include five steps in a first direction and four steps at either end in a second direction. The steps at either end in the second direction may be symmetrical about a line extending along the first direction.

[0070] The edge portions of the initial second sacrificial pattern in the first direction are transferred to the bottom and top layers of the first stepped structure S1, respectively. Therefore, the bottom and top layers of the first stepped structure S1 can each have a shape substantially the same as the shape of the edge portions of the initial second sacrificial pattern in the first direction.

[0071] Simultaneously, during the trimming and etching processes, the third sacrificial pattern 126 and the fourth sacrificial pattern 128 exposed by the sixth photoresist pattern 152 can be etched and transferred to the underlying layer. For example, the third sacrificial pattern 126 and the fourth sacrificial pattern 128 can be formed on the sacrificial layer 120 at the 25th layer level.

[0072] The third sacrificial pattern 126 can be spaced apart from the first stepped structure S1 in the first direction. The third sacrificial pattern 126 can be disposed between the first stepped structure S1 and the fourth sacrificial pattern 128. Through subsequent processes, the third sacrificial pattern 126 can be used as a dummy stepped structure.

[0073] Reference Figure 13 A seventh photoresist pattern 154 is formed, covering a portion of the first sacrificial pattern 122, the first stepped structure S1, the third sacrificial pattern 126, and the fourth sacrificial pattern 128. The seventh photoresist pattern 154 can completely cover the first sacrificial pattern 122, the first stepped structure S1, the third sacrificial pattern 126, and the sacrificial layer 120 between them. Therefore, only the stepped portion of the edge of the fourth sacrificial pattern 128 in the first direction can be exposed by the seventh photoresist pattern 154.

[0074] Reference Figure 14 The seventh photoresist pattern 154 can be used as an etching mask to etch the three layers included in the fourth sacrificial pattern 128, as well as the sacrificial layer.

[0075] Subsequently, the trimming of the seventh photoresist pattern 154 and the etching of the exposed fourth sacrificial pattern 128 and the sacrificial layer can be repeated.

[0076] In the example embodiment, a total of five etching processes and four trimming processes can be performed. Therefore, a second step structure S2 can be formed on the sacrificial layer at level 45. Hereinafter, the pattern included in the second step structure S2 is referred to as the sixth sacrificial pattern 128a.

[0077] In an example embodiment, the number of etching processes and trimming processes used to form the second stepped structure S2 can be the same as the number of etching processes and trimming processes used to form the first stepped structure S1. In this case, similar to the first stepped structure S1, the second stepped structure S2 can include five steps in the first direction and four steps in the second direction. The steps of the second stepped structure S2 can be symmetrical about a line extending along the first direction. However, the number of etching processes and trimming processes used to form the second stepped structure S2 is not limited thereto.

[0078] The edge portions of the initial fourth sacrificial pattern in the first direction are transferred to the bottom and top layers of the second stepped structure S2, respectively. Therefore, the bottom and top layers of the second stepped structure S2 can each have a shape substantially the same as the shape of the edge portions of the initial fourth sacrificial pattern in the first direction.

[0079] The seventh photoresist pattern 154 can completely cover the first sacrificial pattern 122, the first step structure S1, the third sacrificial pattern 126, and the sacrificial layer between them. Therefore, the first sacrificial pattern 122, the first step structure S1, and the third sacrificial pattern 126 can be left unetched by the etching process and can be retained.

[0080] Reference Figures 15 to 17 The seventh photoresist pattern 154 can be removed to form a molded structure 140. The molded structure 140 may include a first sacrificial pattern 122, a first step structure S1, a third sacrificial pattern 126, and a second step structure S2. Through a subsequent metal replacement process, the molded structure 140 formed on the second region II can be used as a pad structure.

[0081] In the molded structure, the stacked structure of the first sacrificial pattern 122 is referred to as the upper step structure 290. Additionally, the stacked structure of the third sacrificial pattern 126 is referred to as the dummy step structure 300.

[0082] like Figures 15 to 17 As shown, a flat surface portion Y with a relatively wide width can be formed between the first stepped structure S1 and the second stepped structure S2. The first stepped structure S1 can be configured to be higher than the flat surface portion Y. A portion of the second stepped structure S2 can be configured to be higher than the flat surface portion Y, and most of the second stepped structure S2 can be configured to be lower than the flat surface portion Y. Furthermore, a dummy stepped structure 300 can be formed on the flat surface portion Y.

[0083] The steps of the first stepped structure S1 and the steps of the second stepped structure S2 can correspond to the exposed upper surfaces of the fifth sacrificial pattern 124a and the sixth sacrificial pattern 128a, respectively. The steps can be used as pads for forming contact pins thereon through subsequent processes.

[0084] A portion of the flat surface portion Y may be a portion used to form a through-path contact for electrical connection with the peripheral circuit.

[0085] After the molded structure 140 is formed, a precise measurement of the width of the molded structure 140 in the first direction can be performed. Specifically, the width of the distinguishable patterns (e.g., steps) in the molded structure 140 in the first direction can be measured separately, and the widths measured in the first direction can be added together to determine the width of the entire molded structure 140 in the first direction.

[0086] like Figure 17 As shown, the width (a) of each step in the first sacrificial pattern 122 in the first direction and the width (b, d) of each step included in the first step structure S1 and the second step structure S2 in the first direction can be measured respectively. A step can also be described as the upper surface of each step. The third sacrificial pattern 126 can be formed on the flat surface portion Y. Therefore, the width (c1) of the step in the third sacrificial pattern 126 in the first direction and the width (c2) of the uppermost surface of the third sacrificial pattern 126 in the first direction can be measured respectively. Furthermore, the width (e) between the first sacrificial pattern 122 and the first step structure S1, the width (f) between the first step structure S1 and the third sacrificial pattern 126, the width (g) between the third sacrificial pattern 126 and the second step structure S2, and the width (h) between the second step structure S2 and the lower end of the molded structure can be measured respectively.

[0087] Therefore, to measure the width of the flat surface portion Y, the width (f) between the lower end of the dummy step structure 300 and the first step structure S1, the width (c1) of each step in the third sacrificial pattern 126, the width (c2) of the uppermost surface of the third sacrificial pattern 126, and the width (g) between the upper edge of the dummy step structure 300 and the second step structure S2 can be measured separately. The measured widths can be added together to determine the total width of the flat surface portion Y. It should be noted that the term "length" can be used to describe the widths described above, as each item can be described as having a specific length in a first direction.

[0088] If the dummy stepped structure 300 is not formed on the flat surface portion Y, the distinguishable pattern used for measurement will not be located on the flat surface portion Y. Therefore, the total width of the flat surface portion Y can be measured in a single measurement. The total width of the flat surface portion Y may be relatively large, making it impossible to measure the total width of the flat surface portion Y at high magnification and high resolution. For example, the total width of the flat surface portion Y may be measured at a lower magnification than that used to measure the width of each step in the first stepped structure S1 and the second stepped structure S2. When the width of the flat surface portion Y is measured at low magnification, the measurement error of the width increases, and accurate measurement may not be possible. Therefore, the total width of the molded structure 140 in the first direction may not be accurately measured.

[0089] In contrast, in the example embodiment, the dummy step structure 300 can be formed on the flat surface portion Y. Therefore, the width of the flat surface portion can be determined by measuring each distinguishable pattern at the third sacrificial pattern 126. Thus, a high magnification can be used to measure the width of the flat surface portion. For example, the width of each distinguishable pattern in the third sacrificial pattern 126 can be measured at the same or higher magnification as that used to measure the width of each step of the first step structure S1 and the second step structure S2.

[0090] Reference Figure 18 A first insulating intermediate layer 200 can be formed on the substrate pattern 100, and the first insulating intermediate layer 200 can cover the molded structure 140 formed on the first region I and the second region II. The first insulating intermediate layer 200 can be planarized until the upper surface of the uppermost insulating layer 110 is exposed. Therefore, the first insulating intermediate layer 200 can cover the sidewalls of the molded structure 140. The first insulating intermediate layer 200 can include, for example, an oxide such as silicon oxide.

[0091] In an example embodiment, an insulating intermediate layer may be further formed on the upper surface of the molded structure 140 and the upper surface of the first insulating intermediate layer 200.

[0092] Reference Figure 19 After forming a first mask (not shown) on the first insulating intermediate layer 200, a molded structure 140 formed on the first region I can be etched using the first mask (not shown) to form a channel hole. The channel hole can pass through the molded structure 140, thus exposing the upper surface of the substrate pattern 100. A plurality of channel holes can be regularly formed on the substrate pattern 100 in the first region I. A channel structure 230 can be formed in the channel hole.

[0093] In an example embodiment, a semiconductor pattern 220 may be further formed between the substrate pattern 100 and the channel structure 230. In this case, the channel structure 230 may be formed on the semiconductor pattern 220. In an example embodiment, the semiconductor pattern 220 may include, for example, monocrystalline silicon or polycrystalline silicon. In some example embodiments, the process for forming the semiconductor pattern 220 may be omitted. In this case, the channel structure 230 may be directly connected to (e.g., in contact with) the substrate pattern 100. Unless the context clearly indicates otherwise, the term "in contact" as used herein refers to a direct connection (e.g., touching).

[0094] In an example embodiment, the channel structure 230 may include a dielectric layer structure 222, a channel 224, a buried insulating pattern 226, and an upper conductive pattern 228.

[0095] The dielectric layer structure 222 may include a tunnel insulating layer, a charge storage layer, and a barrier layer sequentially stacked from the outer wall of the channel 224. The upper conductive pattern 228 may include polysilicon.

[0096] Reference Figure 20 and Figure 21 A second insulating intermediate layer 202 can be formed on the molding structure 140, the channel structure 230, and the first insulating intermediate layer 200. A second mask (not shown) can be formed on the second insulating intermediate layer 202. The second mask can be used as an etching mask to etch the first insulating intermediate layer 200, the second insulating intermediate layer 202, and the molding structure 140 to form a trench 240 through the first insulating intermediate layer 200, the second insulating intermediate layer 202, and the molding structure 140. The upper surface of the substrate pattern 100 can be exposed by the trench 240.

[0097] In some example embodiments, trenches 240 may be formed on a first region I and a second region II of the substrate 600 and may extend along a first direction. A plurality of trenches 240 may be formed to be arranged along a second direction.

[0098] After removing the second mask, the sacrificial layer exposed by trench 240 can be removed to form a gap 242 between the insulating layers 110. A portion of the outer sidewall of the channel structure 230 and a portion of the sidewall of the semiconductor pattern 220 can be exposed by the gap 242.

[0099] Reference Figures 22 to 25 A gate conductive layer is formed in the gap 242. Before forming the gate conductive layer, a barrier metal layer (not shown) may also be conformally formed on the surface of the gap 242.

[0100] For example, the gate conductive layer may include a low-resistance metal, such as tungsten or aluminum, and the barrier metal layer may include a metal nitride, such as titanium nitride or tantalum nitride.

[0101] Subsequently, the gate conductive layer in trench 240 can be selectively removed to form a gate conductive pattern filling the gap 242. When forming a barrier metal layer, a barrier metal pattern can be formed by a removal process. The structure including the gate conductive pattern and the barrier metal pattern can be used as gate pattern 250.

[0102] In an example embodiment, the gate pattern 250 may extend along a first direction, and a plurality of gate patterns 250 may be arranged along a second direction. The plurality of gate patterns 250 may be spaced apart from each other by trenches 240 in the second direction.

[0103] Gate patterns 250 can be stacked and spaced apart from each other in a vertical direction. Each gate pattern 250 can extend along a first direction and thus can be formed on a first region I and a second region II of the substrate 600.

[0104] The gate pattern 250 can be formed by replacing the sacrificial layer included in the molding structure located on the first region I and the second region II with metal.

[0105] All sacrificial layers of the molded structure 140 formed on the first region I can be replaced with gate pattern 250. The gate pattern 250 formed on the first region I can be referred to as a cell gate pattern. At least a portion of the sacrificial layers of the molded structure 140 formed on the second region II can be replaced with gate pattern 250.

[0106] In the example embodiment, at least a portion of the sacrificial patterns included in the first step structure S1 and the second step structure S2 are replaced with the gate pattern 250, and the first step structure and the second step structure replaced with the gate pattern 250 can also be referred to as the first step structure S1 and the second step structure S2, respectively.

[0107] Furthermore, at least a portion of the first sacrificial pattern included in the upper step structure 290 can be replaced with the gate pattern 250, and the upper step structure 290 replaced with the gate pattern 250 can be referred to as the first upper step structure 290a. At least a portion of the third sacrificial pattern included in the dummy step structure 300 can be replaced with the gate pattern 250, and the dummy step structure 300 replaced with the gate pattern 250 can be referred to as the first dummy step structure 300a.

[0108] The sacrificial layer exposed by the sidewalls of trench 240 can be removed to form gap 242. Therefore, the position of gap 242 can be controlled by the position of trench 240. For example, the position of the gate pattern 250 in the molded structure and the position of the non-gate pattern can be controlled by the position of gap 242.

[0109] In an example embodiment, the molded structure 140 may be spaced apart from other molded structures by trenches 240, thus the spaced-apart molded structures 140 may extend along a first direction. In this case, the portion of the molded structure 140 that forms steps in the first and second directions may be replaced with a gate pattern 250, and this portion may be used as a pad. The sacrificial layer of the steps connected in the horizontal direction to the first step structure S1 and the second step structure S2 may be replaced with the gate pattern 250. In an example embodiment, a portion of the molded structure is not replaced with a gate pattern, and at least the steps of the molded structure 140 in the first and second directions are replaced with a gate pattern. Figure 24 As shown, trench 240 can be formed at opposite ends of the molded structure 140 in the second direction, and only the sacrificial layer positioned at a predetermined distance from trench 240 in the second direction can be removed. Therefore, the sacrificial layer and insulating layer can remain at the central portion of the molded structure 140 in the second direction. Additionally, the portion where gaps are formed can be replaced with gate pattern 250, so only this portion can be used as a pad. The portion not replaced with gate pattern can retain a structure comprising alternately stacked sacrificial and insulating layers, thus this portion can be used as an insulating structure 330. The insulating structure 330 can extend along the central portion A of the molded structure 140 in the second direction in the first direction.

[0110] In the example embodiment, the sacrificial layer located directly below the central portion A' of the flat surface portion Y of the molded structure 140 in the second direction and the third sacrificial pattern located on the flat surface portion Y may not be replaced with a gate pattern. Figure 25 As shown, a groove 240 can be formed at opposite ends of the molded structure 140 in the second direction, and an additional groove 240a can be further formed in the portion of the molded structure 140 between the steps in the first and second directions. However, the additional groove 240a may not be formed on the flat surface portion. Figure 25 In this process, the sacrificial layer located directly below the flat surface portion Y can be etched from the trenches 240 formed at both ends of the molded structure 140 in the second direction, so that the sacrificial layer and the insulating layer can be retained at the central portion A' of the flat surface portion Y of the molded structure 140 in the second direction. On the other hand, the sacrificial layer corresponding to the step portion can be completely removed from the trenches 240 and the additional trenches 240a located at both ends of the molded structure 140 in the second direction. Therefore, the step portion can be replaced with the gate pattern 250, so that the step portion can be used as a pad. The portion that is not replaced with the gate pattern can retain the structure including the alternately stacked sacrificial layer and the insulating layer, so that the portion can be used as the insulating structure 330.

[0111] Therefore, the remaining sacrificial layer and the third sacrificial pattern located below the flat surface portion Y can be used as the insulating structure 330 (see [link]). Figure 27 In an example embodiment, the insulating structure 330 located below the flat surface portion Y can be used as a portion for forming a through-path contact for electrical connection to peripheral circuitry. The insulating structure 330 may include vertically stacked insulating layers without gate patterns therebetween (e.g., a stack of alternating sacrificial and insulating layers).

[0112] In the first dummy step structure 300a, the portion replaced by the gate pattern 250 may not be electrically connected to the cell gate pattern, and therefore, this portion may not be used as a pad. Thus, this portion can be used as a dummy pad.

[0113] In some example embodiments, all sacrificial layers included in the molding structure 140 of the first region I and the second region II can be replaced with gate patterns 250, respectively. In this case, an insulating structure may not be formed below the flat surface portion Y, and therefore, through-path contacts electrically connected to peripheral circuitry may not be formed on the flat surface portion.

[0114] Although not shown, impurities can be injected into the upper portion of the substrate pattern 100 exposed by the trench 240 to form an impurity region. Spacers can be formed to cover the sidewalls of the trench 240. A common source line can be formed on the impurity region and can fill the trench 240.

[0115] Reference Figure 26 and Figure 27 A first contact plug 310 can be formed on the upper surface of the conductive pattern to pass through the second insulating intermediate layer 202.

[0116] Second to fourth contact bolts 312, 314 and 316 can be formed on the upper surface of the steps in the first step structure S1 and the second step structure S2 to pass through the first insulating intermediate layer 200 and the second insulating intermediate layer 202.

[0117] Each second contact pin 312 can contact the upper surface of the gate pattern 250 in the upper stepped structure, and each third contact pin 314 can contact the upper surface of the gate pattern in the first stepped structure S1. Each fourth contact pin 316 can contact the upper surface of the gate pattern 250 in the second stepped structure S2.

[0118] The through-path contact 318 can be formed to pass through the first insulating intermediate layer 200, the second insulating intermediate layer 202, the insulating structure, the insulating pattern, and the second lower insulating intermediate layer 730, and the through-path contact 318 can contact the upper surface of the third lower wiring 720.

[0119] Figure 27It is a cross-sectional view of the first dummy stepped structure cut along the second direction.

[0120] like Figure 27 As shown, in the example embodiment, the through-path contact 318 may pass through the insulating structure 330 beneath the flat surface portion Y. Therefore, the through-path contact 318 may be electrically insulated from the gate pattern 250. As described above, the insulating structure 330 may be a portion of a molded structure that is not replaced by the gate pattern 250. Therefore, the insulating structure 330 may include alternately stacked sacrificial and insulating layers. The gate pattern 250, comprising conductive material, may not be disposed beneath part or all of the flat surface portion Y (e.g., at least not in the region directly surrounding the through-path contact 318).

[0121] Reference Figure 28 and Figure 29 A third insulating intermediate layer 340 may be formed on the second insulating intermediate layer 202, the first to fourth contact plugs 310, 312, 314 and 316, and the through-path contact 318. A bit line 342 may be formed through the third insulating intermediate layer 340, and the bit line 342 may contact the upper surface of the first contact plug 310. In an example embodiment, the bit line 342 may extend along a second direction, and multiple bit lines 342 may be arranged along a first direction.

[0122] Upper wiring 344 can be formed on the second to fourth contact pins 312, 314, and 316 and the through-path contact 318, respectively. Upper wiring 344 can be electrically connected to the second to fourth contact pins 312, 314, and 316 and the through-path contact 318, respectively. Upper wiring 344 can be formed at the same horizontal height as the bit line 342. Alternatively, upper wiring 344 may not be formed at the same horizontal height as the bit line 342.

[0123] To avoid the complexity of the accompanying drawings, Figure 29 In the diagram, the third contact bolt, the fourth contact bolt, the upper wiring, and a portion of the through-path contact are briefly shown as lines.

[0124] For example, such as Figure 29 As shown, the third contact pin 314, which contacts the gate pattern 250 at the same level, can be electrically connected to the upper wiring 344. Additionally, the upper wiring 344 can extend to a portion above the insulating structure 330. The upper wiring 344 and the through-path contact 318 can be electrically connected to each other. The through-path contact 318 can pass through the insulating structure 330 and can extend to the third lower wiring 720 (see...). Figure 2 The through-path contact 318 can be electrically connected to the third lower wiring 720. Therefore, the gate pattern 250, which is electrically connected to the third contact pin 314, can be electrically connected to the peripheral circuitry.

[0125] Furthermore, a fourth contact pin 316, contacting the gate pattern 250 at the same level, can be electrically connected to the upper wiring 344. Additionally, the upper wiring 344 can extend to the portion above the insulating structure 330. The upper wiring 344 and the through-path contact 318 can be electrically connected to each other. The through-path contact 318 can pass through the insulating structure 330 and can extend to the third lower wiring 720 (see...). Figure 2 The through-path contact 318 can be electrically connected to the third lower wiring 720. Therefore, the gate pattern 250, which is electrically connected to the fourth contact pin 316, can be electrically connected to the peripheral circuitry.

[0126] Vertical storage devices can be manufactured using the processes described above.

[0127] On the other hand, vertical storage devices can have the following structural features. These structural features can be mainly described in the process used to manufacture vertical storage devices. Therefore, in the following text, repeated descriptions can be omitted, and only key components can be described with reference to the accompanying drawings.

[0128] Reference Figures 26 to 29 The vertical memory device may include a stacked structure in which an insulating layer 110 and a gate pattern 250 are stacked vertically in a vertical direction. The stacked structure may extend along a first direction from a first region I of the substrate 600 to a second region II.

[0129] The channel structure 230 can be formed as a stacked structure passing through the first region I of the substrate 600.

[0130] The stacked structure on the second region II of the substrate 600 can be used as a pad structure. That is, each gate pattern 250 stacked in the vertical direction can have a stepped shape at the edge of the stacked structure in the first direction. Therefore, the upper surface of the gate pattern 250 can be exposed at the edge of the stacked structure in the first direction. The exposed upper surface of the gate pattern 250 can be used as a pad.

[0131] The pad structure may include a first upper step structure 290a, a first step structure S1, a second step structure S2, and a first dummy step structure 300a.

[0132] The first upper step structure 290a can be formed by replacing the first sacrificial pattern with a gate pattern, and the first upper step structure 290a can be located at the uppermost part of the pad structure. The first upper step structure 290a can have multiple steps in the first direction. For example, the first upper step structure 290a can include four levels of steps in the first direction.

[0133] The first step structure S1 can be formed by replacing the fifth sacrificial pattern 124a with a gate pattern, and a large portion of the first step structure S1 can be formed below the first upper step structure 290a. The first step structure S1 may include multiple steps in each of the first and second directions. For example, the first step structure S1 may include five or six steps in the first direction and four steps in the second direction. The steps included in the first step structure S1 may be symmetrical about a line extending along the first direction. As can be seen from the drawings and this specification, relative terms such as “above” and “below” used herein have their general meaning; for example, element A may be located above element B even if there is no overlap between them when viewed from above (just as an object in the air is generally located above an object on the ground, even if it is not directly above it).

[0134] The second step structure S2 can be formed by replacing the sixth sacrificial pattern 128a with a gate pattern, and a large portion of the second step structure S2 can be formed below the first step structure S1. The second step structure S2 can be spaced apart from the first step structure S1 in a first direction. The second step structure S2 can include multiple steps in each of the first and second directions. For example, the second step structure S2 can include five levels of steps in the first direction and four levels of steps in the second direction. The steps included in the second step structure S2 can be symmetrical about a line extending along the first direction.

[0135] In an example embodiment, the second step structure may include steps with the same shape as the steps of the first step structure.

[0136] The steps included in each of the first step structure S1 and the second step structure S2 can be used as pads for connection to the cell gate pattern formed in the first region. Contact pins can respectively contact the upper surface of the step.

[0137] The flat surface portion Y can be formed between the first stepped structure S1 and the second stepped structure S2. The flat surface portion Y can extend from the lower end of the first stepped structure S1 along a first direction.

[0138] In an example embodiment, the through-path contact 318 may be formed at the flat surface portion Y, such that the flat surface portion Y may have a sufficient width for forming the through-path contact 318. In an example embodiment, the width of the flat surface portion Y in the first direction may be approximately 15 μm to 40 μm. Terms such as “approximately” or “about” can reflect amounts, dimensions, orientations, or layouts that vary only in a relatively small manner and / or in a manner that does not significantly alter the operation, function, or structure of certain elements. For example, the range “approximately 0.1 to approximately 1” can encompass ranges such as deviations of 0% to 2% near 0.1 and deviations of 0% to 2% near 1, especially when such deviations maintain the same effect as the listed ranges.

[0139] The first dummy stepped structure 300a can be formed on the flat surface portion Y.

[0140] The first dummy step structure 300a may have the shape of a line extending in a direction parallel to the boundary of the first region I. For example, the first dummy step structure 300a may extend in a second direction.

[0141] The first dummy step structure 300a can be formed by replacing at least a portion of the third sacrificial pattern 126 with the gate pattern 250. Therefore, the first dummy step structure 300a may have steps at both edges in the first direction. The first dummy step structure 300a may include steps in the first direction but may not include steps in the second direction. The first dummy step structure 300a may have steps only in the direction perpendicular to the boundary of the first region. Additionally, the two sidewalls of the first dummy step structure 300a in the second direction may be perpendicular to the upper surface of the substrate. For example, the first dummy step structure 300a may extend to the opposite outermost ends of the pad structure in the second direction. In an example embodiment, the number of steps in the first direction of the first dummy step structure 300a may be equal to the number of steps in the first direction of the lowermost portion of the first step structure S1. Furthermore, the number of steps in the first direction of the first dummy step structure 300a may be equal to the number of steps in the first direction of the uppermost portion of the second step structure S2. In addition, the first dummy step structure 300a may have the same bottom-to-top height as the top part of the second step structure S2, and may have a bottom surface and a top surface that are coplanar with the corresponding bottom surface and top surface of the top part of the second step structure S2.

[0142] Therefore, the height of the first dummy step structure 300a (e.g., from top to bottom) can be lower than the height of the first step structure S1 (e.g., from top to bottom). The height of the upper surface of the first dummy step structure 300a can be substantially the same as the height of the upper surface of the lowermost step that is configured to contact the vertical sidewall of the lowermost part of the first step structure S1. Furthermore, the height of the uppermost surface of the first dummy step structure 300a can be substantially the same as the height of the uppermost step that is configured to contact the vertical sidewall of the uppermost part of the second step structure S2.

[0143] In an example embodiment, the lowermost step of the first step structure S1 in the first direction and the opposite step of the dummy step structure may be symmetrical to each other. Similarly, the uppermost step of the second step structure S2 in the first direction and the opposite step of the dummy step structure may be symmetrical to each other. In some embodiments, the dummy step structure does not include any layer for electrical connection to any through-path contact 318 passing through it, and / or is not electrically connected to any lines such as word lines for electrical connection within a vertical storage device.

[0144] In the example embodiment, refer to Figure 17 and Figure 29 In the first direction, the width (f) between the lower end of the first dummy step structure 300a and the first step structure S1, the width (c1) of each step of the first dummy step structure 300a, the width (c2) of the upper surface of the first dummy step structure 300a, and the width (g) between the upper end of the first dummy step structure 300a and the second step structure S3 can all be in the range of 0.1 μm to 10 μm. For example, the width (f) between the lower end of the first dummy step structure 300a and the first step structure S1, the width (c1) of each step of the first dummy step structure 300a, the width (c2) of the upper surface of the first dummy step structure 300a, and the width (g) between the upper end of the first dummy step structure 300a and the second step structure S3 can all be in the range of 0.1 μm to 8 μm.

[0145] In an example embodiment, the first dummy step structure 300a may include portions not replaced with the gate pattern. For example, a portion of the sacrificial layer below the flat surface portion Y and a portion of the third sacrificial pattern on the flat surface portion Y may not be replaced with the gate pattern. Therefore, the portion of the sacrificial layer below the flat surface and the portion of the third sacrificial pattern on the flat surface portion Y can be used as the insulating structure 330.

[0146] In an example embodiment, a through-path contact 318 may be formed through the insulating structure 330, and the through-path contact 318 may be electrically connected to an external circuit. Contact pins 312, 314, and 316 may extend in a vertical direction, and contact pins 312, 314, and 316 may respectively contact the upper surface of the pads included in the first upper stepped structure 290a, the first stepped structure S1, and the second stepped structure S2.

[0147] In some example embodiments, the first step structure S1, the second step structure S2, and the first dummy step structure 300a may each include portions not replaced with the gate pattern. For example, apart from the stepped portions on both sides of the first step structure S1 and the second step structure S2 in the second direction, other portions of each of the first step structure S1 and the second step structure S2 may not be replaced with the gate pattern. Therefore, the insulating structure 330 may extend along the central portion A of the first step structure S1 and the second step structure S2 in the second direction in the first direction.

[0148] In an example embodiment, a through-path contact 318 may be formed through the insulating structure 330, and the through-path contact 318 may be electrically connected to an external circuit.

[0149] In some example embodiments, the sacrificial layer and sacrificial pattern in the molded structure can all be replaced with the gate pattern. Therefore, the sacrificial layer and sacrificial pattern of the first step structure S1, the second step structure S2, and the first dummy step structure 300a can all be replaced with the gate pattern.

[0150] Different terms can be used to refer to specific parts of each stepped structure to indicate which parts are being discussed. For example, the term "platform" used to describe a surface can be used to refer to the topmost surface of a structure that protrudes from the lower surface (e.g., the topmost surface of the dummy stepped structure 300a, the topmost surface of the second stepped structure S2, or the topmost surface of the first stepped structure S1). The term "base plate" can be used to refer to a flat platform below the platform. Furthermore, a particular structure can be described as having a platform structure. The bottom layer of a platform structure can refer to the layer adjacent to but above the base plate.

[0151] Vertical storage devices may include a first dummy step structure located on a flat surface portion of the pad structure, thereby enabling precise measurement of the width of the flat surface portion. Therefore, the width of the pad structure can be accurately measured, and failures in vertical storage devices can be reduced.

[0152] Figures 30 to 37 This is a cross-sectional view, a top view, and a perspective view illustrating a method for manufacturing a vertical storage device according to an example embodiment. Specifically, Figure 30 , Figures 32 to 35It is a perspective view. Figure 31 and Figure 36 It is a top view. Figure 37 It is a cross-sectional view.

[0153] Figure 31 and Figure 36 yes Figure 1 A top view of region X. Figure 30 and Figures 32 to 35 yes Figure 1 A perspective view of region X. Figure 37 It is along Figure 1 The cross-sectional view taken by line C-C' in the diagram.

[0154] Methods for manufacturing vertical storage devices include those referenced. Figures 1 to 29 The processes described are substantially the same or similar. Therefore, their detailed descriptions will be omitted.

[0155] Reference Figure 30 and Figure 31 First, execution and reference. Figures 1 to 4 The processes shown are essentially the same or similar.

[0156] Subsequently, second to fifth photoresist patterns 142, 144, 146a, and 148 can be formed on the first sacrificial pattern 122 and the exposed sacrificial layer 120 at the second level. The second photoresist pattern 142, the third photoresist pattern 144, and the fifth photoresist pattern 148 can be respectively aligned with a reference... Figure 5 The second photoresist pattern 142, the third photoresist pattern 144, and the fifth photoresist pattern 148 described are the same.

[0157] A fourth photoresist pattern 146a may be formed on a flat surface portion between the third photoresist pattern 144 and the fifth photoresist pattern 148, and the fourth photoresist pattern 146a may be spaced apart from each of the third photoresist pattern 144 and the fifth photoresist pattern 148 in a first direction. In a top view, the fourth photoresist pattern 146a may have a quadrilateral shape. The fourth photoresist pattern 146a may be located at the portion used to form the dummy stepped structure.

[0158] Although not shown in the perspective view, as Figure 31 As shown, the third to fifth photoresist patterns 144, 146a and 148 may have trapezoidal shapes instead of rectangular shapes. However, in each perspective view, to avoid the complexity of the figures, the third to fifth photoresist patterns 144, 146a and 148 are shown as having the same rectangular shape.

[0159] The exposed sacrificial layer 120 can be etched using the second to fifth photoresist patterns 142, 144, 146a, and 148 as etching masks. For example, the sacrificial layer 120 at the second level can be etched using an etching process.

[0160] The first sacrificial pattern 122 can be further formed by an etching process; therefore, the first sacrificial pattern 122 may include two layers. Additionally, the second sacrificial pattern 124 may be spaced apart from the first sacrificial pattern 122 in a first direction and may have a quadrilateral shape in a top view. The fourth sacrificial pattern 128 may be spaced apart from the second sacrificial pattern 124 in the first direction and may also have a quadrilateral shape in a top view. A third sacrificial pattern may be formed between the second sacrificial pattern 124 and the fourth sacrificial pattern 128, and the third sacrificial pattern may be spaced apart from each of the second and fourth sacrificial patterns 124 in the first direction. The third sacrificial pattern may also have a quadrilateral shape in a top view.

[0161] Reference Figure 32 It can be executed and referenced. Figure 8 and Figure 9 The processes shown are substantially the same or similar to those used to form initial first to fourth sacrificial patterns 122, 124, 326, and 128 on the sacrificial layer at the fifth level. Initial first sacrificial pattern 122, initial second sacrificial pattern 124, and initial fourth sacrificial pattern 128 can be respectively compared with reference to... Figure 9 The initial first sacrifice pattern 122, initial second sacrifice pattern 124, and initial fourth sacrifice pattern 128 shown are identical. Additionally, the third initial sacrifice pattern 326 may have steps in each of the first and second directions.

[0162] Reference Figure 33 and Figure 34 It can be executed and referenced. Figures 10 to 12 The processes shown are essentially the same or similar.

[0163] In an example embodiment, an etching process using the sixth photoresist pattern 152 can be performed, followed by repeated trimming and etching processes to form a shape such as Figure 34 The first step structure S1 is shown. The third sacrificial pattern 326 may be spaced apart from the first step structure S1 in the first direction. The third sacrificial pattern 326 may be formed between the first step structure S1 and the fourth sacrificial pattern 128. The stacked structure of the third sacrificial pattern 326 may be referred to as the dummy step structure 302.

[0164] Reference Figure 35 and Figure 36 It can be executed and referenced. Figures 13 to 17The processes shown are essentially the same or similar.

[0165] In an example embodiment, an etching process using a seventh photoresist pattern can be performed, followed by repeated trimming and etching processes to form a shape such as Figure 35 The molded structure shown includes the second step structure S2.

[0166] As shown, a flat surface portion Y with a relatively wide width can be disposed between the first stepped structure S1 and the second stepped structure S2. A dummy stepped structure 302 can be formed on the flat surface portion Y, and the dummy stepped structure 302 can be spaced apart from each of the first stepped structure S1 and the second stepped structure S2.

[0167] After the molded structure 140 is formed, a precise measurement of the width of the molded structure 140 in the first direction can be performed.

[0168] For example, such as Figure 36 As shown, the widths (a to h) of the distinguishable patterns (e.g., steps and platforms) in the molding structure 140 in the first direction can be measured separately, and the widths measured in the first direction can be added together to determine the width of the entire molding structure 140 in the first direction.

[0169] To measure the width of the flat surface portion Y, the width (f) between the lower end of the dummy step structure 302 and the first step structure S1, the width (c1) of the step in the third sacrificial pattern 326, the width (c2) of the uppermost surface of the third sacrificial pattern 326 in the first direction, and the width (g) between the upper end of the dummy step structure 302 and the second step structure S2 can be measured respectively.

[0170] After that, it can be executed and referenced. Figures 18 to 29 The illustrated process is essentially the same or similar to that used to manufacture vertical memory devices. Except for the shape of the dummy stepped structure, the vertical memory device can be compared with the reference... Figures 26 to 29 The vertical storage devices shown are essentially the same.

[0171] For example, such as Figure 26 and Figure 28 As shown, the sacrificial layer included in the molding structure 140 on the first region I and the second region II can be replaced with the gate pattern 250. Therefore, the vertical memory device can include an upper stepped structure, a first stepped structure, a second stepped structure, and a first dummy stepped structure 300a located between the first stepped structure and the second stepped structure. The first dummy stepped structure 300a may have steps in each of the first and second directions.

[0172] Specifically, the cross-sectional view of the vertical storage device cut along the first direction can be compared with... Figure 28 They are essentially the same. However, the cross-sectional view of the first dummy stepped structure cut along the second direction can differ. Figure 27 .

[0173] like Figure 37 As shown, the first dummy step structure 300a may have a step in the second direction.

[0174] The sacrificial layer located below the central portion A' of the flat surface portion Y of the molded structure 140 in the second direction, and the third sacrificial pattern located on the flat surface portion Y, may not be replaced with a gate pattern. Therefore, the sacrificial layer and the third sacrificial pattern not replaced with a gate pattern below the flat surface portion Y can serve as the insulating structure 330. In an example embodiment, a through-path contact 318 may be formed through the insulating structure 330 below the flat surface portion Y, and the through-path contact 318 may be electrically connected to peripheral circuitry.

[0175] Figures 38 to 46 These are top views, cross-sectional views, and perspective views illustrating a method for manufacturing a vertical storage device according to an example embodiment. Specifically, Figure 39 and Figure 44 It is a top view. Figure 43 , Figure 45 and Figure 46 It is a cross-sectional view. Figure 38 and Figures 40 to 42 It is a perspective view.

[0176] Figure 39 and Figure 44 yes Figure 1 A top view of region X. Figure 38 and Figures 40 to 42 yes Figure 1 A perspective view of region X. Figure 45 It is along Figure 1 A cross-sectional view taken from line A-A'. Figure 46 It is along Figure 1 The cross-sectional view taken from line C-C'. Figure 43 Is Figure 1 A cross-sectional view taken along the first direction in region X.

[0177] Methods for manufacturing vertical storage devices may include those referencing Figures 1 to 29 The processes shown are substantially the same or similar, therefore their detailed descriptions can be omitted.

[0178] Reference Figure 38 and Figure 39 First, it can be executed and referenced. Figures 1 to 4 The processes shown are essentially the same or similar.

[0179] Subsequently, second to fourth photoresist patterns 142, 144a, and 148a can be formed on the first sacrificial pattern 122 and the exposed sacrificial layer 120 at the second level. The second photoresist pattern 142 can be compared with a reference... Figure 5 The second photoresist pattern 142 shown is identical. As stated above, unless the context otherwise indicates, terms such as “second,” “third,” and “fourth” are used only as naming conventions, and names such as “first” used to indicate items in the claims may refer to any such item in the specification and are not necessarily consistent with items named “first” in the specification.

[0180] The third photoresist pattern 144a may be spaced apart from the second photoresist pattern 142 in a first direction. In a top view, the third photoresist pattern 144a may have a quadrilateral shape. The third photoresist pattern 144a may cover the portion used to form the first stepped structure and may partially cover the portion used to form the flat surface portion.

[0181] The fourth photoresist pattern 148a can be formed to be spaced apart from the third photoresist pattern 144a in a first direction. In a top view, the fourth photoresist pattern 148a can have a quadrilateral shape. The fourth photoresist pattern 148a can cover the portion used to form the second stepped structure and can partially cover the portion used to form the flat surface portion.

[0182] The third photoresist pattern 144a and the fourth photoresist pattern 148a can each extend into a portion of the flat surface portion. Additionally, the portion between the third photoresist pattern 144a and the fourth photoresist pattern 148a can be located on the flat surface portion.

[0183] Although not shown in the perspective view, as Figure 39 As shown, the third photoresist pattern 144a and the fourth photoresist pattern 148a can have a trapezoidal shape instead of a completely rectangular shape.

[0184] The exposed sacrificial layer 120 can be etched using the second to fourth photoresist patterns 142, 144a, and 148a as etching masks. In this way, the sacrificial layer 120 at the second level can be etched by an etching process.

[0185] Therefore, a first sacrificial pattern 122 can be further formed at the second layer, thus the first sacrificial pattern can include two layers. Additionally, a second sacrificial pattern 324 can be formed to be spaced apart from the first sacrificial pattern 122 in a first direction and can have a quadrilateral shape in a top view. A third sacrificial pattern 328 can be formed to be spaced apart from the second sacrificial pattern 324 in a first direction and can also have a quadrilateral shape in a top view.

[0186] Reference Figure 40 It can be executed and referenced. Figure 8 and Figure 9 The processes shown are substantially the same or similar. Therefore, the initial first to initial third sacrificial patterns 122, 324 and 328 can be formed on the sacrificial layer at the fifth level.

[0187] Reference Figure 41 It can be executed and referenced. Figures 10 to 12 The processes shown are essentially the same or similar.

[0188] In an example embodiment, an etching process using the sixth photoresist pattern 152 can be performed, followed by repeated trimming and etching processes to form a shape such as Figure 41 The first step structure S1 is shown. The first step structure S1 may include stacked fourth sacrificial patterns 324a.

[0189] The portion of the first stepped structure S1 formed on a flat surface (e.g., a base plate) can be referred to as the lowermost pattern 325a. The upper surface of the lowermost pattern can contact the lowermost vertical sidewall portion of the first stepped structure S1. The upper surface of the lowermost pattern 325a can extend along a first direction. The first stepped structure S1 can extend to the flat surface portion. The third sacrificial pattern 328 can be formed to be spaced apart from the first stepped structure S1.

[0190] Reference Figures 42 to 44 It can be executed and referenced. Figures 13 to 17 The processes shown are essentially the same or similar.

[0191] In an example embodiment, an etching process using a seventh photoresist pattern can be performed, followed by repeated trimming and etching processes to form a shape such as Figure 42 The molded structure shown includes a second step structure S2. The second step structure S2 may include stacked fifth sacrificial patterns 328a.

[0192] The portion of the second step structure S2 formed on the flat surface portion is referred to as the uppermost pattern 325b, which may have a platform shape with a pedestal at the top. The upper surface of the uppermost pattern 325b (e.g., the pedestal) may contact the uppermost vertical sidewall portion of the second step structure S2. As described herein, a vertical sidewall extending along the same plane to include at least two sacrificial layers (later replaced by gate patterns) is referred to as an extended vertical sidewall. A single sidewall of a step comprising only one sacrificial layer (later replaced by a gate pattern) may be referred to as a step sidewall. Additionally, the top surface of the step may be referred to as a step top surface. The upper surface of the uppermost pattern 325b of the second step structure S2 may extend in a first direction. That is, the second step structure S2 may extend to the flat surface portion.

[0193] As shown, the lowermost pattern 325a of the first stepped structure S1 and the uppermost pattern 325b of the second stepped structure S2 can be respectively disposed on the flat surface portion (e.g., the base plate). Therefore, the lowermost pattern 325a and the uppermost pattern 325b can be used as distinguishable patterns for accurately measuring the flat surface portion of the molded structure.

[0194] In an example embodiment, in the first direction, the width of the upper surface of the lowermost pattern 325a of the first stepped structure S1 and the width of the uppermost pattern 325b of the second stepped structure S2 can be substantially the same as each other.

[0195] In some example embodiments, the width of the upper surface of the lowermost pattern 325a of the first stepped structure S1 and the width of the uppermost pattern 325b of the second stepped structure S2 may be different from each other.

[0196] like Figure 44 As shown, the widths a, b, c1, c, c2, d, e, and h of the distinguishable patterns (e.g., steps) in the molding structure 140 in the first direction can be measured separately, and the widths measured in the first direction can be added together to determine the width of the entire molding structure 140 in the first direction.

[0197] For example, in order to measure the width of the flat surface portion, the width c1 of the step of the lowest pattern of the first stepped structure S1 in the first direction, the width c2 of the step of the uppermost pattern of the second stepped structure S2 in the first direction, and the width c of the portion between the first stepped structure S1 and the second stepped structure S2 in the first direction can be measured respectively.

[0198] After that, it can be executed and referenced. Figures 18 to 29 The processes shown are substantially the same or similar to those used to manufacture vertical storage devices.

[0199] like Figure 45 and Figure 46 As shown, the vertical storage device may include a first upper step structure 290a, a first step structure S1, and a second step structure S2.

[0200] Vertical storage devices may not have a dummy step structure. However, the lowermost pattern 325a of the first step structure and the uppermost pattern 325b of the second step structure can be used as distinguishable patterns for measuring the flat surface portion of the molded structure in the same manner as the dummy step structure.

[0201] like Figure 46 As shown, a through-path contact 318 can be formed through the sacrificial layer that is not replaced by the gate pattern 250, and the through-path contact 318 can be electrically connected to peripheral circuitry. Therefore, the through-path contact 318 can pass through the valley created by the gate pattern 250 in the vertical memory device.

[0202] Figures 47 to 52 These are top and perspective views of a method for manufacturing a vertical storage device according to an exemplary embodiment. Specifically, Figure 48 It is a top view. Figure 47 , Figures 49 to 52 It is a perspective view.

[0203] Figure 48 yes Figure 1 A top view of region X. Figure 47 and Figures 49 to 52 yes Figure 1 A perspective view of region X.

[0204] Because the methods for manufacturing vertical storage devices include those referenced Figures 1 to 29 The processes shown are essentially the same or similar, so their detailed descriptions can be omitted.

[0205] Reference Figure 47 and Figure 48 First, execution and reference. Figures 1 to 4 The processes shown are essentially the same or similar.

[0206] Subsequently, a second photoresist pattern 142 and a third photoresist pattern 144b can be formed on the first sacrificial pattern 122 and the exposed sacrificial layer 120 at the second level, respectively. The second photoresist pattern 142 can be compared with a reference... Figure 5 The second photoresist pattern 142 shown is essentially the same.

[0207] The third photoresist pattern 144b can be formed to be spaced apart from the second photoresist pattern 142 in a first direction. In a top view, the third photoresist pattern 144b can have a quadrilateral shape. The third photoresist pattern 144b can cover the portions used to form the first stepped structure, the flat surface portion, and the second stepped structure.

[0208] Although not shown in the perspective view, as Figure 48 As shown, the third photoresist pattern 144b can have a trapezoidal shape instead of a rectangular shape.

[0209] The exposed sacrificial layer 120 can be etched using the second photoresist pattern 142 and the third photoresist pattern 144b as etching masks. Therefore, the sacrificial layer 120 at the second level can be etched by an etching process.

[0210] Therefore, a first sacrificial pattern 122 can be further formed, and thus, the first sacrificial pattern can include two layers. In addition, a second sacrificial pattern 160 can be formed to be spaced apart from the first sacrificial pattern 122 in a first direction, and in a top view, the second sacrificial pattern 160 can have a quadrilateral shape.

[0211] Reference Figure 49 First, it can be executed and referenced. Figure 8 and Figure 9 The processes shown are substantially the same or similar to those used to form an initial first sacrificial pattern and an initial second sacrificial pattern on a sacrificial layer at the fifth level.

[0212] After that, it can be executed and referenced. Figures 10 to 12 The processes shown are essentially the same or similar.

[0213] In an example embodiment, an etching process using the sixth photoresist pattern 152 can be performed, followed by repeated trimming and etching processes to form a shape such as Figure 49 The first step structure shown.

[0214] Then, it can be executed and referenced. Figures 13 to 17 The processes shown are essentially the same or similar.

[0215] In an example embodiment, an etching process using a seventh photoresist pattern can be performed, followed by repeated trimming and etching processes to form a shape such as Figure 49 The second-step structure shown.

[0216] When the process is performed, a flat surface portion can be formed from the first stepped structure S1 to the second stepped structure S2. In this case, it is not necessary to form a raised pattern on the flat surface portion.

[0217] Reference Figure 50 The flat surface portion between the first stepped structure S1 and the second stepped structure S2 can be partially etched to form a groove 300b on the flat surface portion.

[0218] In the example embodiment, in a top view, the groove 300b may have a quadrilateral shape. Additionally, the sidewalls of the groove 300b in the first and second directions may each have a stepped shape.

[0219] Specifically, a photoresist pattern can be formed that exposes only a portion of the flat surface, and the photoresist pattern can be used to partially etch a sacrificial layer corresponding to the flat surface portion. A trimming process for the photoresist pattern and an etching process can be performed to form steps at the sidewalls of the groove 300b in the first and second directions.

[0220] In some example embodiments, such as Figure 51 As shown, the groove 300c can extend along a first direction in the top view. Therefore, the upper portions of the flat surface portions can be spaced apart by the groove 300c. Furthermore, the sidewalls of the groove 300c in the first direction can have a stepped shape. In this way, a valley can be formed.

[0221] The above process can be used to form a molded structure 140.

[0222] On the other hand, after the molding structure 140 is formed, a precise measurement of the width of the molding structure 140 in the first direction can be performed. During the measurement process, the width of the distinguishable patterns (e.g., steps) in the molding structure 140 in the first direction can be measured separately, and the widths measured in the first direction can be added together to determine the width of the entire molding structure 140 in the first direction.

[0223] like Figure 50 or Figure 51 As shown, grooves 300b and 300c can be formed on the flat surface portion, and the sidewalls of the grooves in the first direction can have steps. Therefore, in order to measure the width of the flat surface portion, the width between the lower end of the first stepped structure S1 and the groove, the width of the step of the groove, the width of the bottom of the groove, and the width between the upper end of the second stepped structure and the groove can be measured respectively. In addition, the measured widths can be added together to determine the width of the entire molded structure 140 in the first direction.

[0224] In some example embodiments, such as Figure 52 As shown, the sidewalls of the groove 300d may not have steps. As an example, in the top view, the groove 300d may have a quadrilateral shape. For example, although not shown, the groove may extend along a first direction in the top view, so that the upper portions of the flat surface portions may be spaced apart by the groove.

[0225] When the sidewall of the groove 300d does not have a stepped shape, in order to measure the width of the flat surface portion, the width between the lower end of the first stepped structure S1 and the groove, the width of the bottom of the groove 300d, and the width between the upper end of the second stepped structure S2 and the groove 300d can be measured respectively.

[0226] After that, it can be executed and referenced. Figures 18 to 29 The processes shown are substantially the same or similar to those used to manufacture vertical storage devices.

[0227] Similar to Figure 45 and Figure 46 As shown, the vertical storage device may include a first upper stepped structure 290a and a first stepped structure S1 and a second stepped structure S2. Additionally, a groove 300d may be formed on a flat surface portion between the first stepped structure S1 and the second stepped structure S2. The groove 300d can be used as a pattern for measuring the flat surface portion of the molded structure.

[0228] Although not shown, a through-path contact 318 may be formed at the flat surface portion Y of the molded structure 140, passing through the portion of the sacrificial layer that is not replaced with the gate pattern, and the through-path contact 318 may pass through the recess 300d. The through-path contact 318 may be electrically connected to peripheral circuitry.

[0229] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. In the claims, the method-plus-function clause is intended to cover structures described herein as performing the listed functions, and not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting to the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims.

[0230] As used herein, terms such as “identical,” “equal,” “planar,” “coplanar,” “perpendicular,” or “parallel” cover identical or include near-identical properties that may vary due to manufacturing processes. Unless the context or other statement indicates otherwise, the term “substantially” may be used herein to emphasize this meaning.

Claims

1. A vertical semiconductor device comprising: a substrate; a cell array region including memory cells, the cell array region being formed on the substrate; a pad region formed on the substrate, and a contact plug electrically connecting the memory cells being formed in the pad region; gate patterns stacked in a vertical direction perpendicular to an upper surface of the substrate, each of the gate patterns extending in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region, and the gate patterns including pads respectively provided in the pad region and at edge portions of the respective gate patterns in the first direction; insulating layers respectively between gate patterns adjacent in the vertical direction; and a channel structure located in the cell array region and passing through the gate patterns, the channel structure extending in the vertical direction, wherein the gate patterns and the insulating layers located on the pad region function as a pad structure, and the pad structure includes a first step structure having a stepped shape, a second step structure having a stepped shape and provided below the first step structure, a flat surface portion between the first step structure and the second step structure, and a dummy step structure formed on the flat surface portion, the second step structure being spaced apart from the first step structure in the first direction, and wherein side walls of the dummy step structure opposite to each other in the first direction have a stepped shape, and wherein an uppermost surface of the dummy step structure is lower than an uppermost surface of the first step structure.

2. The vertical semiconductor device of claim 1, wherein, At least two opposite side walls of the dummy step structure have a stepped shape.

3. The vertical semiconductor device of claim 1, wherein, The first step structure includes a step in the first direction and a second direction perpendicular to the first direction, and a height of an uppermost surface of the dummy step structure is the same as a height of an upper surface of a lowermost step provided to be in contact with an extended vertical side wall of a lowermost portion of the first step structure.

4. The vertical semiconductor device of claim 1, wherein, The second step structure includes a step in the first direction and a second direction perpendicular to the first direction, and a height of an upper surface of a high step of the dummy step structure is the same as a height of an upper surface of a high step of the second step structure.

5. The vertical semiconductor device of claim 1, wherein, The dummy step structure is spaced apart from each of the first step structure and the second step structure, and the dummy step structure extends to opposite outermost ends of the pad structure in a second direction perpendicular to the first direction.

6. The vertical semiconductor device of claim 5, wherein, Side walls of the dummy step structure opposite to each other in the second direction are perpendicular to the upper surface of the substrate.

7. The vertical semiconductor device of claim 1, wherein, In a plan view of the vertical semiconductor device, the dummy step structure is spaced apart from each of the first step structure and the second step structure, and the dummy step structure has a quadrangular shape.

8. The vertical semiconductor device of claim 1, wherein, The second step structure includes a step having the same shape as a shape of a step of the first step structure.

9. The vertical semiconductor device of claim 1, wherein, A recess is formed on the flat surface portion, and opposite side walls of the recess in the first direction have a stepped shape, wherein the recess functions as the dummy stepped structure.

10. The vertical semiconductor device of claim 1, further comprising: Contact plugs that extend in the vertical direction and respectively contact upper surfaces of the pads of the first stepped structure and the pads of the second stepped structure.

11. The vertical semiconductor device according to claim 1, further comprising a through via contact that passes through the flat surface portion.

12. The vertical semiconductor device of claim 1, wherein, A width of the flat surface portion in the first direction is 15 μm to 40 μm.

13. The vertical semiconductor device of claim 1, wherein, A width in the first direction between the dummy stepped structure and an upper end of the second stepped structure is 0.1 μm to 10 μm.

14. A vertical semiconductor device comprising: a substrate; a cell array region and a pad region formed on the substrate; gate patterns stacked in a vertical direction perpendicular to an upper surface of the substrate, each of the gate patterns extending in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate, and the gate patterns including pads respectively located at edge portions of the gate patterns in the first direction; insulating layers respectively located between gate patterns adjacent in the vertical direction; channel structures located on the cell array region and passing through the gate patterns, the channel structures extending in the vertical direction; and contact plugs that extend in the vertical direction and respectively contact upper surfaces of the pads, wherein the gate patterns and the insulating layers located on the pad region function as a pad structure, and the pad structure includes a first stepped structure having a stepped shape and including the pads, a second stepped structure provided below the first stepped structure, a flat surface portion located between the first stepped structure and the second stepped structure, and a dummy stepped structure formed on the flat surface portion, the second stepped structure having a stepped shape and including the pads, wherein the dummy stepped structure extends to opposite outermost ends of the pad structure in a second direction perpendicular to the first direction, and wherein opposite side walls of the dummy stepped structure in the first direction have a stepped shape, and wherein an uppermost surface of the dummy stepped structure is lower than an uppermost surface of the first stepped structure.

15. The vertical semiconductor device of claim 14, wherein, The first stepped structure includes steps in the first direction and the second direction, and a height of the uppermost surface of the dummy stepped structure is the same as a height of an upper surface of a lowermost step provided in contact with an extended vertical side wall of a lowermost portion of the first stepped structure.

16. The vertical semiconductor device of claim 14, wherein, Opposite side walls of the dummy stepped structure in the second direction are extended vertical side walls perpendicular to the upper surface of the substrate.

17. The vertical semiconductor device of claim 14, further comprising a through- via contact through the planar surface portion.

18. A vertical semiconductor device comprising: a substrate; a cell array region and a pad region formed on the substrate; gate patterns stacked in a vertical direction perpendicular to an upper surface of the substrate, each of the gate patterns extending in a first direction parallel to the upper surface of the substrate on the cell array region and the pad region of the substrate, and the gate patterns including pads respectively located at edge portions of the gate patterns in the first direction; and insulating layers respectively located between gate patterns adjacent in the vertical direction; wherein the gate patterns and the insulating layers located on the pad region function as a pad structure, and the pad structure includes a first step structure having a step shape, a second step structure having a step shape and disposed below the first step structure, a planar surface portion located between the first step structure and the second step structure, and a dummy step structure formed on the planar surface portion, wherein the dummy step structure is spaced apart from each of the first step structure and the second step structure, and wherein sidewalls of the dummy step structure opposite each other in the first direction have a step shape, wherein an uppermost surface of the dummy step structure is lower than an uppermost surface of the first step structure.

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