Semiconductor device

Abstract

The present application provides a semiconductor device that can achieve suppression of reduction in withstand voltage of a super junction semiconductor device having a drift layer as a parallel pn layer, suppression of reduction in avalanche resistance, and low on-resistance. Among layers of an epitaxial layer (43) that forms a first parallel pn layer (5) in multiple layers, the number of layers from the first layer to half or less of the total number of layers is n ‑ In the n-type epitaxial layer (43a), at least one layer or more from the drain side is n ‑ The n-type region (3) and the p-type region (4) of the n-type epitaxial layer (43a) are configured to be asymmetric in the impurity concentration gradient in the first direction X. Thus, the n-type region (3) and the p-type region (4) of the first parallel pn layer (5) that is the active region (10) are configured to be symmetric in the impurity concentration gradient in the first direction X on the source side and asymmetric on the drain side.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Previously, it was known that superjunction (SJ) semiconductor devices were constructed by alternately and repeatedly arranging n-type and p-type regions adjacent to each other in a direction parallel to (laterally) to the main surface of the semiconductor substrate (semiconductor chip), thereby making the drift layer a parallel pn layer. As a method for forming the parallel pn layer of a superjunction semiconductor device, a multilayer epitaxial method is known whereby n-type and p-type regions are formed in each of the multiple epitaxial layers that serve as drift layers, with regions of the same conductivity type facing each other adjacent to each other in the depth direction (longitudinal direction), thereby forming a parallel pn layer.

[0003] Taking the superjunction MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as an example, the structure of existing superjunction semiconductor devices is explained. Figure 20 This is a top view showing the layout of parallel pn layers of an existing superjunction semiconductor device as viewed from the front side of a semiconductor substrate. Figure 21 It is shown Figure 20 A cross-sectional view of the structure at the cutting line AA-AA'. Figure 21 The cross-sectional structure of the parallel pn layer 105 of the active region 110 is shown.

[0004] Figure 20 , Figure 21 The existing superjunction semiconductor device 150 shown has an n-type region 103 and a p-type region 104 arranged alternately and repeatedly adjacent to each other in a first direction X parallel to the main surface of the semiconductor substrate 140, thereby making the drift layer in the active region 110 a superjunction MOSFET of a parallel pn layer 105. The n-type region 103 and the p-type region 104 are strips that are parallel to the main surface of the semiconductor substrate 140 and extend along a second direction Y orthogonal to the first direction. The n-type region 123 and the p-type region 124 of the parallel pn layer 125 are arranged alternately and repeatedly adjacent to each other in the first direction X in the edge termination region 120 in a manner that is the same as the n-type region 103 and the p-type region 104, respectively, thereby forming a parallel pn layer 125.

[0005] Parallel pn layers 105 and 125 are set up via an n-type epitaxial layer 142 that becomes an n-type buffer 102. + n of type leak region 101 +On the front side of the semiconductor substrate 141, parallel pn layers 105 and 125 are adjacent to each other. The n-type region 103 and the p-type region 104 are formed by multiple epitaxial layers (on the side of the parallel pn layers 105) that are stacked together. Figure 21 The epitaxial layers (represented by a single epitaxial layer 143) are formed by ion implantation of n-type and p-type impurities, respectively, so that regions of the same conductivity type are adjacent to each other along the depth direction Z.

[0006] The semiconductor substrate 140 is formed by sequentially depositing an n-type epitaxial layer 142 and an epitaxial layer 143 as parallel pn layers 105 and 125 on the substrate. + An epitaxial substrate on the front side of a type semiconductor substrate 141. In the parallel pn layer 105, and n... + On the opposite side of the leak area 101, there is a [structure / feature] made of p - Type base region 106, n + The source region 107, trench 108, gate insulating film 109, and gate electrode 111 form a typical MOS gate. Symbols 112 to 114 represent the interlayer insulating film, source electrode, and drain electrode, respectively. Symbol 130 is the intermediate region between the active region 110 and the edge termination region 120.

[0007] In the existing superjunction semiconductor device 150, to ensure a predetermined breakdown voltage, the paired and adjacent n-type regions 103 and p-type regions 104 of the parallel pn layers 105 in the active region 110 are charged to achieve a balance, and the epitaxial layers 143, which are multilayered, are symmetrically arranged in the same position and shape. The charge balance is represented by the ratio of the amount of charge expressed as the product of the carrier concentration (impurity concentration) and the width of the n-type region 103 of the parallel pn layer 105, to the amount of charge expressed as the product of the carrier concentration (impurity concentration) and the width of the p-type region 104. During turn-off, the breakdown voltage is ensured by extending the depletion layer from the pn junction of the adjacent p-type regions 104 and n-type regions 103 to the parallel pn layer 105, exceeding the breakdown voltage achievable using the impurity concentration of the drift layer. By increasing the impurity concentration in the drift layer, the on-resistance can be significantly reduced.

[0008] As a conventional superjunction semiconductor device, a device has been proposed that includes a parallel pn layer in the active region to achieve charge balance between the n-type and p-type regions, preventing the field plate and the p-type reduced surface electric field region, which are arranged in a ring around the active region, from contacting (electrically contacting) at the chip corners (for example, see Patent Document 1 below). In Patent Document 1, by preventing the field plate and the p-type reduced surface electric field region from contacting at the chip corners where the equipotential surface distribution is curved, the potential in the relatively flat straight portion of the chip between the chip corners is supplied to the chip corners via the field plate.

[0009] In addition, as another existing superjunction semiconductor device, a device has been proposed in which a temperature sensing region, in which a temperature sensing diode is disposed, and an active region surrounding the temperature sensing region are arranged periodically, with parallel pn layers of the same structure achieving charge balance between the n-type and p-type regions (for example, see Patent Document 2 below). In Patent Document 2 below, by arranging a gate electrode on the n-type region of the parallel pn layer with the same width as the n-type region and a temperature sensing diode made of polysilicon with the same width and thickness as the gate electrode, the collapse of the charge balance between the n-type and p-type regions of the parallel pn layer is suppressed.

[0010] In addition, as another existing superjunction semiconductor device, the following device has been proposed: the drain side portion of both the n-type and p-type regions of the parallel pn layer is set as a low impurity concentration region with a lower impurity concentration than the source side portion, and the drain side end of the p-type region of the parallel pn layer (low impurity concentration region) is structured such that a first portion with a higher impurity concentration than the portion in contact with the low impurity concentration region and a second portion with a lower impurity concentration than the portion in contact with the low impurity concentration region are arranged alternately and at equal intervals adjacent to each other in a direction that extends linearly along the p-type region parallel to the front side of the semiconductor substrate (for example, see Patent Document 3 below).

[0011] Furthermore, in Patent Document 3 below, a first portion with high impurity concentration in the drain side of the p-type region of the parallel pn layer is set to a width wider than the source side of the n-type region, and a second portion with low impurity concentration in the drain side of the p-type region of the parallel pn layer is set to a width narrower than the source side of the n-type region. Thus, by configuring the drain side end of the drain side of the p-type region of the parallel pn layer with a selectively provided first portion of high p-type impurity concentration, which serves as the starting point for the inflow of current (hereinafter referred to as avalanche current) during avalanche breakdown, the operating area of ​​the parasitic bipolar transistor is reduced, thereby increasing avalanche tolerance.

[0012] Furthermore, as another existing superjunction semiconductor device, a device has been proposed in which the repetition spacing between the n-type and p-type regions of the tandem pn layer in a part of the edge termination region is narrower than the repetition spacing between the n-type and p-type regions of the tandem pn layer in the active region (for example, see Patent Document 4 below). In Patent Document 4 below, by narrowing the repetition spacing between the n-type and p-type regions of the tandem pn layer in the edge termination region, the depletion layer in the tandem pn layer in the edge termination region is more likely to expand than that in the tandem pn layer in the active region, thereby dispersing the accumulated carriers and making it less likely for the tandem pn layer in the edge termination region to cause electric field concentration, thereby improving the reverse recovery tolerance.

[0013] Furthermore, as a manufacturing method for other existing superjunction semiconductor devices, a method has been proposed that involves acquiring different first and second characteristics related to the feedback capacity of a semiconductor element, and evaluating the feedback capacity of the semiconductor element based on these first and second characteristics to screen whether it is a good product (for example, see Patent Document 5 below). In Patent Document 5 below, avalanche voltage and on-resistance, which can be easily measured respectively, are acquired as the first and second characteristics, and deviations in the feedback capacity obtained based on these first and second characteristics are evaluated to detect the variation (positional offset) in the width of the n-type and p-type regions of the parallel pn layer, which are the main causes of feedback capacity variation.

[0014] Existing technical documents

[0015] Patent documents

[0016] Patent Document 1: Japanese Patent No. 6207676

[0017] Patent Document 2: Japanese Patent Application Publication No. 2017-037997

[0018] Patent Document 3: International Publication No. 2014 / 013888

[0019] Patent Document 4: Japanese Patent Application Publication No. 2004-022716

[0020] Patent Document 5: Japanese Patent Application Publication No. 2017-143234 Summary of the Invention

[0021] Technical issues

[0022] However, in a superjunction semiconductor device, as described above, by configuring the depletion layer to expand from the pn junction of the adjacent p-type region 104 and n-type region 103 of the parallel pn layer 105 within the parallel pn layer 105 when turned off, a breakdown voltage exceeding that achievable by the impurity concentration of the drift layer is ensured. Therefore, if the charge balance between the n-type region 103 and p-type region 104 of the parallel pn layer 105 collapses (for example, the charge ratio of the n-type region 103 and p-type region 104 deviates from 1:1, or the charge deviation of each n-type region 103 and p-type region 104 configured within the parallel pn layer 105 becomes larger, the breakdown voltage decreases. On the other hand, if the charge between the n-type region 103 and the p-type region 104 of the parallel pn layer 105 is too balanced (for example, the charge ratio of the n-type region 103 and the p-type region 104 is 1:1, etc.), the avalanche tolerance will be greatly reduced due to minor process deviations such as impurity concentration and / or position matching deviations.

[0023] Furthermore, if the charge balance between the n-type region 103 and the p-type region 104 of the parallel pn layer 105 is too high, then if the charge in the parallel pn layer 105 near the p-type region... - Partial avalanche breakdown in the base region 106 causes the avalanche current to flow into the p-type region 104, which serves as the basis of the npn parasitic bipolar transistor, instead of through the resistive component (drift resistance) of the p-type region 104. - In the base region 106, the avalanche resistance is significantly reduced. Therefore, it is necessary to avoid a configuration that achieves charge balance between the n-type region 103 and the p-type region 104, as this reduces characteristics such as on-resistance compared to a configuration that has already achieved charge balance.

[0024] In order to eliminate the problems of the prior art, the present invention aims to provide a semiconductor device that can suppress the voltage drop, suppress the avalanche resistance drop, and reduce the on-resistance of a superjunction semiconductor device with the drift layer set as a parallel pn layer.

[0025] Technical solution

[0026] To address the aforementioned issues and achieve the objectives of this invention, the semiconductor device of this invention has the following features: A first parallel pn layer is disposed on the upper surface of a semiconductor substrate of a first conductivity type, and an insulating gate structure is disposed on the upper surface of the first parallel pn layer. The first parallel pn layer has a first first conductivity type region and a first second conductivity type region alternately and repeatedly disposed in a first direction parallel to the upper surface of the semiconductor substrate.

[0027] The impurity concentration in the first conductivity region decreases as it moves away from the first peak position where the impurity concentration is greatest along the first direction. The slope of the impurity concentration in the first direction of the first conductivity region is symmetrical about the first peak position on both sides of the first direction in a first portion extending from the upper surface of the first parallel pn layer to a predetermined depth, and is different about the first peak position on both sides of the first direction in a second portion closer to the lower surface of the first parallel pn layer than the first portion.

[0028] The impurity concentration in the first second conductivity region decreases as it separates towards both sides along the first direction from the position of the second peak where the impurity concentration is at its maximum. The slope of the impurity concentration in the first direction of the first second conductivity region is symmetrical about the second peak position on both sides of the first direction in the third portion, from the upper surface of the first parallel pn layer to the predetermined depth, and is different about the second peak position on both sides of the first direction in the fourth portion, which is closer to the lower surface of the first parallel pn layer than the third portion.

[0029] Furthermore, based on the above-described invention, the semiconductor device of the present invention is characterized in that: the first peak position of the first portion is the center in the first direction of the first first conductivity type region; the first peak position of the second portion is located at a position offset along the first direction from the center in the first direction of the first first conductivity type region; the second peak position of the third portion is the center in the first direction of the first second conductivity type region; and the second peak position of the fourth portion is located at a position offset along the first direction from the center in the first direction of the first second conductivity type region.

[0030] Furthermore, based on the above-described invention, the semiconductor device of the present invention is characterized in that the offset of the first peak position of the first portion and the first peak position of the second portion in the first direction is more than 7% and less than 18% of the repetition spacing between the first first conductivity type region and the first second conductivity type region.

[0031] Furthermore, based on the above-described invention, the semiconductor device of the present invention is characterized in that the direction in which the first peak position of the second portion is offset along the first direction is the same as the direction in which the second peak position of the fourth portion is offset along the first direction. The direction in which the first peak position of the second portion is offset along the first direction is the same in all the second portions. The direction in which the second peak position of the fourth portion is offset along the first direction is the same in all the fourth portions.

[0032] Furthermore, based on the above-described invention, the semiconductor device of the present invention is characterized in that it further comprises a second parallel pn layer surrounding the first parallel pn layer, and a second first conductivity type region and a second second conductivity type region are alternately and repeatedly arranged along the first direction at a spacing narrower than the repeating spacing of the first first conductivity type region and the first second conductivity type region. The impurity concentration of the second first conductivity type region decreases as it separates to both sides along the first direction from the position where the impurity concentration reaches its maximum third peak.

[0033] The impurity concentration gradient in the first direction of the second first conductivity type region is symmetrical on both sides of the first direction, based on the position of the third peak. The impurity concentration in the second second conductivity type region decreases as it moves away from the position of the fourth peak, where the impurity concentration is at its maximum, along the first direction. The impurity concentration gradient in the first direction of the second second conductivity type region is symmetrical on both sides of the first direction, based on the position of the fourth peak.

[0034] Furthermore, based on the above-described invention, the semiconductor device of the present invention is characterized in that it further comprises a third parallel pn layer, which is disposed between the first parallel pn layer and the second parallel pn layer, surrounding the periphery of the first parallel pn layer. The third first conductivity type region and the third second conductivity type region are alternately and repeatedly arranged along the first direction at a spacing identical to the repeating spacing of the first first conductivity type region and the first second conductivity type region. The impurity concentration distribution of the third second conductivity type region is the same as that of the first second conductivity type region. Only the impurity concentration slope in the first direction of the innermost third second conductivity type region is the same as that of the first second conductivity type region.

[0035] Furthermore, based on the above-described invention, the semiconductor device of the present invention is characterized in that a semiconductor layer of a first conductivity type is provided between the semiconductor substrate and the first parallel pn layer.

[0036] Furthermore, the semiconductor device of the present invention, based on the above-described invention, is characterized in that the semiconductor device includes first and second insulated-gate field-effect transistors. The first insulated-gate field-effect transistor is disposed on the semiconductor substrate and has the first parallel pn layer and the insulated gate structure. The second insulated-gate field-effect transistor is disposed on the semiconductor substrate and has a plurality of cells with the same cell structure as the first insulated-gate field-effect transistor, in a manner fewer in number than the first insulated-gate field-effect transistor.

[0037] According to the invention described above, since the first first conductivity type region and the first second conductivity type region of the first parallel pn layer only shift the position of the second main surface side portion along the first direction by a predetermined offset without changing the impurity concentration and area (width), the charge balance does not collapse. Therefore, charge balance between the first first conductivity type region and the first second conductivity type region of the first parallel pn layer can be achieved. Furthermore, a portion with a locally steep impurity concentration slope can be formed on the second main surface side portion of the first parallel pn layer, and the site of avalanche breakdown can be induced to the second main surface side of the first parallel pn layer. Additionally, in the base region of the npn parasitic bipolar transistor formed in the semiconductor substrate, avalanche current can flow through the resistive component (drift resistance) of the first second conductivity type region of the first parallel pn layer.

[0038] Technical effect

[0039] The semiconductor device according to the present invention has the following effects: it can suppress the voltage drop of a superjunction semiconductor device with the drift layer as a parallel pn layer, suppress the avalanche withstand capability drop, and reduce the on-resistance. Attached Figure Description

[0040] Figure 1 This is a top view showing the layout of the semiconductor device of Embodiment 1 as viewed from the front side of the semiconductor substrate.

[0041] Figure 2 It is shown Figure 1 A cross-sectional view of the structure at the cutting line A-A'.

[0042] Figure 3 It is shown Figure 1 A cross-sectional view of the structure at the cutting line B-B'.

[0043] Figure 4 It is shown Figure 2 An illustrative diagram showing the planar structure and impurity concentration distribution at the cutting line C-C'.

[0044] Figure 5 It is shown Figure 2 An illustrative diagram showing the planar structure and impurity concentration distribution at the cutting line D-D'.

[0045] Figure 6 This is a flowchart illustrating an outline of a method for manufacturing a semiconductor device according to Embodiment 1.

[0046] Figure 7 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0047] Figure 8This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0048] Figure 9 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0049] Figure 10 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0050] Figure 11 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0051] Figure 12 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0052] Figure 13 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1.

[0053] Figure 14 This is a top view showing the parallel pn layers during the manufacturing process of the semiconductor device according to Embodiment 1, viewed from the front side of the semiconductor substrate.

[0054] Figure 15 This is a top view showing the parallel pn layers during the manufacturing process of the semiconductor device according to Embodiment 1, viewed from the front side of the semiconductor substrate.

[0055] Figure 16 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2.

[0056] Figure 17 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 3.

[0057] Figure 18 This is a characteristic graph illustrating the relationship between the p / n ratio of the first parallel pn layer in the embodiment and the withstand voltage BVdss and on-resistance Ron.

[0058] Figure 19 This is a characteristic graph illustrating the relationship between the p / n ratio of the first parallel pn layer in the embodiment and the withstand voltage BVdss and avalanche withstand capacity.

[0059] Figure 20 This is a top view showing the layout of parallel pn layers of an existing superjunction semiconductor device as viewed from the front side of a semiconductor substrate.

[0060] Figure 21 It is shown Figure 20 A cross-sectional view of the structure at the cutting line AA-AA'.

[0061] Symbol Explanation

[0062] 1 n + Leakage area

[0063] 2 n-type buffer

[0064] 3, 93, 93' The n-type region of the first parallel pn layer

[0065] 3a, 3b, 3c, 3d, 3e n-type impurity injection regions

[0066] 4, 94, 94' The p-type region of the first parallel pn layer

[0067] 4a, 4b, 4c, 4d, 4e p-type impurity injection regions

[0068] 5. Parallel pn layers of the 95 active region (first parallel pn layer)

[0069] 6, 6a p - Base region

[0070] 7 n + Source area

[0071] 8. Grooves

[0072] 9. Gate insulating film

[0073] 10 Active Area

[0074] 11. Gate electrode

[0075] 12-layer interlayer insulation film

[0076] 13 Source Electrode

[0077] 14 Drain electrode

[0078] 15 Gate electrode pads

[0079] 20 Edge Terminal Area

[0080] 21 p -- Type of reduced surface electric field region

[0081] 22 p - Type of trench cut-off area

[0082] 23 The n-type region of the second parallel pn layer

[0083] 24. P-type regions of the second parallel pn layer

[0084] 25. Parallel PN layers in the edge terminal area (second parallel PN layer)

[0085] 26 LOCOS membrane

[0086] 27 Gate polysilicon layer

[0087] 28 Channel cutoff electrode

[0088] 29 Gate metal layer

[0089] 30 Middle Zone

[0090] 33 The n-type region of the third parallel pn layer

[0091] 34, 34a, 34b The p-type regions of the third parallel pn layer

[0092] 35. Parallel pn layers in the middle region (third parallel pn layer)

[0093] 40 Semiconductor substrate

[0094] 41 n + type substrate

[0095] 42 n-type epitaxial layer

[0096] 43, 43a~43f n - epitaxial layer

[0097] 43' n - Type Drift Zone

[0098] 50, 80, 90 semiconductor devices

[0099] 61, 63, 65, 67 Ion implantation masks

[0100] Openings of ion implantation masks of types 61a, 63a, 65a, and 67a

[0101] 62, 64, 66, 68 Ion implantation

[0102] 71, 72, 73, 74 The overlapping portions of the n-type impurity implantation region and the p-type impurity implantation region due to thermal diffusion

[0103] C column offset direction

[0104] d: Offset in the direction of column offset

[0105] The width of the overlap between the n-type and p-type regions of the parallel pn layers w1, w2, w3, and w4 due to thermal diffusion.

[0106] w11 Width of the n-type region in the first parallel pn layer

[0107] w12 Width of the p-type region in the first parallel pn layer

[0108] w21 Width of the n-type region in the second parallel pn layer

[0109] w22 Width of the p-type region in the second parallel pn layer

[0110] w31 Width of the n-type region in the third parallel pn layer

[0111] w32 Width of the p-type region in the third parallel pn layer

[0112] X is the direction parallel to the main surface of the semiconductor substrate (first direction).

[0113] Y is the direction parallel to the main surface of the semiconductor substrate and orthogonal to the first direction (the second direction).

[0114] Z Depth Direction

[0115] P1 The repetition spacing between the n-type and p-type regions of the first parallel pn layer P1

[0116] P2 The repetition spacing between the n-type and p-type regions of the second parallel pn layer P2

[0117] P3 The repetition spacing between the n-type and p-type regions of the third parallel pn layer P3 Detailed Implementation

[0118] Hereinafter, preferred embodiments of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings. In this specification and the drawings, layers or regions prefixed with n or p respectively indicate that electrons or holes are the majority carriers. Furthermore, the + and - symbols marked with n or p respectively indicate that the impurity concentration is higher and lower than the impurity concentration in layers or regions not marked with + and -. It should be noted that in the following description of the embodiments and the accompanying drawings, the same symbols are used to refer to the same structures, and repeated descriptions are omitted.

[0119] (Implementation Method 1)

[0120] The structure of the semiconductor device according to Embodiment 1 will be described. Figure 1 This is a top view showing the layout of the semiconductor device 50 of Embodiment 1 as viewed from the front side of the semiconductor substrate. Figure 1 The semiconductor device 50 of Embodiment 1 shown has n-type regions (first first conductivity type regions) 3 and p-type regions (first second conductivity type regions) 4 alternately arranged adjacent to each other in a first direction X parallel to the main surface of the semiconductor substrate (semiconductor chip) 40, thereby making the drift layer in the active region 10 a first parallel pn layer 5 (see reference). Figure 2 , Figure 3 () superjunction MOSFET with trench gate structure.

[0121] The active region 10 is the area where current flows when the MOSFET is in the on-state. The active region 10 has, for example, a planar shape in which a gate electrode pad 15 is formed, forming a recess on three sides surrounding a generally rectangular planar shape of the gate electrode pad 15. It should be noted that... Figure 1 In this context, although the lower part of the gate electrode pad 15 is set as the middle region 30, the lower part of the gate electrode pad 15 can be set as the active region 10, and the active region 10 can be set as a roughly rectangular planar shape.

[0122] The active region 10 is disposed approximately at the center of the semiconductor substrate 40 (the center of the chip). The active region 10 is a region further inward than the center of the trench 8, which is disposed on the outermost side in the first direction X (described later). Figure 2 ), and in the second direction Y, which is parallel to the main surface of the semiconductor substrate 40 and orthogonal to the first direction X, compared to n described later. + Source area 7 (refer to) Figure 2 The region on the inner side of the end of the ) (not shown).

[0123] In the active region 10, MOSFET unit cells are arranged adjacent to each other (the constituent unit of the element: refer to...). Figure 2 The active region 10 is surrounded by the edge terminal region 20 via the intermediate region 30. The intermediate region 30 is the area between the active region 10 and the edge terminal region 20, and is configured with p -- The surface electric field reduction region 21 is formed. The edge termination region 20 is the LOCOS film 26 described later (see reference). Figure 2 The region between the inner end of the semiconductor substrate 40 and the end of the semiconductor substrate 40 (chip end) alleviates the electric field on the front side of the semiconductor substrate 40 and maintains voltage resistance.

[0124] Edge terminal area 20 is configured with, for example, p - The voltage-resistant structures, such as the channel cut-off region 22 and the channel cut-off electrode 28 described later (see reference). Figure 2 , Figure 3 Withstand voltage is the limit of voltage that will not cause malfunction or damage to the component. Figure 1 The image shows the source electrode 13, the gate electrode pad 15, and the gate metal layer 29 electrically connected to the gate electrode pad 15. Dashed lines are used to indicate the boundaries between the active region 10 and the intermediate region 30, and between the intermediate region 30 and the edge termination region 20. Thinner dashed lines than those between the active region 10 and the intermediate region 30, and between the intermediate region 30 and the edge termination region 20, are used to represent p. - The outline of the truncated section 22 of the channel. - The outer periphery of the channel cut-off region 22 overlaps with the edges of the semiconductor substrate 40 as solid lines.

[0125] An intermediate region 30 is disposed between the active region 10 and the edge terminal region 20, adjacent to both the active region 10 and the edge terminal region 20. The intermediate region 30 surrounds the active region 10. -- A surface electric field reduction region 21 is disposed in the intermediate region 30, surrounding the active region 10. -- The type of reduced surface electric field region 21 can extend from the middle region 30 to the edge terminal region 20. - Type 22 tidal channel cutoff zone in ratio p -- The position of the reduced surface electric field region 21 is further outward (on the chip end side), compared to p. -- The surface electric field region 21 is separated and configured to reduce the surface electric field.

[0126] p - The channel cutoff region 22 is disposed along each side of the semiconductor substrate 40 and generally rectangularly surrounds the p-type semiconductor substrate. - The inner part (central side of the chip) of the channel cutoff region 22. - The channel cutoff region 22 is exposed at the ends of the semiconductor substrate 40 on each side of the semiconductor substrate 40, and is disposed at the corners (chip corners) of the semiconductor substrate 40 at a position slightly inward than the ends of the semiconductor substrate 40, and is not exposed at the ends of the semiconductor substrate 40. The corners of the semiconductor substrate 40 correspond to the four vertices of the semiconductor substrate 40.

[0127] Next, the cross-sectional structure of the semiconductor device 50 according to Embodiment 1 will be described. Figure 2 It is shown Figure 1 A cross-sectional view of the structure at the cutting line A-A'. Figure 3 It is shown Figure 1 A cross-sectional view of the structure at the cutting line B-B'. Figure 4 It is shown Figure 2 Characteristic diagram of planar structure and impurity concentration distribution at the cutting line C-C'. Figure 5 It is shown Figure 2 The characteristic diagram of the planar structure and impurity concentration distribution at the cutting line D-D'. Figure 4 , Figure 5 In the image, the layout of the first parallel pn layer 5 as viewed from the front side of the semiconductor substrate 40 is shown on the lower side, and the impurity concentration distribution of the first parallel pn layer 5 is shown on the upper side.

[0128] Figure 4 The upper part is the second to fifth layers of the epitaxial layer 43, which constitutes the first parallel pn layer 5 and is formed by multiple layers (equivalent to...). Figure 13 The impurity concentration distribution of symbols 43b to 43e. Figure 5 The upper part is the first layer of the epitaxial layer 43, which is formed by the deposition of multiple layers constituting the first parallel pn layer 5 (equivalent to...). Figure 13The impurity concentration distribution is shown in symbol 43a). Figure 4 , Figure 5 In the diagram, dashed lines passing through n-type region 3 and p-type region 4 are used to represent the centers of n-type region 3 and p-type region 4, respectively, and dashed and solid lines are used to represent the distribution of impurity concentrations in n-type region 3 and p-type region 4, respectively.

[0129] like Figure 2 , Figure 3 As shown, in the first embodiment, the semiconductor device 50 has a first parallel pn layer 5, a third parallel pn layer 35, and a second parallel pn layer 25 respectively in the active region 10, the intermediate region 30, and the edge terminal region 20, within the semiconductor substrate 40. The semiconductor substrate 40 is formed as n + n of the type drain region (low resistance layer) 1 + An epitaxial substrate is formed by sequentially depositing an n-type buffer zone 2 and epitaxial layers 42 and 43, consisting of the first to third parallel pn layers 5, 25, and 35, on the front (upper surface) of the substrate 41. The structure of the first to third parallel pn layers 5, 25, and 35 will be described later.

[0130] In the active region 10, a p-type p-layer is disposed between the front side of the semiconductor substrate 40 (the main surface on the side of the epitaxial layer 43) and the first parallel pn layer 5. - Type base region 6. p - The base region 6 contacts the n-type region 3 and p-type region 4 of the first parallel pn layer 5. On the front side of the semiconductor substrate 40 and the p... - Between type base region 6 and p - The base region 6 is selectively provided with n in contact with it. + Source region 7. p - Type base region 6 and n + The source region 7 is selectively exposed on the front side of the semiconductor substrate 40 through contact holes provided in the interlayer insulating film 12 described later.

[0131] On the front and p of the semiconductor substrate 40 - p can be set between the base regions 6. + Type contact area (not shown). When a p is provided... + In the case of a type contact area, n + Type source region 7 and p + The contact areas are selectively exposed on the front side of the semiconductor substrate 40 through contact holes provided in the interlayer insulating film 12 (described later). + The contact area is in the depth direction Z and p - Type base region 6 is adjacent to n in the first direction X. + Source area 7 is adjacent. Trench 8 is continuous. + Type source region 7 and p -The base region 6 reaches the n-type region 3 of the first parallel pn layer 5.

[0132] Although the illustration is omitted, when viewed from the front side of the semiconductor substrate 40, p - Type base region 6, n + Type source region 7 and p + The contact area between adjacent grooves 8 (platform area) is configured as a straight line extending parallel to the grooves 8 and in the same direction as the grooves 8 (second direction Y). The p of each plaform area... - Type base region 6 and p + All contact areas of type p -- The surface electric field region 21 is connected to reduce the electric field, and through p -- The surface electric field region 21 is reduced and electrically connected to each other.

[0133] The groove 8 extends in a strip shape to the intermediate region 30 in the second direction Y, at p -- The type-reduced surface electric field region 21 terminates within the trench. The outermost half of the trench 8 in the first direction X is disposed in the intermediate region 30. As described above, the center of the outermost trench 8 in the first direction X is located at the boundary between the active region 10 and the intermediate region 30. The trench 8 is configured to reach the n-type region 3 of the first parallel pn layer 5 in the depth direction Z, but not in the p-type region 4 of the first parallel pn layer 5. A gate electrode 11 is disposed inside the trench 8 via a gate insulating film 9.

[0134] An interlayer insulating film 12 is formed on the entire front side of the semiconductor substrate 40. A contact hole is formed that penetrates the interlayer insulating film 12 along the depth direction Z to reach the semiconductor substrate 40. In the active region 10, p is exposed at the contact hole. - Type base region 6 and n + Source region 7. Source electrode 13 is disposed on the entire front side of semiconductor substrate 40 in active region 10, and is located within contact hole and p - Type base region 6 and n + The source region 7 is in contact with p. - Type base region 6 and n + Type source area 7 electrical connection.

[0135] With p set + In the case of a type contact area, the source electrode 13 is in contact with p within the contact hole. + Type contact area and n + The source region 7 is in contact with p. - Type base region 6, p + Type contact area and n + Source region 7 is electrically connected. In the first to third parallel pn layers 5, 25, 35 and n (described later). - Type drift region 43' and n +Between the type-leaking region 1, and the first to third parallel pn layers 5, 25, 35, and n. - Type drift region 43' and n + Type n buffer 2 is set up adjacent to type n leak area 1.

[0136] The n-type buffer 2 is composed of an n-type epitaxial layer 42. Additionally, n + Type 1 leak area 1 consists of n + The substrate 41 is composed of n-type buffer 2 and n-type buffer 3. + The drain region 1 covers the entire area of ​​the semiconductor substrate 40 and has a uniform thickness. Uniform thickness means approximately the same thickness within a range that includes allowable errors due to process variations. This applies to the entire back surface (n) of the semiconductor substrate 40. + The main surface (n) on the side of the substrate 41 + A drain electrode 14 is provided on the back side of the substrate 41. The drain electrode 14 and n + Type leak region 1 contacts and is in contact with n + Type 1 leakage area electrical connection.

[0137] In the intermediate region 30, between the front side of the semiconductor substrate 40 and the third parallel pn layer 35, a p-type ... - Type base region 6. Hereinafter, the symbol 6a will be used to represent p in the intermediate region 30. - Type base region 6. p - The base region 6a terminates at a position further inward than the boundary between the intermediate region 30 and the edge termination region 20. Additionally, between the front side of the semiconductor substrate 40 and the third parallel pn layer 35, in a position further inward than the pn layer... - The outermost position of the base region 6a is related to p. - p is provided adjacent to the base region 6a. -- Type 21 reduces surface electric field region.

[0138] p -- Type 21 reduces surface electric field region 21 in p - The base region 6a is located further outward, exposed on the front side of the semiconductor substrate 40, and extends from the middle region 30 to the edge terminal region 20. -- Type 21 reduces surface electric field region compared to p - The base region 6a reaches the front-facing n at a distance of 40 from the semiconductor substrate. + The deeper part (depth) on the side of the leak area 1. -- Type 21 reduces surface electric field region 21 in p - The base region 6a extends inward between the base region 6a and the third parallel pn layer 35, reaching the outermost trench 8 in the first direction X, and surrounding the bottom corner of the outer side of the trench 8. Figure 2 ).

[0139] p --Type 21 reduces surface electric field region 21 in p - The base region 6a extends inward between the third parallel pn layer 35 and surrounds the bottom corner of the end (end in the length direction) of all the trenches 8 in the second direction Y. Figure 3 The bottom corner of trench 8 forms the boundary between the sidewall and the bottom surface of trench 8. In the intermediate region 30, on the front side of the semiconductor substrate 40, the source electrode 13 extends from the active region 10 and intersects with the p-type electrode within the contact hole. - The base region 6a is in contact with p. - The base region 6a is electrically connected. The source electrode 13 is disposed on the interlayer insulating film 12 within the intermediate region 30. In addition, the source electrode 13 is separated from and electrically insulated from the gate metal layer 29 disposed outside the source electrode 13.

[0140] In the edge termination region 20, a second parallel pn layer 25 is exposed on the front side of the semiconductor substrate 40. Between the second parallel pn layer 25 in the edge termination region 20 and the end of the semiconductor substrate 40, an n-layer is disposed adjacent to the second parallel pn layer 25. - Type-aspect drift region 43'. - The drift region 43' is exposed at the end of the semiconductor substrate 40. - Type 43' is a drift region that does not drift towards n during the formation of the first to third parallel pn layers 5, 25, and 35. - Ion implantation of impurities into the epitaxial layer, and the n during deposition - The portion obtained by leaving the same impurity concentration as the epitaxial layer 43.

[0141] On the front side of the semiconductor substrate 40 and n - Between the 43' type drift region and n - Type drift region 43' is selectively provided with p - Type 22 trench cutoff zone. - The channel cutoff region 22 is exposed on the front side and at the ends of the semiconductor substrate 40. In p -- Type reduction of surface electric field region 21 and p - Between the channel cutoff regions 22, the entire front side of the semiconductor substrate is covered by a LOCOS (Local Oxidation of Silicon) film 26.

[0142] The front side of the semiconductor substrate 40 in the edge terminal region 20, except for the exposed p -The entire surface except for the portion of the channel cutoff region 22 is covered by a LOCOS film 26. Therefore, the LOCOS film 26 sandwiches the intermediate region 30 in the middle and surrounds the active region 10. A gate polysilicon layer 27 is disposed on the LOCOS film 26 in such a way that it surrounds the active region 10. The gate polysilicon layer 27 extends from the edge termination region 20 to the intermediate region 30. The gate polysilicon layer 27 can extend to a point greater than p... -- The area where the surface electric field is reduced is located further outward.

[0143] The gate polysilicon layer 27 is, for example, a gate wiring that contacts the gate electrode 11 at its end in the second direction Y of each trench 8 and is electrically connected to all the gate electrodes 11. The gate polysilicon layer 27 is electrically insulated from the semiconductor substrate 40 by a gate insulating film 9 extending from the sidewall of the trench 8 to the front side of the semiconductor substrate 40 and a LOCOS film 26. The channel cutoff electrode 28 is disposed separately from the gate polysilicon layer 27 and surrounds the LOCOS film 26.

[0144] Channel cutoff electrode 28 and p - The truncated section 22 of the channel is in contact with p - The channel cutoff region 22 is electrically connected. The channel cutoff electrode 28 can extend inward on the LOCOS film 26. The LOCOS film 26, the gate polysilicon layer 27, and the channel cutoff electrode 28 are covered by the interlayer insulating film 12. The source electrode 13, the gate polysilicon layer 27, and the channel cutoff electrode 28 are electrically insulated from each other by the interlayer insulating film 12.

[0145] A gate metal layer 29 is disposed on the gate polysilicon layer 27 via an interlayer insulating film 12 in the edge termination region 20. The gate metal layer 29 is circumferentially opposed to the gate polysilicon layer 27. Between the gate metal layer 29 and the gate polysilicon layer 27, a contact hole is provided in the interlayer insulating film 12 to surround the active region 10. The gate metal layer 29 contacts and is electrically connected to the gate polysilicon layer 27 within the contact hole of the interlayer insulating film 12.

[0146] Contact holes for contact between the gate metal layer 29 and the gate polysilicon layer 27 can, for example, be provided at a position opposite the LOCOS film 26 along the depth direction Z. The gate metal layer 29 is configured separately from the source electrode 13. The gate metal layer 29 can extend to the intermediate region 30 without contacting the source electrode 13. The gate metal layer 29 can extend to a position further outward than the gate polysilicon layer 27. The gate metal layer 29 is, for example, located further inward than the channel cutoff electrode 28 and electrically connected to the gate electrode pad 15.

[0147] Next, the structure of the first to third parallel pn layers 5, 25, and 35 will be described. As mentioned above, the first to third parallel pn layers 5, 25, and 35 are respectively disposed in the active region 10, the edge terminal region 20, and the intermediate region 30. The first to third parallel pn layers 5, 25, and 35 are formed, for example, through a multilayer epitaxy (see [reference]). Figure 11 , 12 The multilayer epitaxial method involves stacking multiple epitaxial layers 43a to 43e to form n-type regions (first to third first conductivity regions) 3, 23, 33 and p-type regions (first to third second conductivity regions) 4, 24, 34, respectively, so that regions of the same conductivity type are adjacent to each other in the depth direction Z.

[0148] The first parallel pn layer 5 has n-type regions 3 and p-type regions 4 arranged alternately and adjacent to each other in the active region 10 along the first direction X. The n-type region 3 is arranged on the outermost side of the first parallel pn layer 5 in the first direction X. The n-type regions 3 and p-type regions 4 extend linearly in the second direction Y. In addition, the n-type regions 3 and p-type regions 4 extend in a generally linear manner in the depth direction Z. The first parallel pn layer 5 achieves charge balance in such a way that the widths w11 and w12 of the n-type regions 3 and p-type regions 4 are approximately the same, and the total impurity mass of the n-type regions 3 and p-type regions 4 is approximately the same.

[0149] The impurity concentration slope in the first direction X of the n-type region 3 and p-type region 4 of the first parallel pn layer 5 is symmetrical in the source side (source electrode 13 side) portion (first and third portions) (refer to...). Figure 4 The asymmetry is observed on the drain side (drain electrode 14 side) in the second and fourth parts (refer to...). Figure 5 The symmetry of the impurity concentration slope in the first direction X of the n-type region 3 means that the n-type region 3 shows a maximum value (peak) at the center (peak position: first peak position) in the first direction X, and has an impurity concentration distribution that gradually decreases from the peak position to both sides of the first direction X until it reaches the pn junction of the adjacent p-type region 4, and its impurity concentration slope is symmetrical with respect to the peak position. The source-side surface of the first parallel pn layer 5 is designated as the upper surface, and the drain-side surface is designated as the lower surface.

[0150] The asymmetry of the impurity concentration slope in the first direction X of n-type region 3 refers to the fact that n-type region 3 shows a maximum value at a position offset from the center along the first direction X (peak position: first peak position), and has an impurity concentration distribution that gradually decreases from the peak position to both sides of the first direction X until it reaches the pn junction of the adjacent p-type region 4, with different impurity concentration slopes on both sides based on the peak position (having a steep impurity concentration slope and a gentle impurity concentration slope). Regarding whether the impurity concentration slope in the first direction X of p-type region 4 is symmetrical or asymmetrical, it is sufficient to rephrase the description of the peak position and impurity concentration slope of the impurity concentration for "n-type region 3" as the peak position (second peak position) and impurity concentration slope of the impurity concentration for "p-type region 4".

[0151] In this embodiment, among the layers of the epitaxial layer 43 that are formed by multiple layers stacked on the n-type epitaxial layer 42 to constitute the first parallel pn layer 5, from the first layer to the total number of layers (in Figure 11 , Figure 12 Up to half of the five floors in the middle (in the middle) Figure 11 , Figure 12 (n up to two layers) - Type epitaxial layer (i.e., in) Figure 11 , Figure 12 The term "n" is equivalent to the term in symbols 43a and 43b, which refers to at least one layer of n starting from the drain side. - The n-type region 3 and p-type region 4 of the epitaxial layer form an asymmetric structure of impurity concentration tilt in the first direction X.

[0152] The remaining n layers - The n-type region 3 and p-type region 4 of the epitaxial layer make the impurity concentration slope in the first direction X symmetrical. The remaining n-type region... - The n-type epitaxial layer has three to five layers. - Type epitaxial layer (in) Figure 11 , Figure 12 In the middle, equivalent to symbols 43c~43e), or in the use of only the first layer n - In the case where the impurity concentration tilt in the first direction X of the n-type region 3 and the p-type region 4 of the epitaxial layer 43a is asymmetrical, the remaining layer's n - The n-type epitaxial layer consists of two to five layers. - Type epitaxial layer (in) Figure 11 , Figure 12 In the middle, it is equivalent to symbols 43b to 43e).

[0153] Here, only the first layer n - The impurity concentration tilt in the first direction X of the n-type region 3 and p-type region 4 of the epitaxial layer 43a is asymmetrical (refer to...). Figure 2 , Figure 11 , Figure 12 ). The first layer of n - The regions of n-type region 3 and p-type region 4 of epitaxial layer 43a with relatively steep impurity concentration slope and high impurity concentration in the first direction X. Figure 5 The first part 5a, which is sandwiched by the opposing horizontal arrow, and the second part (part other than the first part 5a) 5b, which has a relatively gentle slope of impurity concentration and low impurity concentration in the first direction X, alternately and repeatedly exist adjacent to each other in the first direction X.

[0154] In only the first layer n - When the epitaxial layer 43a is configured with an asymmetric impurity concentration tilt in the first direction X, as will be described later, as long as the impurity concentration tilt is asymmetric in the n direction X, - The ion implantation mask 63 used for ion implantation 64 to form the p-type region 4 in the epitaxial layer 43a (see reference) Figure 8 The ratio is used for n in the second to fifth layers. - The ion implantation mask 67, which has the same pattern as the ion implantation mask 63, is used for ion implantation 68 to form the p-type region 4 in the epitaxial layers 43b-43e (see reference). Figure 10 It can be configured to offset from the first direction X in one direction (hereinafter referred to as the column offset direction) C.

[0155] By forming the first layer n in this way - The p-type region 4 of the epitaxial layer 43a, thus the n-type region of the first layer - The p-type region 4 of the epitaxial layer 43a is configured in a manner different from that of the n-type region. - The position of the p-type region 43b-43e of the epitaxial layer 4 offset in the nematic offset direction C. The n-type region of the first layer. - The p-type region 4 of the epitaxial layer 43a, directed towards other n - The offset d of the column offset direction C based on the position of the p-type region 4 of the epitaxial layers 43b to 43e is, for example, more than 7% and less than 18% of the repetition spacing between the n-type region 3 and the p-type region 4.

[0156] Therefore, n in the first layer - The peak position where the impurity concentration in all p-type regions 4 of the epitaxial layer 43a reaches its maximum along the first direction X is located at a position offset by only the aforementioned offset amount d from the center of the p-type region 4 along the first direction X. - The peak position of the impurity concentration in all n-type regions 3 of the n-type epitaxial layer 43a in the first direction X is located at a position offset by the aforementioned offset amount d from the center of the n-type region 3 in the first direction X.

[0157] Based on the desired withstand voltage and the n of each layer - The thicknesses of the n-type epitaxial layers 43a to 43e are determined to form the first parallel pn layer 5 by multiple layers being deposited on the n-type epitaxial layer 42. - Among the layers of the type epitaxial layer 43, n is the number of layers from the first layer up to less than half the total number of layers. - Several n layers in the epitaxial layer - The n-type region 3 and p-type region of the epitaxial layer can be configured such that the impurity concentration tilt is asymmetrical in the first direction X. It should be noted that the n-type region of each layer... - The thinner the epitaxial layer (43a-43e), the lower the voltage resistance.

[0158] The third parallel pn layer 35 has n-type regions 33 and p-type regions 34 alternately and repeatedly arranged adjacent to each other in the first direction X in the middle region 30. The third parallel pn layer 35 is adjacent to the outer side of the first parallel pn layer 5. The p-type region 34 is arranged on the innermost side of the third parallel pn layer 35 in the first direction X. The p-type region 34 arranged on the innermost side of the third parallel pn layer 35 in the first direction X is in contact with the n-type region 34 arranged on the outermost side of the first parallel pn layer 5 in the first direction X. The n-type region 33 is arranged on the outermost side of the third parallel pn layer 35 in the first direction X.

[0159] Similar to the n-type region 3 and p-type region 4 of the first parallel pn layer 5, the n-type region 33 and p-type region 34 extend linearly in the second direction Y and in the depth direction Z. The third parallel pn layer 35 achieves charge balance by making the widths w31 and w32 of the n-type region 33 and p-type region 34 approximately the same, and making the total impurity mass of the n-type region 33 and p-type region 34 approximately the same. The widths w31 and w32 of the n-type region 33 and p-type region 34 of the third parallel pn layer 35 are the same as the widths w11 and w12 of the n-type region 3 and p-type region 4 of the first parallel pn layer 5, respectively. Therefore, the repetition spacing P3 (the sum of widths w31 and w32) of the n-type region 33 and p-type region 34 of the third parallel pn layer 35 is the same as the repetition spacing P1 (the sum of widths w11 and w12) of the n-type region 3 and p-type region 4 of the first parallel pn layer 5.

[0160] Similar to the p-type region 4 of the first parallel pn layer 5, the impurity concentration slope of the innermost p-type regions 34 (34a, 34b) disposed only in the first direction X of the third parallel pn layer 35 is symmetrical on the source side and asymmetrical on the drain side. Therefore, the impurity concentration slope of the first layer is symmetrical on the source side and asymmetrical on the drain side, as is the case with the innermost p-type regions 34 (34a, 34b) disposed only in the first direction X of the third parallel pn layer 35. - The p-type region 34 of the epitaxial layer 43a is configured in a manner different from that of the n-type region.- The position of the p-type region 34 of the epitaxial layer 43b to 43e offset in the nematic offset direction C.

[0161] Because the innermost p-type regions 34a and 34b, located in the first direction X of the third parallel pn layer 35, have asymmetrical impurity concentration tilts in the first direction X, they are different from the n-type regions of the first layer. - The width of the adjacent n-type region 33 on the outer side of the p-type region 34 of the p-type epitaxial layer 43a is wider than that of other n-type regions 33, and it has a lower impurity concentration. Therefore, in this n-type region 33, during turn-off, the depletion layer is difficult to expand from the pn junction with the adjacent p-type region 34, the electric field strength becomes higher, and thus the breakdown voltage decreases in this n-type region 33.

[0162] Moreover, with the first layer n - The width of the adjacent n-type region 33 on the outer side of the p-type region 34b offset outward from the p-type region 34 of the epitaxial layer 43a is narrower than the width of other n-type regions 33, and it becomes a high impurity concentration area. Therefore, this n-type region 33 becomes a region of electric field concentration, and the breakdown voltage decreases in this n-type region 33. Therefore, through the p-type region not in the middle region 30... - Type base region 6a configuration n + Type source region 7, thereby enabling p - The area of ​​the parasitic diode formed by the pn junction in the base region 6a and the n-type region 33 increases, suppressing the decrease in breakdown voltage in these n-type regions 33.

[0163] The second parallel pn layer 25 has n-type regions 23 and p-type regions 24 alternately and repeatedly arranged adjacent to each other in the first direction X in the edge terminal region 20. The second parallel pn layer 25 is adjacent to the outer side of the third parallel pn layer 35. The p-type region 24 is arranged on the innermost side of the second parallel pn layer 25 in the first direction X. The p-type region 24 arranged on the innermost side of the second parallel pn layer 25 in the first direction X contacts the n-type region 33 arranged on the outermost side of the third parallel pn layer 35 in the first direction X. On the outermost side of the second parallel pn layer 25 in the first direction X, the n-type region 23 is adjacent to the outermost side of the third parallel pn layer 35 in the first direction X. - The n-type region 23 is configured in contact with the type drift region 43'.

[0164] Similar to the n-type region 3 and p-type region 4 of the first parallel pn layer 5, the n-type region 23 and p-type region 24 extend linearly in the second direction Y and in the depth direction Z. The second parallel pn layer 25 achieves charge balance by making the widths w21 and w22 of the n-type region 23 and p-type region 24 approximately the same, and making the total impurity mass of the n-type region 23 and p-type region 24 approximately the same. The widths w21 and w22 of the n-type region 23 and p-type region 24 of the second parallel pn layer 25 are narrower than the widths w11 and w12 of the n-type region 3 and p-type region 4 of the first parallel pn layer 5, respectively. Therefore, the repetition spacing P2 (the sum of widths w21 and w22) of the n-type region 23 and p-type region 24 of the second parallel pn layer 25 becomes narrower than the repetition spacing P1 (the sum of widths w11 and w12) of the n-type region 3 and p-type region 4 of the first parallel pn layer 5.

[0165] The impurity concentration tilt in the first direction X of the n-type region 23 and p-type region 24 of the second parallel pn layer 25 is symmetrical. For the symmetry of the impurity concentration tilt in the first direction X of the n-type region 23 and p-type region 24, it is sufficient to replace the description of the peak position and impurity concentration tilt of the "n-type region 3" of the first parallel pn layer 5 with the peak position (third peak position) and impurity concentration tilt of the "n-type region 23", and the peak position (fourth peak position) and impurity concentration tilt of the "p-type region 24", respectively.

[0166] The symmetry of the impurity concentration tilt in the first direction X indicates that the n layer in the first layer of the second parallel pn layer 25 is symmetrical. - The p-type region 24 of the epitaxial layer 43a does not have the n-type region of the first layer, as is the one set in the first parallel pn layer 5 and the third parallel pn layer 35. - Like the p-type region 4 and p-type region 34a of the epitaxial layer 43a, it is configured in a manner that is different from other n-type regions. - The position of the p-type region 4 and p-type region 34a of the epitaxial layers 43b to 43e offset in the nematic offset direction C.

[0167] The p-type regions 4, 24, and 34 of the first to third parallel pn layers 5, 25, and 35 can extend into the n-type buffer 2 in the depth direction Z. The n-type region 23 and p-type region 24 of the second parallel pn layer 25, for example, reach into the n-type buffer 2 from the front side of the semiconductor substrate 40. The p-type region 34 of the third parallel pn layer 35, for example, can extend into the n-type buffer 2 in the thickness direction of the semiconductor substrate 40 (in a direction parallel to the depth direction Z, from the back side of the semiconductor substrate 40 towards the front side). --The p-type region 34 of the third parallel pn layer 35 may, for example, not reach the front side of the semiconductor substrate 40 in the thickness direction of the semiconductor substrate 40.

[0168] While not specifically limited, for example, in the case of a superjunction MOSFET in Embodiment 1 with a withstand voltage of 100V, the dimensions and impurity concentrations of each part are taken as follows. The thickness of the n-type buffer 2 (n-type epitaxial layer 42) is, for example, about 3.5 μm. The impurity concentration of the n-type buffer 2 is, for example, 1.0E+16 / cm². 3 Above and 3.0E+16 / cm 3 The following. - The thickness of the epitaxial layer 43 is, for example, 2.0 μm. - Type base region 6 and p -- The depths of the surface electric field reduction region 21 are, for example, 1.0 μm and 1.5 μm. - The impurity concentration in base region 6 is, for example, 5.0E+16 / cm³. 3 Above and 5.0E+17 / cm 3 Below. p -- The impurity concentration in the reduced surface electric field region 21 is, for example, 5.0E+15 / cm². 3 Above and 2.0E+17 / cm 3 The width of the edge terminal region 20 is, for example, 50 μm. The width of the middle region 30 is, for example, 30 μm. It should be noted that E refers to a power of 10, for example, 1.0E+16 / cm. 3 It refers to 1×10 16 / cm 3 .

[0169] The widths w11 and w12 of the n-type region 3 and p-type region 4 of the first parallel pn layer 5 are, for example, 1 μm or more and 2 μm or less (with a repeating interval of 2 μm or more and 4 μm or less). The impurity concentration of the n-type region 3 and p-type region 4 of the first parallel pn layer 5 is, for example, 2.0E+16 / cm³. 3 Above and 5.0E+16 / cm 3 The widths w21 and w22 of the n-type region 23 and p-type region 24 of the second parallel pn layer 25 are, for example, 0.7 μm or more and 1.5 μm or less (with a repeating interval of 1.4 μm or more and 3 μm or less). The impurity concentration of the n-type region 23 and p-type region 24 of the second parallel pn layer 25 is, for example, 1.0E+16 / cm³. 3 Above and 4.0E+16 / cm 3The widths w31 and w32 of the n-type region 33 and p-type region 34 of the third parallel pn layer 35 are, for example, 1.5 μm (with a repeating interval of 3.0 μm). The impurity concentration of the n-type region 33 and p-type region 34 of the third parallel pn layer 35 is, for example, 2.0E+16 / cm³. 3 Above and 5.0E+16 / cm 3 the following.

[0170] Next, the manufacturing method of the semiconductor device 50 according to Embodiment 1 will be described. Figure 6 This is a flowchart illustrating an outline of a method for manufacturing a semiconductor device according to Embodiment 1. Figures 7-13 This is a cross-sectional view showing the state of the semiconductor device during manufacturing according to Embodiment 1. Figure 14 , Figure 15 This is a top view showing the parallel pn layers during the manufacturing process of the semiconductor device of Embodiment 1, viewed from the front side of the semiconductor substrate. Figures 7-13 The state of active region 10 is shown in the figure. (Refer to...) Figure 2 This describes the state of the edge terminal area 20 and the middle area 30.

[0171] First, such as Figure 7 As shown, preparing to become n + n of type leak region 1 + Substrate (semiconductor wafer) 41. Next, in n + On the front side of the n-type substrate 41, an n-type epitaxial layer 42, forming an n-type buffer zone 2, is deposited (formed) by epitaxial growth (step S1). Next, on the n-type epitaxial layer 42, a first layer of n-type buffer zone 2 is formed by epitaxial growth to a predetermined thickness. - The epitaxial layer 43a is deposited as part of the epitaxial layer 43 constituting the first to third parallel pn layers 5, 25, 35 (step S2).

[0172] Next, in n - An ion implantation mask 61 is formed on the epitaxial layer 43a. The ion implantation mask 61 has openings corresponding to the formation regions of the n-type regions 3 of the first parallel pn layer 5, the n-type regions 23 of the second parallel pn layer 25 (not shown), and the n-type regions 33 of the third parallel pn layer 35 (not shown). The ion implantation mask 61 is, for example, a photoresist film. The width of the opening 61a of the ion implantation mask 61 (opening width) is narrower in the edge terminal region 20 than in the active region 10 and the intermediate region 30 (the same applies to the ion implantation masks 63, 65, and 67 described later).

[0173] Next, using ion implantation mask 61 as a mask, a first ion implantation 62 is performed on an n-type impurity, such as phosphorus (P), (step S3). Through this first ion implantation 62, n-type impurities are implanted in the active region 10, the edge terminal region 20, and the intermediate region 30. - n-type impurity implantation regions 3a are selectively formed on the surface regions of the epitaxial layer 43a at predetermined repeating intervals. Figure 7 In the diagram, the n-type impurity injection region 3a is represented by a dashed line (in...). Figures 8-11 The same applies to the n-type impurity implantation region. Then, the ion implantation mask 61 is removed.

[0174] Next, as Figure 8 As shown, in n - An ion implantation mask 63 is formed on the epitaxial layer 43a. The ion implantation mask 63 has openings corresponding to the formation regions of the p-type region 4 of the first parallel pn layer 5, the p-type region 24 of the second parallel pn layer 25 (not shown), and the p-type region 34 of the third parallel pn layer 35 (not shown). The openings 63a of the ion implantation mask 63 are offset in one direction (column offset direction C) by a predetermined offset amount d, such that a portion of each different n-type impurity implantation region 3a is exposed at each opening 63a.

[0175] In the second parallel pn layer 25 of the edge terminal region 20, an ion implantation mask 63 is formed without shifting the position of the opening 63a of the formation region (not shown) of the p-type region 24. Similarly, for the outermost p-type region 34 of the intermediate region 30 (on the edge terminal region 20 side), an ion implantation mask 63 is also formed without shifting the position of the opening 63a of the formation region (not shown) of the p-type region 34. The width of the opening 63a in the edge terminal region 20 is narrower than the widths of the openings 63a in the active region 10 and the intermediate region 30.

[0176] Next, using ion implantation mask 63 as a mask, a second ion implantation 64 is performed to implant p-type impurities such as boron (B) (step S4). Through this second ion implantation 64, p-type impurities such as boron (B) are implanted in the active region 10, the edge terminal region 20, and the intermediate region 30. - The surface regions of the epitaxial layer 43a are selectively formed with p-type impurity implantation regions 4a at predetermined repeating intervals. The p-type impurity implantation regions 4a are formed such that a portion overlaps with the n-type impurity implantation regions 3a by a predetermined offset amount d as described above.

[0177] Therefore, in n -The surface region of the epitaxial layer 43a has overlapping portions of the n-type impurity implantation region 3a and the p-type impurity implantation region 4a, as well as portions where the n-type impurity implantation region 3a and the p-type impurity implantation region 4a are separated from each other. Figure 8 In the diagram, a thicker dashed line than that used in the n-type impurity implantation region 3a is used to represent the p-type impurity implantation region 4a (in...). Figures 9-11 (The same applies to the p-type impurity implantation region). Then, remove the ion implantation mask 63. The steps of step S3 and step S4 can be interchanged.

[0178] Here, n is formed by multiple layers of strata, which will only become the first to third parallel pn layers 5, 25, and 35. - Among the epitaxial layers 43a to 43e, n formed in the first layer - The example will be illustrated by setting a portion of the p-type region 4 and p-type region 34 of the p-type epitaxial layer 43a to be offset in the column offset direction C by a predetermined offset amount d. Furthermore, in the n layers after the second layer... - In the case where a portion of the p-type region 4 and p-type region 34 are offset by a predetermined offset amount d in the nematic offset direction C of the epitaxial layer (Embodiment 2, see reference 34) Figure 16 The process can be repeated in groups of steps S2 to S4 according to the number of layers.

[0179] Next, as Figure 9 As shown, in n - On the epitaxial layer 43a, a second layer n is grown to a predetermined thickness via epitaxial growth. - The epitaxial layer 43b is deposited as part of the epitaxial layer 43 constituting the first to third parallel pn layers 5, 25, 35 (step S5). Next, in n - On the epitaxial layer 43b, an ion implantation mask 65 is formed using the same mask pattern as the ion implantation mask 61 used in step S3. The symbol 65a represents the opening of the ion implantation mask 65.

[0180] Next, using ion implantation mask 65 as a mask, a third ion implantation 66 is performed on n-type impurities, such as phosphorus (step S6). Through this third ion implantation 66, n-type impurities are thus implanted. - The surface region of the epitaxial layer 43b is respectively connected to the underlying n layer. - An n-type impurity implantation region 3b is selectively formed at an opposite position along the depth direction Z within the n-type epitaxial layer 43a. Then, the ion implantation mask 65 is removed.

[0181] Next, as Figure 10 As shown, in n -An ion implantation mask 67 is formed on the epitaxial layer 43b. The ion implantation mask 67 has openings corresponding to the formation regions of the p-type region 4 of the first parallel pn layer 5, the p-type region 24 of the second parallel pn layer 25 (not shown), and the p-type region 34 of the third parallel pn layer 35 (not shown). The openings 67a of the ion implantation mask 67 are not offset in the column offset direction C. The openings 67a of the ion implantation mask 67 expose the n-type impurity implantation regions 3b located between adjacent n-type impurity implantation regions 3b. - Type epitaxial layer 43b.

[0182] Next, using ion implantation mask 67 as a mask, a fourth ion implantation 68 is performed to implant p-type impurities such as boron (step S7). Through this fourth ion implantation 68, p-type impurities such as boron are implanted in the active region 10, the edge terminal region 20, and the intermediate region 30. - p-type impurity implantation regions 4b are selectively formed on the surface regions of the n-type epitaxial layer 43b at predetermined repeating intervals. The p-type impurity implantation regions 4b are formed between adjacent n-type impurity implantation regions 3b and do not overlap with them. The steps of step S6 and step S7 can be interchanged.

[0183] Next, as Figure 11 As shown, in n - On the epitaxial layer 43b, multiple layers (e.g., three layers) are further deposited through epitaxial growth. - The epitaxial layers 43c to 43f form an n-type layer. - Epitaxial layers 43 of a predetermined thickness are formed by epitaxial layers 43a to 43f. At this time, n... - Type epitaxial layers 43c~43e, each stack of n - The epitaxial layers 43c to 43e are then subjected to a series of processes, with steps S5 to S7 performed repeatedly. Figure 6 In this process, arrows pointing from step S7 to step S5 are used to indicate the repetition of steps S5 to S7 as a group.

[0184] Therefore, in n - Type epitaxial layers 43c to 43e, respectively, are connected to the second layer n along the depth direction Z. - The n-type impurity implantation regions 3b within the epitaxial layer 43b overlap at the same position, so that each n-type impurity implantation region 3c~3e is formed in an overlapping manner along the depth direction Z. - Type epitaxial layers 43c to 43e, respectively, are connected to the second layer n along the depth direction Z. -The p-type impurity implantation regions 4b in the epitaxial layer 43b overlap at the same position, so that each p-type impurity implantation region 4c to 4e overlaps along the depth direction Z.

[0185] n becomes the epitaxial layer 43 - Among the epitaxial layers 43a to 43f, the uppermost n layer - The epitaxial layer 43f may not require third and fourth ion implantation 66 and 68. Alternatively, third and fourth ion implantation 66 and 68 may be performed on a portion (e.g., edge termination region 20) to allow the parallel pn layers to reach the front side of the semiconductor substrate 40. Through the processes up to this point, epitaxial layers 42 and 43 are sequentially deposited on an n-type substrate. + n of type leak region 1 + Semiconductor substrate (semiconductor wafer) 40 on the front side of substrate 41.

[0186] Next, as Figure 12 As shown, n is made more resistant to heat treatment. - Impurity diffusion within the n-type epitaxial layers 43a-43e (step S8). Each n-type impurity implantation region 3a-3e and each p-type impurity implantation region 4a-4e diffuses in a generally cylindrical shape around an ion implantation site that is approximately linear and parallel to the second direction Y. As a result, the n-type impurity implantation regions 3a-3e are interconnected along the depth direction Z to form n-type regions 3, 23, and 33, and the p-type impurity implantation regions 4a-4e are interconnected along the depth direction Z to form p-type regions 4, 24, and 34.

[0187] The first layer n after the process in step S8 - The epitaxial layer 43a has a wide portion 73 of the overlap width w3 between the n-type impurity implantation region 3a and the p-type impurity implantation region 4a, and a narrow portion 74 of the overlap width w4 between the n-type impurity implantation region 3a and the p-type impurity implantation region 4a. Figure 15 The reason is that in step S4, the p-type impurity injection region 4a is formed at a position deviating from the predetermined offset amount d. This results in the formation of an n-type region 3 and a p-type region 4 with asymmetrical impurity concentration tilt in the first direction X (see reference). Figure 5 The p-type impurity injection region 4a can also diffuse into the n-type buffer zone 2.

[0188] Additionally, the n layers from the second to the fifth layer after step S8. - In the epitaxial layers 43b-43e, the overlap widths w1 and w2 of the portions 71 and 72 of the p-type impurity implantation regions 4b-4e overlapping with the n-type impurity implantation regions 3b-3e on both sides through thermal diffusion in the first direction X are all equal. Figure 14The reason is that in steps S6 and S7, the n-type impurity injection regions 3b-3e and p-type impurity injection regions 4b-4e are formed in a manner that prevents them from overlapping. This results in the formation of n-type regions 3 and p-type regions 4 with symmetrical impurity concentration inclination in the first direction X (see reference). Figure 4 ).

[0189] Furthermore, in steps S3, S4, S6, and S7, the first to fourth ion implantations 62, 64, 66, and 68 are not performed between the end of the semiconductor substrate 40 and the second parallel pn layer 25, but are instead performed with the deposited n... - When the epitaxial layer is 43, the same impurity concentration remains as n. - The portion of the drift region 43'. In addition, during the process of step S4, the innermost p-type regions 34 (34a, 34b) disposed on the first direction X of the third parallel pn layer 35 are also formed with the same offset d and column offset direction C as the p-type regions 4 of the first parallel pn layer 5.

[0190] Next, as Figure 13 As shown, using conventional methods, in the active region 10, in n - The epitaxial layer 43f is formed by p - Type base region 6, n + The front-side element structure, consisting of the source region 7, trench 8, gate insulating film 9, and gate electrode 11, and / or source electrode 13, is formed (step S9). Additionally, in step S9, p... -- Type 21, p of reducing surface electric field region - The structure includes a channel cutoff region 22, a LOCOS film 26, a gate polysilicon layer 27, a channel cutoff electrode 28, and a gate metal layer 29.

[0191] At this time, the gate polysilicon layer 27 is formed simultaneously with the gate electrode 11, for example, by leaving a portion of the polysilicon layer deposited to form the gate electrode 11 on the front side of the semiconductor substrate 40. For example, after the gate electrode 11 and the gate polysilicon layer 27 are formed, p - The base region 6 is formed by ion implantation using these gate electrodes 11 and the gate polysilicon layer 27 as an ion implantation mask. - Type 22 channel cutoff section can be connected with p - The same ion implantation was performed simultaneously in the base region 6.

[0192] The source electrode 13, the channel cutoff electrode 28, and the gate metal layer 29 are formed simultaneously in a manner that the same metal film (or metal laminate) pattern deposited on the front side of the semiconductor substrate 40 is formed into a predetermined pattern. Next, the drain electrode 14 and other back-side element structures are formed on the back side of the semiconductor substrate 40 using conventional methods (step S10). Subsequently, the semiconductor substrate (semiconductor wafer) is cut (slit) to monolithically form individual chips, thereby completing the process. Figures 1-5 The superjunction MOSFET shown.

[0193] As described above, according to Embodiment 1, the configuration is as follows: the impurity concentration slope of the n-type and p-type regions of the first parallel pn layer in the active region is symmetrical about the peak position of the impurity concentration along the first direction in the source-side portion, and asymmetrical about the peak position along the first direction in the drain-side portion, with the peak position shifted in the first direction. Since the positions of the n-type and p-type regions of the first parallel pn layer are shifted along the first direction by a predetermined offset without changing the impurity concentration and / or area (width), the charge balance does not collapse. Therefore, the decrease in breakdown voltage BVdss can be suppressed without disrupting the charge balance of the n-type and p-type regions of the first parallel pn layer. In addition, although the condition of a p / n ratio of 1, which causes a sharp decrease in avalanche tolerance (described later), is avoided in the past, and the condition of a p-rich side with a high p / n ratio for avalanche tolerance is used, even when the condition of a p / n ratio of 1 is used in this embodiment, the avalanche tolerance does not decrease sharply. Therefore, by using a p / n ratio that does not collapse the charge balance, the on-resistance can be reduced.

[0194] In addition, by offsetting the positions of the drain-side portions of the n-type and p-type regions of the first parallel pn layer along the first direction by a predetermined offset, a steep portion with a steep impurity concentration gradient can be locally formed on the drain-side portion of the first parallel pn layer, and the site of avalanche breakdown can be induced to the drain side of the first parallel pn layer, thereby suppressing the decrease in withstand voltage. Furthermore, as a component of n... + Source region, p - The p-type base region and the n-type buffer region constitute the basis of the npn parasitic bipolar transistor. - The base region is able to carry avalanche current through the resistive component (drift resistance) of the p-type region of the first parallel pn layer, thus suppressing the reduction of avalanche tolerance.

[0195] (Implementation Method Two)

[0196] Next, the structure of the semiconductor device according to Embodiment 2 will be described. Figure 16This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 2. The layout of the semiconductor device 80 according to Embodiment 2, viewed from the front side of the semiconductor substrate 40, is similar to that of the semiconductor device 50 according to Embodiment 1 (see reference). Figure 1 )same.

[0197] The semiconductor device 80 of Embodiment 2 differs from the semiconductor device 50 of Embodiment 1 in that it is configured to have two or more n layers - The n-type region 3 and p-type region 4 of the epitaxial layer exhibit asymmetric impurity concentration tilt along the first direction X. Figure 16 The diagram shows the n layers formed by the accumulation of multiple stratigraphic units that constitute the first to third parallel pn layers 5, 25, and 35. - n in the first and second layers of epitaxial layers 43a to 43e - The n-type region 3 and p-type regions 4 and 34 of the epitaxial layers 43a and 43b are configured to have an asymmetrical impurity concentration tilt in the first direction X.

[0198] As in implementation method two, in multiple layers of n - In the case where the epitaxial layer forms an n-type region 3 and a p-type region 4, 34 with asymmetrical impurity concentration tilt in the first direction X, the n-type region containing the first layer... - Type epitaxial layer 43a, and along the depth direction Z and n - The number of consecutive adjacent layers n in type epitaxial layer 43a - The epitaxial layer forms an n-type region 3 and p-type regions 4 and 34 with asymmetric impurity concentration tilt in the first direction X. At this point, the configuration is such that in all these n-type layers... - The type of epitaxial layer makes the offset d and the column offset direction C the same.

[0199] The manufacturing method of the semiconductor device 80 in Embodiment 2 is as described above. It only requires that, in the manufacturing method of the semiconductor device 50 in Embodiment 1, the n-type region 3 and p-type regions 4, 34 with asymmetrical impurity concentration tilt in the first direction X are formed... - The number of epitaxial layers determines the number of steps S2 to S4 in a group (refer to...). Figure 6 That's all.

[0200] As described above, according to Embodiment 2, in n layers - In the case where the n-type region and p-type region with asymmetrical impurity concentration tilt in the first direction are formed by the epitaxial layer of the first parallel pn layer, the same effect as in Embodiment 1 can also be obtained.

[0201] (Implementation Method 3)

[0202] Next, the structure of the semiconductor device in Embodiment 3 will be described. Figure 17 This is a cross-sectional view showing the structure of the semiconductor device according to Embodiment 3. The layout of the semiconductor device 90 of Embodiment 3, viewed from the front side of the semiconductor substrate 40, is similar to that of the semiconductor device 50 of Embodiment 1 (see reference). Figure 1 )same.

[0203] The difference between the semiconductor device 90 of Embodiment 3 and the semiconductor device 50 of Embodiment 1 is that the n-type epitaxial layer 42, which will become the n-type buffer 2, is used as the epitaxial layer of the first layer forming the n-type region 93' and p-type region 94' with asymmetrical impurity concentration tilt in the first direction X of the first parallel pn layer 95.

[0204] exist Figure 17 In the epitaxial layer 43, although it is configured such that an n-type region 93 and a p-type region 94 with symmetrical impurity concentration tilt in the first direction X are formed, it is also possible to form an n-type region 93 and a p-type region 94 in the first layer of the epitaxial layer 43. - The epitaxial layer 43a has an n-type region 93 and a p-type region 94 with an asymmetric impurity concentration tilt in the first direction X.

[0205] The manufacturing method of the semiconductor device 90 in Embodiment 3 is simply the same as the manufacturing method of the semiconductor device 50 in Embodiment 1, except that steps S2 to S4 are performed as a group in the n-type epitaxial layer 42, which becomes the n-type buffer 2 (see...). Figure 6 This can be achieved by forming an n-type region 93' and a p-type region 94' with an asymmetrical impurity concentration tilt in the first direction X.

[0206] Although not specifically limited, in Embodiment 3, the thickness of the n-type buffer 2 (n-type epitaxial layer 42) is, for example, about 3.5 μm. The impurity concentration of the n-type region 93' and p-type region 94' of the first parallel pn layer 95 formed on the n-type epitaxial layer 42 is, for example, 1.0E+16 / cm³. 3 Above and 4.0E+16 / cm 3 the following.

[0207] As described above, according to Embodiment 3, when the n-type epitaxial layer that forms the n-type buffer 2 has an n-type region and a p-type region with an asymmetric impurity concentration tilt in the first direction of the first parallel pn layer, the same effect as Embodiment 1 can also be obtained.

[0208] (Example)

[0209] Next, the relationship between the ratio of impurities in the n-type region 3 and the p-type region 4 of the first parallel pn layer 5 (hereinafter referred to as the p / n ratio of the first parallel pn layer 5), and the withstand voltage BVdss, the on-resistance Ron, and the avalanche withstand capability is examined. Figure 18This is a characteristic graph illustrating the relationship between the p / n ratio of the first parallel pn layer in the embodiment and the withstand voltage BVdss and on-resistance Ron. Figure 19 This is a characteristic graph illustrating the relationship between the p / n ratio of the first parallel pn layer in the embodiment and the withstand voltage BVdss and avalanche withstand capacity.

[0210] exist Figure 18 , Figure 19 The horizontal axis shows the p / n ratio of the first parallel pn layer 5. The p / n ratio of the first parallel pn layer 5 is the ratio of the impurity mass of the p-type region 4 to the impurity mass of the n-type region 3 in the first parallel pn layer 5. Figure 18 , Figure 19 The center of the horizontal axis represents the case where the amount of impurities in the n-type region 3 and the p-type region 4 of the first parallel pn layer 5 are equal (p = n, i.e., p / n ratio = 1). The more the n-type region 3 moves to the left, the more impurities it contains (n ​​is rich, p < n), and the more the p-type region 4 moves to the right, the more impurities it contains (p is rich, p > n).

[0211] exist Figure 18 The results show the breakdown voltage BVdss and on-resistance Ron of a superjunction MOSFET (e.g., having the configuration of the semiconductor device 50 of Embodiment 1 described above, measured by varying the p / n ratio of the first parallel pn layer 5.) Figure 19 The results of measuring the withstand voltage BVdss and avalanche withstand capacity of the embodiment by varying the p / n ratio of the first parallel pn layer 5 are shown. Figure 19 The results of the withstand voltage BVdss of the embodiments and existing examples are consistent with Figure 18 The results for the withstand voltage BVdss are the same.

[0212] The embodiment consists of five epitaxial layers 43a-43e constituting the first to third parallel pn layers 5, 25, and 35, and only the n layers formed in the first layer are included. - The epitaxial layer 43a forms an n-type region 3 and a p-type region 4 with asymmetric impurity concentration tilt in the first direction X. The first layer's n... - The offset d of the p-type region 4 on the n-type epitaxial layer 43a is set to 15% of the repeating interval between the n-type region 3 and the p-type region 4.

[0213] exist Figure 18 , Figure 19 In comparison, a conventional superjunction semiconductor device 150 is described, in which an n-type region 103 and a p-type region 104 with symmetrical impurity concentration tilt in a first direction are respectively disposed on the epitaxial layer 143 constituting all layers of the parallel pn layer 105. Figure 20 , Figure 21(Hereinafter referred to as the Existing Example), the measurement results of the same items as those in the Embodiment are shown. Except for the configuration of the parallel pn layer 105 of the active region in the Existing Example, it is the same as that in the Embodiment.

[0214] according to Figure 18 The results shown, as confirmed in the embodiments, indicate that when the impurity mass of the n-type region 3 and the p-type region 4 of the first parallel pn layer 5 are equal (p / n ratio = 1) due to the asymmetric impurity concentration tilt of the n-type region 3 and p-type region 4 in the first direction X being configured in a portion of the first parallel pn layer 5, the breakdown voltage BVdss is reduced by about 10% compared to the prior art (indicated by the arrow shown by symbol D1), but the increase in on-resistance Ron is suppressed to less than 5% (in Figure 18 The arrow in the middle (indicated by symbol D2) increases avalanche tolerance by about 20% to 30% (in Figure 19 (The arrow shown by symbol D3)

[0215] In the existing example, in order to avoid problems caused by excessive charge balance between the n-type region 103 and the p-type region 104 of the parallel pn layer 105, the impurity mass of the n-type region 103 and the impurity mass of the p-type region 104 of the parallel pn layer 105 are deliberately made unequal, and the maximum withstand voltage BVdss that could have been obtained (the withstand voltage BVdss when the p / n ratio of the first parallel pn layer 105 is 1) is not used.

[0216] Therefore, it was confirmed in the embodiments that even when the withstand voltage BVdss decreases under the condition that the p / n ratio of the first parallel pn layer 5 is 1, it is possible to obtain a withstand voltage BVdss that is approximately the same as that obtained under the condition of the conventional example. Although the on-resistance itself increases somewhat under the condition that the p / n ratio is 1, the range of p / n ratios with low on-resistance can be used, which can make the on-resistance Ron lower than that of the conventional example and can increase the avalanche resistance.

[0217] The present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. For example, by forming an epitaxial layer with an asymmetric impurity concentration tilt of n-type and p-type regions in the active region in a first direction, the offset and column offset directions of all p-type regions can be made the same, and the layout of the n-type and p-type regions of the parallel pn layer as viewed from the front side of the semiconductor substrate can be modified in various ways. For example, the present invention can form a parallel pn layer having p-type regions configured in a lattice pattern and surrounding n-type regions when viewed from the front side of the semiconductor substrate.

[0218] Furthermore, in this invention, as long as the drain-side portion of the first parallel pn layer of the active region can be configured as an n-type region and a p-type region with asymmetrical impurity concentration tilt in the first direction, the parallel pn layer can be formed using a trench embedding method. This trench embedding method involves embedding epitaxial layers of different conductivity types into trenches formed in the epitaxial layer. In this case, for example, an n-type region and a p-type region with asymmetrical impurity concentration tilt in the first direction can be formed in the epitaxial layer of the first layer using a multilayer epitaxial method or a trench embedding method. Subsequently, on the epitaxial layer of the first layer, the parallel pn layer can be formed on the epitaxial layer of the second layer, which is stacked in a manner that is equal to the total thickness of the semiconductor substrate, using a trench embedding method.

[0219] Furthermore, in the above embodiments, a current sensing unit (second insulated-gate field-effect transistor) can be disposed separately from the main semiconductor element on the same semiconductor substrate as the superjunction MOSFET (first insulated-gate field-effect transistor). The current sensing unit operates under the same conditions as the main semiconductor element and has the function of detecting overcurrent (OC) flowing to the main semiconductor element. The current sensing unit has superjunction MOSFETs with the same unit cell structure as the main semiconductor element, but fewer unit cells than the main semiconductor element. This current sensing unit may have a first parallel pn layer with the same structure as the main semiconductor element.

[0220] Furthermore, in the above embodiments, although an n-type region and a p-type region with asymmetrical impurity concentration tilt in the first direction are formed by shifting the p-type region of the first parallel pn layer in the column offset direction, an n-type region and a p-type region with asymmetrical impurity concentration tilt in the first direction can also be formed by shifting the n-type region of the first parallel pn layer in the column offset direction.

[0221] Industrial availability

[0222] As described above, the semiconductor device of the present invention is useful for superjunction semiconductor devices used in power conversion devices or power supply devices for various industrial machinery.

Claims

1. A semiconductor device, characterized in that, have: First conductivity type semiconductor substrate; A first parallel pn layer is disposed on the upper surface of the semiconductor substrate, and a first first conductivity type region and a first second conductivity type region are alternately and repeatedly arranged in a first direction parallel to the upper surface of the semiconductor substrate. as well as An insulating gate structure is disposed on the upper surface of the first parallel pn layer. The impurity concentration in the first conductivity type region decreases as it moves away from the first peak position where the impurity concentration is at its maximum along the first direction to both sides. The impurity concentration slope in the first direction of the first first conductivity type region is symmetrical on both sides of the first direction, with reference to the first peak position, in the first portion extending from the upper surface of the first parallel pn layer to a predetermined depth; and in the second portion, which is closer to the lower surface of the first parallel pn layer than the first portion, the slope is different on both sides of the first direction, with reference to the first peak position. The impurity concentration in the first second conductivity type region decreases as it moves away from the second peak position where the impurity concentration is at its maximum along the first direction to both sides. The impurity concentration slope of the first second conductivity type region in the first direction is symmetrical on both sides of the first direction with reference to the second peak position in the third part from the upper surface of the first parallel pn layer to the predetermined depth, and is different on both sides of the first direction with reference to the second peak position in the fourth part, which is closer to the lower surface of the first parallel pn layer than the third part.

2. The semiconductor device according to claim 1, characterized in that, The first peak position of the first portion is the center in the first direction of the first first conductivity type region. The first peak position of the second part is located at a position offset along the first direction from the center of the first conductivity type region. The second peak position in the third part is the center in the first direction of the first second conductivity type region. The second peak position of the fourth part is located at a position offset along the first direction from the center of the first direction relative to the first second conductivity type region.

3. The semiconductor device according to claim 1, characterized in that, The offset in the first direction between the first peak position of the first part and the first peak position of the second part is more than 7% and less than 18% of the repetition spacing between the first first conductivity type region and the first second conductivity type region.

4. The semiconductor device according to claim 2, characterized in that, The offset in the first direction between the first peak position of the first part and the first peak position of the second part is more than 7% and less than 18% of the repetition spacing between the first first conductivity type region and the first second conductivity type region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The direction in which the first peak position of the second part shifts along the first direction is the same as the direction in which the second peak position of the fourth part shifts along the first direction. The direction in which the position of the first peak in the second part shifts along the first direction is the same in all the second parts. The direction in which the second peak position of the fourth part is offset along the first direction is the same in all the fourth parts.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor device further includes a second parallel pn layer surrounding the first parallel pn layer, and a second first conductivity region and a second second conductivity region are alternately and repeatedly arranged along the first direction at a spacing narrower than the repeating spacing of the first first conductivity region and the first second conductivity region. The impurity concentration in the second first conductivity type region decreases as it moves away from the third peak position where the impurity concentration is at its maximum along the first direction to both sides. The impurity concentration slope in the first direction of the second first conductivity type region is symmetrical on both sides of the first direction with reference to the position of the third peak. The impurity concentration in the second second conductivity type region decreases as it moves away from the fourth peak position where the impurity concentration is at its maximum along the first direction to both sides. The impurity concentration slope in the first direction of the second second conductivity type region is symmetrical on both sides of the first direction with reference to the position of the fourth peak.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a third parallel pn layer disposed between the first parallel pn layer and the second parallel pn layer, surrounding the periphery of the first parallel pn layer, and having a third first conductivity type region and a third second conductivity type region alternately and repeatedly arranged along a first direction at a spacing equal to the repeating spacing of the first first conductivity type region and the first second conductivity type region. The impurity concentration distribution in the third second conductivity region is the same as the impurity concentration distribution in the first second conductivity region. The impurity concentration inclination in the first direction of the third second conductivity type region, which is located on the innermost side, is the same as the impurity concentration inclination in the first direction of the first second conductivity type region.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that, A semiconductor layer of a first conductivity type is provided between the semiconductor substrate and the first parallel pn layer.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor device includes: A first insulated-gate field-effect transistor is disposed on the semiconductor substrate and has the first parallel pn layer and the insulated gate structure; and A second insulated-gate field-effect transistor is disposed on the semiconductor substrate and has a plurality of cells having the same cell structure as the first insulated-gate field-effect transistor in a manner that is fewer in number than the first insulated-gate field-effect transistor.

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