Using reconfigurable photodiodes in pixel arrays for high voltage generation

Abstract

Various embodiments of the present disclosure relate to high voltage generation using reconfigurable photodiodes in a pixel array. An imaging sensor includes a pixel array containing photodiodes that are isolated from each other by through-thickness deep trench isolation. On a row-by-row basis, row control circuitry controls which rows of the pixel array operate in an imaging mode and which rows of the pixel array operate in an energy harvesting mode. Switching circuitry selectively connects different groups of the rows of photodiodes operating in the energy harvesting mode into a forward-biased series configuration between a voltage output line and a ground line, or into a forward-biased parallel configuration between the voltage output line and the ground line.

Description

Technical Field

[0001] The present application relates to the field of photodiodes, and in particular to a reconfigurable photodiode pixel array capable of both image sensing and photovoltaic power generation. Background Art

[0002] CMOS semiconductor technology is used in a variety of applications, such as image sensors. Because such image sensors are often incorporated into portable devices (such as smartphones), they are battery-powered. However, image sensors have high energy consumption, and therefore frequent use of such image sensors can quickly deplete the battery of the device into which the image sensor is incorporated. In the case of smartphones, battery depletion is particularly undesirable because users desire both long battery life and the ability to frequently utilize the image sensor (e.g., to capture digital images or videos, use video chat applications, etc.).

[0003] Therefore, it is known to incorporate separate photovoltaic devices that harvest energy from the environment into devices containing CMOS image sensors.However, the use of separate photovoltaic devices with CMOS image sensors may undesirably increase the cost, complexity, and size of the devices into which they are incorporated.

[0004] Therefore, CMOS image sensor systems capable of harvesting energy have been developed. However, high voltage generation using these designs is area inefficient, inflexible in post-manufacturing, and involves additional circuitry (such as boost converters and charge pumps) to assist in energy harvesting. Furthermore, when using known CMOS technology, inherently formed parasitic structures impose additional disadvantages on high voltage generation, such as the creation of parasitic junction diodes formed due to the common shared substrate, which consume a large portion of the harvested power. Additionally, where low voltage generation is used to mitigate these disadvantages, new disadvantages arise, such as low operating speed and accuracy. Furthermore, where these CMOS image sensor systems capable of harvesting energy are placed behind a lens (e.g., in the case of a camera unit having a fixed pattern of CMOS imaging pixels and CMOS energy harvesting pixels), the projected image may cause shadows on the CMOS energy harvesting pixels, which reduces the generated power.

[0005] Therefore, it is clear that further development of CMOS energy harvesting technology is needed. Summary of the Invention

[0006] An imaging sensor is disclosed herein, including a pixel array, each pixel of the pixel array including a photodiode, the photodiodes being isolated from each other by through-thickness deep trench isolation. Mode selection circuitry is configured to control which groups of pixels of the pixel array operate in an imaging mode and which groups of pixels of the pixel array operate in an energy harvesting mode. Switching circuitry is configured to selectively connect different groups of the photodiodes in a row operating in the energy harvesting mode in a forward-biased series configuration between a voltage output line and a ground line, or in a forward-biased parallel configuration between the voltage output line and the ground line.

[0007] The switching circuit device can connect a given group of photodiodes into a forward biased series configuration by connecting the anode of a first photodiode of the given group to a voltage output line, connecting the anode of a second photodiode of the given group to a cathode of the first photodiode of the given group, connecting the anode of a third photodiode of the given group to a cathode of the second photodiode of the given group, connecting the anode of a fourth photodiode of the given group to a cathode of the third photodiode of the given group, and connecting the cathode of the fourth photodiode of the given group to a ground line.

[0008] The switching circuit device can connect a given group of photodiodes into a forward biased parallel configuration by connecting the anode of a first photodiode of the given group to a voltage output line, connecting the anode of a second photodiode of the given group to the cathode of the first photodiode of the given group, connecting the cathode of the second photodiode of the given group to a ground line, connecting the anode of a third photodiode of the given group to the voltage output line, connecting the anode of a fourth photodiode of the given group to the cathode of the third photodiode of the given group, and connecting the cathode of the fourth photodiode of the given group to the ground line.

[0009] The switching circuit device can connect a given group of photodiodes into a forward biased parallel configuration by connecting the anode of the first photodiode of the given group to the voltage output line and the cathode of the first photodiode of the given group to the ground line, connecting the anode of the second photodiode of the given group to the voltage output line and the cathode of the second photodiode of the given group to the ground line, connecting the anode of the third photodiode of the given group to the voltage output line and the cathode of the third photodiode of the given group to the ground line, and connecting the anode of the fourth photodiode of the given group to the voltage output line and the cathode of the fourth photodiode of the given group to the ground line.

[0010] The switching circuit device can be configured to connect at least one group of photodiodes in a row operating in the energy harvesting mode in a forward biased series configuration, and to connect at least one group of photodiodes in a row operating in the energy harvesting mode in a forward biased parallel configuration.

[0011] Each group of photodiodes may include four photodiodes.

[0012] Each row of photodiodes may be selectively switchable between an imaging mode and an energy harvesting mode.

[0013] For each first pixel of a given pixel group, the mode selection circuitry may include an imaging selection transistor and an energy harvesting selection transistor, wherein the imaging selection transistor couples an anode of a photodiode of the pixel to ground when in the imaging mode and couples a cathode of the photodiode of the pixel to ground when in the energy harvesting mode. Additionally, for each pixel of the given pixel group other than the first pixel of the given pixel group, the mode selection circuitry may include an imaging selection transistor and an energy harvesting selection transistor, wherein the imaging selection transistor couples an anode of the photodiode of the pixel to ground when in the imaging mode and couples a cathode of the photodiode of the pixel to the switch circuitry for the pixel when in the energy harvesting mode.

[0014] For each pixel of a given pixel group except the last pixel of the given pixel group, the switching circuit device may include a transfer gate and a selection transistor, wherein the transfer gate selectively couples the anode of the photodiode of the pixel to the energy collection selection transistor of the next pixel of the given pixel group; when the transfer gate does not couple the anode of the photodiode of the pixel to the energy collection selection transistor of the next pixel of the given pixel group, the selection transistor selectively couples the energy collection selection transistor of the next pixel of the given pixel group to ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram of a reconfigurable CMOS imaging array capable of capturing image data in imaging mode and harvesting power in photovoltaic mode.

[0016] Figure 2A When configured as a series connection, Figure 1 Block diagram of the reconfigurable CMOS imaging unit within the CMOS imaging array.

[0017] Figure 2B When configured as a parallel connection of two series circuits, Figure 1 Block diagram of the reconfigurable CMOS imaging unit within the CMOS imaging array.

[0018] Figure 2C When configured as parallel connections, Figure 1 Block diagram of the reconfigurable CMOS imaging unit within the CMOS imaging array.

[0019] Figure 3 yes Figure 1 A schematic diagram of a pixel group of a reconfigurable CMOS imaging unit, and a switching circuit arrangement are shown in a block diagram.

[0020] Figure 4 yes Figure 3 Schematic diagram of a pixel group of a reconfigurable CMOS imaging unit, the pixels are shown in simplified form, but the switching circuit device is shown in complete schematic form.

[0021] Figure 5 yes Figure 3 Schematic cross-sectional view of a pixel. DETAILED DESCRIPTION

[0022] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those described in detail above without departing from the spirit and scope of the present disclosure. The present disclosure is not intended to be limited to the embodiments shown, but should be given the widest scope consistent with the principles and features disclosed or suggested herein.

[0023] Imaging sensor 100 is now described. Imaging sensor 100 includes a pixel array 101 formed on a substrate. Row control circuitry 104 and switching circuitry 105 are also formed on the substrate. Thus, the image sensor may be an integrated circuit chip formed using CMOS technology.

[0024] Pixel array 101 is an array of imaging pixels, each of which includes a photodiode that is isolated from one another by full-thickness deep trench isolation formed in the substrate and an isolation layer of the integrated circuit chip.

[0025] Row control circuitry 104 controls which rows of pixel array 101 have their photodiodes reverse biased to operate in imaging mode, and controls which rows of pixel array 101 have their photodiodes forward biased to operate in energy harvesting mode (row control circuitry 104 drives EH and IM lines (described below). As illustrated, some rows 102 may operate in energy harvesting mode while other rows 103 operate in imaging mode, meaning that some portions of pixel array 101 may be performing image capture while (simultaneously) other portions of pixel array 101 are harvesting energy.

[0026] The rows 102 operating in energy harvesting mode are arranged into groups of four pixels (each pixel containing a photodiode isolated by full-thickness deep trench isolation), with n such groups in the x-direction and m such groups in the y-direction, it being understood that n and m can be any number and that m can be dynamically selectable by the row control circuitry 104. The groups are arranged into m group rows. For example, here, there are group rows 110a...110m. Group row 110a contains groups 110a1...110an, and group row 110m contains groups 110m1...110mn. Each group contains four pixels arranged in a square. For example, group 110a1 contains pixels PV1-PV4. As will be shown later, each pixel includes a corresponding photodiode (e.g., pixel PV1 includes photodiode D1, pixel PV2 includes photodiode D2, pixel PV3 includes photodiode D3, and pixel PV4 includes photodiode D4).

[0027] The photodiodes in pixels from different groups 110 share the same cathode and anode lines, i.e., all pixels PV1 in groups 110a1 to 110an are connected to nodes PV1C and GND / PV1A. Similarly, for the other pixels PV2-PV4 in these groups, the cathode and anode lines are shared, i.e., all pixels PV2-PV4 in groups 110a1 to 110an are connected to nodes PVxC and GND / PVxA (for PV2, x is 2; for PV3, x is 3; for PV4, x is 4).

[0028] All pixels PV1 in groups 110m1 to 110mn will share the node PVm1C and the node GND / PVm1A. Similarly, for the other pixels PV2-PV4, the nodes PVmxC and GND / PVmxA are shared and connected to the switching circuit device 105.

[0029] Switching circuitry 105 selectively controls the interconnections between shared nodes PVxC and GND / PVxA, PVmxC and GND / PVmxA, and GND and a single VOUT. Switches 160 , 161 , 162 and transistors MN17 , MN19 , MN21 , MN23 , MP9 , MP10 , MP11 , and MP12 are part of block 105 .

[0030] exist Figures 2A to 2C Examples of different ways in which a group of photodiodes can be arranged by the switching circuitry 105 are shown in FIG. Figure 2AInitially, the photodiodes may be coupled in series between the voltage output line VOUT and ground. In more detail, the anode of photodiode D1 is coupled to the voltage output line VOUT, the anode of photodiode D2 is coupled to the cathode of photodiode D1, the anode of photodiode D3 is coupled to the cathode of photodiode D2, the anode of photodiode D4 is coupled to the cathode of photodiode D3, and the cathode of photodiode D4 is coupled to ground. Therefore, note that this means Figure 2A The photodiodes D1-D4 shown in FIG are forward biased. In addition, there is isolation between all anodes and all cathodes of the diodes D1-D4, which is achieved using full-thickness deep trench isolation.

[0031] Continue to Figure 2B In the example shown in , the photodiodes can be arranged in two series strings coupled in parallel. More specifically, the anode of photodiode D1 is coupled to the voltage output line VOUT, the anode of photodiode D3 is coupled to the cathode of photodiode D1, and the cathode of photodiode D3 is coupled to ground, while the anode of photodiode D2 is coupled to the voltage output line VOUT, the anode of photodiode D4 is coupled to the cathode of photodiode D2, and the cathode of photodiode D4 is coupled to ground. Therefore, it is noted that photodiodes D1 and D3 are coupled in series, and then coupled in parallel with the series-coupled photodiodes D2 and D4. Figure 2B The photodiodes D1-D4 shown in FIG are forward biased.

[0032] Continue to Figure 2C In the example shown in , the photodiodes can be coupled in parallel with each other between the voltage output line VOUT and the ground. In more detail, the anodes of the photodiodes D1-D4 are coupled to the voltage output line VOUT, and the cathodes of the photodiodes D1-D4 are coupled to the ground. Figure 2C The photodiodes D1-D4 shown in FIG are forward biased.

[0033] For the group at row 110, from Figures 2A to 2C In the arrangement shown in , the switch circuit device 105 can select or change the voltage generated at the voltage output line VOUT through dynamic selection. Note that in some embodiments, each row 110 is intended to have the same selected arrangement, but this is not necessary in other embodiments. Moreover, the row control circuit device 104 can select the physical location of the energy harvesting pixels, thereby allowing rows that are obscured by the image projected onto those rows by the lens covering the imaging sensor 100 to be avoided, and allowing rows on which unobstructed light is incident to be selected.

[0034] Switch control circuitry 105 outputs a VOUT line. In a device into which imaging sensor 100 is incorporated, output voltage VOUT may be used for any desired purpose.

[0035] Although the groups above have been shown as groups of four, it should be understood that a group can be any number of pixels, such as two, six, or eight pixels, and that the switching circuitry 105 can couple the photodiodes of these pixels into any suitable series, parallel, or series-parallel combination, respectively. Further, although group rows have been shown as each containing two rows, group rows can contain any number of group rows, meaning that a group can be any number of pixels in any arrangement.

[0036] Now refer to Figure 3 An example electrical configuration of pixel group 110a1 is described, with the understanding that the same electrical configuration may also be used for other pixel groups.Pixel group 110a1 includes pixels PV1-PV4.

[0037] Pixel PV1 includes an n-channel transistor MN1 having a source coupled to the PV1C line, a drain coupled to the node N1, and a gate coupled to the EH line. Photodiode D1 has its anode coupled to the GND / PV1A line and its cathode coupled to the node N1. N-channel transistor MN30 has its source coupled to the node N2, its drain coupled to the node N1, and its gate coupled to the RST line. P-channel transistor MP2 has its source coupled to the supply voltage VDD, its drain coupled to the node N2, and its gate coupled to the VSEL line. N-channel transistor MN2 has its source coupled to ground, its drain coupled to the node N2, and its gate coupled to the node N1. N-channel transistor MN3 has its source coupled to ground, its drain coupled to the source of n-channel transistor MN4, and its gate coupled to the node N2. N-channel transistor MN4 has its source coupled to the line COL. <11> A drain of the n-channel transistor MN3, a source thereof coupled to the drain of the n-channel transistor MN3, and a gate thereof coupled to the RD line.

[0038] Pixel PV2 includes an n-channel transistor MN5 having a source coupled to the PV2C line, a drain coupled to the node N3, and a gate coupled to the EH line. Photodiode D2 has its anode coupled to the GND / PV2A line and its cathode coupled to the node N3. N-channel transistor MN31 has its source coupled to the node N4, its drain coupled to the node N3, and its gate coupled to the RST line. P-channel transistor MP4 has its source coupled to the supply voltage VDD, its drain coupled to the node N4, and its gate coupled to the VSEL line. N-channel transistor MN6 has its source coupled to ground, its drain coupled to the node N4, and its gate coupled to the node N3. N-channel transistor MN7 has its source coupled to ground, its drain coupled to the source of n-channel transistor MN8, and its gate coupled to the node N4. N-channel transistor MN8 has its source coupled to the line COL. <12> A drain of the n-channel transistor MN7, a source thereof coupled to the drain of the n-channel transistor MN7, and a gate thereof coupled to the RD line.

[0039] Pixel PV3 includes an n-channel transistor MN9 having a source coupled to the PV3C line, a drain coupled to the node N5, and a gate coupled to the EH line. Photodiode D3 has its anode coupled to the GND / PV3A line and its cathode coupled to the node N5. N-channel transistor MN13 has its source coupled to the node N6, its drain coupled to the node N5, and its gate coupled to the RST line. P-channel transistor MP6 has its source coupled to the supply voltage VDD, its drain coupled to the node N6, and its gate coupled to the VSEL line. N-channel transistor MN10 has its source coupled to ground, its drain coupled to the node N6, and its gate coupled to the node N5. N-channel transistor MN11 has its source coupled to ground, its drain coupled to the source of n-channel transistor MN12, and its gate coupled to the node N6. N-channel transistor MN12 has its source coupled to the line COL. <21> A drain of the n-channel transistor MN11 is coupled to a source thereof, a drain of the n-channel transistor MN11 is coupled to a drain of the n-channel transistor MN11, and a gate thereof is coupled to the RD line.

[0040] Pixel PV4 includes an n-channel transistor MN13 having a source coupled to the PV4C line, a drain coupled to the node N7, and a gate coupled to the EH line. Photodiode D4 has its anode coupled to the GND / PV4A line and its cathode coupled to the node N7. N-channel transistor MN33 has its source coupled to the node N8, its drain coupled to the node N7, and its gate coupled to the RST line. P-channel transistor MP8 has its source coupled to the supply voltage VDD, its drain coupled to the node N8, and its gate coupled to the VSEL line. N-channel transistor MN14 has its source coupled to ground, its drain coupled to the node N8, and its gate coupled to the node N7. N-channel transistor MN15 has its source coupled to ground, its drain coupled to the source of n-channel transistor MN16, and its gate coupled to the node N8. N-channel transistor MN16 has its source coupled to the line COL. <22> A drain of the n-channel transistor MN15, a source thereof coupled to the drain of the n-channel transistor MN15, and a gate thereof coupled to the RD line.

[0041] Note that in some designs, n-channel transistors MN1, MN5, MN9, and MN13 may be replaced with PMOS transistors or CMOS transmission gates.

[0042] When group row 110a is to operate in imaging mode, row control circuitry 104 drives the EH line low and the IM line high to turn off n-channel transistors MN1, MN5, MN9, and MN13 and turn on n-channel transistors MN17, MN19, MN21, and MN23 (in the case of a 100A transistor). Figure 4 Since the focus of the present disclosure is on the energy harvesting mode, for the sake of brevity, the description of the group row 110a in the imaging mode will not be further described.

[0043] In energy harvesting mode, row control circuitry 104 drives the EH line high to turn on n-channel transistors MN1, MN5, MN9, and MN13, and drives the IM line low. Additionally, the RST line is driven low to turn off n-channel transistors MN30, MN31, MN32, and MN33, and the VSEL line is driven high to turn off p-channel transistors MP2, MP4, MP6, and MP8.

[0044] In energy harvesting mode, the switching circuit device 151 appropriately interconnects the various PV1C, PV2C, PV3C and PV4C lines and the GND / PV1A, GND / PV2A, GND / PV3A, GND / PV4A lines to electrically connect the pixels PV1-PV4 in the above-mentioned series, parallel or series-parallel configurations.

[0045] Additional references Figure 4 , the structure and function of the switching circuit device 151 will be described in the context of the pixel group 110a1. Here, it is noted that the structure of the pixels PV1-PV4 is simplified, and transistors not relevant to the energy harvesting mode are not shown, so that the rest of the structure can be more clearly shown and understood. Pixel PV1 can be referred to as the "first pixel" in the pixel group 110a1, and pixel PV4 can be referred to as the "last pixel" in the pixel group 110a1.

[0046] The structure of pixel PV1 is as described above. Figure 3 However, here, it is shown that switching circuit device 151 includes n-channel transistor MN17, which has its source coupled to ground, its drain coupled to the GND / PV1A line, and its gate coupled to the IM line. P-channel transistor MP9 has its source coupled to the VOUT line, its drain coupled to the GND / PV1A line, and its gate coupled to control signal A.

[0047] The structure of pixel PV2 is as above Figure 3 As described above, switching circuitry 151 is shown as further comprising a transmission gate 160 that operates based on a Boolean OR operation performed on control signal B and control signal C to selectively couple the GND / PV1A line to the drain of n-channel transistor MN18. N-channel transistor MN18 has its drain coupled to the output of transmission gate 160, its source coupled to ground, and its gate coupled to control signal A. N-channel transistor MN19 has its source coupled to ground, its drain coupled to the GND / PV2A line, and its gate coupled to the IM line. P-channel transistor MP10 has its source coupled to the VOUT line, its drain coupled to the GND / PV2A line, and its gate coupled to the result of the Boolean OR operation performed on control signal A and control signal B.

[0048] The structure of pixel PV3 is as above Figure 3As described above. However, here, it is shown that switching circuit device 151 also includes a transmission gate 161 that operates based on control signal C to selectively couple the GND / PV2A line to the drain of n-channel transistor MN20. N-channel transistor MN20 has its drain coupled to the output of transmission gate 161, its source coupled to ground, and its gate coupled to the result of the Boolean OR operation performed on control signal A and control signal B. N-channel transistor MN21 has its source coupled to ground, its drain coupled to the GND / PV3A line, and its gate coupled to the IM line. P-channel transistor MP11 has its source coupled to the VOUT line, its drain coupled to the GND / PV3A line, and its gate coupled to control signal A.

[0049] The structure of pixel PV4 is as above Figure 3 As described above, switching circuitry 151 is shown here as further including a transmission gate 162 that operates based on a Boolean OR operation performed on control signal B and control signal C to selectively couple the GND / PV3A line to the drain of n-channel transistor MN22. N-channel transistor MN22 has its drain coupled to the output of transmission gate 162, its source coupled to ground, and its gate coupled to control signal A. N-channel transistor MN23 has its source coupled to ground, its drain coupled to the GND / PV4A line, and its gate coupled to the IM line. P-channel transistor MP12 has its source coupled to the VOUT line, its drain coupled to the GND / PV4A line, and its gate coupled to the result of the Boolean OR operation performed on control signal A, control signal B, and control signal C.

[0050] The following table illustrates the states of control signals A, B, and C for placing pixels PV1-PV4 into series, parallel, or series-parallel configurations as described above. The states of these control signals may be programmed into the switching circuitry 105.

[0051] model Control signal A Control signal B Control signal C Series 0 0 1 in parallel 1 0 0 Series-Parallel 0 1 0

[0052] The operation of the switching circuit arrangement 151 and the pixel group 110a1 in the energy harvesting mode will now be described. In the energy harvesting mode, the EH signal is driven high, turning on the n-channel transistors MN1, MN5, MN9, and MN13, while the IM signal is driven low, turning off the n-channel transistors MN17, MN19, MN21, and MN23.

[0053] In order to connect the pixels PV1-PV4 in series and thus the photodiodes D1-D4 in series ( Figure 2A), control signal A and control signal B are driven low, while control signal C is driven high. This has the effect of turning on transmission gates 160-162, turning off p-channel transistors MP9, MP10, and MP11, turning on p-channel transistor MP12, turning off n-channel transistors MN18, MN20, and MN22, and turning on n-channel transistors MN1, MN5, MN9, and MN13. As a result, photodiodes D1-D4 are connected in series and forward biased between ground and VOUT. When light is incident on photodiodes D1-D4, a current path is formed between ground and VOUT through n-channel transistor MN1, photodiode D1, transmission gate 160, n-channel transistor MN5, photodiode D2, transmission gate 161, n-channel transistor MN9, photodiode D3, transmission gate 162, n-channel transistor MN13, photodiode D4, and p-channel transistor MP12. Note that here, pixels PV2-PV4 can all be considered to be in "interconnected mode" because the cathodes of their diodes D3-D4 are all connected to the anodes of diodes D1-D3 of the previous pixels PV1-PV3. For example, the cathode of photodiode D2 is connected to the anode of photodiode D1 through transistor MN5 and transfer gate 160, the cathode of photodiode D3 is connected to the anode of photodiode D2 through transistor MN9 and transfer gate 161, and the cathode of photodiode D4 is connected to the anode of photodiode D3 through transistor MN13 and transfer gate 162.

[0054] In order to connect the pixels PV1-PV4 in parallel and thus the photodiodes D1-D4 in parallel ( Figure 2C), control signal A is driven high, while control signals B and C are driven low. This has the following effects: transmission gates 160-162 are turned off, p-channel transistors MP9, MP10, MP11, and MP12 are turned on, and n-channel transistors MN1, MN18, MN5, MN20, MN9, MN22, and MN13 are turned on. As a result, photodiodes D1-D4 are connected in parallel with each other and forward biased between ground VOUT. When light is incident on photodiodes D1-D4, four current paths are formed. A first current path is formed between ground and VOUT through n-channel transistor MN1, photodiode D1, and p-channel transistor MP9. A second current path is formed between ground and VOUT through n-channel transistor MN18, n-channel transistor MN5, photodiode D2, and p-channel transistor MP10. A third current path is formed between ground and VOUT through n-channel transistor MN20, n-channel transistor MN9, photodiode D3, and p-channel transistor MP11. A fourth current path is formed between ground and VOUT through n-channel transistor MN22, n-channel transistor MN13, photodiode D4, and p-channel transistor MP12. Note that here, pixels PV1-PV4 can each be considered to be in "isolation mode" because the cathodes of their diodes D1-D4 are not connected to the anodes of any other diodes, but are instead connected to ground through transistors MN1, MN5, MN18, MN9, MN20, MN13, and MN22.

[0055] In order to connect the pixels PV1-PV4 in series-parallel and thus the photodiodes D1-D4 in series-parallel ( Figure 2B), control signal B is driven high, while control signals A and C are driven low. This has the effect of turning on transfer gates 160 and 162 while turning off transfer gate 161, turning off p-channel transistors MP9 and MP11, turning off n-channel transistors MN18 and MN22, turning on n-channel transistors MN1, MN5, MN20, MN9, and MN13, and turning on p-channel transistors MP10 and MP12. As a result, photodiodes D1 and D3 are connected in series and forward biased between ground and VOUT, photodiodes D2 and D4 are connected in series and forward biased between ground and VOUT, and the series combination of D1 and D3 is connected in parallel with the series combination of D2 and D4. When light is incident on photodiodes D1-D4, two current paths are formed. A first current path is formed between ground and VOUT via n-channel transistor MN1, photodiode D1, transfer gate 160, n-channel transistor MN5, photodiode D2, and p-channel transistor MP10. A second current path is formed between ground and VOUT via n-channel transistors MN20 and MN9, photodiode D3, transfer gate 162, n-channel transistor MN13, photodiode D4, and p-channel transistor MP12. Note that pixels PV2 and PV4 can both be considered to be in "interconnected mode" because the cathodes of their diodes D2 and D4 are connected to the anodes of diodes D1 and D3 of pixels PV1 and PV3, respectively. For example, the cathode of photodiode D2 is connected to the anode of photodiode D1 via transistor MN5 and transfer gate 160, and the cathode of photodiode D4 is connected to the anode of photodiode D3 via transistor MN13 and transfer gate 162. Note also that pixel PV3 can be considered to be in "isolated mode" because the anode of its photodiode D3 is connected to ground via transistors MN9 and MN20.

[0056] As described above, each pixel includes a photodiode separated from the transistors of that pixel (and from other photodiodes and other pixels) by full-thickness deep trench isolation. Figure 5 A schematic cross-sectional view of pixel PV1 is shown in FIG. As can be seen, the lightly doped P- region of photodiode D1 is formed on the isolation layer and surrounded by full-thickness deep trench isolation (DTI), while the heavily doped P+ and N+ regions of D1 are formed within the lightly doped P- region of photodiode D1.

[0057] A lightly doped P-region (where the various heavily doped regions of transistors MN1 , MN2 , MN3 , MN4 , MN30 and MP2 are formed) is formed on the isolation layer and separated from the lightly doped P-region of photodiode D1 by full-thickness deep trench isolation.

[0058] Although described above for pixel PV1 of a given pixel group and Figure 5 This structure is shown in FIG, but it should be understood that each pixel of the pixel array 101 can have this structure.

[0059] While the present disclosure has been described with respect to a limited number of embodiments, those skilled in the art having benefit of this disclosure will appreciate that other embodiments are contemplated without departing from the scope of the present disclosure as disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the appended claims.

Claims

1. An imaging sensor, comprising: a pixel array, each pixel in the pixel array comprising a photodiode, the photodiodes being isolated from each other by through-thickness deep trench isolation; mode selection circuitry configured to control which groups of pixels in the pixel array operate in an imaging mode and which groups of pixels in the pixel array operate in an energy harvesting mode; as well as a switching circuit arrangement configured to selectively connect different groups of the photodiodes in a row operating in the energy harvesting mode in a forward-biased series configuration between a voltage output line and a ground line or in a forward-biased parallel configuration between the voltage output line and the ground line; wherein, for each first pixel of a given pixel group, the mode selection circuitry includes an imaging select transistor that couples an anode of the photodiode of the pixel to ground when in the imaging mode and an energy harvesting select transistor that couples a cathode of the photodiode of the pixel to ground when in the energy harvesting mode; and wherein, for each pixel of the given pixel group other than the first pixel of the given pixel group, the mode selection circuitry includes an imaging selection transistor and an energy harvesting selection transistor, the imaging selection transistor coupling an anode of the photodiode of the pixel to ground when in the imaging mode and the energy harvesting selection transistor coupling a cathode of the photodiode of the pixel to the switch circuitry for the pixel when in the energy harvesting mode; Wherein, for each pixel of the given pixel group except for the last pixel of the given pixel group, the switch circuit device comprises: a transfer gate that selectively couples the anode of the photodiode of the pixel to the energy harvesting select transistor of the next pixel of the given pixel group; as well as A select transistor selectively couples the energy harvesting select transistor of the next pixel of the given pixel group to ground when the transfer gate does not couple the anode of the photodiode of the pixel to the energy harvesting select transistor of the next pixel of the given pixel group.

2. The imaging sensor of claim 1 , wherein the switching circuitry connects a given group of photodiodes into the forward-biased series configuration by connecting the anode of a first photodiode of the given group to the voltage output line, connecting the anode of a second photodiode of the given group to the cathode of the first photodiode of the given group, connecting the anode of a third photodiode of the given group to the cathode of the second photodiode of the given group, connecting the anode of a fourth photodiode of the given group to the cathode of the third photodiode of the given group, and connecting the cathode of the fourth photodiode of the given group to the ground line.

3. The imaging sensor of claim 1 , wherein the switching circuitry connects a given group of photodiodes into the forward-biased parallel configuration by connecting an anode of a first photodiode of the given group to the voltage output line, connecting an anode of a second photodiode of the given group to a cathode of the first photodiode of the given group, connecting a cathode of the second photodiode of the given group to the ground line, connecting an anode of a third photodiode of the given group to the voltage output line, connecting an anode of a fourth photodiode of the given group to a cathode of the third photodiode of the given group, and connecting a cathode of the fourth photodiode of the given group to the ground line.

4. The imaging sensor of claim 1 , wherein the switching circuitry connects a given group of photodiodes into the forward-biased parallel configuration by connecting the anode of a first photodiode of the given group to the voltage output line and the cathode of the first photodiode of the given group to the ground line, connecting the anode of a second photodiode of the given group to the voltage output line and the cathode of the second photodiode of the given group to the ground line, connecting the anode of a third photodiode of the given group to the voltage output line and the cathode of the third photodiode of the given group to the ground line, and connecting the anode of a fourth photodiode of the given group to the voltage output line and the cathode of the fourth photodiode of the given group to the ground line.

5. The imaging sensor of claim 1 , wherein the switching circuitry is configured to connect at least one group of photodiodes in a row operating in the energy harvesting mode into the forward-biased series configuration and to connect at least one group of photodiodes in a row operating in the energy harvesting mode into the forward-biased parallel configuration.

6. The imaging sensor of claim 1, wherein each group of photodiodes comprises four photodiodes.

7. The imaging sensor of claim 1, wherein each row of photodiodes is selectively switchable between the imaging mode and the energy collection mode.

8. An imaging sensor comprising: An array of pixels divided into a plurality of pixel group rows, the pixel group rows divided into a plurality of pixel groups, wherein each pixel group comprises: The first pixel includes: a first photodiode; and mode selection circuitry that couples an anode of the first photodiode to ground when the pixel group row to which the pixel group belongs is in imaging mode, and couples a cathode of the first photodiode to ground when the pixel group row to which the pixel group belongs is in energy harvesting mode; and interconnect circuitry coupled between the pixel group and an output line; and The final pixel includes: Finally, the photodiode; and mode selection circuitry to couple a cathode of the last photodiode to ground when the pixel group row to which the pixel group belongs is in the energy harvesting mode and the last pixel is in the isolation mode; to couple the cathode of the last photodiode to the interconnect circuitry when the pixel group row to which the pixel group belongs is in the energy harvesting mode and the last pixel is in the interconnect mode; and to couple an anode of the last photodiode to ground when the pixel group row to which the pixel group belongs is in the imaging mode; wherein, for each first pixel of a given pixel group, the mode selection circuitry includes an imaging select transistor that couples an anode of the photodiode of the pixel to ground when in the imaging mode and an energy harvesting select transistor that couples a cathode of the photodiode of the pixel to ground when in the energy harvesting mode; and wherein, for each pixel of the given pixel group other than the first pixel of the given pixel group, the mode selection circuitry includes an imaging selection transistor and an energy harvesting selection transistor, wherein when in the imaging mode, the imaging selection transistor couples the anode of the photodiode of the pixel to ground, and when in the energy harvesting mode, the energy harvesting selection transistor couples the cathode of the photodiode of the pixel to the switch circuitry for the pixel; Wherein, for each pixel of the given pixel group except for the last pixel of the given pixel group, the switch circuit device comprises: a transfer gate that selectively couples the anode of the photodiode of the pixel to the energy harvesting select transistor of the next pixel of the given pixel group; and A select transistor selectively couples the energy harvesting select transistor of the next pixel of the given pixel group to ground when the transfer gate does not couple the anode of the photodiode of the pixel to the energy harvesting select transistor of the next pixel of the given pixel group.

9. The imaging sensor of claim 8, wherein the mode selection circuitry of the first pixel comprises: a first n-channel transistor having a source coupled to ground, a drain coupled to the anode of the first photodiode, and a gate coupled to an imaging select signal, the imaging select signal being asserted when the pixel group row to which the pixel group belongs is in the imaging mode, and a second n-channel transistor having a source coupled to ground, a drain coupled to the cathode of the first photodiode, and a gate coupled to an energy harvesting select signal, the energy harvesting select signal being asserted when the pixel group row to which the pixel group belongs is in the energy harvesting mode.

10. The imaging sensor of claim 9, wherein each pixel group further comprises: The second pixel includes: a second photodiode; and mode selection circuitry to couple an anode of the second photodiode to ground when the pixel group row to which the pixel group belongs is in the imaging mode, to couple the anode of the second photodiode to ground when the pixel group row to which the pixel group belongs is in the energy harvesting mode and the second pixel is in the isolation mode, and to couple the anode of the second photodiode to the interconnect circuitry when the pixel group row to which the pixel group belongs is in the energy harvesting mode and the second pixel is in the interconnect mode; The mode selection circuit device comprises: a third n-channel transistor having a source coupled to ground, a drain coupled to the anode of the second photodiode, and a gate coupled to the imaging select signal; and A fourth n-channel transistor has a source coupled to the interconnect circuitry, a drain coupled to the cathode of the second photodiode, and a gate coupled to the energy harvesting select signal.

11. The imaging sensor of claim 10, wherein the interconnect circuitry comprises: a first transmission gate coupled between the anode of the first photodiode and the source of the fourth n-channel transistor, the first transmission gate operating based on a result of a logical OR operation performed on a second control signal and a third control signal; a fifth n-channel transistor having a source coupled to ground, a drain coupled to the source of the fourth n-channel transistor, and a gate coupled to a first control signal; as well as A first transistor has a source coupled to the output line, a drain coupled to the anode of the first photodiode, and a gate coupled to the first control signal.

12. The imaging sensor of claim 11 , wherein each pixel group further comprises: The third pixel includes: a third photodiode; and mode selection circuitry to couple an anode of the third photodiode to ground when the pixel group row to which the pixel group belongs is in the imaging mode, to couple the anode of the third photodiode to ground when the pixel group row to which the pixel group belongs is in the energy harvesting mode and the third pixel is in the isolation mode, and to couple the anode of the third photodiode to the interconnect circuitry when the pixel group row to which the pixel group belongs is in the energy harvesting mode and the third pixel is in the interconnect mode; The mode selection circuit device comprises: a sixth n-channel transistor having a source coupled to ground, a drain coupled to the anode of the third photodiode, and a gate coupled to the imaging selection signal; and a seventh n-channel transistor having a source coupled to the interconnect circuitry, a drain coupled to the cathode of the third photodiode, and a gate coupled to the energy harvesting select signal.

13. The imaging sensor of claim 12, wherein the interconnect circuitry further comprises: a second transmission gate coupled between the anode of the second photodiode and the source of the seventh n-channel transistor, the second transmission gate operating based on the third control signal; an eighth n-channel transistor having a source coupled to ground, a drain coupled to the source of the seventh n-channel transistor, and a gate coupled to a result of the logical OR operation performed on the first control signal and the second control signal; as well as A second transistor has a source coupled to the output line, a drain coupled to the anode of the second photodiode, and a gate coupled to the result of the logical OR operation performed on the first control signal and the second control signal.

14. The imaging sensor of claim 13 , wherein the mode selection circuitry of the last pixel comprises: a ninth n-channel transistor having a source coupled to ground, a drain coupled to the anode of the last photodiode, and a gate coupled to the imaging select signal; as well as A tenth n-channel transistor has a drain coupled to the cathode of the last photodiode, a source coupled to the interconnect circuitry, and a gate coupled to the energy harvesting select signal.

15. The imaging sensor of claim 14, wherein the interconnect circuitry further comprises: a third transistor having a source coupled to the output line, a drain coupled to the anode of the third photodiode, and a gate coupled to the first control signal; a third transmission gate coupled between the anode of the third photodiode and the source of the tenth n-channel transistor, the third transmission gate operating based on the result of the logical OR operation performed on the second control signal and the third control signal; an eleventh n-channel transistor having a drain coupled to the source of the tenth n-channel transistor, a source coupled to ground, and a gate coupled to the first control signal; as well as a fourth transistor having a source coupled to the output line, a drain coupled to the anode of the last photodiode, and a gate coupled to a result of a logical OR operation performed on the first control signal, the second control signal, and the third control signal.

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