Semiconductor Etching Method

Abstract

The present invention discloses a method for etching into one or more epitaxial layers of each semiconductor material in a semiconductor structure of a vertical cavity surface emitting laser (VCSEL), wherein the semiconductor material or each semiconductor material is a III-V semiconductor material, a III-N semiconductor material or a II-VI semiconductor material. The method comprises placing a substrate having a semiconductor structure thereon on a support table in a plasma processing chamber, the semiconductor structure carrying a patterned mask on a surface of the semiconductor structure away from the support table. The method also comprises the following process steps: establishing an etching gas mixture flow through the plasma processing chamber, and generating a plasma in the plasma processing chamber, while applying a radio frequency (RF) bias to the support table; thereby exposing a portion of the semiconductor structure not covered by the patterned mask to the etching gas mixture plasma, thereby being etched to form at least one feature in the semiconductor structure; wherein greater than 90% of the etching gas mixture consists of a mixture of silicon tetrachloride (SiCl4) and nitrogen (N2).

Description

Technical Field

[0001] The present invention relates to methods for etching vertical cavity surface emitting lasers (VSCELs), light emitting diodes (LEDs) and photodiode semiconductor structures, and more particularly to plasma etching methods. Each of these semiconductor structures is an example of an optoelectronic device. The disclosed method is particularly suitable for etching trenches in multiple epitaxial layers of different materials in semiconductor structures forming optoelectronic devices of the above types. Background Art

[0002] Many semiconductor devices include a stack of different semiconductor materials, typically III-V materials and / or II-VI materials, deposited on a substrate using known techniques. For example, a VCSEL structure may consist of a III-V heterojunction semiconductor structure with a light-confining mirror grown in the same epitaxial stack. To define the device, a mesa shape is formed by etching one or more trenches in the stack to be used around the active area. Various etching methods are known, and one example is disclosed in US-A-5034092, which describes a reactive ion etching system using primarily silicon tetrachloride (SiCl 4 ) and boron trichloride (BCl 3 ) is used to etch the masked VCSEL structure. This etching gas mixture is said to achieve a slow, controllable etching rate, and it is believed that the sidewall protection (passivation) caused by the deposition of silicon and / or boron compounds on the sidewalls of the trench causes a more anisotropic (directional) etching. JW Lee et al., "Advanced selective dry etching of GaAs / AlGaAs in high density inductively coupled plasmas", J. Vac. Sci. Technol. A 18(4), July / August 2000, pp. 1220-1224 disclose another exemplary etching method. In this case, a gas mixture containing boron trichloride (BCl 3 ), sulfur hexafluoride (SF 6 ), nitrogen (N 2 ) and helium (He) to etch GaAs (with selectivity over AlGaAs) using a patterned photoresist mask. The addition of nitrogen and helium was found to significantly improve the surface morphology, although it also reduced the etch rate. The authors speculate that the presence of nitrogen improves sidewall passivation (and the anisotropy of the etch) by reacting with the photoresist mask to form organic polymer compounds that are deposited on the sidewalls and elsewhere.

[0003] Improved etching techniques are always sought. Summary of the invention

[0004] A first aspect of the present invention provides a method of etching into one or more epitaxial layers of semiconductor materials in a VCSEL semiconductor structure, wherein the or each semiconductor material is a III-V semiconductor material, a III-N semiconductor material or a II-VI semiconductor material, the method comprising:

[0005] Placing a substrate having a semiconductor structure thereon on a support table in a plasma processing chamber, the semiconductor structure carrying a patterned mask on a surface of the semiconductor structure away from the support table; and the following process steps:

[0006] Establishing a flow of an etching gas mixture through a plasma processing chamber; and generating a plasma in the plasma processing chamber while applying a radio frequency (RF) bias to the support stage;

[0007] thereby exposing portions of the semiconductor structure not covered by the patterned mask to the etching gas mixture plasma and thereby being etched to form at least one feature in the semiconductor structure;

[0008] More than 90% of the etching gas mixture consists of silicon tetrachloride (SiCl 4 ) and nitrogen (N 2 ) of the mixture.

[0009] A second aspect of the invention provides a method of etching into one or more epitaxial layers of semiconductor materials in an LED semiconductor structure, wherein the or each semiconductor material is a III-V semiconductor material, a III-N semiconductor material or a II-VI semiconductor material, the method comprising:

[0010] Placing a substrate having a semiconductor structure thereon on a support table in a plasma processing chamber, the semiconductor structure carrying a patterned mask on a surface of the semiconductor structure away from the support table; and the following process steps:

[0011] establishing a flow of an etching gas mixture through a plasma processing chamber; and

[0012] generating plasma in a plasma processing chamber and simultaneously applying a radio frequency (RF) bias to a support table;

[0013] thereby exposing portions of the semiconductor structure not covered by the patterned mask to the etching gas mixture plasma and thereby being etched to form at least one feature in the semiconductor structure;

[0014] More than 90% of the etching gas mixture consists of silicon tetrachloride (SiCl 4 ) and nitrogen (N 2 ) of the mixture.

[0015] A third aspect of the present invention provides a method of etching into one or more epitaxial layers of semiconductor materials in a photodiode semiconductor structure, wherein the or each semiconductor material is a III-V semiconductor material, a III-N semiconductor material or a II-VI semiconductor material, the method comprising:

[0016] Placing a substrate having a semiconductor structure thereon on a support table in a plasma processing chamber, the semiconductor structure carrying a patterned mask on a surface of the semiconductor structure away from the support table; and the following process steps:

[0017] establishing a flow of an etching gas mixture through a plasma processing chamber; and

[0018] generating plasma in a plasma processing chamber and simultaneously applying a radio frequency (RF) bias to a support table;

[0019] thereby exposing portions of the semiconductor structure not covered by the patterned mask to the etching gas mixture plasma and thereby being etched to form at least one feature in the semiconductor structure;

[0020] More than 90% of the etching gas mixture consists of silicon tetrachloride (SiCl 4 ) and nitrogen (N 2 ) of the mixture.

[0021] The present inventors have found that the use of a 4 ) and nitrogen (N 2) produces unexpectedly good etching results. This is not only in terms of etching anisotropy, but also in terms of obtaining a flatter substrate for etching features (e.g., which may be grooves or holes). In particular, conventional etching processes produce regions of reduced etching depth adjacent to the walls of the grooves (or other features), which are referred to as "footings." The "footing" is located between the walls and the "bottom plate," which is the deepest part of the etched feature and tends to be substantially flat. If the entire etching substrate (i.e., the footing and the bottom plate) terminates in a single epitaxial layer on as many etching regions as possible, it is very beneficial for the operation of the semiconductor device forming the structure. For example, not only does device yield increase, but in the case of VCSELs, if the footing is as horizontal as possible, the resulting laser line width is reduced. However, in conventional etching techniques, most of the attention has been focused on the etching morphology of the mesa, including the shape of the bottom corner of the groove, and the inventors have recognized that morphology control should extend from one side of the etching bottom plate to the other, and have developed the above-mentioned method for achieving this. Low "footers" have been achieved using the techniques disclosed herein, such as those having a maximum height above the etched floor of less than 200 nm (thereby ideally keeping the substrate within one epitaxial layer of the structure), or less than 4% of the total etch depth (whichever is smaller), or even less than 2% or 3% of the total etch depth.

[0022] In general, plasma etching is performed by generating new volatile species from the input gas and the semiconductor material to be etched, assisted by ion bombardment. Etching compound semiconductors with two, three or more solid elemental components is more difficult than etching a single material such as silicon, because several different volatile compounds must be formed. In cases where anisotropic etching is required, the formation of volatile species by neutral gas species when in contact with the semiconductor surface (without ion bombardment) needs to be avoided and / or suppressed by a deposition process that protects the vertical surfaces generated by etching, a method known as "sidewall passivation". This allows the trench to grow downward between steep sidewalls.

[0023] However, as mentioned above, the sidewalls have a direct impact on the floor morphology of the trench base and tend to result in the presence of a "footing". For example, ions can be reflected from the forming sidewalls and increase etching at the floor of features away from the sidewalls, a process known as "grooving". Areas adjacent to the vertical walls have a lower etch rate due to the shielding effect of the wall on the inflowing gas species or the quenching of active free radicals on the exposed sidewalls. Excessive sidewall passivation can also result in a rough etched floor due to the deposition of material. All of these factors can result in a "footing" with a significant height.

[0024] The present inventors have found that using SiCl4 / N 2 The etching gas mixture (as defined above) reduces the height of the footing, thereby generally improving the planarity of the etched feature substrate. Without wishing to be bound by theory, it is believed that by providing nitrogen as a significant portion of the etching gas mixture and in combination with the SiCl 4 Combined, this has a direct passivation effect on the etch sidewalls, where it counteracts the additional ion flux that can cause notching, but to a lesser extent than is usually achieved by conventional methods that over-passivate the etch bottom plate. 4 and N 2 The resulting passivated etch sidewalls do not quench free radicals as much as conventional etching methods, thereby providing a more constant free radical flux on the etched floor. Unlike the techniques disclosed by Lee et al., we intend to achieve passivation by nitrogen gas without the need for a photoresist mask through a "direct" passivation effect (e.g., the techniques disclosed herein have been shown to work using inorganic masks such as silicon nitride, which has the additional benefit that additional organic polymer is not formed and deposited on the structure, which may require additional cleaning).

[0025] In addition, the inventors have found that high etching rates can be achieved using the disclosed etching gas mixtures, which is beneficial to yield. For example, using the techniques disclosed herein, etching rates of at least 500 nm / min have been achieved with GaAs, which is advantageous compared to the etching rates of conventional techniques (e.g., Lee et al. achieved a maximum etching rate of about 300 nm / min). High selectivity to silicon nitride masks (e.g., a selectivity ratio of more than 4:1) and high-angle sidewalls (e.g., an angle of 60 to 80 degrees between a wall and a line parallel to the etched floor) have also been demonstrated.

[0026] The etching gas mixture is mainly (more than 90%) SiCl 4 and N 2 , but may contain small amounts of other gases as described below. Nevertheless, SiCl 4 and N 2 The proportion of the total gas mixture is high, so in a preferred embodiment, at least 95% of the etching gas mixture consists of silicon tetrachloride (SiCl 4 ) and nitrogen (N 2 ), and in some preferred cases, substantially 100% of the etching gas mixture will be composed of these two components. Other gases may or may not still be present at trace levels (which have negligible effect on the results), for example, less than 1% of the etching gas mixture.

[0027] In the case where the etching gas mixture does contain one or more other gases, these other gases may be for purposes such as promoting ion bombardment, diluting the etching gas, regulating the chemical reaction that occurs, or improving heat transfer (in the latter case, the other gases are injected under the wafer). In a preferred embodiment, the etching gas mixture further contains one or more inert gases, such as helium, and the inert gases preferably form less than 5% of the etching gas mixture.

[0028] Preferably, silicon tetrachloride (SiCl 4 ) is the only halogen-containing gas present in the etching gas mixture at more than trace levels. Trace levels of a gas have been defined above as less than 1% of the etching gas mixture. Advantageously, the etching process is performed using a minimum number of different gases in the mixture to help optimize and reduce problems caused by changes in the ratio of gases in use. In particular, it is preferred that the etching gas mixture does not contain more than trace levels of boron trichloride (BCl 3 ), preferably does not contain boron trichloride. The inventors have found that the presence of boron trichloride can cause a decrease in the flatness of the etched foot.

[0029] Establishing the etching gas mixture flow through the plasma processing chamber may include introducing the components of the etching gas mixture separately into the plasma processing chamber so that the etching gas mixture is formed within the plasma processing chamber. However, preferably, the etching gas mixture is premixed and fully supplied to the chamber.

[0030] As described above, the inventors have discovered that a significant amount of nitrogen should be present in the etching gas mixture in order to best improve the flatness of the footing. The specific ratio of the two gases (relative to each other) that achieves the flattest footing depends on the semiconductor material being etched, but it has been found that a ratio of silicon tetrachloride to nitrogen in the etching gas mixture (SiCl 4 :N 2 ) is preferably in the range of about 1:3 to 3:1 (i.e., 25% SiCl 4 / 75% N 2 Up to 75% SiCl 4 / 25%N 2 ), more preferably in the range of about 1:2 to 4:3 (i.e., 33% SiCl 4 / 67% N 2 to 57% SiCl 4 / 43% N 2 ), and most preferably about 1:2 (i.e., 33% SiCl 4 / 67% N 2). Most preferably, the amount of nitrogen contained in the etching gas mixture is equal to or greater than the amount of SiCl contained in the etching gas mixture. 4 It has been found that a nitrogen-rich etch gas mixture such as this achieves the lowest footing morphology.

[0031] The etched semiconductor structure comprises a plurality of epitaxial layers of respective semiconductor materials, at least some of which are different from one another (i.e., the semiconductor structure is a heterostructure). In the etching method, etching is performed into at least one layer, preferably multiple layers, and most preferably all layers of the VCSEL, LED, or photodiode semiconductor structure. The etched semiconductor material or each semiconductor material is a III-V semiconductor material, a III-N semiconductor material, or a II-VI semiconductor material. It has been found that the method is particularly effective for such materials. The semiconductor material or each semiconductor material may be a binary, ternary, or quaternary semiconductor material. In particularly preferred embodiments, the semiconductor material or each semiconductor material is any one of the following: GaN, GaAs, AlGaAs, InGaAs, or AlInGaP (in the case of binary, ternary, and quaternary compounds, it will be understood that each compound may contain any relative proportion of elements).

[0032] As mentioned at the outset, these methods are applicable to the production of VCSEL, LED and photodiode semiconductor devices. Examples of such devices are given below.

[0033] The plasma may be generated by any suitable means, and in preferred examples, the plasma is generated using an inductively coupled plasma source, a capacitively coupled plasma source, or a microwave plasma source. In an advantageous embodiment, the plasma is generated using a plasma power in the range of 200 W to 1500 W. The inventors have found that increasing the plasma power tends to increase the etch rate without reducing the flatness of the footing.

[0034] The RF bias applied to the support stage may be, for example, a continuous bias, a pulse bias or a modulated bias. Preferably, the bias power density of the bias applied to the support stage is in the range of 0.5W to 2W per square centimeter.

[0035] In a preferred embodiment, the total gas flow rate of the etching gas mixture is in the range of 5 sccm to 200 sccm, preferably in the range of 80 sccm to 120 sccm, and more preferably about 100 sccm. These preferred values ​​are for substrates with a diameter of 150 mm. For substrates with larger areas, higher flow rates are required.

[0036] Preferably, the method further comprises controlling the pressure within the plasma processing chamber to a value in the range of 0.5 mTorr to 10 mTorr. The inventors have found that increasing the pressure tends to increase the etch rate without reducing the flatness of the footing.

[0037] Preferably, the method further comprises controlling the temperature of the support table to a value in the range of -10 degrees Celsius to +50 degrees Celsius.

[0038] As mentioned at the outset, the disclosed technology enables better control of the footing morphology, so in a particularly preferred embodiment, the process steps (including, for example, selecting the etching gas mixture ratio and optional plasma power, bias power, pressure and / or temperature) are controlled so that the depth of the base of the etched feature varies by no more than 200 nm over the feature width, preferably no more than 4% (more preferably 2%) of the average feature depth. It will be understood that the "base" here includes the foot and the bottom plate of the feature. Generally, this will enable the level variation of the base (usually caused by the presence of the foot) to be maintained within a single layer of the semiconductor structure.

[0039] Preferably, the process steps are controlled such that the etching rate is at least 500 nm / min.

[0040] Advantageously, the process steps are controlled so that the wall angle of the or each etched trench is between 60 degrees and 80 degrees, preferably between 65 degrees and 75 degrees.

[0041] Preferably, the process steps are controlled so that the etching selectivity ratio between the semiconductor and the mask is at least 4:1, and the patterned mask preferably comprises silicon nitride.

[0042] Each of the above results can be obtained experimentally by varying the process parameters within the various identified preferred ranges described above, examining the etch characteristics, and adjusting one or more process parameters if the desired results are not achieved.

[0043] The end of the etching process can be determined in a variety of ways. In a preferred embodiment, the method also includes stopping etching after a predetermined period of time. In the case of the etching rate of the specific structure in question being well established, this simple method may be suitable. In other preferred embodiments, the method also includes monitoring the progress of etching, and preferably stops etching when a predetermined depth has been reached and / or when a predetermined layer in the semiconductor structure has been reached. For example, an optical interferometer or an emission spectrometer can be used to monitor the progress of etching. This can obtain more accurate results, particularly in the case of structures of a type that have not been etched under the same conditions before.

[0044] The above-mentioned etching method can be a complete independent process applied to a semiconductor structure. However, in other cases, the method can be a sub-part of another process, in which case the disclosed method can be performed as one of a series of process steps, and the other process steps each include any one of a deposition step, a passivation step, a heat treatment step, and another etching step. Preferably, this series of process steps is cyclical, and / or can be defined as an atomic layer etching process or a reactive ion etching process. For example, the entire process can be a Bosch-type etching process, including alternating steps of etching (as described herein) and passivation (not described herein). An example of a Bosch-type etching process is described in WO2013 / 128181. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Examples of the etching method and apparatus according to the present invention will now be described with reference to the accompanying drawings, and compared with conventional techniques, in which:

[0046] Figure 1 An exemplary surface treatment tool suitable for carrying out the methods disclosed herein is schematically depicted;

[0047] Figure 2 is a schematic cross-sectional view of an exemplary VCSEL semiconductor structure that can be etched in an embodiment of the first aspect of the present invention;

[0048] Figure 3 (a) shows Figure 2 an enlarged portion of an exemplary VCSEL semiconductor structure after etching, and Figure 3 (b) shows an enlarged detail thereof;

[0049] Figure 4 is a schematic cross-sectional view of an exemplary LED semiconductor structure that can be etched in an embodiment of the second aspect of the present invention;

[0050] Figure 5 is a schematic cross-sectional view of an exemplary photodiode semiconductor structure that can be etched in an embodiment of the third aspect of the present invention;

[0051] Figure 6 and Figure 7 is a SEM image of a cross section of an exemplary semiconductor structure etched using a method according to a comparative example;

[0052] Figure 8 , Fig. 9 and Fig.10 are SEM images of cross-sections of exemplary semiconductor structures etched according to various embodiments of the present invention; and

[0053] Figures 11(a) and 11(b) depict two examples of endpoint detection devices that may be used in either embodiment. DETAILED DESCRIPTION

[0054] Figure 1 An example of a plasma processing tool suitable for implementing the semiconductor etching method disclosed herein is shown. The plasma processing tool 1 includes a processing chamber 2, in which a substrate 30 is placed during use. In order to perform etching, two or more input gases are introduced into the processing chamber 2, and the conditions are controlled to achieve the desired etching mechanism. If necessary, the term "input gas" includes precursor gases and inert carrier gases. The process parameters in the chamber are controlled and can be adjusted by a set of at least one (but typically a plurality of) devices, examples of which are shown exemplarily in Figure 1 In this example, the tool 1 is equipped with two input gas supplies 4 (a) and 4 (b) for supplying a first input gas G 1 and the second input gas G 2 are respectively supplied to the processing chamber 2. For example, the first input gas G 1 It can be silicon tetrachloride (SiCl 4 ), and the second input gas G 2 It can be nitrogen (N 2 ). The entry of the various gases into the chamber 2 is controlled by valves 6(a) and 6(b) and respective mass flow controllers (not shown). Exhaust gases, including unreacted input gases and any reaction products, are exhausted from the processing chamber 2 via conduit 7 and associated pump 8, which is typically capable of reducing the pressure within the chamber to near vacuum conditions. The chamber pressure will be determined primarily by the exhaust pump system, in particular by the pumping speed from the chamber to the pump and the "conductivity" of the pumping line (which is a factor related to the geometry of the pumping line). However, during processing, when plasma is generated and / or when etching or deposition is performed, gaseous materials may be lost or generated in the chamber, which may affect the pressure. In order to control such changes, an automatic pressure control valve 8a is preferably provided, as is known in the art. Valve 8a varies the conductivity of the pumping line so that the chamber pressure can be maintained substantially constant at a desired level when plasma is struck and when material is etched.

[0055] The plasma processing tool 1 is equipped with a plasma source for generating a plasma within a processing chamber by an electric discharge. Here, the plasma source is described as an inductively coupled plasma source, which comprises a coil 9 surrounding a chamber 2, to which RF power is provided by a power supply 10 via an RF matching unit 11. The RF matching unit 11 is configured to match the plasma impedance with the impedance of the RF power supply 10 so as to maximize the efficiency of power transfer from the power supply to the plasma. Examples of suitable matching units are disclosed in WO-A-2010 / 073006. Other types of plasma sources, such as a capacitively coupled plasma (CCP) source or a microwave plasma source, may alternatively be used.

[0056] In use, a substrate 30 is mounted on a platen 14. As described below, in use, a bias voltage is applied to the substrate 30, which is achieved by connecting a voltage source 12 to the platen 14. If an RF power source 12 is used, an automatic impedance matching unit (AMU) is preferably provided to ensure a good match between the power from the power source 12 and the wafer stage 14. The tool 1 may also include a temperature control unit 16, such as a heater and / or cooling system, for regulating the processing temperature of the substrate (additional means for heating and / or cooling the processing chamber and plasma source may be provided to assist process control and / or maintain hardware stability). For example, when etching is mainly performed, the substrate is preferably cooled using a circulating coolant to prevent a large amount of energy from being transferred to the substrate during ion bombardment and / or during the exothermic chemical reaction, thereby causing an undesirable increase in the substrate temperature.

[0057] These devices operate according to instructions from a controller 20, such as a programmable logic controller (PLC) or similar device. In some cases, more than one controller may be provided, each of which controls a device or sub-device. The controller is also connected to a user interface device, such as a computer workstation 25, for receiving input from a user and / or returning output.

[0058] exist Figure 1In the embodiment of the present invention, the data connection between various devices and the controller 20 is represented by a dotted line. In practice, this can be implemented as a network such as a CAN bus bridge, which can be connected to each device and a user interface 25. The bus typically includes a plurality of network channels (including one or more data channels, such as a serial data channel (e.g., RS485)) and optionally one or more power channels. The controller 20 issues commands via the bus, each command being addressed to one or more devices and including instructions for one or more process parameters to be implemented by the device in question. An example of a network protocol that can be used to issue commands for controlling a device is given in WO-A-2010 / 100425. Of course, as will be appreciated by those skilled in the art, many other network implementations are also possible.

[0059] Figure 2 An example of a semiconductor structure 30 to be etched is shown in a schematic cross-sectional view. In this example, the semiconductor structure 30 represents a vertical cavity surface emitting laser (VCSEL), but in other examples, the semiconductor structure can be a light emitting diode (LED) device or a photodiode. Suitable structures for such devices are well known. Typically, each semiconductor layer to be etched typically comprises a III-V or II-VI semiconductor material. For example, the method is particularly suitable for III-N semiconductor materials. The semiconductor layer or each semiconductor layer can be a binary semiconductor material such as GaN or GaAs, or a ternary and quaternary mixture of semiconductor materials such as AlGaAs, InGaAs or AlInGaP.

[0060] In this example, the VCSEL semiconductor structure 30 is based on a support substrate 31 (such as silicon, sapphire, etc.), followed by a metal contact layer 32. Alternatively, the support substrate 31 can be a compound semiconductor wafer, and the metal contact layer 32 is omitted. Next is a substrate 33 (such as n-GaAs), and then a first reflector 34 (such as a distributed Bragg reflector), which is actually formed by multiple sublayers with alternating refractive indices. For example, the sublayers can be alternating layers of n-AlGaAs and n-GaAs. Figure 2In the figure, most of the sublayers forming the reflector 34 are collectively labeled as 34a, while the last layer of the reflector 34 is labeled as 34b and its thickness is exaggerated for clarity only. Above the first reflector 34 is an active region 35 composed of one or more quantum wells for generating laser light. The active region 35 may also include multiple component layers, including confinement layers, the quantum wells themselves, and quantum well barriers. These layers can be formed of, for example, AlGaAs, InGaAs, and GaAs, respectively. Above the active region 35 is a second reflective layer 36, and the structure of the second reflective layer 36 is similar to that of the first reflective layer 34. The top of the semiconductor structure is a patterned mask 39 formed of silicon nitride, photoresist, etc. The mask 39 is consistent with the pattern of the mask area M separated by one or more gaps, and the trench T is etched in the gap. 1 and T 2 After etching, the remaining mask material 39 is removed and metal contacts are applied to complete the device structure.

[0061] A detailed example of the etching process itself will be provided below, but first Figure 3 (a) shows the reference Figure 2 The completed trench T in the semiconductor structure 30 is described. 1 The schematic cross-sectional view of the groove T thus completed is provided for reference. 1 The maximum depth of the groove is d, and its side wall S forms a wall angle α with the horizontal line (i.e., a line parallel to the groove foot). Figure 3 In the enlarged view of (b), it can be seen that the base B of the groove actually includes a foot F* and a bottom plate F, and the foot F* is adjacent to the side wall S and is located between the side wall S and the bottom plate F. The height of the foot F* above the bottom plate F is indicated by the arrow H. As described below, in a preferred embodiment of the present invention, this height H is ideally no greater than 200 nanometers, and preferably no greater than 4% (even more preferably 2%) of the average groove depth d.

[0062] Figure 4 A schematic cross-sectional view of an exemplary LED semiconductor structure 40 is shown. The semiconductor structure 40 includes a supporting substrate 41 on which a contact layer 42 is formed, which can be used as an electrical contact in a completed device. A substrate layer 43 is formed on the contact layer 42, and the substrate layer 43 can be, for example, n-GaAs, and above the substrate 43 is an n-type semiconductor material layer 44 (e.g., GaAs). A p-type semiconductor material layer 45 (e.g., GaAsP) is formed on the n-type layer 44. In this embodiment, the semiconductor materials forming the n-type layer 44 and the p-type layer 45 can be selected so that the semiconductor structure 40 can be used as an LED device. A patterned mask 46 is provided on the p-type layer 45, and the mask region M and the trench T are defined by the patterned mask 46. 1 、T 2The pattern is formed by etching the semiconductor structure 40 into the semiconductor structure 40. The mask 46 is removed after etching and additional metal contacts can be provided over the p-type layer 45 to complete the LED device.

[0063] Figure 5 1 shows a schematic cross-sectional view of an exemplary photodiode semiconductor structure 50. The semiconductor structure 50 includes a supporting substrate 51 (similar to the above reference Figure 3 a. Figure 3 b and Figure 4 The semiconductor structure 30, 40 described above and the contact layer 52 formed thereon. An n-type semiconductor material layer 53 (e.g., n-type InP) is formed above the contact layer 52, and an intrinsic (i.e., undoped) semiconductor material layer 54 (e.g., InGaAs) is formed above the n-type layer 53. A p-type semiconductor material layer 55 (e.g., p-type InP) is disposed on the intrinsic semiconductor material layer 54. A patterned mask 56 is disposed on the p-type layer 55. The mask 56 defines a mask region M and a trench T to be etched into the semiconductor structure 50. 1 、T 2 The pattern of the etched groove T 1 、T 2 Afterwards, mask 56 can be removed and additional metal contacts can be placed over p-type layer 55 to complete the photodiode device. After etching, other features can also be introduced into the finished device. For example, an anti-reflective coating can be formed over p-type layer 55 to improve the transmission of light into the device.

[0064] In order to perform etching, a semiconductor structure 30 (eg Figure 2 The support table 14 is exposed to the etching gas mixture flow established in the plasma processing chamber 2 (as shown). At the same time, plasma is generated by the plasma source, and a bias voltage is applied to the support table 14, which may be a continuous (DC) bias voltage or a modulated (e.g., RF) bias voltage. Exemplary values ​​of various parameters are given below.

[0065] Typically, the etching gas mixture will contain one or more of the following components, and the overall composition is optimized experimentally:

[0066] 1. One or more gases that provide raw materials for the target volatile reaction products, usually halogen-containing gases or methyl-forming mixtures.

[0067] 2. Optionally, an inert gas, usually a noble gas of considerable mass, to facilitate the effect of ion bombardment in breaking bonds in the solid material. Argon is a common gas used for this purpose.

[0068] 3. Optionally, a diluent gas with minimal impact on the process chemistry. This diluent gas is usually an inert gas, and helium is often chosen because of its lack of chemical interaction and low mass, thereby avoiding sputtering.

[0069] 4. Optionally, a gas for controlling the chemical process. Hydrogen or oxygen are common choices, which are chemically active in the plasma. Additions of up to 20% are known to optimize the generation of certain free radicals, or to promote or inhibit the formation of polymers in which these free radicals can be formed.

[0070] 5. Optionally, a gas to promote sidewall passivation and prevent undercutting.Boron trichloride and silicon tetrachloride are both potential candidates here and have been used in mixtures with each other or with chlorine to etch compound semiconductor materials.

[0071] In order to explain the advantages of the etching gas mixture intended for use with the embodiment of the present invention, first, results obtained using the etching gas mixture according to the comparative example will be described for comparison.

[0072] Figure 6 Sample 1 is shown, which is a sample prepared by using BCl 3 , Cl 2 and N 2 The results of the etching process with an etching gas mixture of 100 mm and 100 mm are shown in Table 1 below. All process parameters used for etching are described in detail with reference to Table 1 below. These tests used 100 mm wafers; the gas flow rate was adjusted according to the substrate area. The foot height H obtained was about 7.8% of the total trench depth, which is large and not desirable. As shown in Table 1 below, under the same process conditions, equal parts of SiCl 4 , Cl 2 and N 2 The etching gas mixture (sample 2) and equal parts of BCl 3 、SiCl 4 and N 2 The test conducted with the etching gas mixture (Sample 3) also produced similar large foot. For all three sample tests listed in Table 1, the other process parameters not mentioned in the table were: ICP (plasma) power was 350W, RF bias power was 110W / 35V (1.4W / cm for 100mm diameter wafers) 2 ), the table temperature is 0°C, the helium behind the wafer is 10 Torr, the flow rate is 2sccm to 3sccm, and the chamber pressure is 1mT. It can be understood that the pressure behind the clamped wafer with the heat transfer gas injected below is much higher than the chamber pressure.

[0073] Table 1

[0074]

[0075] Increasing amounts of boron trichloride (BCl 3 ) resulted in an increase in the foot height and was therefore found to be unfavorable.

[0076] Then, according to an embodiment of the present invention, SiCl is used to form the majority (more than 90%) of the total gas flow. 4 and N 2 The etching gas mixture was tested. Figure 8 , Fig. 9 and Fig.10 The cross-sections of various sample semiconductor structures etched using this etching gas mixture under various different process parameters are shown. Full details of each sample test are given in Table 2 below. Figure 8 In the example (Sample 4), the etching gas mixture contains SiCl in a ratio of 1:2 4 and N 2 (10 sccm SiCl 4 and 20 sccm of N 2 ). A foot height of 3.9% was obtained. Further experiments (including those in Table 2 below) showed that increasing N 2 The ratio of helps to reduce the foot height, but the etch rate is also found to be slower. However, this can be offset by increasing the plasma power as shown in Sample Run 7, the results of which are shown in Fig. 9 Here, SiCl 4 With N 2 The ratio is again 1:2, but the ICP power has been increased from 350 W to 750 W, which increases the etch rate from 349 nm / min to 412 nm / min.

[0077] It was further discovered that increasing the process pressure can also help increase the etch rate without deteriorating the foot height, and this was demonstrated in Sample Experiment 11, the results of which are shown in Fig.10 Here, it was found that at an ICP plasma power of 900 W and a process pressure of 6 mT, SiCl 4 With N 2A small increase in the ratio of (ratio 3:4) was acceptable, resulting in only 0.7% footing and an etch rate of 800 nm / min. Finally, for comparison, in one experimental sample 5, an argon (Ar) flow was used instead of a nitrogen flow to compare the results, and an undesirable large footing of 11.8% was produced. For each sample listed, the process parameters not mentioned in Table 2 were as follows: RF bias power 110 W / 35 V, workbench temperature 0 ° C, 10 Torr, 2 sccm to 3 sccm helium.

[0078] Table 2

[0079]

[0080] It can be seen that all the etching gas mixtures mainly composed of SiCl in different proportions have different 4 and N 2 Embodiments of the etching gas mixtures composed to achieve reduced foot height. 4 With N 2 Ratios ranging from 1:2 to 4:3 were tried and found to give good results, although in general, SiCl 4 More than N 2 The mixture is significantly better.

[0081] As mentioned above, SiCl 4 and N 2 Together they should make up more than 90% of the etching gas mixture, although other gases may be present in small amounts, i.e., less than 10% of the mixture, and preferably less than 5%, as in the present embodiment. The helium background mentioned in the present embodiment falls within this category, and is provided here to improve heat transfer between the wafer 30 and the workbench 14.

[0082] In all samples 4, 5 and 7 to 12 above, the angle α between the trench wall and the horizontal was found to be in the range of 60 to 80 degrees, typically about 75 degrees. In all cases, the etch depth d was between 4 and 5 microns, averaging about 4.669 microns.

[0083] According to these process parameters, an etch rate of more than 500 nm / min was achieved, and a footing of less than 4%, or preferably less than 3%, was achieved. A mask selectivity ratio of up to 4.8 was also achieved. Overall, it was noted that the etching produced a smooth etched surface without residue.

[0084] The etching process can be terminated in a variety of different ways. For example, the etching can be performed for a predetermined period of time, after which the process stops.

[0085] Alternatively, a method for monitoring the progress of the etching may be provided so that etching may be stopped once a certain depth or layer within the structure 30 has been reached. Fig.11a and Fig.11b Two exemplary endpoint detection devices 400 are shown. Fig.11a In the embodiment of the present invention, the depth of the etched trench T (or other feature) is sensed and monitored by an optical interferometer, which includes an electromagnetic radiation (e.g., light) source 410 and a corresponding detector 420. One or more wavelengths of radiation are directed downward to the feature being etched on the wafer 30, and the radiation reflected by the different layers interferes, causing the amplitude of the reflected light to change over time as the etching proceeds. When the interference amplitude corresponding to the desired depth is obtained, it is known that the endpoint has been reached.

[0086] exist Fig.11b In the embodiment of the present invention, the composition of the material currently being etched (i.e., in either case, the composition of the semiconductor layer of the substrate forming the groove T) is sensed by observing the radiation in the chamber emitted by the process using a radiation collector such as an optical fiber 450. The collector 450 can be connected to a spectrometer 460 to select certain wavelengths corresponding to known atomic transitions that occur when etching the relevant material. Alternatively, a filter can be used to select one or more wavelengths to which the sensor responds to achieve the same effect. When the etching depth reaches the desired layer (e.g., layer 34b) where the grooving will stop, the emission wavelength will change accordingly due to the specific material now being etched. When it is detected that the etching feature has reached the desired end point, the device 40 outputs a signal to the controller to stop etching.

[0087] The described etching process may be an independent etching step that forms a complete process by itself, or may be part of a longer overall process that includes multiple process steps or stages. For example, the entire process may be a cyclic etching and passivation process, such as the Bosch process, and the described etching method may be used to implement the etching step in this process.

Claims

1. A method of etching into one or more epitaxial layers of semiconductor materials in a vertical cavity surface emitting laser (VCSEL) semiconductor structure, wherein the or each semiconductor material is any one of the following: GaAs, AlGaAs, InGaAs and GaAsP, the method comprising: placing a substrate having the semiconductor structure thereon on a support stage in a plasma processing chamber, the semiconductor structure carrying a patterned mask on a surface of the semiconductor structure remote from the support stage; And the following process steps: establishing a flow of an etching gas mixture through the plasma processing chamber; as well as generating plasma in the plasma processing chamber and simultaneously applying a radio frequency (RF) bias to the support table; thereby exposing portions of the semiconductor structure not covered by the patterned mask to an etching gas mixture plasma and thereby being etched to form at least one feature in the semiconductor structure; wherein greater than 90% of the etching gas mixture consists of a mixture of silicon tetrachloride (SiCl4) and nitrogen (N2), and wherein the etching gas mixture comprises more nitrogen (N2) than silicon tetrachloride (SiCl4), and wherein the amount of N2 in the etching gas mixture does not exceed three times the amount of SiCl4, The process steps are controlled so that the depth of the base of the etched feature does not vary by more than 200 nm over the width of the etched feature.

2. A method of etching into one or more epitaxial layers of semiconductor materials in a light emitting diode (LED) semiconductor structure, wherein the or each semiconductor material is any one of the following: GaAs, AlGaAs, InGaAs and GaAsP, the method comprising: placing a substrate having the semiconductor structure thereon on a support stage in a plasma processing chamber, the semiconductor structure carrying a patterned mask on a surface of the semiconductor structure remote from the support stage; And the following process steps: establishing a flow of an etching gas mixture through the plasma processing chamber; as well as generating plasma in the plasma processing chamber and simultaneously applying a radio frequency (RF) bias to the support table; thereby exposing portions of the semiconductor structure not covered by the patterned mask to an etching gas mixture plasma and thereby being etched to form at least one feature in the semiconductor structure; wherein greater than 90% of the etching gas mixture consists of a mixture of silicon tetrachloride (SiCl4) and nitrogen (N2), and wherein the etching gas mixture comprises more nitrogen (N2) than silicon tetrachloride (SiCl4), and wherein the amount of N2 in the etching gas mixture does not exceed three times the amount of SiCl4, The process steps are controlled so that the depth of the base of the etched feature does not vary by more than 200 nm over the width of the etched feature.

3. A method of etching into one or more epitaxial layers of semiconductor materials in a photodiode semiconductor structure, wherein the or each semiconductor material is any one of the following: GaAs, AlGaAs, InGaAs and GaAsP, the method comprising: placing a substrate having the semiconductor structure thereon on a support stage in a plasma processing chamber, the semiconductor structure carrying a patterned mask on a surface of the semiconductor structure remote from the support stage; And the following process steps: establishing a flow of an etching gas mixture through the plasma processing chamber; as well as generating plasma in the plasma processing chamber and simultaneously applying a radio frequency (RF) bias to the support table; thereby exposing portions of the semiconductor structure not covered by the patterned mask to an etching gas mixture plasma and thereby being etched to form at least one feature in the semiconductor structure; wherein greater than 90% of the etching gas mixture consists of a mixture of silicon tetrachloride (SiCl4) and nitrogen (N2), and wherein the etching gas mixture comprises more nitrogen (N2) than silicon tetrachloride (SiCl4), and wherein the amount of N2 in the etching gas mixture does not exceed three times the amount of SiCl4, The process steps are controlled so that the depth of the base of the etched feature does not vary by more than 200 nm over the width of the etched feature.

4. The method according to any of the preceding claims, wherein at least 95% of the etching gas mixture consists of silicon tetrachloride (SiCl4) and nitrogen (N2).

5. The method of claim 4, wherein 100% of the etching gas mixture consists of silicon tetrachloride (SiCl4) and nitrogen (N2).

6. The method of any one of claims 1 to 3, wherein the etching gas mixture further comprises one or more inert gases. The method according to claim 6 , wherein the inert gas is helium.

8. The method of claim 6, wherein the one or more inert gases form less than 5% of the etching gas mixture.

9. The method of any one of claims 1 to 3, wherein the silicon tetrachloride (SiCl4) is the only halogen-containing gas present in the etching gas mixture at greater than trace levels.

10. The method of any one of claims 1 to 3, wherein the etching gas mixture does not contain more than trace levels of boron trichloride (BCl3). The method of claim 10 , wherein the etching gas mixture does not contain boron trichloride.

12. The method of any one of claims 1 to 3, wherein establishing a flow of an etching gas mixture through the plasma processing chamber comprises mixing components of the etching gas mixture together upstream of the plasma processing chamber and then introducing the etching gas mixture into the plasma processing chamber.

13. The method according to any one of claims 1 to 3, wherein the ratio of silicon tetrachloride to nitrogen (SiCl4:N2) in the etching gas mixture is 1:

3.

14. The method of claim 13, wherein the ratio of silicon tetrachloride to nitrogen (SiCl4:N2) in the etching gas mixture is 1:

2.

15. The method of any one of claims 1 to 3, wherein the semiconductor structure comprises a plurality of epitaxial layers of respective semiconductor materials, at least some of the respective semiconductor materials being different from one another.

16. The method of any one of claims 1 to 3, wherein the plasma is generated using an inductively coupled plasma source, a capacitively coupled plasma source, or a microwave plasma source.

17. The method according to any one of claims 1 to 3, wherein the plasma is generated using a plasma power in the range of 200 W to 1500 W.

18. The method according to any one of claims 1 to 3, wherein the bias applied to the support table is a continuous bias, a pulse bias or a modulated bias.

19. The method according to any one of claims 1 to 3, wherein a bias power density of the bias voltage applied to the support table is in the range of 0.5 W to 2 W per square centimeter.

20. The method of any one of claims 1 to 3, wherein a total gas flow rate of the etching gas mixture is in a range of 5 sccm to 200 sccm.

21. The method of claim 20, wherein a total gas flow rate of the etching gas mixture is in a range of 80 sccm to 120 sccm.

22. The method of claim 20, wherein the total gas flow rate of the etching gas mixture is 100 seem.

23. The method of any one of claims 1 to 3, further comprising controlling the pressure within the plasma processing chamber to a value in the range of 0.5 mTorr to 10 mTorr.

24. The method of any one of claims 1 to 3, further comprising controlling the temperature of the support table to a value in the range of -10 degrees Celsius to +50 degrees Celsius.

25. The method of claim 1, wherein the process steps are controlled so that the depth of the base of the etched feature varies by no more than 4% of the average feature depth across the width of the etched feature.

26. The method of claim 1, wherein the process steps are controlled so that the depth of the base of the etched feature varies by no more than 3% of the average feature depth across the width of the etched feature.

27. The method of claim 1, wherein the process steps are controlled so that the depth of the base of the etched feature varies by no more than 2% of the average feature depth across the width of the etched feature.

28. The method according to any one of claims 1 to 3, wherein the process step is controlled such that the etching rate is at least 500 nm / min.

29. A method according to any one of claims 1 to 3, wherein the process steps are controlled such that the wall angle (a) of the or each etched feature is between 60 degrees and 80 degrees.

30. A method as claimed in claim 29, wherein the process steps are controlled such that the wall angle (a) of the or each etched feature is between 65 degrees and 75 degrees.

31. The method according to any one of claims 1 to 3, wherein the step is controlled so that an etching selectivity ratio of the semiconductor to the mask is at least 4:

1.

32. The method of any one of claims 1 to 3, wherein the patterned mask comprises silicon nitride.

33. The method of any one of claims 1 to 3, further comprising stopping the etching after a predetermined period of time has elapsed.

34. The method of any one of claims 1 to 3, further comprising monitoring the progress of the etching.

35. The method of claim 34, wherein the etching is stopped when a predetermined depth has been reached and / or when a predetermined layer in the semiconductor structure has been reached.

36. The method of claim 34, wherein the progress of the etching is monitored using optical interferometry or emission spectroscopy.

37. A method of processing a semiconductor structure, comprising performing the method according to any one of claims 1 to 3 as one of a series of process steps, the other process steps each comprising any one of a deposition step, a passivation step, a heat treatment step and a further etching step.

38. The method of claim 37, wherein the series of process steps are performed in cycles.

39. The method of claim 37, wherein the series of process steps is defined as an atomic layer etching process or a reactive ion etching process.

40. A semiconductor structure etched according to the method of any one of claims 1 to 3.

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