Error detection method

Abstract

Embodiments of the present disclosure relate to error detection methods. A method for testing multiple devices, each device including a test chain having multiple positions for storing test data. The test includes comparing the test data in the last position of the test chain of each device in the device. The test data in the test chain of the device is shifted forward by one position. The shifting includes writing the test data in the last position of the test chain to the first position in the test chain. Repeating the comparison and shifting until the test data in the last position of each test chain is shifted back to the last position of the corresponding test chain when the test starts. The multiple devices can have the same structure and the same function.

Description

Technical Field

[0001] The present disclosure relates generally to detection of errors in electronic devices, and more particularly to detecting errors by comparison of electronic devices. The present disclosure also relates to devices that enable implementation of such error detection methods in electronic devices. Background Art

[0002] In electronic devices, the use of electronic devices such as processors, microprocessors, integrated systems, etc. is increasingly subject to performance and reliability constraints. In order to comply with certain standards and / or quality regulations, such devices are often coupled with detection and / or error correction devices. In practice, operating errors can occur when executing one of these devices and interfere with the operation of these devices and / or the general operation of the electronic system in which these devices are included.

[0003] Several types of errors or faults may occur in electronic devices. As an example, certain errors (SPF, Single Point Fault) directly or quickly affect the operation of the electronic device and / or the general operation of the electronic system including the electronic device. These errors are easy to identify by observation of the device and / or system. Other errors are called latent errors (LF, latent Fault) and do not lead to failure immediately, but may lead to failure, for example, later or when these latent errors are combined with other errors. Such errors are more difficult to detect, because simply observing the operation of the device or system is usually not enough. Summary of the invention

[0004] In an embodiment, a method includes testing a plurality of devices, each device including a test chain having a plurality of locations for storing test data. The test includes: comparing the test data in the last position of the test chain of each device in the device; shifting the test data in the test chain of the device forward by one position, the shifting including writing the test data in the last position of the test chain to the first position in the test chain; and repeating the comparison and repeating the shifting until the test data in the last position of each test chain when the test starts is shifted back to the last position of the corresponding test chain. In one embodiment, the method includes storing a segment of the test data in a test point. In one embodiment, the test point is a register or a flip-flop. In one embodiment, the test data includes a binary word. In one embodiment, the test data includes a single-bit binary word. In one embodiment, the devices each include a plurality of test chains. In one embodiment, the plurality of devices include more than two devices. In one embodiment, the method includes generating an output signal based on the comparison. In one embodiment, the plurality of devices have the same structure and the same function.

[0005] In one embodiment, a device includes: a comparator; and a control circuit device coupled to the comparator, wherein the control circuit device controls the testing of multiple electronic circuits in operation, each electronic circuit including a test chain having multiple positions for storing test data. The test includes: comparing the test data of the last position of the test chain of each electronic circuit in the electronic circuit; shifting the test data in the test chain of the electronic circuit forward by one position, the shifting including writing the test data in the last position of the test chain to the first position in the test chain; and repeating the comparison and repeating the shifting until the test data in the last position of each test chain is shifted back to the last position of the corresponding test chain when the test starts. In one embodiment, the control circuit includes multiple feedback loops, each feedback loop coupling the input and output of the corresponding test chain. In one embodiment, each feedback loop includes a multiplexer. In one embodiment, the comparator includes an "exclusive or" logic gate.

[0006] In one embodiment, a system includes: a plurality of electronic devices, each of which includes a test chain having a plurality of locations for storing test data; and a test circuit device coupled to the plurality of electronic devices, and the test circuit device tests the plurality of electronic devices in operation. The test includes: comparing the test data in the last position of the test chain of each of the electronic devices; shifting the test data in the test chain of the electronic device forward by one position, the shifting including writing the test data in the last position of the test chain to the first position in the test chain; and repeating the comparison and repeating the shifting until the test data in the last position of each test chain is shifted back to the last position of the corresponding test chain when the test starts. In one embodiment, the test chain includes a test point, and the test point stores a segment of the test data in operation. In one embodiment, the test point includes a register or a flip-flop. In one embodiment, the test data includes a binary word. In one embodiment, the test data includes a binary word of one bit. In one embodiment, the electronic devices each include a plurality of test chains. In one embodiment, the plurality of devices include more than two devices. In one embodiment, the test includes generating an output signal based on the comparison. In one embodiment, the plurality of electronic devices have the same structure and the same function.

[0007] One embodiment provides an error detection method, the method comprising comparing at least two identical electronic devices including at least one test data, the method comprising the following steps:

[0008] (a) comparing the test data of the last position in the chain of two devices;

[0009] (b) Shifting other test data forward one position in its data chain;

[0010] (c) writing the test data of step (a) into the first position in its initial chain,

[0011] Repeat steps (a), (b), and (c) until all test data have been restored to their original positions.

[0012] According to one embodiment, each piece of test data is stored in a test point.

[0013] According to one embodiment, the test points are registers or flip-flops.

[0014] According to one embodiment, the test data are binary words.

[0015] According to one embodiment, the test data is a single bit binary word.

[0016] According to one embodiment, the electronic device comprises two or more test data chains.

[0017] According to one embodiment, the method is a method for comparing more than two identical electronic devices.

[0018] According to one embodiment, the comparison result of step (a) is transmitted in the form of a signal.

[0019] Another embodiment provides a device for comparison suitable for executing the above method.

[0020] According to one embodiment, the device is adapted to compare at least two identical electronic devices comprising at least one test data chain, the device comprising:

[0021] a comparator circuit; and

[0022] At least two feedback loops, each feedback loop coupling an input and an output of one of the chains.

[0023] According to one embodiment, each feedback loop couples an input and an output of one of the chains via a multiplexer.

[0024] According to one embodiment, the comparator circuit comprises an XOR logic gate.

[0025] An electronic system comprising:

[0026] at least two identical electronic devices including at least one test data link; and

[0027] The above comparison device. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1An electronic device is schematically shown in the form of a block;

[0030] Figure 2 The diagram is schematically shown in the form of a box. Figure 1 Embodiments of an error detection device in an electronic device of the type of device;

[0031] Figure 3 Shows Figure 2 Embodiments of the implementation of the device;

[0032] Figure 4 Shows Figure 2 Embodiments of the implementation of the device;

[0033] Figure 5 The diagram is schematically shown in the form of a box. Figure 1 Another embodiment of an error detection device in an electronic device of the device type;

[0034] Figure 6 A logic circuit of a comparator of an embodiment of an error detection device is shown;

[0035] Figure 7 A logic circuit of a comparator of an embodiment of an error detection device is shown. DETAILED DESCRIPTION

[0036] In different drawings, the same elements are denoted by the same reference numerals. In particular, common structural and / or functional elements of different embodiments may be denoted by the same reference numerals and may have the same structure, size and material properties.

[0037] For clarity, only those steps and elements that are useful for understanding the described embodiments are shown and described in detail.

[0038] Throughout this disclosure, the term “connected” is used to specify a direct electrical connection between circuit elements and no intervening elements, while the term “coupled” is used to specify an electrical connection between circuit elements, which may be direct or via one or more intervening elements.

[0039] In the following description, when reference is made to terms defining absolute positions, such as terms “front”, “back”, “up”, “down”, “left”, “right”, etc., or terms defining relative positions, such as terms “upward”, “downward”, “upper”, “lower”, etc., or terms defining directions, such as terms “horizontal”, “vertical”, etc., unless otherwise specified, they are considered to be the orientation of the drawings.

[0040] The terms "about," "substantially," and "approximately" are used herein to indicate a tolerance of plus or minus 10%, plus or minus 5% of the value in question.

[0041] Figure 1 The electronic device 100 is schematically shown in the form of a block. The electronic device 100 is, for example, a processor, a microprocessor, an integrated system, a control unit, etc.

[0042] The electronic device 100 includes a plurality of test points 101. Each test point 101 stores functional data, which is used during the execution of the device and calls the test data during the test phase. As an example, the test point 101 is a register or one or more flip-flops. The test data is, for example, a binary word encoded on N bits. As an example, N is in the range from 1 to 64 bits, for example, equal to 1. The test points 101 are arranged in the device 100, for example, once the device 100 is designed, and are each coupled to one or more modules or components of the device 100. The test data stored in the test point 101 is data that provides an indication of the state of (multiple) components, and the components have test points attached to the components. The test points 101 are organized in one or more test chains 103. Each test chain 103 includes an input point 103IN and an output point 103OUT.

[0043] The apparatus 100 may include as many test points as needed, the test points being organized in as many test chains as needed. The test chains 103 may all have the same number of test points, but as a variant may have different numbers of test points. As an example, Figure 1 The device 100 shown in , for example, comprises 33 test points 101 organized in three test chains 103 , each test chain 103 comprising 11 test points 101 .

[0044] The phase of detection or testing of an error or malfunction of the device 100 usually comprises reading and comparing all the data stored in the test points. Therefore, the number of test points 101 included in the device 100 has an impact on the duration of the test phase. In fact, the more test points 101 there are in the device 100, the longer the risk of the test phase. The organization of the test points 101 in the test chain 103 can make it possible to shorten this period of time by making it possible to read a plurality of test points 101 in parallel.

[0045] Will combine Figure 2 and Figure 3 An apparatus and method for error detection in the apparatus 100 is described.

[0046] Figure 2 The diagram schematically shows the comparison of Figure 1 The device 100 type includes two devices 100A and 100B to detect errors in the device 200. The device 100A and the device 100B may be identical in structure to the device 100A and the device 100B, and also process the same operation work, and should have the same test data.

[0047] According to one embodiment, each device 100A and device 100B includes a corresponding test chain 103A and a test chain 103B, respectively, and the test chain 103A and the test chain 103B include corresponding test points 101A and test points 101B, respectively. As an example, each test chain 103A and 103B includes corresponding seven test points 101A and seven test points 101B, respectively. Each test chain 103A and the test chain 103B include corresponding inputs 103INA and 103INB and outputs 103OUTA and 103OUTB, respectively. The corresponding last test points 101A and 101B of each test chain 103A and the test chain 103B store data dA and dB, respectively.

[0048] The detection circuit 200 includes two feedback loops 210A and a feedback loop 201B. The feedback loop 210A couples or connects the output 103OUTA of the test chain 103A of the device 100A to the input of the multiplexer 215A. The feedback loop 210B couples or connects the output 103OUTB of the test chain 103B of the device 100B to the input of the multiplexer 215B. Each multiplexer 215A, 215B includes a second input receiving a signal "Scan-IN". Each multiplexer 215A, 215B also includes an output coupled or connected to the input of the test chain 103A, the test chain 103B. The multiplexer 215A and the multiplexer 215B are entry points for inserting data into the test chain 103A and the test chain 103B, and allow data to be inserted from the feedback loop 210A and the feedback loop 210B or from another pin or device.

[0049] The detection circuit 200 also includes a comparator circuit 220, which includes two inputs 220INA and 220INB and an output 220OUT. The input 220INA is coupled or connected to the output 103OUTA of the test chain 103A of the device 100A. The input 220INB is coupled or connected to the output 103OUTB of the test chain 103B of the device 100B. The output 220OUT transmits a signal representing the comparison result between the two signals provided as inputs. The comparator circuit 220 is, for example, an XOR type logic gate. The combination Figure 6 and Figure 7 Other examples of comparator circuits suitable for different types of devices are described.

[0050] As shown, the detection circuit 200 includes a control circuit 230 that, in operation, controls the multiplexer 215A, the multiplexer 215B, etc. In some embodiments, the control circuit 230 may be combined with or include the comparator circuit 220 .

[0051] Now combine Figure 3 and Figure 4 An error detection method using the detection device 200 is described.

[0052] Figure 3 and Figure 4 The combination is schematically shown in the form of a box Figure 2 The implementation of the detection device 200 is described.

[0053] The test points of the test chain 103A and the test chain 103B are numbered from 101A-1 to 101A-M and from 101B-1 to 101B-M, and store data A1 to AM and store data B1 to BM. Figure 3 and Figure 4 , the number of test points of each test chain is 7, and thus the test points of the test chain 103A and the test chain 103B are numbered from 101A-1 to 101A-7 and from 101B-1 to 101B-7, and store data A1 to A7 and store data B1 to B7.

[0054] In the error detection phase ( Figure 3 ), the data AM and BM stored in the last test point 101AM and the last test point 101BM of the test chain 103A and the test chain 103B ( Figure 3 The data AM and BM should be identical due to the structure of the device 100A and the state of the device 100A and the device 100B. If this is not the case, an error is detected and the comparator transmits an error signal ERROR at its output 220OUT.

[0055] Each segment of data AM and data BM is further sent to the input of multiplexer 215A and the input of multiplexer 215B by feedback loop 210A and feedback loop 201B respectively.

[0056] Once the data AM and the data BM have been compared ( Figure 4 ), data Ai (i changes from 1 to M-1) is shifted to the next test point 101A-i+1, and data Bi is shifted to the next test point 101B-i+1. In addition, data AM and BM are written to test point 101A-1 and test point 101B-1 by multiplexer 215A and multiplexer 215B respectively without being modified.

[0057] The error detection phase is performed by comparing the data AM-1 and data BM-1 stored in the test points 101A-M and 101B-M and other data in the test points immediately following by shifting. Once all data Ai have been compared with data Bi, and data AM and data BM have been returned to their original positions by shifting, the test phase ends.

[0058] An advantage of the detection device 200 and the detection method implemented by the detection device 200 is that it facilitates the detection of different types of errors. More specifically, it facilitates the detection of errors without observing the operation of the device 100A, the device 100B or the general operation of the system to which the device 100A, the device 100B belongs. The detection device 200 therefore also facilitates the detection of errors that have a direct impact on the operation (SPF, single point failure) and errors that have no direct impact on the operation of the device 100A and the device 100B (LFM, latent fault metric).

[0059] Another advantage of the detection device 200 is that the detection device 200 is independent of the properties of the device 100A and the device 100B, and can be applied to a variety of devices including the combination of Figure 1 The type described is any type of test chain device.

[0060] Another advantage of the detection device 200 is that since the detection device 200 only includes one comparison circuit, feedback loop and multiplexer, the detection device 200 is easy to be used in a circuit including Figure 1 The device 100 is implemented in a system of an electronic device of the type described.

[0061] Figure 5 The diagram is schematically shown in the form of a box. Figure 1 An embodiment of the error detection device 300 between two devices 100C and 100D of the type of device 100. The device 100C and the device 100D may be identical in their structures, and also have processed the same operation, and should have the same test data.

[0062] The apparatus 100C and the apparatus 100D shown in the figure are substantially the same as the apparatus 100A and the apparatus 100B, but each of the apparatus 100C and the apparatus 100D includes a plurality of test chains instead of one test chain. Figure 5 In the embodiment, the apparatus 100C and the apparatus 100D each include two test chains 103C and 103C, and 103D and 103D, and the chains 103C and 103D are different from each other.

[0063] The error detection device 300 is similar to the error detection device 200, except that the error detection device 300 includes the same number of feedback loops 210C, 210D and multiplexers 215C, 215D as the number of test chains 103C, 103D. More specifically, the input of each test chain 103C, 103D is coupled or connected to the input of the multiplexer 215C, 215D through the feedback loop 210C, 210D, and the output of the multiplexer 215C, 215D is coupled or connected to the input of the test chain 103C, 103D. Figure 5 , the device 300 therefore includes four feedback loops 210C and 210D, and four multiplexers 215C and 215D.

[0064] The apparatus 300 further comprises a comparator circuit 320 having as many inputs as the total number of the test chains 103C and the test chains 103D. Figure 5 In , the circuit 320 comprises four inputs. The device 300 receives as input all the outputs of the test chain 103C and the test chain 103D. More specifically, the comparator circuit 320 enables the comparison of the chain 103C and the chain 103D which are expected to have the same data. The circuit 320 may comprise one or more outputs 320OUT. In Figure 5 In the example, the circuit 320 has two outputs. In the case where the circuit 320 comprises a single output, the output can supply a signal representing information of a global comparison between two devices. In the case where the circuit 320 comprises a plurality of outputs 320OUT, each output can, for example, supply a signal representing a comparison between two test chains.

[0065] As an example, the comparator circuit includes as many reference circuits as the test chains in the apparatus 100C, 100D. Figure 2 The comparator circuit 220 is described. Figure 5 In the embodiment, the comparator circuit 320 includes two circuits 220. Figure 6 and Figure 7 Other embodiments of comparator circuit 320 are described.

[0066] Operation and Integration of Device 300 Figure 2 The operation of the device 200 described is identical, performing the comparison of different groups of test chains 103C, 103D in parallel.

[0067] Figure 6 Shows about Figure 2 and Figure 3 A logic circuit 400 of a comparator circuit of the type of detection device is described.

[0068] The logic circuit 400 is a logic circuit that enables comparison of data of two devices E and F, each device comprising four test chains E1 to E4, F1 to F4 respectively. The data of the test chain Ei, with i varying from 1 to 4, are compared with the data of the test chain Fi.

[0069] The logic circuit 400 comprises a first stage comprising four XOR logic gates 401. Each of these gates receives input data from the test chain Ei and input data from the test chain Fi to compare the input data from the test chain Ei with the input data from the test chain Fi.

[0070] The logic circuit 400 includes a second stage, which includes two OR-type logic gates 403. Each gate of the gates 403 receives as input the output of one of the logic gates 401 of the first stage.

[0071] The logic circuit 400 includes a third stage, which includes an OR-type logic gate 405. The logic gate receives as input the output of the logic gate 403 of the second stage.

[0072] Figure 7 Shows about Figure 2 and Figure 3 A logic circuit 500 of a comparator circuit of the type of detection device is described.

[0073] The logic circuit 500 is a logic circuit that enables comparison of data of two identical devices G and H, each of which includes six test chains G1 to G6, H1 to H6, respectively. The data of the test chain Gi with i varying from 1 to 6 is compared with the data of the test chain Hi.

[0074] The logic circuit 500 comprises a first stage including six XOR logic gates 501. Each of these gates receives input data from the test chain Gi and input data from the test chain Hi to compare the input data from the test chain Gi with the input data from the test chain Hi.

[0075] The logic circuit 500 includes a second stage, which includes four "OR" logic gates 503. Each of these gates receives as input the output of one of the logic gates 501 of the first stage. More specifically, some of the gates 501 transmit the output of these gates to multiple gates 503 (see Figure 7 ).

[0076] The logic circuit 500 includes a third stage, which includes two OR-type logic gates 505. Each logic gate 505 receives as input the output of the logic gate 503 of the second stage.

[0077] The logic circuit 500 includes a fourth stage, which includes an OR logic gate 507. The logic gate receives as input the output of the logic gate 505 of the third stage.

[0078] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these various embodiments and variations may be combined, and that other variations will occur to those skilled in the art. In particular, the error detection apparatus 200 and the error detection apparatus 300 may be adapted to compare more than two combinations. Figure 1 An apparatus of the type described is apparatus 100 .

[0079] Finally, based on the functional indications given above, the practical implementation of the described embodiments and variants is within the capabilities of a person skilled in the art.

[0080] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer readable medium is provided, the computer readable medium including a computer program suitable for performing one or more of the methods of the functions described herein. The medium may be a physical storage medium (such as a read-only memory (ROM) chip), or a disk (such as a versatile disk (DVD-ROM), a compact disk (CD-ROM), a hard disk), a memory, a network, or a portable media item to be read by an appropriate drive or via an appropriate connector, including one or more bar codes or other related codes encoded in one or more such computer readable media and readable by an appropriate reader device.

[0081] In some embodiments, some or all of the methods and / or functions may be implemented or provided in other ways, such as at least partially implemented or provided in firmware and / or hardware, including but not limited to one or more application specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), etc., as well as devices using RFID technology and various combinations thereof.

[0082] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications, and publications to provide further embodiments.

[0083] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for detecting an error in an electronic device, comprising: Testing a plurality of electronic devices, each electronic device comprising a test chain having a plurality of test point locations, each test point location storing test data indicating a state of a component coupled to the test point location, the testing comprising: comparing test data in a last test point position of the test chain for each of the electronic devices; Shifting the test data in the test chain of the electronic device forward by one test point position, the shifting comprising writing the test data in the last test point position of the test chain into the first test point position in the test chain; and The comparing and the shifting are repeated until the test data in the last test point position of each test chain when the test starts are shifted back into the last test point position of the corresponding test chain.

2. The method of claim 1, comprising storing segments of test data in the test point locations. The method of claim 2 , wherein the test point location comprises a register or a flip-flop. The method of claim 1 , wherein the test data comprises binary words. The method of claim 1 , wherein the test data comprises a one-bit binary word. The method of claim 1 , wherein the electronic devices each include a plurality of test chains. The method of claim 1 , wherein the plurality of electronic devices comprises more than two electronic devices. The method of claim 1 , comprising generating an output signal based on the comparison. 9 . The method according to claim 1 , wherein the plurality of electronic devices have the same structure and the same function.

10. An electronic device comprising: Comparator; as well as a control circuit arrangement coupled to the comparator, wherein the control circuit arrangement in operation controls testing of a plurality of electronic circuits, each electronic circuit comprising a test chain having a plurality of test point locations, each test point location storing test data indicative of a state of a component coupled to the test point location, the testing comprising: comparing test data in a last test point location of the test chain for each of the electronic circuits; Shifting the test data in the test chain of the electronic circuit forward by one test point position, the shifting comprising writing the test data in the last test point position of the test chain into the first test point position in the test chain; and The comparing and the shifting are repeated until the test data in the last test point position of each test chain when the test starts are shifted back into the last test point position of the corresponding test chain.

11. The device of claim 10, wherein the control circuit device comprises: A plurality of feedback loops are provided, each feedback loop coupling an input and an output of a corresponding test chain.

12. The apparatus of claim 11, wherein each feedback loop comprises a multiplexer.

13. The apparatus of claim 10, wherein the comparator comprises an XOR logic gate.

14. An electronic system comprising: a plurality of electronic devices, each electronic device including a test chain having a plurality of test point locations, each test point location storing test data indicating a state of a component coupled to the test point location; as well as A test circuit device is coupled to the plurality of electronic devices, and the test circuit device is operable to test the plurality of electronic devices, the test comprising: comparing test data in a last test point position of the test chain for each of the electronic devices; Shifting the test data in the test chain of the electronic device forward by one test point position, the shifting comprising writing the test data in the last test point position of the test chain into the first test point position in the test chain; and The comparing and the shifting are repeated until the test data in the last test point position of each test chain when the test starts are shifted back into the last test point position of the corresponding test chain.

15. The system of claim 14, wherein the test point comprises a register or a flip-flop.

16. The system of claim 14, wherein the test data comprises binary words.

17. The system of claim 14, wherein the test data comprises a one-bit binary word.

18. The system of claim 14, wherein the electronic devices each include a plurality of test chains.

19. The system of claim 14, wherein the plurality of electronic devices comprises more than two electronic devices.

20. The system of claim 14, wherein the testing comprises generating an output signal based on the comparison.

21. The system according to claim 14, wherein the plurality of electronic devices have the same structure and the same function.

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