Memory system, method for performing noise cancellation, and computer program product

Abstract

The present disclosure provides a memory system, a method for performing noise cancellation, and a computer program product. A memory system includes a memory device and a memory controller, and the memory controller includes a processor and an internal memory. A computer program including a neural network is stored in the memory system. The processor runs the computer program to: extract a voltage level from each of a plurality of memory cells connected to a string select line (SSL), where the memory cells and the SSL are included in a memory block of the memory device; provide the voltage levels as inputs to the neural network; and perform noise cancellation on the SSL by using the neural network to change at least one of the voltage levels from a first voltage level to a second voltage level. The first voltage level is classified into a first group of memory cells, and the second voltage level is classified into a second group of memory cells different from the first group.

Description

Technical Field

[0001] Exemplary embodiments of the inventive concept relate to a memory device configured to perform noise cancellation using a neural network and a method of performing noise cancellation on a memory device using a neural network. Background Art

[0002] Modern NAND flash memory devices allow storing several bits of data in each memory cell, thereby improving manufacturing cost and performance. A memory cell storing multiple bits of data may be referred to as a multi-level memory cell. The multi-level memory cell divides a threshold voltage range of the memory cell into several voltage states and extracts a data value written to the memory cell using a memory cell voltage level. However, storing multiple bits per memory cell may reduce a dynamic voltage range of each voltage state, making the memory cell more vulnerable to noise. Summary of the Invention

[0003] According to an exemplary embodiment, a memory system includes a memory device and a memory controller, the memory controller including a processor and an internal memory. The memory device operates under the control of the memory controller. A computer program including a neural network is stored in the internal memory of the memory controller or in the memory device. The processor is configured to: run the computer program to extract a voltage level from each of a plurality of memory cells connected to a string select line (SSL), wherein the memory cells and the SSL are included in a memory block of the memory device; provide the voltage level of the memory cell as an input to the neural network; and perform noise cancellation on the SSL using the neural network by changing at least one of the voltage levels of the memory cells from a first voltage level to a second voltage level. The first voltage level is classified into memory cells of a first cluster, and the second voltage level is classified into memory cells of a second cluster different from the first cluster.

[0004] According to an exemplary embodiment, a method of performing noise cancellation on a memory device using a neural network includes: extracting a voltage level from each of a plurality of memory cells connected to a string select line (SSL), wherein the memory cells and the SSL are included in a memory block of the memory device; providing the voltage level of the memory cell as an input to the neural network; and performing noise cancellation on the SSL using the neural network by changing at least one of the voltage levels of the memory cells from a first voltage level to a second voltage level. The first voltage level is classified into memory cells of a first cluster, and the second voltage level is classified into memory cells of a second cluster different from the first cluster.

[0005] According to an exemplary embodiment, a computer program product for performing noise cancellation on a memory device using a neural network includes a computer-readable storage medium having program instructions embodied thereon. The program instructions are executable by a processor to cause the processor to: extract a voltage level from each of a plurality of memory cells connected to a string select line (SSL), wherein the memory cells and the SSL are included in a memory block of the memory device; provide the voltage levels of the memory cells as inputs to the neural network; and perform noise cancellation on the SSL using the neural network by changing at least one of the voltage levels of the memory cells from a first voltage level to a second voltage level. The first voltage level is classified into a first group of memory cells, and the second voltage level is classified into a second group of memory cells different from the first group. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The above and other features of the inventive concept will become more apparent by describing in detail exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0007] Figure 1 is a block diagram showing an implementation of a data processing system including a memory system according to an exemplary embodiment of the inventive concept.

[0008] Figure 2 is according to an exemplary embodiment of the inventive concept Figure 1 detailed block diagram of a non-volatile memory device.

[0009] Figure 3 is a block diagram showing an exemplary embodiment of the inventive concept Figure 1 block diagram of a memory system.

[0010] Figure 4 is according to an exemplary embodiment of the inventive concept Figure 2 block diagram of a memory cell array.

[0011] Figure 5 is according to an exemplary embodiment of the inventive concept Figure 4 circuit diagram of a memory block of a memory cell array.

[0012] Figure 6 is a block diagram showing interference that may occur when programming a word line of a memory block.

[0013] Figure 7 is a flowchart showing an overview of a continuous noise cancellation process performed on a memory block according to an exemplary embodiment of the inventive concept.

[0014] Figure 8It is a diagram showing the structure of a residual neural network (ResNet) for performing noise cancellation according to an exemplary embodiment of the inventive concept.

[0015] Figure 9 It is a graph showing a loss function with respect to a voltage interval (distance) related to ResNet according to an exemplary embodiment of the inventive concept.

[0016] Figure 10 It is a graph showing the result of performing noise cancellation on a memory device using a neural network according to an exemplary embodiment of the inventive concept.

[0017] Figure 11 It is a graph showing the effect of performing noise cancellation on a specific level of a memory block according to an exemplary embodiment of the inventive concept.

[0018] Figure 12 It is a block diagram of a computing system including a non - volatile memory system according to an exemplary embodiment of the inventive concept. Detailed Description

[0019] Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. In all the drawings, like reference numerals may refer to like elements.

[0020] It should be understood that terms such as "first", "second", "third", etc. are used herein to distinguish one element from another, and the elements are not limited by these terms. Thus, the "first" element in an exemplary embodiment may be described as the "second" element in another exemplary embodiment.

[0021] It should be understood that the description of features or aspects in each exemplary embodiment should generally be considered applicable to other similar features or aspects in other exemplary embodiments, unless the context clearly indicates otherwise.

[0022] As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0023] Here, when a value is described as being approximately equal to another value or substantially the same as or equal to another value, it should be understood that these values are equal to each other within the measurement error, or if not equal in measurement, as would be understood by a person of ordinary skill in the art, these values are close enough such that they are functionally equal to each other. For example, considering the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), the term "about" as used herein includes the stated value and means within an acceptable deviation of the particular value as determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, as would be understood by a person of ordinary skill in the art. In addition, it should be understood that although a parameter may be described herein as having "about" a certain value, according to an exemplary embodiment, the parameter may be an exact certain value or approximately a certain value within the measurement error, as would be understood by a person of ordinary skill in the art.

[0024] Figure 1 is a block diagram showing an implementation of a data processing system including a memory system according to an exemplary embodiment of the inventive concept.

[0025] Referring Figure 1 , the data processing system 10 may include a host 100 and a memory system 200. Figure 1 The memory system 200 shown in may be used in various systems including a data processing function. The various systems may be various devices, including for example, mobile devices such as smart phones or tablet computers. However, the various devices are not limited thereto.

[0026] The memory system 200 may include various types of memory devices. Here, an exemplary embodiment of the inventive concept will be described as including a memory device as a non-volatile memory. However, the exemplary embodiment is not limited thereto. For example, the memory system 200 may include a memory device as a volatile memory.

[0027] According to an exemplary embodiment, the memory system 200 may include a non-volatile memory device, such as, for example, a read-only memory (ROM), a magnetic disk, an optical disk, a flash memory, etc. The flash memory may be a memory that stores data based on a change in the threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET), and may include, for example, NAND and NOR flash memories. The memory system 200 may be implemented using a memory card including a non-volatile memory device, such as, for example, an embedded multimedia card (eMMC), a secure digital (SD) card, a micro SD card, or a universal flash storage (UFS), or the memory system 200 may be implemented using, for example, a solid state drive (SSD) including a non-volatile memory device. Here, it will be assumed that the memory system 200 is a non-volatile memory system to describe the configuration and operation of the memory system 200, and thus the memory system 200 may also be directly referred to as the non-volatile memory system 200 hereinafter. However, the memory system 200 is not limited thereto. The host 100 may include, for example, a system-on-chip (SoC) application processor (AP) mounted on a mobile device or a central processing unit (CPU) included in a computer system.

[0028] As described above, the host 100 may include the AP 110. The AP 110 may include various intellectual property (IP) blocks. For example, the AP 110 may include a memory device driver 111 that controls the non-volatile memory system 200. The host 100 may communicate with the non-volatile memory system 200 to send commands related to memory operations and receive acknowledgment commands in response to the sent commands.

[0029] The non-volatile memory system 200 may include, for example, a memory controller 210 and a non-volatile memory device 220. The memory controller 210 may receive commands related to memory operations from the host 100, generate internal commands and internal clock signals using the received commands, and provide the internal commands and internal clock signals to the non-volatile memory device 220. The non-volatile memory device 220 may store write data in the memory cell array in response to the internal commands, or may provide read data to the memory controller 210 in response to the internal commands.

[0030] The non-volatile memory device 220 includes a memory cell array that retains data stored therein even when the non-volatile memory device 220 is not powered on. The memory cell array may include, for example, a NAND or NOR flash memory, a magnetoresistive random-access memory (MRAM), a resistive random-access memory (RRAM), a ferroelectric access-memory (FRAM), or a phase change memory (PCM) as memory cells. For example, when the memory cell array includes a NAND flash memory, the memory cell array may include a plurality of blocks and a plurality of pages. Data may be programmed and read in units of pages, and data may be erased in units of blocks. Figure 4 An example of a memory block included in the memory cell array is shown.

[0031] Figure 2 is of an exemplary embodiment according to the inventive concept Figure 1 detailed block diagram of the non-volatile memory device 220.

[0032] Referring to Figure 2 , the non-volatile memory device 220 may include, for example, a memory cell array 221, a control logic 222, a voltage generation unit 223, a row decoder 224, and a page buffer 225.

[0033] The memory cell array 221 may be connected to one or more string select lines (SSL), a plurality of word lines (WL), one or more ground select lines (GSL), and a plurality of bit lines (BL). The memory cell array 221 may include a plurality of memory cells disposed at intersections between the plurality of word lines (WL) and the plurality of bit lines (BL).

[0034] The control logic 222 may receive a command CMD (e.g., an internal command) and an address ADD from the memory controller 210, and receive a control signal CTRL for controlling various functional blocks within the non-volatile memory device 220 from the memory controller 210. The control logic 222 may output various control signals for writing data to or reading data from the memory cell array 221 based on the command CMD, the address ADD, and the control signal CTRL. In this way, the control logic 222 may control the overall operation of the non-volatile memory device 220.

[0035] Various control signals output from the control logic 222 may be provided to the voltage generation unit 223, the row decoder 224, and the page buffer 225. For example, the control logic 222 may provide a voltage control signal CTRL_vol to the voltage generation unit 223, a row address X-ADD to the row decoder 224, and a column address Y-ADD to the page buffer 225.

[0036] The voltage generation unit 223 may generate various voltages for performing programming, reading, and erasing operations on the memory cell array 221 based on the voltage control signal CTRL_vol. For example, the voltage generation unit 223 may generate a first driving voltage VWL for driving a plurality of word lines WL, a second driving voltage VSSL for driving one or more string selection lines SSL, and a third driving voltage VGSL for driving one or more ground selection lines GSL. In this case, the first driving voltage VWL may be a programming voltage (e.g., write voltage), a read voltage, an erase voltage, a pass voltage, or a programming verification voltage. In addition, the second driving voltage VSSL may be a string selection voltage (e.g., turn-on voltage or turn-off voltage). Further, the third driving voltage VGSL may be a ground selection voltage (e.g., turn-on voltage or turn-off voltage).

[0037] The row decoder 224 may be connected to the memory cell array 221 through a plurality of word lines WL, and may activate a part of the plurality of word lines WL in response to the row address X-ADD received from the control logic 222. For example, in a read operation, the row decoder 224 may apply a read voltage to the selected word lines and a pass voltage to the unselected word lines.

[0038] In a programming operation, the row decoder 224 may apply a programming voltage to the selected word lines and a pass voltage to the unselected word lines. In an exemplary embodiment, in at least one of a plurality of programming cycles, the row decoder 224 may apply a programming voltage to the selected word lines and additionally selected word lines.

[0039] The page buffer 225 may be connected to the memory cell array 221 through a plurality of bit lines BL. For example, in a read operation, the page buffer 225 may operate as a sense amplifier for outputting data stored in the memory cell array 221. Alternatively, in a programming operation, the page buffer 225 may operate as a write driver for writing desired data to the memory cell array 221.

[0040] Figure 3 is a block diagram of a Figure 1 memory system 200 according to an exemplary embodiment of the inventive concept.

[0041] Reference Figure 3 Figure 3 , the memory system 200 includes a memory device 220 and a memory controller 210. Here, the memory controller 210 may also be referred to as a controller circuit. The memory device 220 may perform a write operation, a read operation, or an erase operation under the control of the memory controller 210.

[0042] The memory controller 210 may control the memory device 220 depending on a request received from the host 100 or an internally specified schedule. The memory controller 210 may include a controller core 121, an internal memory 124, a host interface block 125, and a memory interface block 126.

[0043] The controller core 121 may include a memory control core 122 and a machine learning core 123, and each of these cores may be implemented by one or more processors. The memory control core 122 may control and access the memory device 220 depending on a request received from the host 100 or an internally specified schedule. The memory control core 122 may manage and run various metadata and codes for managing or operating the memory system 200.

[0044] The machine learning core 123 may be used to perform training and inference of a neural network that is designed to perform noise cancellation on the memory device 220, as described in further detail below.

[0045] The internal memory 124 may be used, for example, as a system memory used by the controller core 121, a cache memory for storing data of the memory device 220, or a buffer memory for temporarily storing data between the host 100 and the memory device 220. The internal memory 124 may store a mapping table MT that indicates the relationship between the logical addresses assigned to the memory system 200 and the physical addresses of the memory device 220. The internal memory 124 may include, for example, DRAM or SRAM.

[0046] In an exemplary embodiment, a neural network (such as the reference Figure 8The described neural network) may be included in a computer program stored in the internal memory 124 of the memory controller 210 or the memory device 220. The computer program including the neural network may be run by the machine learning core 123 to denoise the data stored in the memory device 220. Accordingly, according to an exemplary embodiment, the memory system 200 may denoise the data stored in the memory device 220 during a normal read operation of the memory device 220. That is, after the manufacturing of the memory system 200 is completed, during the normal operation of the memory system 200, and in particular, during a normal read operation of the memory system 200 in which data is read from the memory device 220, the data stored in the memory device 220 being read may be denoised using a neural network locally stored in the memory system 200 and run by the memory system 200, and the denoised data may be read out from the memory device 220.

[0047] The host interface block 125 may include components for communicating with the host 100, such as, for example, physical blocks. The memory interface block 126 may include components for communicating with the memory device 220, such as, for example, physical blocks.

[0048] Next, the operation of the memory system 200 over time will be described. When power is supplied to the memory system 200, the memory system 200 may perform initialization using the host 100.

[0049] The host interface block 125 may provide a first request REQ1 received from the host 100 to the memory control core 122. The first request REQ1 may include a command (e.g., a read command or a write command) and a logical address. The memory control core 122 may convert the first request REQ1 into a second request REQ2 suitable for the memory device 220.

[0050] For example, the memory control core 122 may convert the format of the command. The memory control core 122 may refer to a mapping table MT stored in the internal memory 124 to obtain address information A1. The memory control core 122 may convert the logical address into a physical address of the memory device 220 by using the address information A1. The memory control core 122 may provide the second request REQ2 suitable for the memory device 220 to the memory interface block 126.

[0051] The memory interface block 126 may register the second request REQ2 from the memory control core 122 in a queue. The memory interface block 126 may send the request first registered in the queue as a third request REQ3 to the memory device 220.

[0052] When the first request REQ1 is a write request, the host interface block 125 may write the data received from the host 100 into the internal memory 124. When the third request REQ3 is a write request, the memory interface block 126 may send the data stored in the internal memory 124 to the memory device 220.

[0053] When the data is completely written, the memory device 220 may send a third response RESP3 to the memory interface block 126. In response to the third response RESP3, the memory interface block 126 may provide a second response RESP2 indicating that the data is completely written to the memory control core 122.

[0054] After the data is stored in the internal memory 124 or after receiving the second response RESP2, the memory control core 122 may send a first response RESP1 indicating that the request is completed to the host 100 through the host interface block 125.

[0055] When the first request REQ1 is a read request, the read request may be sent to the memory device 220 through the second request REQ2 and the third request REQ3. The memory interface block 126 may store the data received from the memory device 220 in the internal memory 124. When the data is completely sent, the memory device 220 may send the third response RESP3 to the memory interface block 126.

[0056] When receiving the third response RESP3, the memory interface block 126 may provide a second response RESP2 indicating that the data is completely stored to the memory control core 122. When receiving the second response RESP2, the memory control core 122 may send the first response RESP1 to the host 100 through the host interface block 125.

[0057] The host interface block 125 may send the data stored in the internal memory 124 to the host 100. In an exemplary embodiment, in the case where the data corresponding to the first request REQ1 is stored in the internal memory 124, the transmission of the second request REQ2 and the third request REQ3 may be omitted.

[0058] Figure 4 and Figure 5 An example of implementing the memory system 200 using a three-dimensional flash memory is shown. The three-dimensional flash memory may include three-dimensional (e.g., vertical) NAND (e.g., VNAND) memory cells. Embodiments of a memory cell array 221 including three-dimensional memory cells are described below. Each of the memory cells described below may be a NAND memory cell.

[0059] Figure 4 is according to an exemplary embodiment of the inventive conceptFigure 2 Block diagram of the memory cell array 221.

[0060] Reference Figure 4 , according to an exemplary embodiment, the memory cell array 221 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz has a three-dimensional structure (e.g., a vertical structure). For example, each of the memory blocks BLK1 to BLKz may include a structure extending in a first to a third direction. For example, each of the memory blocks BLK1 to BLKz may include a plurality of NAND strings extending in a second direction. For example, a plurality of NAND strings may be provided in a first to a third direction.

[0061] Each of the NAND strings is connected to a bit line BL, a string select line SSL, a ground select line GSL, a word line WL, and a common source line CSL. That is, each of the memory blocks BLK1 to BLKz may be connected to a plurality of bit lines BL, a plurality of string select lines SSL, a plurality of ground select lines GSL, a plurality of word lines WL, and a common source line CSL. The memory blocks BLK1 to BLKz will be described in more detail below with reference to Figure 5 the memory blocks BLK1 to BLKz will be described in more detail.

[0062] Figure 5 is a circuit diagram of the memory block BLKi according to an exemplary embodiment of the inventive concept. Figure 5 Shows Figure 4 an example of one of the memory blocks BLK1 to BLKz in the memory cell array 221.

[0063] The memory block BLKi may include a plurality of cell strings CS11 to CS41 and CS12 to CS42. The plurality of cell strings CS11 to CS41 and CS12 to CS42 may be arranged in a column direction and a row direction to form columns and rows. Each of the cell strings CS11 to CS41 and CS12 to CS42 may include a ground select transistor GST, memory cells MC1 to MC6, and a string select transistor SST. The ground select transistor GST, the memory cells MC1 to MC6, and the string select transistor SST included in each of the cell strings CS11 to CS41 and CS12 to CS42 may be stacked in a height direction substantially perpendicular to the substrate.

[0064] Columns of multiple cell strings CS11 to CS41 and CS12 to CS42 can be respectively connected to different string select lines SSL1 to SSL4. For example, the string select transistors SST of cell strings CS11 and CS12 can be commonly connected to string select line SSL1. The string select transistors SST of cell strings CS21 and CS22 can be commonly connected to string select line SSL2. The string select transistors SST of cell strings CS31 and CS32 can be commonly connected to string select line SSL3. The string select transistors SST of cell strings CS41 and CS42 can be commonly connected to string select line SSL4.

[0065] Rows of multiple cell strings CS11 to CS41 and CS12 to CS42 can be respectively connected to different bit lines BL1 and BL2. For example, the string select transistors SST of cell strings CS11 to CS41 can be commonly connected to bit line BL1. The string select transistors SST of cell strings CS12 to CS42 can be commonly connected to bit line BL2.

[0066] Columns of multiple cell strings CS11 to CS41 and CS12 to CS42 can be respectively connected to different ground select lines GSL1 to GSL4. For example, the ground select transistors GST of cell strings CS11 and CS12 can be commonly connected to ground select line GSL1. The ground select transistors GST of cell strings CS21 and CS22 can be commonly connected to ground select line GSL2. The ground select transistors GST of cell strings CS31 and CS32 can be commonly connected to ground select line GSL3. The ground select transistors GST of cell strings CS41 and CS42 can be commonly connected to ground select line GSL4.

[0067] Memory cells set at the same height from the substrate (or ground select transistor GST) can be commonly connected to a single word line, and memory cells set at different heights from the substrate can be respectively connected to different word lines WL1 to WL6. For example, memory cell MC1 can be commonly connected to word line WL1. Memory cell MC2 can be commonly connected to word line WL2. Memory cell MC3 can be commonly connected to word line WL3. Memory cell MC4 can be commonly connected to word line WL4. Memory cell MC5 can be commonly connected to word line WL5. Memory cell MC6 can be commonly connected to word line WL6. The ground select transistors GST of cell strings CS11 to CS41 and CS12 to CS42 can be commonly connected to a common source line CSL.

[0068] Figure 6 It is a block diagram showing interference that may occur when programming the word lines of a memory block.

[0069] When storing many bits in a single memory cell, programming noise may cause errors in the stored data. For example, in a VNAND memory device, when a word line is being programmed (written), this programming may cause noise to occur on adjacent word lines, which may cause errors when those word lines are read later. Memory cells that are geometrically one above the other (e.g., memory cells in the same pillar or column) may generate particularly strong noise.

[0070] Examples will be described herein with reference to Figures 6 to 11 a case where 6 bits per cell (6BPC) are written across an entire memory block. However, it should be understood that the exemplary embodiments are not limited thereto. For example, the exemplary embodiments may be applied to a 5 bits per cell (5BPC) or 4 bits per cell (4BPC) scheme.

[0071] In the 6BPC scheme, when the state of a memory cell (e.g., the voltage contained in the memory cell) belongs to one of 2 6 ^6 = 64 states (the states of each combination of 0s and 1s for 6 bits), the memory cell stores information for 6 bits. That is, in the 6BPC scheme, there are 64 possible states for each memory cell, where each state corresponds to one of 64 predefined voltage levels. As a result, the memory cells are naturally grouped into 64 different groups, where each group is characterized by the voltage level shared by all the memory cells in that group. A group of memory cells having the same voltage may be referred to as a logical entity, and this logical entity is called a level (hereinafter also referred to as a memory cell level). Memory cells included in the same group (the same memory cell level) may have voltage levels that are substantially the same as each other. For example, in the 6BPC scheme, since there is a relatively small voltage window (e.g., about 120 millivolts per level) for each of the 64 levels required to maintain the 6BPC scheme, the difference between the voltage levels grouped into the same group is typically less than about 120 millivolts.

[0072] Since each word line WL is physically connected to multiple different memory cells, each memory cell having one of 64 voltage levels, each word line WL can be described as having 64 voltage levels. Thus, in the 6BPC scheme, the word line WL can have 64 different voltage levels (2 6 ^6 = 64), in the 5BPC scheme, the word line WL can have 32 different voltage levels (2 5 ^5 = 32), or in the 4BPC scheme, the word line WL can have 16 different voltage levels (2 4= 16). As the voltage levels become increasingly dense, the probability of leakage from one level to another and thus the probability of an error occurring increases. Thus, the probability of an error occurring in the 6BPC scheme is higher than in the 5BPC or 4BPC schemes.

[0073] Since memory cells are grouped according to their voltages and since the voltage can change due to various interferences, some memory cells may change their voltage by a large enough amount to cause misclassification (i.e., some memory cells may be grouped into the wrong group because they are now closer to the voltage level of that group than to their own correct voltage). Since the levels (i.e., groups) correspond to the assumed state of the memory cells (and thus to the content of their bits), the content of the misclassified memory cells will be misread, resulting in an error. Thus, the exemplary embodiment attempts to correct the voltage of this memory cell when the memory cell is being read to reduce the amount of misclassification that occurs. The exemplary embodiment achieves this by using a neural network that attempts to classify the errant memory cells back into their expected groups by correcting the errors in their voltages during the memory read operation.

[0074] Memory cells storing the same bit information are programmed to have approximately the same voltage level and are grouped / together in the same level of the memory block 601. Thus, each word line WL contains memory cells that are grouped together into 64 different groups (voltage levels) according to their voltage. Referring again to Figure 5 , each string select line is connected to a plurality of cell strings. For example, the string select line SSL1 is connected to the cell strings CS11 and CS12, the string select line SSL2 is connected to the cell strings CS21 and CS22, and so on. Thus, one string select line is connected to a plurality of different memory cells in different levels. As an example, the string select line SSL1 may be connected to the memory cell MC1 connected to the word line WL1, which may contain a voltage that groups it into level 6, and then may be connected to the memory cell MC2 connected to the word line WL2, which may contain a different voltage that groups it into level 2, and so on.

[0075] Writing 6 bits per cell across the entire memory block involves many write operations. During the programming process, subsequent programming pulses may cause noise that significantly interferes with the memory cells previously programmed by earlier programming pulses. This noise can severely limit the effectiveness of block programming. This noise is generally not linear in nature. Instead, this noise is typically repeatedly applied (by each new programming pulse), making it difficult to model probabilistically.

[0076] Exemplary embodiments of the inventive concept are directed to implicitly modeling and subsequently eliminating this noise using machine learning and deep learning tools. For example, an exemplary embodiment may use a neural network to model and eliminate this noise, and the neural network is trained offline using supervised learning. The neural network may be trained based on the BPC scheme utilized by the memory device. For example, since the data distribution is different in each of the 6BPC scheme, 5BPC scheme, and 4BPC scheme, the neural network may be trained differently to process data stored according to the 6BPC scheme, 5BPC scheme, or 4BPC scheme. An exemplary embodiment may be implemented during a read operation to obtain a more accurate reading of the voltage level of the memory cell. After an inaccurate (e.g., noisy) voltage measurement of the memory cell is read, at least some of the inaccurate noise is eliminated before the memory cells are binned into their respective voltage levels. Then, when data corresponding to the binned cells is read out from the memory device, the cell may be converted into digital data and output by the memory device. An exemplary embodiment may utilize a deep residual network as well as additional preprocessing and postprocessing algorithms to eliminate this noise, as described in further detail below.

[0077] Although Figure 6 the example of shows 100 word lines WL, the exemplary embodiment is not limited thereto. For example, the exemplary embodiment may be used in a memory device having 128 or 256 word lines or another number of word lines divisible by 4.

[0078] Referring Figure 6 , in an exemplary embodiment, a single memory block 601 in which 6 bits are written per cell is divided into four quarters, each quarter including 25 vertically stacked word lines WL (see word lines WL1 to WL100). The word lines of each quarter are connected to a string select line SSL. For example, word lines WL1, WL5... WL97 are connected to a first string select line SSL1, word lines WL2, WL6... WL98 are connected to a second string select line SSL2, word lines WL3, WL7... WL99 are connected to a third string select line SSL3, and word lines WL4, WL8... WL100 are connected to a fourth string select line SSL4. In Figure 6 , for ease of illustration, some word lines and string select lines are not explicitly labeled. However, the positions of these word lines and string select lines are clear relative to the labeled word lines and string select lines.

[0079] To write to memory block 601, word lines WL1 to WL100 are continuously written by applying programming pulses to the memory cells connected to the word lines until all memory cells have their correct voltage levels. During this write process, voltage leakage may occur whenever a target memory cell is being programmed, and all other memory cells connected to the same string select line SSL as the target memory cell may be disturbed by noise. As described above, this noise may cause the voltage levels of other previously programmed memory cells on the string select line SSL to change, which may lead to additional errors when these memory cells are read later.

[0080] For example, as Figure 6 shown, word lines WL3, WL7…WL99 are connected to the same string select line SSL3. When word line WL7 is being programmed (written) ( Figure 6 the "programmed word line" in Figure 6 ), the memory cells connected to word line WL7 are programmed ( Figure 6 the "programmed cell" in Figure 6 ). In the example of

[0081] , the programmed memory cell is the target memory cell. When the target memory cell connected to word line WL7 and string select line SSL3 is being programmed, all other memory cells connected to the same string select line SSL3 may be disturbed by noise ( Figure 6 the "perturbed cells" in

[0081] ). For example, when the target memory cell is being programmed to a high voltage level while an adjacent memory cell (e.g., a perturbed cell) connected to the same string select line SSL3 has a low voltage level, the programming of the target memory cell may cause particularly large interference to its adjacent cell.

[0081] For example, when interference occurs repeatedly as a result of programming many word lines WL of memory block 601, these interferences may cause voltage offsets of up to several hundred millivolts. In some exceptional cases, larger voltage offsets may occur. Since there is a relatively small voltage window (e.g., approximately 120 millivolts per level) for each of the 64 levels required to maintain the 6BPC scheme, such interference may render all levels of the memory cell array 221 unreadable, which may lead to a large number of errors when reading data from the memory cell array 221. Exemplary embodiments of the inventive concept solve this problem by attempting to restore each word line WL to its corresponding state after the word line WL has been programmed and before the programming of adjacent word lines WL causes interference during a memory read operation. For example, each word line WL can be restored during a memory read operation by decoding the memory cells back to the information bits they hold. Thus, in an exemplary embodiment, the memory cells can be denoised during a memory read operation to correct errors that occurred previously during a memory write operation.

[0082] Figure 7 is a flowchart showing an overview of a successive noise cancellation process performed on a memory block according to an exemplary embodiment of the inventive concept.

[0083] Figure 7 The successive noise cancellation process shown is performed during a memory block read phase and can correct errors caused during a memory block write phase. The successive noise cancellation process accepts a noisy memory block as its input and then returns a cleaned (denoised) memory block as its output. The cleaned memory block will be returned per SSL as described below. In a 6BPC scheme, the output denoised memory block can then be read as bits of 6 * n_wls pages, where n_wls is the number of word lines in the memory block.

[0084] Algorithm 1 shown below corresponds to Figure 7 the flowchart of Figure 7 and describes how each of operations 701 to 707 of is implemented according to an exemplary embodiment. The values used in Algorithm 1 correspond to the 6BPC scheme. For example, X in Algorithm 1 corresponds to the noisy SSL received as input in operation 701, 1 in Algorithm 1 corresponds to operation 702, 2 in Algorithm 1 corresponds to operation 703, 3 in Algorithm 1 corresponds to operation 704, 4 in Algorithm 1 corresponds to operation 705, 5 in Algorithm 1 corresponds to operation 706, and

[0085] Algorithm 1: 25 word lines

[0086] · X - Noisy data - 25 word lines X 147456 cell matrix

[0087] · M i - Constant mean at level i, 0 ≤ i < 64

[0088] 1. Data normalization

[0089] (a) X = (X + 2500) / (6500 + 2500) * 2 - 1

[0090] 2. Electrical mean correction

[0091] (a) T i = Threshold at levels i, i + 1, 0 ≤ i < 64

[0092] (b) L i = Level i = {x | T i-1 ≤ x < T i , x ∈ X}

[0093] (c) μ i = mean(L i )

[0094] (d) L i = L i - (μ i - M i ) = {x - (μ i - M i ) | x ∈ L i}

[0095] 3. ResNet Noise Cancellation

[0096] (a)

[0097] 4. Word Line and Level Skipping

[0098] (a) for in

[0099] i. for in

[0100] A.

[0101] B.

[0102] 5. Data Denormalization

[0103] (a)

[0104] 6. Return

[0105] Reference Figure 7 , operations 702 and 703 belong to the preprocessing stage of the noise cancellation method, operations 704 and 705 belong to the training / inference stage of the noise cancellation method, and operation 706 belongs to the postprocessing stage of the noise cancellation method.

[0106] In operation 701, the noisy SSL on which continuous noise cancellation is to be performed is read and used as the input to the neural network for performing noise cancellation. That is, in operation 701, the voltage levels of the memory cells connected to the noisy SSL are received as input. In the 6BPC scheme, algorithm 1 is run independently on four SSls (once for each SSL in the memory block), as further described below. Algorithm 1 can be executed independently on the four SSls either in parallel or sequentially. Thus, once each of the four SSls (in the 6BPC scheme) in the memory block is received as input and denoised, the noisy memory block is considered denoised. Refer to Figure 8Describe the neural network in more detail. For example, in operation 701, the voltage levels of the memory cells connected to the noisy SSL on which continuous noise cancellation is being performed can be read and extracted from the noisy SSL and provided as inputs to the neural network. In an exemplary embodiment, the value of each of the voltage levels of the memory cells can be between approximately -3000 millivolts and approximately 6000 millivolts.

[0107] Reference Figure 6 and Figure 7 , in operation 701, in an exemplary embodiment, each of the string selection lines SSL1, SSL2, SSL3, and SSL4 is connected to a set of word lines, and each of the string selection lines SSL1, SSL2, SSL3, and SSL4 is independently processed to denoise the word lines (and memory cells) connected thereto. For example, to perform the noise cancellation method on the memory block 601, operations 702 to 706 (operations 1 to 5 in Algorithm 1) can be continuously performed 4 times on the string selection lines SSL1 to SSL4. Once each of the string selection lines SSL1 to SSL4 has been denoised, the memory block 601 is finally considered to be denoised. For example, operations 702 to 706 can first be performed on the string selection line SSL1 connected to Quarter 0, then on the string selection line SSL2 connected to Quarter 1, then on the string selection line SSL3 connected to Quarter 2, and then on the string selection line SSL4 connected to Quarter 3. Thus, the width of the input to the neural network is equal to the number of word lines WL connected to a single string selection line SSL (e.g., the number of word lines WL in the memory block divided by 4) (e.g., Figure 6 25 in

[0108] In operation 702, the data received in operation 701 is normalized before being provided as an input to the neural network. For example, in operation 702, each of the voltage levels of the memory cells connected to the input SSL and extracted in operation 701 is normalized such that the input received by the neural network has fixed upper and lower limits. Normalization of the voltage levels can allow the data to fit better in the neural network used for performing noise cancellation. In an exemplary embodiment, all the voltage levels of the memory cells received as inputs (via the input SSL) in operation 701 are normalized to the range [-1, 1]. However, the exemplary embodiment is not limited thereto.

[0109] In operation 703, voltage electrical average correction is performed. That is, mean correction is performed on the normalized voltage levels. For example, the offset of the mean of the normalized voltage levels is compensated to allow the voltage levels to be provided as inputs to the neural network. As a result of performing mean correction on the normalized voltage levels, when the voltage levels are provided as inputs to the neural network, the neural network in the exemplary embodiment only needs to learn to correct the deviation of the voltage levels.

[0110] In an exemplary embodiment, voltage electrical average correction is performed using a (plurality of) predefined tables including the mean of the voltage levels of the sanitized (denoised) memory blocks. The size of the table can be n_wls * n_levels, where n_wls is the number of word lines, n_levels is the number of levels, and each memory cell (i, j) contains an estimated placement of the mean of level j in word line i. The value of the sanitized version of the noisy memory block can be estimated by averaging many different memory blocks. In an exemplary embodiment, the variation of the memory block over time can be considered. Each word line WL in the noisy memory block can be divided into 64 voltage levels (in the 6BPC scheme), and the estimated noise levels can be shifted so that their mean is consistent with the predefined mean of the sanitized version. By bringing the estimated means of many memory cells within a few tens of millivolts of the sanitized mean, performing voltage electrical average correction can greatly reduce their overall offset, thus improving the ability of the neural network to learn.

[0111] For example, in operation 703, the mean of the noisy voltage level distribution is corrected to be as close as possible to the mean of the original (sanitized) voltage level distribution. This allows the neural network to be able to focus on reducing the variance of the noise, only making a small correction to the mean. For example, since this interval correction is common to all memory cells in the stage, the noisy voltage level distribution is corrected to be closer to the distribution in the case without noise. As a result, the neural network can perform noise cancellation by only learning the memory cell-specific noise.

[0112] Even if the voltage electrical average correction performed in operation 703 is not precise, most of the difference between the means can still be eliminated. As a result, for example, by focusing on the in-depth details instead of spending time on the rough differences, the neural network can work less to bring each memory cell to its correct (sanitized) position. As a result, the accuracy and precision of noise cancellation can be improved. For example, if the difference between the means of the sanitized level data and the noisy level data is 150 millivolts and is corrected to -10, the performance and efficiency of the neural network will increase because the neural network will only need to correct each memory cell by approximately (10 + noise_std) millivolts instead of (150 + noise_std) millivolts.

[0113] In operation 704, a neural network is used to perform noise cancellation. The neural network can be, for example, a Residual Neural Network (ResNet). ResNet can cancel the noise present in the input data and return a purified (denoised) memory block.

[0114] Noise cancellation can be performed based on deep learning using a database. Deep learning is a sub-concept of machine learning and is a neural network model of a type of machine learning related to artificial intelligence. Various neural network architectures can be used for deep learning. For example, an artificial neural network (ANN), a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), and a generative adversarial network (GAN) can be used for deep learning. However, the network architectures available for deep learning are not limited to this.

[0115] The following will refer to Figure 8 describe in more detail the use of a neural network to perform noise cancellation as implemented in operation 704.

[0116] Referring to operation 705, although performing noise cancellation on a memory block can provide an improvement in the bit error rate (BER) of some memory cells, it is possible that performing noise cancellation may have no effect on other memory cells, or may actually cause the BER of other memory cells to become worse. In operation 705, a validity check is performed during training, and a level skip operation based on the result of the validity check is performed during inference.

[0117] For example, during training, a validity check can be performed to determine for which levels on which word lines WL the noise cancellation improves the BER, and for which levels on which word lines WL the noise cancellation does not improve the BER or makes the BER worse. The validity check can be implemented by checking each level on each word line WL and comparing the BER of each level before performing the noise cancellation with the BER after performing the noise cancellation. Since the true value of the voltage level of the memory cells is known during training, this analysis can be performed. The result of the validity check can be saved in, for example, a (multiple) table and used during inference to perform the level skip operation.

[0118] Still referring to operation 705, during inference, a level skip operation is performed based on the result of the validity check. In the level skip operation, the voltage levels that have become worse due to the noise cancellation performed during operation 704 are restored to their original noisy state before being read out from the memory device. That is, the voltage levels of the memory cells belonging to the word lines WL for which the BER has not improved (or has become worse) are restored to their voltage levels before noise cancellation before being read out from the memory device. Thus, the exemplary embodiment applies noise cancellation only when such application is likely to provide a positive result, and avoids applying noise cancellation when such application will not improve the result or will make the result worse.

[0119] In operation 706, data denormalization is performed to convert the purified (denoised) data in the range of [-1, 1] back to the original range (e.g., [-3000, 6000]).

[0120] In operation 707, the neural network outputs a denoised version of the SSL input in operation 701. When the memory device outputs (e.g., reads from the memory device) data corresponding to the SSL, the denoised version of the SSL output by the neural network can be used, as described in further detail below with reference to Figure 8 Once each SSL in the memory block (e.g., Figure 6 SSL1 to SSL4 therein) has been denoised, the memory block 601 is considered to be denoised.

[0121] In the exemplary embodiment, operations 702 and 706 and / or operation 703 may be omitted.

[0122] Figure 8 is a diagram showing the structure of a neural network used in Figure 7 operation 704 according to an exemplary embodiment of the inventive concept, and more specifically, shows the structure of a residual neural network (ResNet).

[0123] In the exemplary embodiment, the noise cancellation performed in Figure 7 operation 704 is performed using a ResNet having a number of identical consecutive residual blocks. An example of such a ResNet is as shown in Figure 8 This configuration allows for an iterative noise cancellation process to be performed, where only the noise is learned (e.g., where only the difference between the purified data and the noisy data is learned). For example, the ResNet can learn to continuously denoise the data, learning only the noise increment for each iteration.

[0124] The input to the ResNet is a single noisy SSL (e.g., Figure 6One of the SSL1, SSL2, SSL3, and SSL4 shown), and the output is the denoised SSL. Since the exemplary embodiment utilizes a single SSL each time noise cancellation is performed, only the loss of voltage (the interval between the noisy cell voltage and the purified cell voltage) is measured in the exemplary embodiment. However, since the original BER is a non - monotonic measurement with respect to the voltage interval, measuring only the loss of voltage allows the reduction or minimization of the original BER.

[0125] In Figure 8 , the numbers in each of the layers 801 - 807, 809 - 815, and 817 indicate the number of neurons in that layer. The indication "x1" in the input layer 801 and the output layer 817 indicates the shape of these layers. For example, each of the input layer 801 and the output layer 817 includes 25 neurons, and its shape is a vector of 25. The width of the input layer is equal to the number of word lines WL connected to a single string selection line SSL (e.g., the number of word lines WL in a memory block divided by 4) (e.g., 25 in the 6BPC scheme as Figure 6 shown). The input layer 801 corresponds to the noisy SSL fed into the neural network for denoising.

[0126] The type of each layer in the neural network is a fully - connected layer. That is, each neuron in each layer is connected to each neuron in the next layer. The connections between these neurons have corresponding weights, which are learned during training. When each layer is filled with certain inputs from the previous layer, it multiplies the inputs by certain weights and then performs a non - linear operation (e.g., the Rectified Linear Unit (ReLU) function) before transmitting the result as an input to the next layer.

[0127] The arrows between the layers indicate the type of activation function for the neurons in that layer. In the exemplary embodiment, the Rectified Linear Unit (ReLU) function, as a non - linear function, is used as the activation function between the layers 802 and 803, 803 and 804, 804 and 805, 805 and 806, 806 and 807, 809 and 810, 810 and 811, 811 and 812, 812 and 813, 813 and 814, and 814 and 815. The ReLU activation function determines whether a neuron should be activated by calculating the weighted sum of the inputs of the neuron and adding a bias, thus introducing non - linearity into the output of the neuron. A linear function is used as the activation function between the layer 801 and the operation 808, the layer 807 and the operation 808, the operation 808 and the layer 809, the layer 809 and the operation 816, the layer 815 and the operation 816, and the operation 816 and the layer 817. That is, between these layers and operations, no non - linear activation function is performed.

[0128] Operation 808 adds the output of layer 807 to the input layer 801 and feeds this output to layer 809. Operation 816 adds the output of layer 815 to layer 809 and feeds this output to the output layer 817. The output layer 817 outputs the denoised SSL.

[0129] When data is output from a memory device (e.g., read from a memory device), the denoised SSL output by the output layer 817 can be used. For example, referring to Figure 6 , assume that the data stored in a memory cell connected to the string select line SSL3 (e.g., one of the memory cells connected to word lines WL3, WL7,..., WL99) is being read out from the memory device. For example, data can be read out from the memory device when accessed by a user, when passed to a subsequent stage of data processing, etc. When reading data from the memory device, the operations described above with reference to Figure 7 can be performed to denoise (e.g., correct) the data before it is read out from the memory device.

[0130] For example, when a request is made to read data from one of the memory cells connected to word lines WL3, WL7,..., WL99, the neural network first denoises the string select line SSL3 by changing the voltage level of at least one of the memory cells connected to word lines WL3, WL7,..., WL99 from a first voltage level to a second voltage level, where the first voltage level is classified as belonging to a first group (out of 64 groups in the 6BPC scheme) and the second voltage level is classified as belonging to a second group (out of 64 groups in the 6BPC scheme).

[0131] It should be noted that at this time, the voltage level of such a memory cell does not actually change within the memory device, because writing to the memory cell would reintroduce noise for the same reasons as above. Instead, the changed (corrected) voltage level of such a memory cell output by the neural network is output by the memory device when reading data from such a memory cell, rather than the actual voltage level of such a memory cell within the memory device being read at this time. That is, a cleaner, denoised version of the data generated by the neural network is output by the memory device, while the noisy version of the data actually stored in the memory device remains untouched and unchanged in the memory device. Therefore, this process can be performed again whenever this data is read out from the memory device.

[0132] As referred to above Figure 7The described level skipping operation 705 can be performed when reading data from a memory device such that when reading from the memory device, voltage levels that have become worse through noise cancellation do not change (e.g., the actual, unchanged voltage levels in the memory device can be read for these memory cells). A cleaner, denoised version of the data (and any data that is intentionally left unchanged according to the level skipping operation 705) can be converted to digital form before being read from the memory device.

[0133] Since the BER is determined by mapping levels to a Grey code of bits, in some cases reducing voltage error may potentially increase the number of error bits per cell. Thus, an exemplary embodiment can approximate the BER loss within a range that is still monotonic and additionally has a constant loss. For example, according to an exemplary embodiment, the loss function can be normalized and approximate a linear loss over two level intervals and then be constant with respect to Figure 9 the voltage intervals shown.

[0134] For example, Figure 9 the curve in shows the behavior of the loss function with respect to the distribution of levels in a word line according to an exemplary embodiment. For example, the loss function can focus on (i.e., increase the loss for) small intervals (separating up to two levels) and then fix the loss from that point on (i.e., by treating the error for intervals greater than two levels as bounded by the intervals of two levels). This forces the neural network to improve small errors, where any correction will translate to an improvement in the BER, and less focus on large errors since correcting such large errors is not guaranteed to help the BER as it is not a monotonic function.

[0135] Figure 10 is a graph showing the result of performing noise cancellation on a memory device using a neural network according to an exemplary embodiment of the inventive concept. Figure 11 is a graph showing the effect of performing noise cancellation on a specific level of a memory block according to an exemplary embodiment of the inventive concept.

[0136] As Figure 10 shown, in a test scenario, according to an exemplary embodiment of the inventive concept, performing noise cancellation on a memory device using a neural network corrected some additional noise and improved the overall raw BER of the noisy data by approximately 14% to about 17%. For example, in Figure 10In it, line A represents noisy data with a mean BER of approximately 0.1779, line B represents predicted data (e.g., denoised data according to an exemplary embodiment) with a mean BER of approximately 0.1478, and line C represents best data (e.g., noise-free data) with a mean BER of approximately 0.0735. The test results were obtained by testing different memory blocks of V2 NAND written using the 6BPC scheme. In Figure 11 An example of the effect of performing noise cancellation on a specific level of a memory block is shown.

[0137] Figure 11 An example of denoising two consecutive levels out of 64 levels in a word line (in the 6BPC scheme) according to an exemplary embodiment is shown. Figure 11 The original (best) level distribution represented by line A, the noisy distribution represented by line B, and the predicted (denoised) distribution represented by line C are shown. Figure 11 The mean and standard deviation of word lines WL1 and WL2 are also shown. It can be assumed that the behavior of other levels is similar to Figure 11 the two levels shown. In Figure 11 it, the solid line and the dashed line each represent a level (e.g., level 21 and level 22 of word line 8, respectively). These distributions are the distributions of memory cell voltages per level, and the vertical lines are the means. As Figure 11 shown, in the test scenario, performing noise cancellation according to an exemplary embodiment corrects the electrical average values back to their original voltage levels, and significantly reduces the deviation of the memory cell distribution per level even though noise may remain in the memory cells of the lowest level, which is the level most affected by interference.

[0138] Figure 12 FIG. 1200 is a block diagram of a computing system including a non-volatile memory system according to an exemplary embodiment of the inventive concept.

[0139] Figure 12 The non-volatile memory system in Figure 1 can be the memory system 200 shown in

[0140] In the computing system 1200, which can be, for example, a mobile device or a desktop computer, the non-volatile memory system can be installed as the non-volatile memory system 1201, however, the exemplary embodiment is not limited thereto. Figure 1 the host 100 shown in Figure 1The memory device driver 111 shown. These components are electrically connected to the bus 1206. The non-volatile memory system 1201 may be connected to the device driver 1205. The host 1202 may control the entire computing system 1200 and perform operations corresponding to user commands input through the user interface 1204. The RAM 1203 may serve as a data memory for the host 1202. The host 1202 may write user data to or read user data from the non-volatile memory system 1201 through the device driver 1205. In Figure 12 , the device driver 1205 that controls the operation and management of the non-volatile memory system 1201 is shown as being provided outside the host 1202, however, the exemplary embodiments are not limited thereto. For example, in an exemplary embodiment, the device driver 1205 may be provided inside the host 1202.

[0141] In an exemplary embodiment of the inventive concept, a three-dimensional (3D) memory array is provided. The 3D memory array monolithically forms one or more physical levels of an array of memory cells, the memory cells having an active region disposed above a silicon substrate and circuitry associated with the operation of these memory cells, whether such associated circuitry is above or within such substrate. The term "monolithic" means that the layers of each level of the array are directly deposited on the layers of each underlying level of the array.

[0142] In an exemplary embodiment of the inventive concept, the 3D memory array includes vertically oriented vertical NAND strings such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trapping layer. The following patent documents, incorporated herein by reference, describe suitable configurations of three-dimensional memory arrays in which the three-dimensional memory arrays are configured in multiple levels sharing word lines and / or bit lines: U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235, and U.S. Patent Publication No. 2011 / 0233648.

[0143] As is conventional in the field of the inventive concept, the exemplary embodiments are described and illustrated in the drawings in terms of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc.) that may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units, and / or modules are implemented by a microprocessor or the like, they are programmed with software (microcode) to perform such functions described herein, and optionally driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware performing certain functions and a processor (e.g., one or more programmed microprocessors and associated circuits) performing other functions. Further, without departing from the scope of the inventive concept, each block, unit, and / or module of the exemplary embodiments may be physically divided into two or more interacting and discrete blocks, units, and / or modules. Additionally, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the exemplary embodiments may be physically combined into more complex blocks, units, and / or modules.

[0144] Exemplary embodiments of the present invention may be embodied directly in hardware, in a software module run by a processor, or in a combination of the two. The software module may be tangibly embodied on a non-transitory program storage device, such as in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, or any other form of storage medium known in the art. The exemplary storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium may be integrated into the processor. Additionally, in some aspects, the processor and the storage medium may be present in an application specific integrated circuit (ASIC).

[0145] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes may be made in form and detail without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A memory system, comprising: a memory device; and a memory controller including a processor and an internal memory, wherein the memory device operates under the control of the memory controller, and a computer program including a neural network is stored in the internal memory of the memory controller or in the memory device; wherein the processor is configured to run the computer program to perform the following operations: (a) Extract a voltage level from each of a plurality of memory cells connected to a string select line SSL, wherein the memory cells and the SSL are included in a memory block of the memory device; (b) Provide the voltage level of the memory cells as an input to the neural network; and (c) Use the neural network to perform noise cancellation on the SSL by changing the voltage level of an error memory cell of the memory cells misclassified into a first group among the memory cells from a first voltage level corresponding to the first group to a second voltage level corresponding to memory cells of a second group different from the first group.

2. The memory system according to claim 1, wherein the processor is further configured to run the computer program to: perform a validity check during a training mode of the neural network, wherein performing the validity check includes: comparing a bit error rate BER of each of the memory cells before performing noise cancellation on the SSL with the BER of each of the memory cells after performing noise cancellation on the SSL.

3. The memory system according to claim 2, wherein the processor is further configured to run the computer program to: perform a level skip operation during an inference mode of the neural network, wherein performing the level skip operation includes: identifying at least one memory cell whose BER is not improved after performing noise cancellation on the SSL based on the validity check; and restoring the corresponding voltage level of the identified at least one memory cell to the value that the identified at least one memory cell had before performing noise cancellation on the SSL.

4. The memory system according to claim 1, wherein the processor is further configured to run the computer program to: perform data normalization on the voltage levels of the memory cells before performing noise cancellation on the SSL; and perform data denormalization on the voltage levels of the memory cells after performing noise cancellation on the SSL.

5. The memory system according to claim 1, wherein the processor is further configured to run the computer program to: perform voltage average value correction on the voltage levels of the memory cells before performing noise cancellation on the SSL.

6. The memory system according to claim 1, wherein the number of the extracted voltage levels corresponds to the number of word lines connected to the SSL.

7. The memory system according to claim 1, wherein During a read operation of the memory device, when the memory block is being read, the processor runs the computer program to perform operations (a) to (c).

8. The memory system according to claim 1, wherein, each memory cell stores 6 bits, each memory cell has one of 64 possible states corresponding to 64 predefined voltage levels, and the SSL included in the memory block is one of four SSLs included in the memory block.

9. The memory system according to claim 8, wherein, the processor runs the computer program to independently perform operations (a) to (c) on each of the four SSLs included in the memory block.

10. The memory system according to claim 8, wherein, the first group and the second group are included among 64 groups corresponding to the 64 predefined voltage levels.

11. The memory system according to claim 1, wherein, the neural network is stored on and runs on the memory device.

12. The memory system according to claim 1, wherein, the neural network is a Residual Neural Network (ResNet).

13. The memory system according to claim 1, wherein, the neural network includes: an input layer having a size corresponding to the number of extracted voltage levels; and an output layer having a size corresponding to the number of extracted voltage levels, wherein each layer in the neural network is a fully connected layer.

14. A method for performing noise cancellation on a memory device using a neural network, comprising: (a) extracting a voltage level from each of a plurality of memory cells connected to a string selection line (SSL), wherein the memory cells and the SSL are included in a memory block of the memory device; (b) providing the voltage levels of the memory cells as inputs to the neural network; and (c) using the neural network to perform noise cancellation on the SSL by changing the voltage levels of the error memory cells of the memory cells misclassified into a first group among the memory cells from a first voltage level corresponding to the first group to a second voltage level corresponding to memory cells of a second group different from the first group.

15. The method according to claim 14, further comprising: performing a validity check during a training mode of the neural network, wherein performing the validity check includes: comparing the bit error rate (BER) of each of the memory cells before performing noise cancellation on the SSL with the BER of each of the memory cells after performing noise cancellation on the SSL.

16. The method according to claim 15, further comprising: performing a level skipping operation during an inference mode of the neural network, wherein performing the level skipping operation includes: Based on the validity check, identify at least one memory cell for which the BER is not improved after performing noise cancellation on the SSL; and Restore the corresponding voltage level of the identified at least one memory cell to the value that the identified at least one memory cell had before performing noise cancellation on the SSL.

17. The method according to claim 14, further comprising: Performing data normalization on the voltage level of the memory cell before performing noise cancellation on the SSL; and Performing data denormalization on the voltage level of the memory cell after performing noise cancellation on the SSL.

18. The method according to claim 14, further comprising: Performing voltage level average value correction on the voltage level of the memory cell before performing noise cancellation on the SSL.

19. The method according to claim 14, wherein the number of the extracted voltage levels corresponds to the number of word lines connected to the SSL.

20. The method according to claim 14, wherein during a read operation of the memory device, when the memory block is being read, operations (a) to (c) are performed.

Images