Antenna package, antenna package system and method for manufacturing antenna package

Abstract

An antenna package, an antenna package system, and a method for manufacturing an antenna package. The method for manufacturing an antenna package includes: depositing an insulating layer including polybenzobisoxazole on a carrier; forming a backside layer including polyimide on an adhesive layer; forming a die attach film on the backside layer; forming one or more interposer through-hole wall structures and one or more interposer through-hole grating structures on a second backside layer; placing a die such as a radio frequency integrated circuit die on the die attach film; encapsulating the die, one or more interposer through-hole wall structures, and one or more interposer through-hole grating structures by a molding compound to form an antenna package including one or more antenna regions; and forming a redistribution layer structure on the encapsulated package body. The redistribution layer structure may include one or more antenna structures coupled to the die. Each of the one or more antenna structures may be positioned above the one or more antenna regions.

Description

Technical Field

[0001] The present disclosure relates to an antenna package, an antenna package system and a method for manufacturing the antenna package. Background Art

[0002] Microwaves and millimeter (mm) waves occupy the spectrum from 1 GHz to 30 GHz and from 30 GHz to 300 GHz, respectively. Printed circuit boards (PCBs) and complementary metal oxide semiconductor (CMOS) substrates can be used to integrate millimeter wave antennas with radio frequency (RF) integrated circuits (ICs). CMOS RF chips may include vertical embedded folded monopole antennas integrated into low-temperature co-fired ceramic (LTCC) substrate carriers. However, the implementation of low-temperature co-fired ceramics may require too large an area, and the number of components (e.g., inductors, capacitors, and baluns) included therein may result in undesirable interference effects of electromagnetic and substrate coupling. Summary of the invention

[0003] According to some embodiments of the present disclosure, a method for manufacturing an antenna package includes the following operations. First, a dielectric layer is deposited on a carrier substrate. Then, a die attachment film is formed on the dielectric layer. Then, one or more interposer through-hole wall structures and one or more interposer through-hole grating structures are formed on the dielectric layer. Then, a die is placed on the die attachment film. Then, the die, one or more interposer through-hole wall structures and one or more interposer through-hole grating structures are encapsulated to form an encapsulated package, which includes one or more antenna regions. Then, an interconnect structure is formed on the encapsulated package, wherein the interconnect structure includes one or more metal wires coupled to the die and the one or more interposer through-hole wall structures.

[0004] According to some embodiments of the present disclosure, an antenna package includes a dielectric layer, a plurality of antenna region structures, a die, a molding compound, and an interconnection layer. Each of the antenna region structures includes: one or more interposer through-hole walls in contact with the dielectric layer, and one or more interposer through-hole gratings in contact with the dielectric layer. The die is attached to the dielectric layer and adjacent to the antenna region structure. The molding compound is disposed between the die and each of the antenna region structures. The interconnection layer is disposed on the die and the antenna region structure.

[0005] According to some embodiments of the present disclosure, an antenna packaging system includes a backside layer, one or more dies, multiple antenna region structures, a molding compound, and a metal layer. Each antenna region structure includes: an interposer through hole wall for electrically coupling one or more dies, and an interposer through hole grating for electrically coupling to one or more ground planes. The molding compound surrounds the one or more dies and the antenna region structure. The metal layer is located on the molding compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or decreased for clarity of illustration and discussion.

[0007] Figure 1A to Figure 1B is a diagram of an insulating substrate antenna incorporating an electrical connector according to some embodiments;

[0008] Figure 2 is a flow chart of a method for forming an insulating substrate antenna according to some embodiments;

[0009] Figures 3 to 15 is an illustration of structures associated with a method for forming an insulating substrate antenna according to some embodiments;

[0010] Fig.16 FIG. 1 is a diagram illustrating the effectiveness characteristics of an antenna on a dielectric substrate according to some embodiments.

[0011] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one skilled in the art to make and use the present disclosure.

[0012]

Explanation of symbols

[0013] 100: Encapsulation

[0014] 105: RF transmission

[0015] 120: first back side layer

[0016] 130: Second back side layer

[0017] 142a: first through hole wall

[0018] 142b: Second through hole wall

[0019] 142c: third through hole wall

[0020] 142d: Fourth through hole wall

[0021] 143: Conductor

[0022] 144a: first interposer through-hole grating

[0023] 144b: Second interposer through-hole grating

[0024] 144c:Third Intermediary Layer Through-hole Grating

[0025] 144d: Fourth intermediary layer through-hole grating

[0026] 150: Die Attach Film

[0027] 152: RF Chip

[0028] 157a: first pad terminal

[0029] 157b: Second pad terminal

[0030] 157c: Third pad terminal

[0031] 160: Sealing layer

[0032] 170: Interconnection structure

[0033] 171: The first top side layer

[0034] 171a: First level conductor (RDL-1)

[0035] 171b: First level via (RDL-1 via)

[0036] 171c: Dielectric layer

[0037] 172: Second top side heavy cloth layer

[0038] 172a: Redistribution layer wiring

[0039] 172b: Second level via (RDL-2 via)

[0040] 172c: Dielectric layer

[0041] 173: The third top layer

[0042] 173a: Third level conductor (RDL-3)

[0043] 173c: Dielectric layer

[0044] 174,175,176: Under Bump Metal Layer

[0045] 180:Solder bump

[0046] 200: Method

[0047] 205,210,215,220,225,230: Operation

[0048] 235,240,245,250: Operation

[0049] 300: Carrier substrate

[0050] 310: light-to-heat conversion layer

[0051] 320: Protective layer

[0052] 330: back layer

[0053] 600: Photoresist layer

[0054] 610,620: Interposer through hole opening

[0055] 610a, 610b: interposer through-hole wall

[0056] 620a, 620b: Intermediate layer through hole grating

[0057] 630: Antenna area

[0058] 700:Titanium and copper seed layer stack

[0059] 800: Copper layer

[0060] 1000: Grain

[0061] 1010: Die attach film

[0062] 1100: Molding compound

[0063] 1300: polymer layer

[0064] 1320:Metal wiring

[0065] 1400: Second layer of cloth

[0066] 1500: Top polymer layer

[0067] 1510: Under bump metal layer contact

[0068] 1520,1530,1540: Solder bumps DETAILED DESCRIPTION

[0069] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the various embodiments of the disclosure. Of course, these are only examples and are not intended to be limiting. In addition, the various embodiments of the disclosure may repeat element symbols and / or letters in various examples. This repetition itself does not represent the relationship between the various embodiments and / or configurations discussed.

[0070] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "an exemplary embodiment," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include this particular feature, structure, or characteristic. Moreover, these phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it will be within the knowledge of those skilled in the art to implement this feature, structure, or characteristic in conjunction with other embodiments.

[0071] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of this specification will be interpreted by persons familiar with the relevant art(s) based on the teachings herein.

[0072] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given quantity varies within 5% of a target value (eg, ±1%, ±2%, ±3%, ±4%, and ±5% of such a target value).

[0073] Overview

[0074] The components and methods described herein are directed to an insulated substrate antenna, which includes one or more radiators and one or more ground planes disposed through an interposer via (TIV). The interposer via forms one or more antenna regions. Compared with other CMOS RF chips, the embodiments described herein achieve better performance, smaller area and higher integration.

[0075] Embodiments of the present disclosure relate to designs for antenna packages that include an RF die and a dielectric substrate having one or more antenna regions. The antenna package includes low-cost, high-efficiency vertical interposer via walls (TIV-walls) and through-interposer via gratings (TIV-gratings) to form antenna regions in an encapsulated package. The vertical interposer via antenna regions enable, for example, lateral transmission and reception of RF signals.

[0076] Antenna packages (also referred to herein as "packages") including the above-described antenna regions are advantageous and suitable for applications operating at high frequencies, such as 5G applications (e.g., greater than 5.8 GHz) and automotive radars (e.g., about 77 GHz to about 120 GHz). Such high frequency applications may be targeted at, for example, radio frequency transceivers and portable, wearable Internet of Things (IoT) and smartphone products.

[0077] In some embodiments, the antenna package includes a molding compound (MC) layer (also referred to herein as a dielectric layer or an insulating layer) above the RF die, wherein the molding compound layer includes polyimide (PI) and has a low relative dielectric constant (k), for example, about 2.8 or between about 2.8 and about 3.0. The molding compound layer can reduce coupling effects caused by RF die components (such as inductors, capacitors, and baluns).

[0078] In some embodiments, the insulator substrate can be formed of various materials, such as polyimide (PI), polybenzobisoxazole (PBO), molding compounds, polymers, silicon dioxide (SiO2), silicon-on-glass (SOG), glass, ceramics, sapphire (Al2O3) and other similar materials. In some embodiments, the insulator substrate can be manufactured to have a flexible thickness between about 200 μm and 2 mm. In addition, integrating the antenna package into a smaller three-dimensional integrated circuit (3D IC) package makes the component suitable for high-frequency 5G and automotive radar applications (e.g., 5.8 GHz, 28 GHz, and 77 GHz to 120 GHz applications).

[0079] Insulating substrate with antenna area

[0080] Figure 1A to Figure 1B Package 100 is shown (also referred to herein as an "insulated substrate antenna", "encapsulated package" or "antenna package"). Package 100 may include one or more IC dies (e.g., RF IC dies) and one or more antenna regions. An integrated fan-out (InFO) package may be integrated with package 100, which includes one or more antenna regions coupled to one or more IC dies. For example, the one or more antenna regions may be integrated with the IC die via an integrated fan-out redistribution structure, which includes a metallization layer (e.g., a redistribution layer or "RDL" structure) that is coupled to the package molding compound through the IC die embedded therein. Some of the embodiments described below are in the context of an InFO package. Based on the description herein, embodiments of the present disclosure are applicable to other types of packages; these other types of packages are within the spirit and scope of multiple embodiments of the present disclosure.

[0081] Figure 1AAn exemplary top plan view of package 100 is shown. Package 100 includes die 152, which may be a radio frequency IC die, coupled to first via wall 142a, second via wall 142b, third via wall 142c, and fourth via wall 142d via redistribution layer (RDL) wiring 172a. According to some embodiments, first interposer via wall 142a to fourth interposer via wall 142d may be coupled to die 152 to act as a radio frequency transmitter.

[0082] Package 100 includes first to fourth interposer via gratings 144a to 144d. As shown here, in some embodiments, first to fourth interposer via gratings 144a to 144d may be laterally (eg, at Figure 1A The first to fourth interlayer via gratings 144a to 144d are arranged outside the first to fourth interlayer via walls 142a to 142d (in the x-direction or in the y-direction). According to some embodiments, the first to fourth interlayer via gratings 144a to 144d may be coupled to one or more ground terminals to act as RF ground planes. Each RF ground plane acts as an electrical conductor to reflect and guide radiation emitted from the first to fourth interlayer via walls 142a to 142d. Therefore, RF transmission 105 may be guided by the RF ground plane provided by the first to fourth interlayer via gratings 144a to 144d. Although RF transmission is discussed herein, other types of signal transmissions are within the spirit and scope of the embodiments of the present disclosure.

[0083] Figure 1B The package 100 is shown in cross-section. Figure 1B As shown in FIG. 1 , package 100 includes a first backside layer 120, a second backside layer 130, a first through-hole wall 142a, a third through-hole wall 142c, a first through-hole grating 144a, a third through-hole grating 144c, a die attach film 150, an RF die 152, a first RF die connector to a third RF die connector, a first pad to a third pad, a first pad terminal 157a to a third pad terminal 157c, and an encapsulation layer 160. Interposer through-hole walls 142a and 142c include conductors 143, respectively. Interposer through-hole gratings 144a and 144c include conductors 143, respectively. Interposer through-hole walls 142b and 142d and interposer through-hole gratings 144b and 144c ( Figure 1B (not shown in the cross-sectional view) also includes a conductor 143.

[0084] The interconnect structure 170 (also referred to as an RDL structure or a topside RDL) is disposed on the encapsulation layer 160. The interconnect structure 170 includes a dielectric layer 171c and a first level conductor 171a. The interconnect structure 170 further includes a dielectric layer 173c formed on the dielectric layer 171c and a third level conductor 173a.

[0085] refer to Figure 1B , providing a backside layer 120. The backside layer 120 is a dielectric layer, which may include a polymer. The backside layer 120 may serve as a final protective insulator for the package 100. This polymer may be, for example, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), ajinomoto buildup film (ABF), solder resist film (SR), or other suitable materials. The backside layer 120 is a flat layer with a uniform thickness, wherein the thickness may be greater than about 2 μm (e.g., between about 2 μm and about 40 μm). The top and bottom surfaces of the backside layer 120 are also flat.

[0086] refer to Figure 1B , a backside layer 130 is disposed on the backside layer 120. The backside layer 130 is a dielectric layer, which may include a polymer. The backside layer 130 may serve as a final protective insulator for the package 100. This polymer may be, for example, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), ajinomoto deposited film (ABF), solder resist (SR), or other suitable materials. The backside layer 130 is a flat layer with a uniform thickness, wherein the thickness may be greater than about 2 μm (e.g., between about 2 μm and about 40 μm). The top and bottom surfaces of the backside layer 130 are also flat.

[0087] The interposer via walls 142a and 142d are disposed on the backside layer 130 to form a first interposer via opening and a second interposer via opening that are spaced apart. The interposer via walls 142a to 142d can be electrically coupled to a die (such as an RF die described below) to perform transceiver communications via RF signals. The interposer via walls 142a to 142d can be formed by first disposing a photoresist layer on the backside layer 130 and etching the photoresist layer to form spaced apart interposer via openings. A titanium and copper seed layer structure can be deposited on the photoresist layer, and a copper layer can be electroplated on the titanium and copper seed layer. The photoresist layer can then be removed, leaving the interposer via walls 142a to 142d. Although in Figure 1A The diagram shows four walls (both in Figure 1B 144a to 144d, but the number of interposer via walls is not limited to any particular number. Interposer via gratings 144a to 144d may be formed in a similar manner to interposer via walls 142a to 142d. Interposer via gratings are connected to one or more ground planes. Thus, antenna area structures are formed by each spacing provided between interposer via walls 142a to 142d and interposer via gratings 144a and 144d.

[0088] Each antenna region may be filled with any of a plurality of insulator materials that are compatible with a packaging process (e.g., an InFO packaging process), without being limited by the dielectric constant of the insulator. In some embodiments described below, the insulator may have a low relative dielectric constant (i.e., k; e.g., about 2.8, or about 2.8 to about 3.0). In other embodiments, the insulator may have a relative dielectric constant specified by the manufacture of the InFO package. Thus, the antenna package of each embodiment of the present disclosure may be robustly implemented in a packaging (e.g., InFO packaging) process using high dielectric constant or low dielectric constant materials.

[0089] A die 152 (e.g., an RF die such as an RF IC die) is placed on the backside layer 130. The die 152 may be adhered to the backside layer 130 using a die-attach-film (DAF) 150. In a non-limiting example, the die 152 may include a semiconductor substrate (e.g., a silicon substrate) having a back surface in contact with the die-attach film 150. A portion of the die 152 (e.g., a top portion) may include conductive pillars (e.g., formed of copper, other metals, or alloys including one or more metals) that electrically connect the die 152 to other conductive elements and interconnect structures.

[0090] Package 100 includes fan-out wiring between input / output (I / O) pins on a die and package I / O pins, which may be formed in an interconnect layer (e.g., a redistribution layer (RDL)) above the die. The die is laterally surrounded by a medium (e.g., a molding compound, an encapsulant, an epoxy, or the like). The interconnect layer may extend laterally beyond the perimeter of the die. The interconnect layer includes a patternable dielectric material in which conductive patterns and conductive vias may be formed. Compared to other fan-out structures for die packaging technology, packages such as InFO packages may provide significantly thinner packages, along with tighter redistribution wiring pitches (e.g., 10 μm). InFO packages may provide advantages over other packages (e.g., flip chip ball grid array (FC-BGA) packages) because passive components (e.g., inductors and capacitors) may be formed above the perimeter of the IC die (e.g., above the molding compound) to reduce substrate losses and improve electrical performance. InFO packaging can result in a compact die size, which can result in improved thermal performance and lower operating temperature at the same power budget. In some embodiments, faster circuit operation can be achieved for the same temperature profile as FC-BGA packaging through improved thermal performance.

[0091] like Figure 1BAs shown in , the redistribution layer (RDL) structure 170 includes three interconnect (also referred to herein as top-side redistribution (RDL)) layers 171, 172, and 173. In other embodiments, a different number of redistribution layers may be included. Each interconnection layer includes a redistribution layer and a via that are metal conductor features, and these metal conductor features provide electrical interconnections through the redistribution layer structure 170 and within the redistribution layer structure 170. In some embodiments, the redistribution layer wiring and the via may include copper. In the first interconnection layer 171, the first level conductor (RDL-1) 171a and the first level via (RDL-1 via) 171b provide interconnections. In the first top-side redistribution layer interconnection layer 171, a dielectric layer 171c is disposed above the first level conductor 171a. In the second top-side redistribution layer 172, the redistribution layer wiring 172a and the second level via (RDL-2 via) 172b provide interconnections. In the second top side redistribution layer 172, a dielectric layer 172c is disposed on the redistribution layer wiring 172a. In the third top side redistribution layer 173, a third level conductor (RDL-3) 173a and under ball metal (UBM) 174, 175 and 176 provide interconnection. Solder bumps 180 are formed on under ball metal layers 174 to 176. In the third top side redistribution layer 173, a dielectric layer 173c is disposed on the third level conductor 173a. A ground plane may be electrically connected to one or more solder bumps 180.

[0092] A die attach film (DAF) 150 may be used to adhere the die 152 to the backside layer 130. The die 152 may include a semiconductor substrate (e.g., a silicon substrate) whose back surface is in contact with the die attach film 150. The die 152 includes pad terminals 157a-157c (e.g., copper pillars) formed as top portions of the die 152, which electrically connect the die 152 to other conductive elements and interconnect structures.

[0093] Manufacturing process of insulating substrate with antenna area

[0094] Reference Figures 3 to 15 Method 200 is described. Figures 3 to 15 are for illustration purposes only and are not drawn to scale. Figures 3 to 15 The actual geometry of the actual structure, features or layers may not be reflected. For the purpose of illustration and clarity, some structures, layers or geometries may have been intentionally added or omitted.

[0095] refer to Figure 2 The exemplary manufacturing method 200 begins with operation 205, where a carrier substrate 300 (such as a glass carrier substrate) having a light to heat conversion layer (LTHC) 310 disposed thereon is provided. Figure 3 . In some embodiments, the carrier substrate 300 provides mechanical support for structural elements that are attached or manufactured in subsequent operations of the method 200. The light-to-heat conversion layer 310 is an adhesive layer that can be cured by ultraviolet (UV) light to form a temporary bond between the polymer layer and the carrier substrate 300. Once the package (e.g., InFO package) is completed, this temporary bond can be broken to release the polymer layer from the carrier substrate 300. By way of example and not limitation, irradiating the light-to-heat conversion layer 310 through the back side of the carrier substrate 300 with a focused laser beam can generate sufficient heat to decompose the light-to-heat conversion layer 310 and release the carrier substrate 300 from the polymer layer. For successful release, the carrier substrate 300 is required to be transparent so that the light source (e.g., laser) that can irradiate and decompose the light-to-heat conversion layer 310 can pass through.

[0096] See also Figure 2 The method 200 continues with operation 210, where a protective layer 320 is formed on the light-to-heat conversion layer 310, such as Figure 4 . By way of example and not limitation, the protective layer 320 may include polyimide (PI), polybenzoxazole (PBO), or another suitable polymer material. In some embodiments, the protective layer 320 (also referred to herein as "polymer layer 320") is a stress relief coating used as a protective layer or "buffer coating" before forming the RF region structure. In some embodiments, the protective layer 320 may be deposited and hardened by a spin coating process followed by a curing process.

[0097] refer to Figure 2 The method 200 continues with operation 215 and the process of forming a backside layer, such as Figure 5 . By way of example and not limitation, the backside layer 330 may include polyimide (PI), polybenzoxazole (PBO), or another suitable polymer material. In some embodiments, the backside layer 330 (also referred to herein as "polymer layer 330") is a radiation suppression layer that allows the backside radiation to be restored to the RF region structure and constructively superimposed to form a laterally directed beam. In some embodiments, the backside layer 330 may be deposited and hardened by a spin coating process followed by a curing process.

[0098] refer to Figure 2 , method 200 continues with operation 220 and a process of forming through interposer vias (TIVs) on backside layer 330. In some embodiments, one or more of the interposer vias may be used to define the surface area of ​​a corresponding interposer via wall, while one or more of the interposer vias may be used to define the surface area of ​​a corresponding interposer via grating. By way of example and not limitation, the interposer vias in operation 220 may be formed using photolithography and etching operations. For example, referring to Figure 6At operation 220, a photoresist layer 600 having a thickness of about 180 μm to about 250 μm may be spin coated over the backside layer 330. The photoresist layer 600 may then be patterned to form interposer via openings 610 and 620, such as Figure 6 as shown in .

[0099] In some embodiments, the interposer via opening 610 is used to define the surface area of ​​the interposer via wall, and the interposer via opening 620 is used to form an interposer via grating. The interposer via opening 610 can be designed to have different dimensions than the interposer via opening 620. For example, the interposer via opening 610 can have a width of 10 μm and a length of 50,000 μm to form a strip-type sheet structure, and the interposer via opening can have a width of 10 μm and a length of 10 μm to form a grating sheet structure. In some embodiments, the interposer via opening 610 can have a width of 20 μm and a length of 90,000 μm, which are different from the corresponding width and length of the interposer via opening 620, such as Figure 6 In other embodiments, the interposer via opening 610 may have the same width of 100 μm and length of 100 μm as the interposer via opening 620 .

[0100] refer to Figure 2 and Figure 7 , the method 200 continues with operation 225 where a titanium and copper seed layer stack 700 is deposited on the patterned photoresist layer 600 (e.g., by a PVD process) to cover the sidewalls and bottom surfaces of the openings 610 and 620. In some embodiments, the seed layer stack 700 is deposited on the photoresist layer 600, such as Figure 7 In some embodiments, the titanium layer may be approximately thick, and the copper seed layer can be about thick.

[0101] refer to Figure 2 and Figure 8 , method 200 continues with operation 230 where a copper layer 800 is electroplated on the titanium and copper seed layer stack 700 to fill the openings 610 and 620 and form corresponding interposer via walls 610a and 610b and interposer via gratings 620a and 620b. In some embodiments, the copper layer 800 so deposited may be grown over the photoresist layer 600 on the seed layer stack 700. The copper layer 800 may then be planarized and polished by a chemical mechanical planarization (CMP) process to remove portions of the copper layer 800 that are above the top surface of the photoresist layer 600. In some embodiments and during the copper CMP process, the seed layer stack 700 is also removed from the top surface of the photoresist layer 600, such as Figure 8At this stage of the manufacturing process, the thickness of the photoresist layer 600, which in some embodiments may range from about 100 μm to about 1000 μm, defines the height of the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b.

[0102] refer to Figure 2 In the method 200, at operation 235, after forming the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b, the photoresist layer 600 may be removed by a wet etching process, such as Fig. 9 According to some embodiments, the Figure 6 Compared to the interposer via gratings 620a and 620b described in the openings 610 and 620 shown in FIG. 1 , the interposer via walls 610a and 610b have different widths. For example, the interposer via walls 610a and 610b may have a width between about 10 μm and about 1000 μm, while the interposer via gratings 620a and 620b may have a width between about 10 μm and 100 μm. The interposer via walls 610a and 610b and the interposer via gratings 620a and 620b provide an antenna region structure between the backside layer 330 and the InFO package in the antenna package.

[0103] refer to Figure 2 The method 200 continues with operation 240 and a process of placing (eg, attaching) the die 1000 on the protective layer 320, such as Fig.10 . In some embodiments, die 1000 may have, for example, RF communication functionality, such as a radio frequency integrated circuit (RF IC) die. Die 1000 may have other or additional functionality. Die 1000 may have been prefabricated using a wafer fabrication process, and may include transistors and a plurality of interconnect layers to implement its functionality (e.g., RF communication). In some embodiments, a portion of die 1000 (e.g., a top portion) may include conductive pillars (e.g., formed of copper, other metals, or alloys including one or more metals) that electrically connect die 1000 to other conductive elements and interconnect structures.

[0104] In some embodiments, a die attach film (DAF) 1010 acts as a glue layer and is interposed between the die 1000 and the backside layer 330. By way of example and not limitation, the die attach film 1010 may have a thickness between about 10 μm and about 20 μm. In some embodiments, the die attach film 1010 is a dielectric material. By way of example and not limitation, the height of the die 1000 may be comparable to the height of the interposer via walls 610a and 610b, the interposer via gratings 620a and 620b. If the die 1000 is taller than the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b, it may be recessed to the same height as the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b. According to some embodiments, a plurality of dies may be attached to the polymer layer 330 during operation 240. To avoid parasitic capacitance between the interposer via and the die 1000, a minimum spacing S between about 20 μm and 30 μm may be appropriate. If a material with a sufficiently low relative dielectric constant (e.g., less than about 2.8) is available to isolate the interposer via and the die 1000, the spacing S may be adjusted to less than about 20 μm.

[0105] refer to Figure 2 and Fig.11 , method 200 continues with operation 245 and a process of disposing a molding compound (MC) 1100 on polymer layer 320 to surround die 1000, interposer via walls 610a and 610b, and interposer via gratings 620a and 620b. By way of example and not limitation, the molding compound 1100 may be spin-coated on polymer layer 320. According to some embodiments, the molding compound 1100 is an epoxy-based material that is solid at room temperature and liquid when heated at a temperature above, for example, 250° C. In some embodiments, the molding compound 1100 is melted before being spin-coated on backside layer 330. By way of example and not limitation, the spin-coated molding compound may have a thickness between about 230 μm and about 300 μm. This means that the molding compound 1100 so coated may have a cover layer of about 50 μm. For example, it may extend about 50 μm above the top surface of the die 1000 , the interposer via walls 610 a and 610 b , and the interposer via gratings 620 a and 620 b .

[0106] According to some embodiments, the die 1000 and the interposer via walls 610a and 610b and the interposer via gratings 620a and 620b may be embedded in a molding compound 1100 having a low relative dielectric constant (e.g., about 2.8) to form an antenna region. This example is not limiting, and the antenna region 630 may be provided and filled with any one of a plurality of insulator materials compatible with a packaging process (e.g., an InFO packaging process) without being limited by the dielectric constant of the insulator. The antenna region structure (e.g., the antenna region 630, which includes the interposer via walls 610a and 610b, the interposer via gratings 620a and 620b, and the molding compound 1100) provided according to some embodiments of the present disclosure may improve the reflection coefficient (S11 parameter) of the insulating substrate antenna structure in the InFO package, especially in high frequency applications employing antenna efficiency at frequencies of 5.8 GHz and above. The antenna region structure also helps to reduce improper coupling of the antenna to nearby circuits and prevent unwanted noise from the circuits from reaching the antenna. In some embodiments, the arrangement of interposer via gratings 620a and 620b extends laterally beyond the interposer via walls 610a and 610b, which achieves improved grounding and return loss.

[0107] After the molding compound 1100 is applied to the carrier substrate 300, the molding compound 1100 may be allowed to cool and harden. Once the molding compound 1100 is hardened, the molding compound 1100 may be partially ground to remove about 98% of the 50 μm cover layer, such as Fig.12 . The grinding process makes the top surface of the molding compound 1100 rough. According to some embodiments, a CMP process may then be used to planarize, polish, and remove the remaining portion of the molding compound 1100 (e.g., about 1 μm, which is about 2% of the remaining portion of the 50 μm cover layer) until the top surface of the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b are exposed. In some embodiments, the molding compound 1100 provides structural support and electrical isolation for the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b. Because the molding compound 1100 melts at temperatures above about 250°C, the thermal budget of any subsequent manufacturing operations should be limited to about 250°C. If a molding compound with a higher temperature tolerance is used, the thermal budget of subsequent manufacturing operations can be increased without other thermal budget constraints.

[0108] refer to Figure 2The method 200 continues to operation 250, where one or more redistribution layers are formed to provide electrical connections to the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b. During operation 250, electrical connections to other components and interposer vias may be formed. For example, electrical connections between the die 1000 and the interposer via walls 610a and 610b may also be completed during operation 250.

[0109] By way of example and not limitation, each additional redistribution layer may include a new polymer layer. Fig.13 , a polymer layer 1300 (which is similar to polymer layer 320) is disposed on molding compound 1100. In some embodiments, polymer layer 1300 is a low-k dielectric material having a dielectric constant value of about 2.8 and a thickness of about 4.5 μm. Polymer layer 1300 may then be patterned to form openings therein, and redistribution layer metal wiring will be formed in these openings. For example, in Fig.13 , a first redistribution layer may be formed on die 1000, interposer via walls 610a and 610b, and interposer via gratings 620a and 620b. Alignment of the first redistribution layer with die 1000, interposer via walls 610a and 610b, and interposer via gratings 620a and 620b may be achieved by one or more photolithography and etching operations. By way of example and not limitation, a photoresist layer may be spin coated over polymer layer 1300. The photoresist layer may be patterned so that openings may be formed in the photoresist layer that are aligned with die 1000, interposer via walls 610a and 610b, and interposer via gratings 620a and 620b. A subsequent etching process may remove portions of polymer layer 1300 not masked by the photoresist to form openings that are substantially aligned with die 1000, interposer via walls 610a and 610b, and interposer via gratings 620a and 620b. Once the openings in polymer layer 1300 have been formed, the photoresist layer may be removed, and a blanket metal stack may be deposited and patterned to form metal wiring 1320 of the first redistribution layer.

[0110] Metal wiring 1320 may include a metal stack of an electroplated copper top layer, a copper seed middle layer, and a titanium bottom layer. By way of example and not limitation, the titanium bottom layer and the copper seed middle layer may be deposited by a PVD process to a thickness of approximately 100 nm and 500 nm, respectively. The electroplated copper top layer may have a thickness of approximately 7 μm or more. In some embodiments, the metal stack may partially fill the opening in polymer layer 1300, such as Fig.15 as shown in .

[0111] The above operations may be repeated continuously to form a second redistribution layer 1400. Fig.14. The number of redistribution layer levels provided herein is illustrative and should not be considered limiting. Thus, fewer or additional redistribution layer levels may be formed depending on the InFO package design. By way of example and not limitation, four or more redistribution layers may be formed over the die 1000, the interposer via walls 610a and 610b, and the interposer via gratings 620a and 620b. Fig.15 , and once all redistribution layers have been formed, the top redistribution layer (e.g. Fig.14 A top polymer layer 1500 is disposed on the second redistribution layer 1400 in the substrate and then patterned. According to some embodiments, after the metal is deposited, a patterning operation is performed to form an under bump metallurgy (UBM) contact 1510. The under bump metal layer contact 1510 forms an interface between the redistribution layer 1400 and the solder bumps 1520, 1530 and 1540. In some embodiments, the under bump metal layer contact 1510 may include a metal stack of an electroplated copper top layer, a copper seed crystal intermediate layer and a titanium bottom layer. Alternatively, the under bump metal layer contact 1510 may include an alloy, such as titanium (Ti) and copper (Cu), titanium (Ti)-tungsten (W) and copper (Cu), aluminum (Al)-nickel (Ni)-vanadium (V) and copper (Cu), or chromium (Cr) and copper (Cu). The solder bumps 1520, 1530, and 1540 may be part of a ball grid array (BGA) and may be made of a metal alloy that may contain tin (Sn), silver (Ag), and copper (Cu), or a metal alloy that may contain lead (Pb) and tin (Sn).

[0112] In some embodiments, the carrier substrate 300 can be detached (released) from the polymer layer 320. For example, irradiating the light-to-heat conversion layer 310 with a focused laser beam through the back side of the glass carrier substrate 300 can generate enough heat to decompose the light-to-heat conversion layer 310 and release the carrier substrate 300 from the polymer layer 320. In some embodiments, the polymer layer 320 acts as a backside protective layer for the antenna package.

[0113] In some embodiments, solder bumps 1520 and 1540 (which may be electrically connected to interposer via gratings 620a and 620b) may be connected to an external ground connection. Solder bump 1530 (which may be electrically connected to die 1000) may be electrically coupled to an external IC that provides input and power signals to die 1000 via under bump metallization contacts 1510 and metal wiring 1320. In addition, Fig.15 The number of solder bumps shown in is not limiting. Therefore, additional solder bumps are within the spirit and scope of the present disclosure.

[0114] According to some embodiments, solder bumps such as solder bumps 1520, 1530, and 1540 may electrically connect the InFO package to one or more external power supplies or to a ground connection. The external power supply is, for example, a power supply that is not integrated into the InFO package. For example, the InFO package with die 1000 may be attached to a die or printed circuit board (PCB) having a solder bump receiver via solder bumps 1520, 1530, and 1540. Die 1000 may be used for internal or external components of the InFO package.

[0115] As described above, the antenna region structure according to some embodiments of the present disclosure can improve the reflection coefficient (S11 parameter) of the integrated block antenna in the InFO package, especially in high frequency applications using antenna efficiency at 5.8 GHz and higher frequencies. Fig.16 To have Fig.15 The S11 parameter (reflection coefficient) of the insulating substrate antenna structure with the antenna area 630 filled with an insulator is shown in FIG. The S11 value is given by Fig.15 A simulation of an embodiment of an insulating substrate antenna structure shown in is produced. As shown in the graph, the antenna effectively radiates frequencies of 5.8 GHz and above, including frequencies of 120 GHz and above. An antenna package with an antenna region according to an embodiment of the present disclosure has RF characteristics suitable for meeting the specifications of fourth generation (e.g., approximately 5.8 GHz) and fifth generation (e.g., approximately 38 GHz) high frequency RF transceivers in mobile communication applications. As described herein, the antenna package, system, and method of forming the same as described herein include a die and an antenna region structure. The antenna region structure may include one or more through interposer via (TIV) wall structures and one or more through interposer via grating structures on the backside layer. The die and antenna region structure are encapsulated by a molding compound. This antenna package obtains benefits in propagation signal transmission (including high frequency lateral RF transmission), along with improved grounding and return loss.

[0116] A method for manufacturing an antenna package includes depositing a dielectric layer on a carrier substrate; forming a die attach film on the dielectric layer; forming one or more interposer through-hole wall structures and one or more interposer through-hole grating structures on the dielectric layer; placing a die on the die attach film; encapsulating the die, one or more interposer through-hole wall structures and one or more interposer through-hole grating structures to form an encapsulated package, the encapsulated package including one or more antenna regions; and forming an interconnect structure on the encapsulated package, wherein the interconnect structure includes one or more metal wires coupled to the die and the one or more interposer through-hole wall structures.

[0117] In some embodiments, the method of manufacturing the antenna package further includes forming a second interconnect structure on the interconnect structure. In some embodiments, the method of manufacturing the antenna package further includes: forming a third interconnect structure on the second interconnect structure; attaching a plurality of solder bumps to the third interconnect structure; attaching a printed circuit board to the solder bumps; and removing the carrier substrate. In some embodiments, the step of forming the dielectric layer includes forming a protective layer comprising polybenzobisoxazole (PBO). In some embodiments, the step of forming one or more interposer through-hole wall structures and one or more interposer through-hole grating structures on the dielectric layer includes: forming a photoresist layer on the dielectric layer; etching the photoresist layer to form a first interposer through-hole opening and a second interposer through-hole opening spaced apart; depositing a titanium and copper seed layer structure on the photoresist layer; electroplating a copper layer on the titanium and copper seed layer; and removing the photoresist layer. In some embodiments, the dielectric layer includes polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), ajinomoto deposited film (ABF), solder resist (SR) or a combination thereof. In certain embodiments, forming the interconnect structure includes positioning an interconnect layer over at least one of the one or more antenna regions.

[0118] An antenna package includes a dielectric layer and an antenna area structure, wherein each of the antenna area structures includes: one or more interposer through-hole walls in contact with the dielectric layer; one or more interposer through-hole gratings in contact with the dielectric layer; a die attached to the dielectric layer and adjacent to the antenna area structure; a molding compound disposed between the die and each of the antenna area structures; and an interconnect layer disposed on the die and the antenna area structure.

[0119] In some embodiments, the antenna package further includes a second interconnect layer and a plurality of solder bumps, wherein the second interconnect layer is used to electrically connect the interconnect layer and the solder bumps are used to electrically connect the second interconnect layer. In some embodiments, each of the one or more interposer through-hole walls has a depth of about 120 μm to about 150 μm. In some embodiments, each of the antenna region structures has a thickness of about 200 μm to about 2 mm. In some embodiments, the molding compound has a relative dielectric constant of about 2.8 to about 3.0. In some embodiments, the dielectric layer includes polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), ajinomoto deposited film (ABF), solder mask (SR) or a combination thereof. In some embodiments, the antenna region structures include a first antenna region structure having a first interposer through-hole wall and a first interposer through-hole grating, and a second antenna region structure having a second interposer through-hole wall and a second interposer through-hole grating.

[0120] An antenna packaging system includes a back side layer, one or more dies, and an antenna area structure, wherein each antenna area structure includes: an intermediate layer through-hole wall for electrically coupling one or more dies; and an intermediate layer through-hole grating for electrically coupling to one or more ground planes; a molding material surrounding the one or more dies and the antenna area structure; and a metal layer on the molding material.

[0121] Summarize

[0122] In some embodiments, the molding compound has a relative dielectric constant of about 2.8 to about 3.0. In some embodiments, the interposer through hole wall has a depth of about 120 μm to about 150 μm. In some embodiments, the antenna packaging system further includes a protective layer, and the protective layer includes polybenzoxazole (PBO). In some embodiments, the backside layer includes polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), Ajinomoto built-up film (ABF), solder resist (SR) or a combination thereof.

[0123] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the various embodiments of the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the various embodiments of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the various embodiments of the present disclosure.

Claims

1. A method for manufacturing an antenna package, characterized in that: include: depositing a dielectric layer on a carrier substrate; forming a die attach film on the dielectric layer; forming one or more interposer via wall structures and one or more interposer via grating structures on the dielectric layer, wherein bottom surfaces of the one or more interposer via grating structures contact a top surface of the dielectric layer; placing a die on the die attach film; encapsulating the die, the one or more interposer via wall structures, and the one or more interposer via grating structures to form an encapsulated package, the encapsulated package including one or more antenna regions; and An interconnect structure is formed on the encapsulated package, wherein the interconnect structure includes one or more metal wires coupled to the die and the one or more interposer via wall structures.

2. The method according to claim 1, characterized in that Also included is forming a second interconnect structure on the interconnect structure.

3. The method according to claim 2, characterized in that Also includes: forming a third interconnect structure on the second interconnect structure; attaching a plurality of solder bumps to the third interconnect structure; attaching a printed circuit board to the plurality of solder bumps; as well as The carrier substrate is removed.

4. The method according to claim 1, characterized in that: The step of forming the dielectric layer includes forming a protective layer including polybenzobisoxazole.

5. The method according to claim 1, characterized in that The step of forming the one or more intermediate layer through hole wall structures and the one or more intermediate layer through hole grating structures on the dielectric layer includes: forming a photoresist layer on the dielectric layer; etching the photoresist layer to form a first interposer through hole opening and a second interposer through hole opening separated from each other; Depositing a titanium and copper seed layer structure on the photoresist layer; electroplating a copper layer on the titanium and copper seed layers; and The photoresist layer is removed.

6. The method according to claim 1, characterized in that The dielectric layer includes polyimide, polybenzoxazole, benzocyclobutene, ajinomoto deposited film, solder resist film or a combination thereof.

7. The method according to claim 1, characterized in that Wherein forming the interconnect structure includes positioning the interconnect structure over at least one of the one or more antenna regions.

8. An antenna package, characterized in that: include: a dielectric layer; A plurality of antenna area structures, wherein each of the plurality of antenna area structures comprises: one or more interposer via walls, the one or more interposer via walls contacting the dielectric layer; and one or more interposer via gratings, the bottom surfaces of the one or more interposer via gratings contacting the top surface of the dielectric layer; a die attached to the dielectric layer and adjacent to the plurality of antenna area structures; a molding compound disposed between the die and each of the plurality of antenna area structures; and An interconnect layer is disposed on the die and the plurality of antenna area structures.

9. The antenna package according to claim 8, characterized in that: The interconnection layer includes a plurality of contacts for electrically connecting the die.

10. The antenna package according to claim 8, characterized in that: Further including: a second interconnect layer, the second interconnect layer being used to electrically connect the interconnect layer; as well as A plurality of solder bumps are provided, and the plurality of solder bumps are used to electrically connect the second interconnect layer.

11. The antenna package according to claim 8, characterized in that: Each of the one or more interposer through-hole walls has a depth of 120 μm to 150 μm.

12. The antenna package according to claim 8, characterized in that: Each of the plurality of antenna region structures has a thickness of 200 μm to 2 mm.

13. The antenna package according to claim 8, characterized in that: The molding compound has a relative dielectric constant of 2.8 to 3.

0.

14. The antenna package according to claim 8, characterized in that: The dielectric layer includes polyimide, polybenzoxazole, benzocyclobutene, ajinomoto deposited film, solder resist film or a combination thereof.

15. The antenna package according to claim 8, characterized in that: The plurality of antenna region structures include a first antenna region structure having a first intermediate layer through hole wall and a first intermediate layer through hole grating, and a second antenna region structure having a second intermediate layer through hole wall and a second intermediate layer through hole grating.

16. An antenna packaging system, characterized in that: include: a dorsal layer; one or more grains; A plurality of antenna area structures, wherein each of the antenna area structures comprises: an interposer through hole wall, the interposer through hole wall is used to electrically couple the one or more dies; and an interposer via grating, the interposer via grating being electrically coupled to one or more ground planes, wherein a bottom surface of the one or more interposer via gratings contacts a top surface of the backside layer; a molding compound surrounding the one or more dies and the plurality of antenna area structures; and A metal layer is located on the molding compound.

17. The antenna packaging system according to claim 16, characterized in that: The molding compound has a relative dielectric constant of 2.8 to 3.

0.

18. The antenna packaging system according to claim 16, characterized in that: The through hole wall of the interposer has a depth of 120 μm to 150 μm.

19. The antenna packaging system according to claim 16, characterized in that: The invention further comprises a protective layer, wherein the protective layer comprises polybenzoxazole.

20. The antenna packaging system according to claim 16, characterized in that: The back side layer includes polyimide, polybenzoxazole, benzocyclobutene, ajinomoto deposited film, solder resist film or a combination thereof.

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