Semiconductor Structure and Method of Manufacturing the Same

Abstract

The semiconductor structure includes a first passivation layer disposed above a metal wire, a copper-containing RDL disposed above the first passivation layer, wherein the copper-containing RDL is electrically coupled to the metal wire, and a portion of the copper-containing RDL in contact with the upper surface of the first passivation layer forms an acute angle, and a second passivation layer disposed above the copper-containing RDL, wherein an interface between the top surface of the second passivation layer and the copper-containing RDL is curved. The semiconductor structure may further include a polymer layer disposed above the second passivation layer, wherein a portion of the polymer layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed above the bump. Embodiments of the present application also relate to a method of manufacturing a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of manufacturing the same. Background Art

[0002] Semiconductor integrated circuit (IC) technology has experienced rapid growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric dimensions (i.e., the smallest components that can be produced using the manufacturing process) have decreased.

[0003] For example, ICs are formed on a semiconductor substrate that can be diced into individual device dies or IC chips. Each IC chip can be further attached (such as by bonding) to an interposer, a reconstituted wafer, a circuit board, or another die to form a package or device. To meet various wiring requirements, a redistribution layer (RDL) of conductive metal lines can be formed on the IC chip to rewire connections from the edge of the chip to the center of the chip, or generally to disperse connections to an area larger than the IC chip. One or more passivation layers have been implemented around the RDL to protect the semiconductor surface from electrical shorts, stress, and chemical contaminants. However, some passivation layers are prone to generating stress and cracking during subsequent processes and may cause voids or cracks at the interface with adjacent metal contacts. Thus, while existing methods of manufacturing RDLs are generally sufficient for their intended purposes, they are not entirely satisfactory in every aspect. Summary of the Invention

[0004] Some embodiments of the present application provide a method of forming a semiconductor structure, including: providing an interconnect structure disposed above a semiconductor substrate, wherein the interconnect structure includes metal lines; forming a first dielectric layer above the metal lines; patterning the first dielectric layer to expose portions of the metal lines in first openings; forming a patterned layer above the first dielectric layer to fill the first openings; forming second openings in the patterned layer; forming a pedestal profile to laterally extend the second openings; forming a redistribution layer (RDL) in the second openings such that the redistribution layer is electrically coupled to the metal lines, wherein the redistribution layer includes a curved top surface; and forming a second dielectric layer above the redistribution layer.

[0005] Some other embodiments of the present application provide a semiconductor structure, including: an interconnect structure disposed above a semiconductor substrate, wherein the interconnect structure includes wires; a first dielectric layer disposed on the interconnect structure; a redistribution layer (RDL) disposed above the first dielectric layer, wherein the redistribution layer extends through the first dielectric layer to contact the wires, and wherein the redistribution layer includes a curved top surface and a pedestal profile disposed above the top surface of the first dielectric layer; a second dielectric layer disposed above the redistribution layer; a protective layer disposed above the second dielectric layer; and a conductive component disposed above the redistribution layer and electrically coupled to the redistribution layer.

[0006] Some other embodiments of the present application provide a semiconductor structure, including: a first passivation layer disposed above a metal wire; a copper-containing redistribution layer (RDL) disposed above the first passivation layer, wherein the copper-containing redistribution layer is electrically coupled to the metal wire, and wherein a portion of the copper-containing redistribution layer in contact with the upper surface of the first passivation layer forms an acute angle; a second passivation layer disposed above the copper-containing redistribution layer, wherein an interface between the second passivation layer and the top surface of the copper-containing redistribution layer is curved; a polymer layer disposed above the second passivation layer, wherein a portion of the polymer layer extends to contact the copper-containing redistribution layer; a bump electrically coupled to the copper-containing redistribution layer; and a solder layer disposed above the bump. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased. It should also be emphasized that the accompanying drawings only show typical embodiments of the present invention and should not be considered as limiting the scope of the present invention, as the present invention can be equally well applied to other embodiments.

[0008] Figure 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 6A 、 Figure 6B 、 Figure 6C 、 Figure 6D 、 Figure 7A 、 Figure 7B 、 Figure 8 、 Figure 9 、 Figure 10 、Figure 11 , Figure 12 , Figure 13 , Figure 14A and Figure 14B are cross-sectional views of workpieces at various stages of an embodiment of a method described in Figure 1 in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description of the present invention, the formation of a component on, connected to, and / or coupled to another component may include embodiments in which the components are formed in direct contact, and may include embodiments in which additional components may intervene between the components such that the components may not be in direct contact. In addition, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "beneath", "upward", "downward", "top", "bottom", and derivatives thereof (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to facilitate understanding of the relationship between one component of the present invention and another component. Spatial relative terms are intended to encompass different orientations of the device of the component.

[0011] In addition, when a numerical value or numerical range is described using "about", "approximately", etc., the term is intended to cover a numerical value within a reasonable range including the numerical value, such as within + / - 10% of the numerical value or other values understood by those skilled in the art. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm. Further, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] On many IC chips, a conductive (i.e., metal-containing) redistribution layer (RDL) that forms conductive metal lines is used to re-join connectors from the edge of the chip to the center of the chip, or generally to distributively join connectors to an area larger than the IC chip. One or more passivation layers that may include one or more dielectric materials may be formed around the RDL to protect the semiconductor surface from electrical shorts, mechanical stress, and / or chemical contaminants. In some cases, a polymer protective layer is formed over the one or more passivation layers. Due to the volume shrinkage of the polymer protective layer caused by curing and the mismatch in the coefficient of thermal expansion (CTE) between the polymer protective layer, the one or more passivation layers, and the RDL, stress can concentrate at the corners of the RDL in contact with the one or more passivation layers. Such concentrated stress can propagate through the one or more passivation layers, causing the one or more passivation layers to crack and / or delaminate from the RDL. At least for these reasons, it is desirable to improve the method of forming the RDL.

[0013] Aspects of the present invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 is a flowchart showing a method 10 for manufacturing a semiconductor device according to an embodiment of the present invention. Method 10 is merely an example and is not intended to limit the present invention to what is explicitly shown in method 10. Additional steps may be provided before, during, and after method 10, and for additional embodiments of the method, some of the described steps may be replaced, omitted, or changed. For simplicity, not all steps are described in detail here. The method 10 will be described below in conjunction with Figures 2 to 14B describes method 10, Figures 2 to 14B is a schematic partial cross-sectional view of a workpiece 200 at different stages of an embodiment of method 10 according to an embodiment of the present invention.

[0014] Refer to Figure 1 and Figure 2, Method 10 forms workpiece 200 at block 12. The workpiece 200 includes substrate 200A, an interconnect structure 200B located above substrate 200A, an etch stop layer (ESL) 210 located above interconnect structure 200B, and a first passivation layer 212. In some embodiments, substrate 200A may be made of silicon or other semiconductor materials such as germanium. In some other embodiments, substrate 200A may include compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In other embodiments, substrate 200A may include alloy semiconductors such as silicon germanium, silicon carbide germanium, gallium arsenide phosphide, or gallium indium phosphide. Additionally or alternatively, substrate 200A may include an epitaxial layer (not described) on top of a bulk semiconductor (not described). Although not described, various microelectronic components may be formed in or on substrate 200A, such as transistor components including source / drain components and / or gate structures, isolation structures including shallow trench isolation (STI), passive components, and / or any other suitable components.

[0015] The interconnect structure 200B formed above substrate 200A may be a multi-layer interconnect (MLI) structure and may include contact vias 208 and wires 209 embedded in multiple inter-metal dielectric (IMD) layers, which are collectively described as Figure 2 an example of IMD layer 206 in. In some instances, each of contact vias 208 and wires 209 is embedded in a separate IMD layer 206. In other instances, contact vias 208 and wires 209 may be formed together in an IMD layer. Wires at the same level may be collectively referred to as metal layers, and different metal layers are interconnected by one or more contact vias 208. The interconnect structure 200B is configured to provide interconnections (e.g., wires) between various microelectronic components that have been or will be formed on workpiece 200. An intermediate layer or component may be provided between interconnect structure 200B and substrate 200A, but these layers or components are not shown for simplicity. IMD layer 206 may include silicon oxide or a low-k dielectric material having a dielectric constant less than that of silicon dioxide, which is about 3.9. In some embodiments, the low-k dielectric material includes a porous organosilicate film such as SiOCH, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide (such as borophosphosilicate glass (BPSG)), fused silica glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or a combination thereof. IMD layer 206 may further include one or more ESLs disposed between contact vias 208 and wires 209 (i.e., between IMD layers 206).

[0016] Contact vias 208 and wires 209 are formed in the IMD layer 206. Each contact via 208 and wire 209 can be formed separately by a single damascene process and / or jointly by a dual damascene process. In the single damascene process, a trench for forming the wire 209 (or a via opening for forming the contact via 208) is first formed in one of the IMD layers 206, and then the trench (or via opening) is filled with a conductive layer. Then, a planarization process (such as a chemical mechanical polishing or planarization (CMP) process) is performed to remove an excessive portion of the conductive layer formed above the top surface of the IMD layer 206, thereby leaving the wire 209 (or contact via 208) in the trench (or via opening). In some embodiments, if the contact via 208 and the wire 209 disposed above it are formed separately using the single damascene process, conductive layers of different compositions may be deposited to form the components. In the dual damascene process, the trench and the via opening are formed together in the IMD layer, and the via opening is disposed below the trench and connected to the trench. Then, the conductive layer is deposited in the trench and the via opening in a single deposition process to form the wire 209 above the contact via 208. The conductive layer may include copper, tungsten, aluminum, cobalt, ruthenium, gold, other suitable metals, their corresponding alloys, or combinations thereof, and may be deposited by any suitable method, such as chemical vapor deposition (CVD), plating (e.g., electroplating, electroless plating, etc.), other suitable methods, or combinations thereof. In some embodiments, the conductive layer includes copper in the form of, for example, elemental copper, cupronickel, copper-aluminum alloy, other copper-containing alloys, or combinations thereof. In some embodiments, although not described, each of the contact via 208 and / or the wire 209 includes a conductive layer disposed above a barrier layer. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, cobalt nitride, tungsten nitride, ruthenium, ruthenium nitride, other suitable metals, other suitable metal nitrides, or combinations thereof. For embodiments in which the conductive layer includes copper (or any of its alloys), the contact via 208 and / or the wire 209 may further include a copper-containing seed layer on which the conductive layer is deposited.

[0017] The workpiece 200 further includes an ESL 210 and a first passivation layer 212 formed over the interconnect structure 200B. The ESL 210 may include silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxynitride (SiON), silicon carbide (SiC), silicon nitride (SiN), or a combination thereof, and may be formed over the interconnect structure 200B by a suitable method such as atomic layer deposition (ALD) and / or CVD. The first passivation layer 212 may be a single layer or a composite layer formed over the ESL 210 by any suitable method such as spin-on glass (SOG) and / or other suitable methods. The first passivation layer 212 may be formed of a non-porous material. In the present embodiment, the first passivation layer 212 is a single layer including undoped silicate glass (USG). The following description is directed to a method of forming an RDL over the ESL 210 and the first passivation layer 212 to electrically connect to the topmost wire 209 of the interconnect structure 200B. Thus, for simplicity, the intermediate stages of method 10 will be discussed with reference to this portion of the workpiece 200, as shown in subsequent Figures 3 to 14B shown.

[0018] Now referring to Figure 1 and Figure 3 , at block 12 of method 10, the first passivation layer 212 and the ESL 210 are patterned to form an opening 214 that exposes a portion of the wire 209. The opening 214 may be formed by a series of patterning and etching processes, including: for example, forming a mask element (not described) over the first passivation layer 212, exposing the mask element including a photoresist layer through a photomask, developing the exposed mask element in a suitable solvent (i.e., developer) to form a patterned mask element including the opening, etching through the first passivation layer 212 and the ESL 210 exposed in the opening, and removing the patterned mask element from the workpiece 200 by a suitable method such as resist stripping, wet etching, and / or plasma ashing.

[0019] Referring to Figure 4, Method 10 is at block 12, and then a seed layer 216 is formed over the patterned first passivation layer 212 such that the seed layer 216 lines the bottom and sidewall surfaces of the opening 214. The seed layer 216 can include copper, tantalum, titanium, titanium nitride, tantalum nitride, other suitable materials, or combinations thereof. The seed layer 216 can be a single-metal layer or optionally a composite layer. In this embodiment, the seed layer 216 includes copper such that it is configured to facilitate the subsequent formation of a copper-containing RDL thereover. The seed layer 216 can be deposited by any suitable method such as CVD, ALD, physical vapor deposition (PVD), or other suitable methods. Although not described, a barrier layer can be formed between the seed layer 216 and the patterned first passivation layer 212. The composition and method of forming such a barrier layer are similar to the composition and method discussed above with respect to the contact via 208 and the wire 209. In this embodiment, the seed layer 216 is configured to provide a substrate for forming an RDL thereover using a plating method such as electroplating, the process of which is discussed in detail below.

[0020] Now refer to Figure 1 and Figures 5A to 5C , Method 10 is at block 14 to form a mask element 220 over the seed layer 216 to fill the opening 214. The mask element 220 can be multilayered as described in Figure 5A and Figure 5B , or optionally, single-layered as described in Figure 5C . Although both structures are equally applicable in this embodiment, they provide different paths for forming the RDL, which will be discussed in detail below.

[0021] Refer to Figure 5A , Method 10 is at block 14, and first a bottom layer 220A is formed over the seed layer 216 to fill the opening 214. In this embodiment, the bottom layer 220A includes a polymeric material containing carbon, hydrogen, oxygen, nitrogen, and / or silicon. In this embodiment, the bottom layer 220A includes silicon. Although the specific composition of the bottom layer 220A is not limited, the bottom layer 220A provided herein can be patterned by a lithography process (discussed in detail below with respect to the photoresist layer 220B) and can provide an etch selectivity with respect to the subsequently formed photoresist layer 220B thereover, i.e., the composition of the bottom layer 220A is sufficiently different from the composition of the photoresist layer 220B, which will be discussed below, to ensure that one of the two layers can be etched at a greater rate with respect to the other layer. The bottom layer 220A can be formed over the seed layer 216 by any suitable method such as spin coating.

[0022] Refer to Figure 5B, Method 10 is at block 14, and then a photoresist layer 220B is formed over the underlying layer 220A. In this embodiment, the photoresist layer 220B comprises a polymeric material comprising at least carbon, hydrogen, oxygen, and / or nitrogen, and is formed by any suitable method such as spin coating. As described above, to ensure an etch selectivity between the underlying layer 220A and the photoresist layer 220B, the composition of the photoresist layer 220B is selected to be different from the composition of the underlying layer 220A. For example, the underlying layer 220A may comprise a polymer containing silicon (e.g., at least 30% silicon by weight), while the photoresist layer 220B comprises a polymer substantially free of silicon (e.g., containing less than 1% silicon by weight). In some embodiments, the photoresist layer 220B further comprises a photoacid generator (PAG), a thermal acid generator (TAG), a photobase generator (PBG), and / or other molecules configured to enhance the photosensitivity of the photoresist layer 220B to a given radiation source. In this embodiment, both the underlying layer 220A and the photoresist layer 220B (collectively referred to as the mask element 220) are configured to be patterned by the same lithography process. For example, the lithography process may include exposing the mask element 220 to a radiation source (e.g., extreme ultraviolet or EUV radiation) through a photomask, and developing the exposed mask element 220 to form a desired pattern in the mask element 220.

[0023] Now refer to Figure 5C , Method 10 is at block 14, and the photoresist layer 220B is optionally formed only over the seed layer 216 so as to fill the opening 214. The composition of the photoresist layer 220B has been discussed in detail above with respect to Figure 5B . Additionally, in the absence of the underlying layer 220A, the composition applied to the photoresist layer 220B is not limited to the embodiments described in Figure 5C as long as it is still patternable by a radiation source.

[0024] Turning to Figure 1 and Figures 6A to 6D , Method 10 is at block 16, and an opening and an undercut member are formed at the bottom of the opening in the mask element 220. Figure 6A and Figure 6B The embodiments described in Figure 5A and Figure 5B collectively correspond to the embodiments described in Figure 6C and Figure 6D where the mask element 220 comprises a photoresist layer 220B formed over the underlying layer 220A, while the embodiments described in Figure 5C collectively correspond to the embodiments described in

[0025] Refer to Figure 6A, at block 16 of method 10, a patterning process 310 is performed on the mask element 220 to form an opening 222 and to re-expose the opening 214. In this embodiment, the patterning process 310 removes portions of the mask element 220 (i.e., both the underlying layer 220A and the photoresist layer 220B), without removing or substantially removing portions of the seed layer 216 or the first passivation layer 212. In this embodiment, performing the patterning process 310 includes exposing the mask element 220 to a radiation source (e.g., EUV) through a photomask and developing the exposed mask element 220 in a suitable solvent (i.e., developer) to form the patterned mask element 220. Depending on the chemical reaction between the mask element 220 and the solvent, the exposed portions (in a positive photoresist scheme) or the unexposed portions (in a negative photoresist scheme) of the mask element 220 can be removed to form the patterned mask element 220. The patterning process 310 can optionally include one or more baking processes after performing the exposure process.

[0026] Proceed to Figure 6B , at block 16 of method 10, an etching process 320 is performed on the patterned mask element 220, thereby forming an undercut member 224A in the bottom of the underlying layer 220A. In this embodiment, due to the compositional difference between the underlying layer 220A and the photoresist layer 220B as described above, the etching process 320 removes portions of the underlying layer 220A at a greater rate than the photoresist layer 220B and the seed layer 216. In some embodiments, the etching process 320 does not remove or substantially remove any portions of the photoresist layer 220B and the seed layer 216. The etching process 320 can be any suitable etching process, such as a dry etching process, a wet etching process, a reactive ion etching (RIE), or a combination thereof. In this embodiment, the etching process 320 is a dry etching process that implements a fluorine-containing etchant (such as CF 4 , CH 3 F, CHF 3 ), other suitable fluorine-containing etchants, or a combination thereof.

[0027] In this embodiment, the lateral dimension L2 of the resulting undercut member 224A is controlled by the duration of the etching process 320, which can be determined based on the etching rate of the photoresist layer 220B. In some instances, the ratio of the width L1 of the opening 222 to L2 can be from about 1:30 to about 1:24. On one hand, a larger L2 can result in smaller angles θ small and / or θθ, as Figure 6B shown, resulting in potential difficulties in filling the undercut member 224A during a subsequent plating process. On the other hand, a smaller L2 can result in larger angles θ to and θθ, thereby limiting the filled undercut member 224A (i.e., as discussed below and in Figure 9The ability of the pedestal component 230B) described in Figure 9 to reduce stress concentration at the corners of the subsequently formed passivation layer (i.e., the second passivation layer 240) described below and in

[0028] Now referring to Figure 6C and Figure 6D , in method 10, at block 16, an opening 222 and an undercut component 224B are selectively formed, followed by a patterning process 330 and a defocusing process 340. Referring to Figure 6C , the patterning process 330 can be a lithography process configured to remove portions of the photoresist layer 220B through a series of exposure and development processes, thereby forming the opening 222 and re-exposing the opening 214. In some embodiments, the patterning process 330 is substantially similar to the patterning process 310 described above. It is noted that the patterning process 310 and the etching process 320 described herein are implemented with different tools. In contrast, the defocusing process 340 is implemented in the same lithography tool as the patterning process 330, but with operating conditions different from those of the patterning process 330.

[0029] Now turning to Figure 6D , method 10 implements the defocusing process 340 to form the undercut component 224B in the mask element 220 (i.e., the photoresist layer 220B). Regarding the patterning process 330, a light beam (i.e., a radiation source) passes through a photomask and is focused on the mask element 220 to form an opening 222 of a desired size. The focused light beam ensures that sufficient energy is provided to initiate a photochemical change in the exposed mask element 220 (i.e., a chemical change in the photoresist layer 220B caused by the light source). However, the defocusing process 340 involves intentionally diffusing or spreading the focus of the light beam, such that portions of the photoresist layer 220B that extend beyond the portion exposed by the photomask can be exposed to the light beam. Thus, defocusing the light beam results in overexposure of the bottom corners of the photoresist layer 220B, and an undercut component 224B is formed after development. In other words, unlike the etched undercut component 224A, the undercut component 224B is directly patterned in the mask element 220. Thus, the lateral dimension L3 of the undercut component 224B can be controlled by adjusting the extent to which the focus of the light beam is diffused, with a greater extent resulting in a greater magnitude of L3. In this embodiment, the magnitude of L3 can be similar to the magnitude of L2 discussed in detail above.

[0030] Regardless of whether the undercut 16 is achieved by the patterning process 310 and the etching process 320 or by the patterning process 330 and the defocusing process 340, the undercut members 224A / 224B as provided herein are configured to extend beyond the vertical sidewalls of the opening 222 in the lateral direction (i.e., along the X-axis in the described embodiment). Although described as having sharp corners, the undercut members 224A / 224B in this embodiment do not need to have corners of a specific shape as long as they extend laterally outward from the sidewalls of the opening 222. In this regard, in some instances, the corners may be blunt. Additionally, it is not required that the magnitudes of the angles θ and θθ be equal. The undercut members 224A / 224B may be defined by the angles θ and θθ as described above, where the angles θ and θθ are acute angles, i.e., measuring less than 90 degrees. In this embodiment, each of the angles θ and θθ is from about 30 degrees to about 70 degrees. It is noted that if the angles θ and θθ are less than about 30 degrees, it is generally difficult to ensure proper filling (e.g., incomplete filling) of the undercut members 224 / 224B during a subsequent plating process, resulting in defects in the subsequently formed RDL. However, if the angles θ and θθ are greater than about 70 degrees, the ability of the filled undercut members 224 / 224B (i.e., the pedestal members 230B) to relieve stress concentration at the corners of the RDL may be diminished.

[0031] Now turning to Figure 1 and Figures 7A to 8 , at block 18 of method 10, the openings of the patterned mask element 220 (i.e., the openings 214, the opening 222, and the undercut members 224A / 224B) are filled to form the RDL 230 over the passivation layer 212. The RDL 230 is configured to electrically connect the wire 209 to subsequently formed bumps (e.g., the bumps 250 as Figures 13 to 14B described). Although Figure 7A and Figure 7B respectively illustrate different embodiments of the present invention starting from Figure 6B and Figure 6D , the processes for forming the RDL 230 are substantially the same and will thus be discussed in general terms with respect to Figure 7A and Figure 7B .

[0032] In this embodiment, the RDL 230 comprises elemental copper and no copper-containing alloy. As provided herein, the RDL 230 is deposited by a plating process (such as electroplating and / or electroless plating) to fill the openings in the patterned mask element 220. In particular, the plating process can be implemented in a bottom-up scheme, during which the RDL 230 first grows on the seed layer 216 and then on itself, rather than on the surface of the patterned mask element 220. Thus, when the plating process is allowed to proceed without limitation, the RDL 230 will continue to grow, where its topmost portion rises above the top surface of the patterned mask element 220, and the process will be discussed in detail below. In other words, the maximum height of the RDL 230 exceeds the depth of the opening 222. In some instances, a wetting agent can be deposited prior to forming the RDL 230 to facilitate the bottom-up plating process. Although not described, a barrier layer can be formed above the portion of the seed layer 216 exposed by the patterned mask element 220 prior to forming the RDL 230. The barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, cobalt, cobalt nitride, tungsten nitride, ruthenium, ruthenium nitride, other metals, other metal nitrides, or combinations thereof.

[0033] Thereafter, refer to Figure 8 , the patterned mask element 220 is removed from the workpiece 200 by any suitable method (such as resist stripping, wet etching, and / or plasma ashing). Subsequently, the portion of the seed layer 216 not disposed under the RDL 230 is selectively removed from the workpiece 200 without removing or substantially removing the portion of the RDL 230 or the first passivation layer 212. In one instance, the etching process can be a dry etching process using a fluorine-based etchant (such as SF 6 ). Additionally or alternatively, method 10 can implement a wet etching process using a strong alkaline solution to remove any residual material from the previous processing step.

[0034] As described herein, the RDL 230 is made up of a bottom 230A formed in the first passivation layer to contact the bottom of the wire 209, a base member 230B formed in the undercut member 224, and a top 230C disposed above the seed layer 216 and located between the vertical sidewalls of the RDL 230. In this embodiment, due to the shape of the undercut members 224A or 224B formed by the etching process 320 or the defocusing process 340, respectively, the base member 230B is defined by acute angles θ sharp and θθ. In this embodiment, the top 230C has an upward curvature and is away from the top surface of the components below the workpiece 200 (which is also the top surface of the RDL 230). In other words, the top surface and the sidewalls of the RDL 230 intersect at a rounded corner. As Figure 8As described, the curved top surface can be defined by the ratio of the height h to the width w of the top 230C. In this embodiment, the ratio ranges from about 0.2 to about 0.3. On the one hand, if the ratio is less than about 0.2, the resulting top 230C may be too flat, i.e., the angle θ4 (described in the enlarged view of the top 230C) defining the inner angle of the RDL 230 may approach or become 90 degrees. On the other hand, if the ratio is greater than about 0.3, the resulting top 230C may not create sufficient contact area to engage with a subsequently formed bump (e.g., bump 250 as Figures 13 to 14B described).

[0035] Additionally, the curved top surface can be characterized by a continuously varying slope that is tangent to the curved surface. For example, as shown in the enlarged view of the top 230C, S1 - S5 represent the slopes of lines drawn tangentially at different points along the curved top surface. It should be understood that the magnitudes of the slopes S1 - S5 vary gradually and continuously. For example, in the described embodiment, the slope gradually decreases from S1 to S5. In contrast, if the top 230C has a substantially flat top surface, referring to Figure 8 configuration 231 outlined by the dashed line therein, which is also shown in an enlarged view, the angle θinner defining the inner angle of configuration 231 is substantially orthogonal (i.e., approximately 90 degrees). This causes the slope to change abruptly rather than gradually from S6 (not defined due to the substantially vertical surface) to S7 (zero due to the substantially horizontal surface).

[0036] Generally, a leveling agent (e.g., containing a phenyl polymer) can be introduced near the end of the plating process to ensure that the top surface of the resulting RDL 230 is substantially horizontal (or flat) with respect to the top surface of the patterned mask element 220, resulting in configuration 231 having an acute angle (e.g., angle θ3), as discussed above and described in Figure 8 . In other words, the leveling agent is configured to inhibit the overgrowth of the RDL230 beyond the top surface of the patterned mask element 220. In these cases, the leveling agent inhibits the growth of the copper layer by selectively adsorbing to copper atoms (through electrostatic attraction), rather than the patterned mask element 220. Thus, after a passivation layer (e.g., the second passivation layer 240 to be discussed in detail below) is formed over the RDL 230, any stress experienced by the passivation layer may concentrate at these orthogonal corners and result in structural defects in the second passivation layer including cracks, delamination, and / or other defects. In some cases, such stress may be caused by the second passivation layer and a subsequently formed protective layer above it (e.g., as Figures 11 to 14Bcaused by non-uniform thermal expansion between the described protective layer 246). To address these challenges, the present invention provides a method of forming an RDL having no or substantially no acute angles (i.e., angles defined by substantially orthogonal angles such as θ3) by forming a base member 230B defined by acute angles (e.g., angle θ degrees and θθ) and by performing a bottom-up plating process without the influence of a planarizing agent to form the curved top surface as described above. In other words, the plating process of this embodiment is intentionally performed without applying a planarizing agent, so that the copper layer is allowed to grow without inhibition beyond the top surface of the patterned mask element 220.

[0037] Now referring to Figure 1 and Figure 9 , in method 10, at block 20, a second passivation layer 240 is formed over the RDL 230. The second passivation layer 240 may include silicon nitride, silicon oxide, other suitable dielectric materials, or combinations thereof. In some embodiments, the second passivation layer 240 includes a dense dielectric material configured to provide protection against contaminants (e.g., moisture and / or oxygen) from entering the RDL 230 and / or other components of the workpiece 200. In some embodiments, the composition of the second passivation layer 240 is different from the composition of the first passivation layer 212. For example, the first passivation layer 212 may include USG, while the second passivation layer 240 may include silicon nitride. The second passivation layer 240 may have a single-layer structure or alternatively a multi-layer structure. The second passivation layer 240 may be formed by CVD, high-density plasma CVD (HDPCVD), plasma-enhanced CVD (PECVD), sub-atmospheric CVD (SACVD), other suitable methods, or combinations thereof. In this embodiment, the RDL 230 has no acute angles at its interface with the second passivation layer 240, thereby reducing stress concentration caused by any potential mismatched thermal expansion between the RDL 230 and the second passivation layer 240.

[0038] Now referring to Figure 1 and Figure 10 , in method 10, at block 22, an opening 242 is formed in the second passivation layer 240 to expose a portion of the RDL 230. The opening 242 may be formed by a series of patterning and etching processes similar to those discussed above with respect to forming the opening 214 ( Figure 3 ). For example, a patterned mask element (not described) having an opening may be formed over the RDL 230, and then the portion of the second passivation layer 240 exposed in the opening is removed by an etching process. In some embodiments, the etching process is performed with an etchant (such as SF 6)The dry etching process implemented. Additionally or optionally, a wet cleaning process using a strong alkaline solution can be implemented to form the opening 242. In some cases, as described herein, the etching process at block 22 can remove portions of the RDL 230, such that the opening 242 extends below the top surface of the RDL 230.

[0039] Reference Figure 1 and Figure 11 , in method 10 at block 24, a protective layer 246 is formed over the patterned second passivation layer 240 to fill the opening 242. The protective layer 246 can include polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable polymeric materials, or combinations thereof. In this embodiment, the protective layer 246 includes polyimide, which is a photoresist material that can undergo photochemical changes when exposed to a radiation source. In some embodiments, the protective layer 246 includes a photosensitivity enhancer, such as PAG, TAG, PBG, other suitable enhancers, or combinations thereof. In some embodiments, the protective layer 246 is formed by a suitable process, such as spin coating. For embodiments in which the opening 242 extends below the top surface of the RDL 230, portions of the protective layer 246 can thus extend below the top surface of the RDL 230.

[0040] Now reference Figure 1 and Figure 12 , in method 10 at block 26, the protective layer 246 is patterned to form an opening 248. For embodiments in which the protective layer 246 includes a photoresist material, such as polyimide, the protective layer 246 can be directly patterned to form the opening 248. In other words, forming the opening 248 can be implemented by exposing the protective layer 246 through a photomask to a radiation source and then developing the exposed protective layer 246 to form the opening 248. In this embodiment, the width of the opening 248 is adjusted such that its sidewalls are defined only by the protective layer 246 and not by portions of the second passivation layer 240, i.e., the sidewalls of the opening 248 are lined with the protective layer 246. This is to ensure that the patterning process removes only the photosensitive protective layer 246 and not the portion of the second passivation layer 240 that includes the dielectric material. In other words, leaving portions of the protective layer 246 in the opening 248 ensures that the resulting sidewalls have a substantially smooth profile. For embodiments in which the opening 242 extends below the top surface of the RDL 230 (as Figure 10 described), the sidewalls at the bottom of the protective layer 246 contact the second passivation layer 240 and the RDL 230.

[0041] After patterning, the protective layer 246 can be cured by baking or by exposure to a radiation source such as ultraviolet light. In some embodiments, curing causes crosslinking of the polymer chains of the protective layer 246, thereby forming a network that protects the underlying RDL 230 from mechanical stresses caused by subsequent processing steps such as a bump forming process. However, curing may also cause the protective layer 246 to shrink due to solvent evaporation or reduction reactions, thereby applying compressive stress to the second passivation layer 240. If the second passivation layer 240 includes sharp corners at its interface with the RDL 230, the compressive stress generated by the cured protective layer 246 may concentrate at such sharp corners, thereby causing structural defects such as cracks, delamination, and / or other defects in the workpiece 200. The present embodiment remedies these structural defects by replacing the sharp corners with curved top and pedestal members 230B, thereby improving the structural integrity of the workpiece 200.

[0042] Now referring to Figure 1 and Figure 13 , method 10 at block 28, forms bumps 250 in the openings 248. In the present embodiment, the bumps 250 are configured to bond (i.e., electrically couple) to the portions of the RDL 230 that are exposed in the openings 248. In the present embodiment, the bumps 250 include a bulk conductive layer comprising copper, nickel, cobalt, aluminum, gold, silver, palladium, tin, bismuth, their respective alloys, or combinations thereof. The bumps 250 may optionally include a seed layer (not described) that is disposed beneath the bulk conductive layer in the openings 248 and is configured to facilitate the formation of the bulk conductive layer. Depending on the composition of the bulk conductive layer, the seed layer may include copper, tantalum, titanium, titanium nitride, tantalum nitride, other suitable materials, or combinations thereof. In an exemplary embodiment, the bumps 250 include a copper-containing bulk conductive layer disposed above a copper-containing seed layer. For embodiments in which the opening 242 extends beneath the top surface of the RDL 230, portions of the bumps 250 also extend beneath the top surface of the RDL 230.

[0043] The bump 250 can be formed through a series of patterning and deposition processes. For example, forming the bump 250 can include forming a mask element (not described) including a photoresist layer over the protective layer 246, exposing the mask element to a radiation source through a photomask, developing the exposed mask element to form a patterned mask element that at least re-exposes the opening 248, then optionally depositing a seed layer in the opening 248, and forming a bulk conductive layer over the seed layer. Thus, the bump 250 is formed in the portion of the workpiece 200 not covered by the patterned mask element. In some embodiments, the patterned mask element remains over the protective layer 246 until a solder layer (e.g., solder layer 252) is subsequently formed over the bump 250 as described below. The bulk conductive layer can be formed by plating processes (e.g., electroplating and / or electroless plating). In some embodiments, the plating process for forming the bump 250 is implemented with the leveling agent described above, such that the top surface of the bump 250 is substantially horizontal.

[0044] After that, the solder layer 252 can be deposited over the bump 250. The solder layer 252 can be a lead-based or lead-free solder layer. In one example, the solder layer 252 can contain lead and tin for a lead-based composition. In another example, for a lead-free composition, the solder layer 252 can include an alloy containing indium and antimony or an alloy containing tin, silver, and copper, which can be referred to as SAC. In a further example, different compositions of the SAC alloy can be used, such as SAC 105 (tin 98.5%, silver 1.0%, copper 0.5%), SAC 305, and / or SAC 405. In some embodiments, the solder layer 252 includes a eutectic material having a eutectic point configured to form a conductive solder joint in an electrical application. The solder layer 252 having a lead-free composition can be formed from tin and copper (and their corresponding alloys or compounds) without using silver. Optionally, the solder layer 252 having a lead-free composition can include tin and silver (and their corresponding alloys or compounds) without using copper. After forming the solder layer 252, the patterned mask element is removed by resist stripping, wet etching, and / or plasma ashing, resulting in Figure 13 the described embodiment.

[0045] After that, refer to Figure 14A and Figure 14B, at block 30, method 10 can anneal workpiece 200 to allow solder layer 252 to reflow over bumps 250 and form reflowed solder layer 252'. The reflowed solder layer 252' can be used as a connection point to an external circuit such as another substrate, printed circuit board (PCB), interposer, reconstituted wafer, IC die, another redistribution layer, other interconnect structures, or other semiconductor devices. Due to the CTE mismatch between the protective layer 246 and the second passivation layer 240, the annealing process at block 30 may generate additional stress. Notably, the curved top surface and / or the pedestal component 230B of the RDL 230 provided herein alleviates this thermally induced stress, thereby preventing structural defects from damaging the second passivation layer 240.

[0046] In some embodiments, bumps 250 can be formed directly above the bottom 230A of the RDL 230 (not depicted), slightly overlapping the bottom 230A along the X-axis as Figure 14A described, or completely offset from the bottom 230A along the X-axis as Figure 14B described. This embodiment does not limit the configuration of the bumps 250 relative to the RDL 230, as long as the wire 209 and the bumps 250 are electrically connected through the RDL 230 and sufficient contact surface is provided between the bumps 250 and the top 230C. Additionally, referring to Figure 14B , depending on the degree of the etching process 320 or the defocusing process 340, angles θθ and θθ can be any acute angles and may not be equal in magnitude. Further, as Figure 14A and Figure 14B described, the transition region from the vertical sidewall of the RDL 230 to the pedestal component 230B can be angled (as described by the solid contour of the RDL 230), curved (as described by the dashed contour), or stepped (not depicted). Regardless of the shape of the transition region, the angles θ real and θθ defined herein are acute angles as described above.

[0047] Although not intended to be limiting, one or more embodiments of the present invention provide numerous benefits for semiconductor devices and their formation. For example, embodiments of the present invention provide a copper-containing RDL that includes a pedestal component and a curved top surface at the interface with the passivation layer. In some embodiments, the pedestal component is formed by over-etching or by photolithographic patterning to laterally extend an opening in which the RDL is formed. In some embodiments, when the RDL is formed in the opening, the curved top surface is formed by implementing a bottom-up scheme, such that the RDL overgrows to a depth beyond the opening. In this embodiment, the resulting RDL has substantially no acute angles (i.e., non-orthogonal angles) at its interface with one or more passivation layers, thereby alleviating structural defects caused by stress at this interface due to, for example, mismatched thermal expansion between the passivation layer and a polymer protective layer formed thereon.

[0048] In one aspect, the present invention provides a method, comprising providing an interconnect structure disposed over a semiconductor substrate, wherein the interconnect structure includes metal lines, forming a first dielectric layer over the metal lines, patterning the first dielectric layer to expose portions of the metal lines in first openings, and forming a patterned layer over the first dielectric layer to fill the first openings. The method further includes subsequently forming a second opening in the patterned layer, forming a pedestal profile to laterally extend the second opening, forming a redistribution layer (RDL) having a curved top surface in the second opening such that the RDL is electrically coupled to the metal lines, and forming a second dielectric layer over the RDL.

[0049] In another aspect, the present invention provides a semiconductor structure, comprising an interconnect structure disposed over a semiconductor substrate, wherein the interconnect structure includes metal lines, a first dielectric layer disposed on the interconnect structure, an RDL disposed over the first dielectric layer, a second dielectric layer disposed over the RDL, a protective layer disposed over the second dielectric layer, and a conductive component disposed in the protective layer and electrically coupled to the RDL. In this embodiment, the RDL extends through the first dielectric layer to contact the wire. Further, the RDL provided by the present invention includes a curved top surface and a pedestal profile disposed above the top surface of the first dielectric layer.

[0050] In yet another aspect, the present invention provides a semiconductor structure, comprising a first passivation layer disposed over metal lines, a copper-containing RDL disposed over the first passivation layer, wherein the copper-containing RDL is electrically coupled to the metal lines, and a second passivation layer disposed over the copper-containing RDL, wherein an interface between the second passivation layer and the top surface of the copper-containing RDL is curved. In this embodiment, a portion of the copper-containing RDL in contact with the top surface of the first passivation layer forms an acute angle. In some embodiments, the semiconductor structure further includes a polymer layer disposed over the second passivation layer, wherein portions of the polymer layer extend to contact the copper-containing RDL, bumps electrically coupled to the copper-containing RDL, and a solder layer disposed over the bumps.

[0051] Some embodiments of the present application relate to a method of forming a semiconductor structure, including: providing an interconnect structure disposed above a semiconductor substrate, wherein the interconnect structure includes metal lines; forming a first dielectric layer above the metal lines; patterning the first dielectric layer to expose a portion of the metal lines in a first opening; forming a pattern shaping layer above the first dielectric layer so as to fill the first opening; forming a second opening in the pattern shaping layer; forming a pedestal profile to laterally extend the second opening; forming a redistribution layer (RDL) in the second opening so that the redistribution layer is electrically coupled to the metal lines, wherein the redistribution layer includes a curved top surface; and forming a second dielectric layer above the redistribution layer. In some embodiments, the method further includes: forming a seed layer on the first dielectric layer before forming the pattern shaping layer; and removing a portion of the seed layer that is not covered by the redistribution layer before forming the second dielectric layer. In some embodiments, forming the pattern shaping layer includes forming a photoresist layer on the first dielectric layer. In some embodiments, forming the second opening includes performing a first lithography process on the photoresist layer, and wherein forming the pedestal profile includes performing a second lithography process on the photoresist layer after performing the first lithography process. In some embodiments, forming the pattern shaping layer includes forming an underlayer on the first dielectric layer and then forming a photoresist layer on the underlayer. In some embodiments, the underlayer includes silicon, and wherein the photoresist layer does not include silicon. In some embodiments, forming the second opening includes performing a lithography process on the photoresist layer, and wherein forming the pedestal profile includes selectively etching the underlayer with respect to the photoresist layer after performing the lithography process. In some embodiments, forming the redistribution layer includes performing a bottom-up plating process. In some embodiments, the method further includes: forming a third opening in the second dielectric layer to expose the top of the redistribution layer; forming a protective layer above the second dielectric layer so that the protective layer extends to contact the top of the redistribution layer in the third opening; forming a fourth opening in the protective layer to expose the top of the redistribution layer; forming a bump in the fourth opening; and forming a solder component above the bump.

[0052] Some other embodiments of the present application relate to a semiconductor structure, including: an interconnect structure disposed above a semiconductor substrate, wherein the interconnect structure includes a wire; a first dielectric layer disposed on the interconnect structure; a redistribution layer (RDL) disposed above the first dielectric layer, wherein the redistribution layer extends through the first dielectric layer to contact the wire, and wherein the redistribution layer includes a curved top surface and a pedestal profile disposed above the top surface of the first dielectric layer; a second dielectric layer disposed above the redistribution layer; a protective layer disposed above the second dielectric layer; and a conductive component disposed above the redistribution layer and electrically coupled to the redistribution layer. In some embodiments, the redistribution layer includes copper. In some embodiments, the angle defined by the inclined surface of the pedestal profile and the bottom surface of the pedestal profile is less than 90 ° . In some embodiments, the sidewall of the conductive component is defined by the protective layer. In some embodiments, the semiconductor structure further includes: a copper-containing seed layer disposed between the redistribution layer and the first dielectric layer. In some embodiments, the semiconductor structure further includes: a solder layer disposed above the conductive component. In some embodiments, the curved top surface intersects the sidewall of the redistribution layer at a rounded corner.

[0053] Some other embodiments of the present application relate to a semiconductor structure, including: a first passivation layer disposed above a metal wire; a copper-containing redistribution layer (RDL) disposed above the first passivation layer, wherein the copper-containing redistribution layer is electrically coupled to the metal wire, and wherein the portion of the copper-containing redistribution layer in contact with the upper surface of the first passivation layer forms an acute angle; a second passivation layer disposed above the copper-containing redistribution layer, wherein the interface between the second passivation layer and the top surface of the copper-containing redistribution layer is curved; a polymer layer disposed above the second passivation layer, wherein a portion of the polymer layer extends to contact the copper-containing redistribution layer; a bump electrically coupled to the copper-containing redistribution layer; and a solder layer disposed above the bump. In some embodiments, the semiconductor structure further includes: a copper-containing seed layer located between the copper-containing redistribution layer and the first passivation layer and between the copper-containing redistribution layer and the metal wire. In some embodiments, the sidewall of the bump extends below the top surface of the copper-containing redistribution layer. In some embodiments, the copper-containing redistribution layer does not contain a copper alloy.

[0054] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. A method of manufacturing a semiconductor structure, comprising: providing an interconnect structure disposed over a semiconductor substrate, wherein the interconnect structure includes metal lines; forming a first dielectric layer over the metal lines; patterning the first dielectric layer to expose portions of the metal lines in a first opening; forming a shaping layer over the first dielectric layer to fill the first opening; forming a second opening in the shaping layer; forming a pedestal profile to laterally extend the second opening, wherein the second opening and the pedestal profile are formed in different steps; forming a redistribution layer (RDL) in the second opening such that the redistribution layer is electrically coupled to the metal lines, wherein the redistribution layer includes a curved top surface; and forming a second dielectric layer over the redistribution layer.

2. The method according to claim 1, further comprising: forming a seed layer on the first dielectric layer before forming the shaping layer; and removing portions of the seed layer not covered by the redistribution layer before forming the second dielectric layer.

3. The method according to claim 1, wherein forming the shaping layer includes forming a photoresist layer on the first dielectric layer.

4. The method according to claim 3, wherein forming the second opening includes performing a first lithography process on the photoresist layer, and wherein forming the pedestal profile includes performing a second lithography process on the photoresist layer after performing the first lithography process.

5. The method according to claim 1, wherein forming the shaping layer includes forming an underlayer on the first dielectric layer and subsequently forming a photoresist layer on the underlayer.

6. The method according to claim 5, wherein the underlayer includes silicon and wherein the photoresist layer does not include silicon.

7. The method according to claim 5, wherein forming the second opening includes performing a lithography process on the photoresist layer, and wherein forming the pedestal profile includes selectively etching the underlayer with respect to the photoresist layer after performing the lithography process.

8. The method according to claim 1, wherein forming the redistribution layer includes performing a bottom-up plating process.

9. The method according to claim 1, further comprising: forming a third opening in the second dielectric layer to expose the top of the redistribution layer; forming a protective layer over the second dielectric layer such that the protective layer extends to contact the top of the redistribution layer in the third opening; forming a fourth opening in the protective layer to expose the top of the redistribution layer; forming a bump in the fourth opening; and forming a solder component over the bump.

10. A semiconductor structure, comprising: an interconnect structure disposed over a semiconductor substrate, wherein the interconnect structure includes conductive lines; a first dielectric layer disposed on the interconnect structure; A redistribution layer (RDL) is disposed above the first dielectric layer, wherein the redistribution layer extends through the first dielectric layer to contact the wire, and wherein the redistribution layer includes a curved top surface and a pedestal profile disposed above the top surface of the first dielectric layer; A second dielectric layer is disposed above the redistribution layer, and the interface between the second dielectric layer and the redistribution layer is curved. The interface includes a continuous first sidewall and a second sidewall. The first sidewall forms an acute angle with the pedestal profile of the first dielectric layer in a first direction, and the extension direction of the second sidewall forms an angle greater than the acute angle with the surface of the first dielectric layer in a second direction, wherein the second direction is opposite to the first direction; A protective layer is disposed above the second dielectric layer; and A conductive component is disposed above the redistribution layer and electrically coupled to the redistribution layer.

11. The semiconductor structure according to claim 10, wherein, the redistribution layer includes copper.

12. The semiconductor structure according to claim 10, wherein, the angle defined by the inclined surface of the pedestal profile and the bottom surface of the pedestal profile is less than 90°.

13. The semiconductor structure according to claim 10, wherein, the sidewall of the conductive component is defined by the protective layer.

14. The semiconductor structure according to claim 10, further comprising: A copper-containing seed layer is disposed between the redistribution layer and the first dielectric layer.

15. The semiconductor structure according to claim 10, further comprising: A solder layer is disposed above the conductive component.

16. The semiconductor structure according to claim 10, wherein, the curved top surface intersects the sidewall of the redistribution layer at a rounded corner.

17. A semiconductor structure, comprising: A first passivation layer is disposed above the metal wire; A copper-containing redistribution layer (RDL) is disposed above the first passivation layer, wherein the copper-containing redistribution layer is electrically coupled to the metal wire, and wherein the portion of the copper-containing redistribution layer in contact with the upper surface of the first passivation layer forms an acute angle; A second passivation layer is disposed above the copper-containing redistribution layer, wherein the interface between the second passivation layer and the copper-containing redistribution layer is curved. The interface includes a continuous first sidewall and a second sidewall. The first sidewall forms the acute angle with the first passivation layer in a first direction, and the extension direction of the second sidewall forms an angle greater than the acute angle with the surface of the first passivation layer in a second direction, wherein the second direction is opposite to the first direction; A polymer layer is disposed above the second passivation layer, wherein a portion of the polymer layer extends to contact the copper-containing redistribution layer; A bump is electrically coupled to the copper-containing redistribution layer; and A solder layer is disposed above the bump.

18. The semiconductor structure according to claim 17, further comprising: A copper-containing seed layer is located between the copper-containing redistribution layer and the first passivation layer and between the copper-containing redistribution layer and the metal wire.

19. The semiconductor structure according to claim 17, wherein, The sidewall of the bump extends below the top surface of the copper-containing redistribution layer.

20. The semiconductor structure according to claim 17, wherein, the copper-containing redistribution layer does not contain a copper alloy.

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