Pad structure and forming method thereof, semiconductor device and forming method thereof

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a pad structure and a method for forming the same, a semiconductor device and a method for forming the same. The pad structure includes: a pad body, including an upper surface and a lower surface that are relatively distributed, and the lower surface is used to electrically connect to the internal circuit of a chip; a groove extending from the upper surface to the inside of the pad body, separating the pad body into a test area and a welding area; a protective layer covering at least the bottom wall of the groove. The present invention separates the test area from the welding area, avoiding the problem of easy failure of package connection due to probe testing, and at the same time avoiding damage to the chip between the test area and the welding area by the external environment, thereby improving the yield and performance stability of semiconductor devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a pad structure and a forming method thereof, a semiconductor device and a forming method thereof. Background Art

[0002] In the back-end packaging process of semiconductor devices such as dynamic random access memory (DRAM), it is usually necessary to form a pad structure on the surface of the semiconductor chip for probe testing and bonding with the package. However, during the current probe testing process, the contact between the probe and the pad structure may cause scratches on the surface of the pad structure or introduce dust on the surface of the pad structure, which may easily pull the metal line and cause the wire to fall off during the subsequent packaging connection, affecting the yield of the semiconductor device and even causing the semiconductor device to be scrapped.

[0003] Therefore, how to reduce the impact of probe testing on package connections and improve the yield of semiconductor devices is a technical problem that needs to be solved urgently. Summary of the invention

[0004] The present invention provides a pad structure and a method for forming the same, a semiconductor device and a method for forming the same, which are used to solve the problem that the existing semiconductor device is prone to failure in connection with external wiring during the packaging process, so as to improve the yield of the semiconductor device and enhance the performance stability of the semiconductor device.

[0005] In order to solve the above problems, the present invention provides a pad structure, comprising:

[0006] The pad body comprises an upper surface and a lower surface which are relatively distributed, and the lower surface is used for electrically connecting with the internal circuit of the chip;

[0007] A groove extending from the upper surface toward the inside of the pad body, dividing the pad body into a test area and a welding area;

[0008] The protective layer at least covers the bottom wall of the groove.

[0009] Optionally, the groove runs through the pad body, and the protective layer is used to cover the chip surface located at the bottom of the groove;

[0010] On the upper surface, there is a gap between the edge of the groove and the edge of the pad body to achieve electrical connection between the test area and the welding area on the upper surface.

[0011] Optionally, the depth of the groove is less than the thickness of the pad body, and the protection layer covers the surface of the pad body at the bottom of the groove.

[0012] Optionally, the protective layer includes:

[0013] a first protective layer, covering at least a bottom wall of the groove;

[0014] The second protective layer covers the first protective layer.

[0015] Optionally, the protection layer covers the bottom wall and side walls of the groove.

[0016] Optionally, on the upper surface, the groove has a length of 30 μm to 80 μm extending along a first direction and a width of 0.5 μm to 20 μm along a second direction perpendicular to the first direction.

[0017] In order to solve the above problem, the present invention also provides a method for forming a pad structure, comprising the following steps:

[0018] Forming a pad body, the pad body comprising an upper surface and a lower surface that are relatively distributed, the lower surface being used to be electrically connected to an internal circuit of the chip;

[0019] Forming a groove on the upper surface of the pad body, wherein the groove extends from the upper surface to the inside of the pad body, and separates the pad body into a test area and a welding area;

[0020] A protection layer is formed to cover at least a bottom wall of the trench.

[0021] Optionally, the following steps are also included:

[0022] Providing a pad base layer;

[0023] Forming a photoresist layer on the surface of the pad base layer, wherein the photoresist layer has an opening exposing the pad base layer;

[0024] The pad base layer is etched to simultaneously form the pad body and the groove.

[0025] Optionally, the specific step of forming a protective layer that at least covers the bottom wall of the groove includes:

[0026] forming a first protective layer, wherein the first protective layer covers the sidewall and the upper surface of the pad body and the inner wall of the groove;

[0027] forming a second protection layer, wherein the second protection layer covers the first protection layer located on the side wall surface of the pad body and the bottom wall surface of the groove;

[0028] The first protective layer is etched using the second protective layer as a mask, and the first protective layer and the second protective layer remaining in the trench serve together as the protective layer.

[0029] Optionally, the groove runs through the pad body, and the protective layer is used to cover the chip surface located at the bottom of the groove;

[0030] On the upper surface, there is a gap between the edge of the groove and the edge of the pad body to achieve electrical connection between the test area and the welding area on the upper surface.

[0031] Optionally, the depth of the groove is less than the thickness of the pad body, and the protection layer covers the surface of the pad body at the bottom of the groove.

[0032] In order to solve the above problem, the present invention further provides a semiconductor device, comprising:

[0033] chip;

[0034] In the pad structure as described in any one of the above items, the lower surface of the pad body is electrically connected to the internal circuit of the chip.

[0035] Optionally, the protection layer at least covers the bottom wall of the groove and the surface of the chip except where the pad structure is formed.

[0036] In order to solve the above problem, the present invention further provides a method for forming a semiconductor device, comprising the following steps:

[0037] Provide chips;

[0038] A pad structure is formed on the surface of the chip by using any of the above-mentioned pad structure forming methods, and the lower surface of the pad body is electrically connected to the internal circuit of the chip.

[0039] Optionally, the protection layer at least covers the bottom wall of the groove and the surface of the chip except where the pad structure is formed.

[0040] The pad structure and its forming method, semiconductor device and its forming method provided by the present invention form a groove on the pad body, on the one hand, to separate the test area and the welding area, avoid the problem of easy failure of packaging connection due to probe test, and improve the yield of semiconductor devices; on the other hand, a protective layer is formed to cover the bottom wall of the groove, covering the chip surface between the test area and the welding area, avoiding damage to the chip between the test area and the welding area by the external environment, and further improving the yield and performance stability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Attached Figure 1 is a cross-sectional schematic diagram of a pad structure in a first specific implementation manner of the present invention;

[0042] Attached Figure 2 is a schematic diagram of a top view of a pad structure in a first specific embodiment of the present invention;

[0043] Attached Figure 3 is a flow chart of a method for forming a pad structure in a first specific embodiment of the present invention;

[0044] Attached Figures 4A-4F It is a schematic cross-sectional view of the main processes in the process of forming a pad structure and a semiconductor device in the first specific embodiment of the present invention;

[0045] Attached Figure 5 is a flow chart of a method for forming a semiconductor device in a first specific embodiment of the present invention;

[0046] Attached Figure 6 It is a cross-sectional schematic diagram of the pad structure in the second specific implementation manner of the present invention. DETAILED DESCRIPTION

[0047] The specific implementation methods of the pad structure and the forming method thereof, the semiconductor device and the forming method thereof provided by the present invention are described in detail below with reference to the accompanying drawings.

[0048] First specific embodiment

[0049] This specific implementation provides a pad structure, attached Figure 1 is a schematic cross-sectional view of a pad structure in a first specific embodiment of the present invention, Figure 2 Schematic diagram of the top view of the pad structure in the first specific embodiment of the present invention. Figure 1 , Figure 2 As shown, the pad structure provided in this specific embodiment includes:

[0050] The pad body 20 includes an upper surface and a lower surface that are relatively distributed, and the lower surface is used to be electrically connected to the internal circuit 101 of the chip 10;

[0051] A groove 13 extending from the upper surface toward the inside of the pad body 20 to separate the pad body 20 into a test area 12 and a welding area 11;

[0052] The protective layer at least covers the bottom wall of the groove 13 .

[0053] Specifically, the material of the pad body 20 is a conductive material, such as a metal material. When the material of the pad body 20 is a metal material, it can be any single metal material of copper, aluminum, and tungsten, or an alloy material formed by two or more of them. The shape of the pad body 20 can be rectangular. For example, the ratio between the length of the pad body along the X-axis direction and the width along the Y-axis direction can be (1:1) to (2:1). The groove 13 extends from the upper surface of the pad body 20 along the Z-axis direction to the inside of the pad body 20, thereby dividing the pad body 20 into the test area 12 and the welding area 11, and the test area 12 and the welding area 11 are distributed on opposite sides of the groove 13 along the X-axis direction. The surface of the test area 12 has a probe mark for probe testing; the welding area 11 is used to electrically connect to an external circuit 14 (such as a gold wire). When the probe 15 is used to test the test area 12, the probe 15 can also fall into the groove 13, and the side wall of the groove 13 can also prevent the probe 15 from damaging the welding area 11; the protective layer in the groove 13 can also prevent damage to the chip, for example, avoiding the problem of cracks on the chip surface caused by the probe directly piercing the chip surface. The relative area size of the welding area 11 and the test area 12 can be set by those skilled in the art according to actual needs, such as according to the requirements of the probe test and the requirements of the wire bonding connected to the external circuit, and this specific embodiment does not limit this.

[0054] In this specific embodiment, the test area 12 is separated from the welding area 11, which can avoid the adverse effects (such as wire falling off) caused by damage caused by probe testing (such as scratches caused by the probe 15, dust generated), and the protective layer covers the bottom wall surface of the groove 13, avoiding the exposure of the chip 10 between the welding area 11 and the test area 12 due to the setting of the groove 13, and ensuring the performance stability of the semiconductor device with the pad structure. In this specific embodiment, the protective layer can only cover the bottom wall of the groove 13, and can also cover the bottom wall and part of the side wall of the groove 13 at the same time. In this specific embodiment, the top surface of the protective layer is located below the top surface of the groove 13 or flush with the top surface of the groove 13, that is, the height of the protective layer is less than or equal to the depth of the groove 13.

[0055] In other specific embodiments, the top surface of the protective layer is located above the top surface of the groove, that is, the height of the protective layer is greater than the depth of the groove. At this time, the protective layer and the upper surface of the pad body are independent of each other, that is, the protective layer does not cover the upper surface of the pad body, and there is a gap between the edge of the protective layer and the test area 12 and the welding area 11.

[0056] Those skilled in the art can set the depth of the groove 13 along the Z-axis direction according to actual needs, for example, according to the thickness of the pad body 20, the requirements for subsequent connection with external circuits, etc. Optionally, the depth of the groove 13 is 100nm to 2μm. For example, in one embodiment, the depth of the groove 13 can be 100nm to 200nm, 200nm to 400nm, or 400nm to 800nm; in another embodiment, the depth of the groove 13 can be 900nm to 1.5μm, or 1.5μm to 2μm.

[0057] This specific embodiment does not limit the specific shape of the groove 13, and those skilled in the art can select it according to actual needs. In order to simplify the formation process of the pad structure, optionally, the cross-sectional shape of the groove 13 along the direction parallel to the upper surface is rectangular, circular or elliptical.

[0058] Optionally, the groove 13 passes through the pad body 20, and the protective layer is used to cover the surface of the chip 10 located at the bottom of the groove 13;

[0059] On the upper surface, there is a gap between the edge of the groove 13 and the edge of the pad body 20 to achieve electrical connection between the test area 12 and the welding area 11 on the upper surface.

[0060] Specifically, the groove 13 penetrates the pad body 20 along the Z-axis direction (the direction perpendicular to the pad body 20), that is, the depth of the groove 13 is the same as the thickness of the pad body 20. The surface of the chip 10 between the test area 12 and the welding area 11 is exposed from the groove 13, and the protective layer covers the surface of the chip 10 exposed between the welding area 11 and the test area 12. Figure 2 As shown, there is a gap 21 with a width D between the edge of the groove 13 and the edge of the pad body 20, forming a narrow neck area for connecting the welding area 11 and the test area 12, thereby further reducing the resistance inside the pad structure.

[0061] In this specific embodiment, the protective layer may be a single layer or a multi-layer stacked structure. In order to simplify the formation process of the pad structure and improve the shielding effect on the surface of the chip 10 between the test area 12 and the welding area 11, the protective layer may optionally include:

[0062] A first protective layer 16 at least covers the bottom wall of the groove 13;

[0063] The second protective layer 17 covers the first protective layer 16 .

[0064] Optionally, the protection layer covers the bottom wall and side walls of the groove 13 .

[0065] Specifically, the first protective layer 16 covers the sidewalls and the bottom wall of the groove 13, and the second protective layer 17 covers the surface of the first protective layer 16. The material of the first protective layer 16 and the material of the second protective layer 17 preferably have a high etching selectivity, for example, an etching selectivity greater than or equal to 3, so as to simplify the formation process of the pad structure.

[0066] Optionally, on the upper surface, the groove 13 extends along a first direction with a length of 30 μm to 80 μm, and has a width along a second direction perpendicular to the first direction of 0.5 μm to 20 μm.

[0067] For example, the Y-axis direction is the first direction and the X-axis direction is the second direction. The groove 13 is rectangular, and the length L of the groove 13 along the Y-axis direction can be 30 μm to 80 μm, and the width W along the X-axis direction can be 0.5 μm to 20 μm.

[0068] In addition, this specific embodiment also provides a method for forming a pad structure. Figure 3 is a flow chart of a method for forming a pad structure in a first specific embodiment of the present invention, Figures 4A-4F is a schematic diagram of the main process cross-section in the process of forming a pad structure in the first specific embodiment of the present invention. The schematic diagram of the pad structure formed in this specific embodiment can be seen in Figure 1 , Figure 2 .like Figure 1-Figure 3 , Figure 4A-4F As shown, the method for forming a pad structure provided in this specific embodiment includes the following steps:

[0069] Step S31, forming a pad body 20, wherein the pad body 20 includes an upper surface and a lower surface that are relatively distributed, and the lower surface is used to be electrically connected to the internal circuit 101 of the chip 10;

[0070] Step S32, forming a groove 13 on the upper surface of the pad body 20, wherein the groove 13 extends from the upper surface to the inside of the pad body 20, and separates the pad body 20 into a test area 12 and a welding area 11. Figure 4C shown.

[0071] Optionally, the following steps are also included:

[0072] Providing a pad base layer 40;

[0073] A photoresist layer 41 is formed on the surface of the pad base layer 40, and the photoresist layer 41 has an opening 411 exposing the pad base layer 40. Figure 4A As shown;

[0074] The pad base layer 40 is etched to form the pad body 20 and the groove 13 at the same time. Figure 4C shown.

[0075] Specifically, a physical vapor deposition process or an atomic layer deposition process can be used to deposit a conductive material on the surface of a chip 10 to form the pad base layer 40. The conductive material can be a metal material, such as any single metal material of copper, aluminum, and tungsten, or an alloy material formed by two or more of them. After forming the pad base layer 40 covering the surface of the chip 10, a pad area is defined on the surface of the pad base layer 40, and a photoresist layer 41 covering the pad area is formed, and the photoresist layer 41 has an opening 411 exposing the pad base layer 40. Next, a dry etching process is used to etch the pad base layer 40 that is not covered by the photoresist layer 41, and at the same time, the pad body 20 and the groove 13 are formed, as shown in FIG. Figure 4B Afterwards, the photoresist layer 41 is removed to form Figure 4C The structure shown.

[0076] Step S33 , forming a protection layer that at least covers the bottom wall of the trench 13 .

[0077] Optionally, the specific steps of forming a protective layer that at least covers the bottom wall of the groove 13 include:

[0078] A first protective layer 16 is formed, wherein the first protective layer 16 covers the side wall and the upper surface of the pad body 20 and the inner wall of the groove 13. Figure 4D As shown;

[0079] A second protective layer 17 is formed, and the second protective layer 17 covers the first protective layer 16 located on the side wall surface of the pad body 20 and the bottom wall surface of the groove 13. Figure 4E As shown;

[0080] The first protective layer 16 is etched using the second protective layer 17 as a mask, and the first protective layer 16 and the second protective layer 17 remaining in the groove 13 are used together as the protective layer. Figure 4F shown.

[0081] Optionally, the groove 13 passes through the pad body 20, and the protective layer is used to cover the surface of the chip 10 located at the bottom of the groove 13;

[0082] On the upper surface, there is a gap 21 between the edge of the groove 13 and the edge of the pad body 20 to achieve electrical connection between the test area 12 and the welding area 11 on the upper surface.

[0083] Specifically, after forming the pad structure, a passivation material is deposited on the surface of the pad body 20 (including the upper surface and sidewalls of the pad body 20) and the inner wall of the groove 13 to form a Figure 4D The first protective layer 16 shown in the figure is formed by depositing an insulating material on the surface of the first protective layer 16 covering the sidewalls of the pad body 20 and the bottom wall of the groove 13 to form the second protective layer 17; then, the first protective layer 16 is etched using the second protective layer 17 as a mask to remove the first protective layer 16 on the upper surface of the pad body 20, and the first protective layer 16 remaining in the groove 13 and the second protective layer 17 located in the groove 13 together serve as the protective layer. In order to fully remove the first protective layer 42 covering the upper surface of the pad body 20, the passivation material and the insulating material should have a high etching selectivity, for example, an etching selectivity greater than or equal to 3.

[0084] In this specific embodiment, after the first protective layer 16 is etched using the second protective layer 17 as a mask, the remaining first protective layer 16 does not completely cover the upper surface of the pad body 20. In other specific embodiments, the first protective layer 16 remaining after etching may also cover the edge area of ​​the upper surface of the test area 12 away from the groove 13, and the edge area of ​​the upper surface of the welding area 11 away from the groove 13.

[0085] Those skilled in the art can control the depth of the formed groove 13 by adjusting the amount of etching gas and etching time. Optionally, the depth of the groove 13 is 100 nm to 2 μm.

[0086] Optionally, on the upper surface, the groove 13 extends along a first direction with a length of 30 μm to 80 μm, and has a width along a second direction perpendicular to the first direction of 0.5 μm to 20 μm.

[0087] This specific embodiment does not limit the specific shape of the groove 13, and those skilled in the art can select it according to actual needs. In order to simplify the formation process of the pad structure, optionally, the cross-sectional shape of the groove 13 along the direction parallel to the upper surface is rectangular, circular or elliptical.

[0088] In addition, this specific embodiment also provides a semiconductor device. The structure of the semiconductor device provided by this specific embodiment can be seen in Figure 1 and Figure 2 .like Figure 1 , Figure 2 As shown, the semiconductor device provided in this specific embodiment includes:

[0089] Chip 10;

[0090] In any of the above-mentioned pad structures, the lower surface of the pad body 20 is electrically connected to the internal circuit 101 of the chip 10 .

[0091] Optionally, the protection layer at least covers the bottom wall of the groove 13 and the surface of the chip 10 except where the pad structure is formed.

[0092] In addition, this embodiment also provides a method for forming a semiconductor device. Figure 5 is a flow chart of a method for forming a semiconductor device in a first specific embodiment of the present invention, Figures 4A-4F is a schematic cross-sectional view of the main process in the process of forming a semiconductor device in the first specific embodiment of the present invention. The structure of the semiconductor device formed in this specific embodiment can be seen in Figure 1 , Figure 2 .like Figure 1 , Figure 2 , Figure 4A-4F and Figure 5 As shown, the method for forming a semiconductor device provided in this specific embodiment includes the following steps:

[0093] Step S51, providing a chip 10;

[0094] Step S52 , forming a pad structure on the surface of the chip 10 by using any of the above-mentioned pad structure forming methods, wherein the lower surface of the pad body 20 is electrically connected to the internal circuit 101 of the chip 10 .

[0095] Optionally, the protection layer at least covers the bottom wall of the groove 13 and the surface of the chip 10 except where the pad structure is formed.

[0096] The pad structure and its formation method, semiconductor device and its formation method provided in this specific embodiment form a groove on the pad body, which, on the one hand, separates the test area and the welding area, avoids the problem of easy failure of packaging connection due to probe testing, and improves the yield of semiconductor devices; on the other hand, forms a protective layer to cover the bottom wall of the groove, covering the chip surface between the test area and the welding area, avoiding damage to the chip between the test area and the welding area by the external environment, and further improving the yield and performance stability of the semiconductor device.

[0097] Second specific embodiment

[0098] This specific embodiment provides a pad structure and a method for forming the same, a semiconductor device and a method for forming the same, Figure 6 2 is a schematic cross-sectional view of a pad structure in a second embodiment of the present invention. This embodiment will not repeat the same points as the first embodiment, and the following mainly describes the differences from the first embodiment. Figure 6 As shown, the pad structure provided in this specific embodiment includes:

[0099] The pad body includes an upper surface and a lower surface that are relatively distributed, and the lower surface is used to be electrically connected to the internal circuit 601 of the chip 60;

[0100] A groove 63 extending from the upper surface toward the inside of the pad body, dividing the pad body into a test area 62 and a welding area 61;

[0101] The protection layer at least covers the bottom wall of the groove 63 .

[0102] Optionally, the depth of the groove 63 is smaller than the thickness of the pad body, and the protection layer covers the surface of the pad body at the bottom of the groove 13 .

[0103] In this specific embodiment, the depth of the groove 63 along the Z-axis direction is less than the thickness of the pad body, that is, the groove 13 does not penetrate the pad body, so that the test area 62 and the welding area 61 are electrically connected through the pad body located at the bottom of the groove 63, thereby avoiding the additional resistance generated inside the pad structure due to the complete isolation between the welding area 61 and the test area 62, thereby ensuring the performance stability of the semiconductor device with the pad structure.

[0104] Since the groove 63 does not penetrate the pad body, the edge of the groove 63 may coincide with the edge of the pad body, that is, the length of the groove 63 along the Y-axis direction may be equal to the width of the pad body along the Y-axis direction.

[0105] In other specific embodiments, in order to further reduce the resistance inside the pad structure, on the upper surface, there is a gap between the edge of the groove 63 and the edge of the pad body to achieve electrical connection between the test area 12 and the welding area 11 on the upper surface.

[0106] Optionally, the protective layer includes:

[0107] A first protective layer 66 at least covers the bottom wall of the groove 63;

[0108] The second protective layer 67 covers the first protective layer 66 .

[0109] In the semiconductor device having the pad structure provided in this specific embodiment, the lower surface of the pad body is electrically connected to the internal circuit 601 of the chip 60 , and the protection layer covers the surface of the pad body at the bottom of the groove 13 .

[0110] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A pad structure, characterized in that: include: The pad body comprises an upper surface and a lower surface which are relatively distributed, and the lower surface is used for electrically connecting with the internal circuit of the chip; a groove extending from the upper surface toward the inside of the pad body, dividing the pad body into a test area and a welding area, wherein the welding area is used to be electrically connected to an external circuit; The protection layer at least covers the bottom wall of the groove and does not cover the upper surface of the pad body.

2. The pad structure according to claim 1, characterized in that: The groove runs through the pad body, and the protection layer covers the chip surface located at the bottom of the groove; On the upper surface, there is a gap between the edge of the groove and the edge of the pad body to achieve electrical connection between the test area and the welding area on the upper surface.

3. The pad structure according to claim 1, characterized in that: The depth of the groove is smaller than the thickness of the pad body, and the protection layer covers the surface of the pad body at the bottom of the groove.

4. The pad structure according to claim 1, characterized in that: The protective layer comprises: a first protective layer, covering at least a bottom wall of the groove; The second protective layer covers the first protective layer.

5. The pad structure according to claim 1, characterized in that: The protection layer covers the bottom wall and side walls of the trench.

6. The pad structure according to claim 1, characterized in that: On the upper surface, the groove has a length of 30 μm to 80 μm extending along a first direction and a width of 0.5 μm to 20 μm along a second direction perpendicular to the first direction.

7. A method for forming a pad structure, characterized in that: The steps include: Forming a pad body, the pad body comprising an upper surface and a lower surface that are relatively distributed, the lower surface being used to be electrically connected to an internal circuit of the chip; A groove is formed on the upper surface of the pad body, the groove extends from the upper surface to the inside of the pad body, and separates the pad body into a test area and a welding area, wherein the welding area is used to be electrically connected to an external circuit; A protection layer is formed to cover at least the bottom wall of the groove, and the protection layer does not cover the upper surface of the pad body.

8. The method for forming a pad structure according to claim 7, characterized in that: The following steps are also included: Providing a pad base layer; Forming a photoresist layer on the surface of the pad base layer, wherein the photoresist layer has an opening exposing the pad base layer; The pad base layer is etched to simultaneously form the pad body and the groove.

9. The method for forming a pad structure according to claim 7, characterized in that: The specific steps of forming a protective layer covering at least the bottom wall of the groove include: forming a first protective layer, wherein the first protective layer covers the sidewall and the upper surface of the pad body and the inner wall of the groove; forming a second protection layer, wherein the second protection layer covers the first protection layer located on the side wall surface of the pad body and the bottom wall surface of the groove; The first protective layer is etched using the second protective layer as a mask, and the first protective layer and the second protective layer remaining in the trench serve together as the protective layer.

10. The method for forming a pad structure according to claim 7, characterized in that: The groove runs through the pad body, and the protection layer is used to cover the chip surface located at the bottom of the groove; On the upper surface, there is a gap between the edge of the groove and the edge of the pad body to achieve electrical connection between the test area and the welding area on the upper surface.

11. The method for forming a pad structure according to claim 7, characterized in that: The depth of the groove is smaller than the thickness of the pad body, and the protection layer covers the surface of the pad body at the bottom of the groove.

12. A semiconductor device, characterized in that: include: chip; According to the pad structure as described in any one of claims 1-6, the lower surface of the pad body is electrically connected to the internal circuit of the chip.

13. The semiconductor device according to claim 12, characterized in that The protection layer at least covers the bottom wall of the groove and the chip surface except the surface where the pad structure is formed, and does not cover the upper surface of the pad body.

14. A method for forming a semiconductor device, characterized in that: The steps include: Provide chips; A pad structure is formed on the surface of the chip using the pad structure forming method described in any one of claims 7 to 11, and the lower surface of the pad body is electrically connected to the internal circuit of the chip.

15. The method for forming a semiconductor device according to claim 14, wherein: The protection layer at least covers the bottom wall of the groove and the chip surface except the surface where the pad structure is formed, and does not cover the upper surface of the pad body.

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