DRAM Array Layout and DRAM Memory

Abstract

An embodiment of the present invention provides a DRAM array layout and a DRAM memory. The DRAM array layout includes word line patterns arranged in parallel and extending along a first direction, bit line patterns arranged in parallel and extending along a second direction, where the first direction and the second direction are not parallel; a first memory cell contact pad pattern and a second memory cell contact pad pattern, the first memory cell contact pad pattern and the second memory cell contact pad pattern are respectively located on both sides of the bit line pattern, and the first memory cell contact pad pattern and the second memory cell contact pad pattern respectively have partial overlapping regions with the word line pattern; active region patterns arranged in parallel and extending along a third direction, and both ends of the active region pattern respectively have partial overlapping regions with the first memory cell contact pad pattern and the second memory cell contact pad pattern. The DRAM array layout design provided by the present invention has a larger word line pitch under the same memory cell area and can be better applied to the next-generation memory manufacturing technology.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductors, and in particular to a DRAM array layout and a DRAM memory. Background Art

[0002] In existing Dynamic Random Access Memory (DRAM), a large number of memory cells are included. One memory cell is composed of a capacitor contacting a transistor and is used to store one byte of information. Compared with the DRAM layout design with a memory cell area of 8F 2 the 6F 2 design is widely adopted in the industry due to its higher transistor density. Among them, the 3×2 layout design has advantages such as better word line reduction and higher array edge utilization compared with the 2×3 layout design, and has become the mainstream design in the industry currently.

[0003] However, in the current 6F 2 array design, the word line pitch is smaller than the bit line pitch, and the word line pitch is small. Therefore, in the next-generation semiconductor manufacturing technology, the word line bears a higher driving voltage and a more complex structure, and reaches the bottleneck of the semiconductor manufacturing process first. Summary of the Invention

[0004] The technical problem solved by the embodiments of the present invention is to provide a DRAM array layout to solve the problem that in the existing 6F 2 design, the requirements of the next-generation manufacturing technology of the DRAM memory cannot be met.

[0005] To solve the above problem, embodiments of the present invention provide a DRAM array layout, including: word line patterns arranged in parallel and extending along a first direction; bit line patterns arranged in parallel and extending along a second direction, the first direction and the second direction not being parallel; a first memory cell contact pad pattern and a second memory cell contact pad pattern, the first memory cell contact pad pattern and the second memory cell contact pad pattern being respectively located on both sides of the bit line pattern, the first memory cell contact pad pattern and the second memory cell contact pad pattern respectively having partial overlapping regions with the word line patterns; active region patterns arranged in parallel and extending along a third direction, both ends of the active region patterns respectively having partial overlapping regions with the first memory cell contact pad pattern and the second memory cell contact pad pattern.

[0006] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages: The storage unit contact pad pattern and the word line pattern have an overlapping area, and the distance between the storage unit contact pads is increased, thus avoiding short circuits between the storage units; moreover, under the same storage unit area, due to the overlapping area arrangement of the storage unit contact pad pattern and the word line pattern, the word line pitch is greater than the bit line pitch. Therefore, the adjacent word line pitch becomes larger, and the reducibility of the word line pitch is better, so as to meet the requirements of the next-generation memory manufacturing technology and achieve a higher storage unit stacking density.

[0007] In addition, the line connecting the center of the first storage unit contact pad pattern and the center of the adjacent second storage unit contact pad pattern forms an angle θ less than or equal to 90 degrees with the second direction, and the angle β between the third direction and the second direction is tan -1 (sinθ / 3) degrees. In this way, the spatial layout of the DRAM array can be optimized, a compact structure design can be achieved, the space inside the DRAM can be better utilized, and thus a higher storage unit stacking density can be achieved.

[0008] In addition, the angle θ is 58 degrees to 62 degrees, and the angle β is 15.78 degrees to 16.4 degrees; preferably, the angle θ is 60 degrees and the angle β is 16.1 degrees. Under this DRAM array design, the DRAM array has a compact layout structure, can better utilize the array space, achieve a higher storage unit stacking density, and compared with the existing DRAM compact structure design, the word line pitch is increased by ~15.4% and has better reducibility.

[0009] In addition, the ratio between the distance between adjacent bit line patterns and the distance between adjacent word line patterns is 0.85 to 0.88; preferably, the ratio is In this way, the array space can be fully utilized, a more compact structure design can be achieved, and thus the stacking density of the storage units can be improved.

[0010] The embodiment of the present invention provides a DRAM memory, including: a semiconductor substrate having a first plane and a second plane parallel to each other; word lines arranged in parallel on the first plane and extending along a first direction; bit lines arranged in parallel on the second plane and extending along a second direction, the first direction and the second direction not being parallel; first storage unit contact pads and second storage unit contact pads located on the semiconductor substrate, the orthographic projections of the first storage unit contact pads and the second storage unit contact pads being respectively on both sides of the orthographic projection of the bit line, and the orthographic projections of the first storage unit contact pads and the second storage unit contact pads respectively having partial overlapping areas with the orthographic projection of the word line; active regions arranged in parallel on the semiconductor substrate and extending along a third direction, the orthographic projections of the active regions respectively having partial overlapping areas with the orthographic projections of the first storage unit contact pads and the second storage unit contact pads.

[0011] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages: at the same storage cell stacking density, the DRAM memory has a larger storage cell contact pad pitch, avoiding short circuits between storage cells, and at the same storage cell area, the word line pitch is larger, having better scalability and meeting the requirements of the next-generation memory manufacturing technology.

[0012] In addition, dielectric layers are provided on both sides of the bit line, and the material of the dielectric layer is a low dielectric constant material. The dielectric layer with a low dielectric constant is used as the isolation structure of the bit line to avoid the parasitic capacitance between bit lines caused by the reduction of the bit line pitch. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] One or more embodiments are illustrated by way of example in the accompanying drawings, which illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the drawings in the figures do not constitute a scale limitation.

[0014] Figure 1 and Figure 2 is a schematic diagram of a DRAM array layout provided by an embodiment of the present invention;

[0015] Figure 3 and Figure 4 is a schematic diagram of the structure of a DRAM memory provided by another embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] As can be seen from the background art, the DRAM memory arrays in the prior art generally adopt a storage cell design of 6F 2 In the existing mainstream layout design, the storage cell contact pad pattern is offset along the word line extension direction and has an overlapping area with the bit line. The pitch between storage cells is equal to the pitch between adjacent bit lines. In a DRAM design, the included angle between the active region extension direction and the bit line extension direction is 21.05 degrees, and the ratio of the word line pitch to the bit line pitch is Under this design, the pitch between adjacent word lines is smaller than the pitch between adjacent bit lines. Since the word line bears a higher driving voltage, it first reaches the process bottleneck in the next-generation manufacturing technology with a higher storage cell stacking density.

[0017] To solve the above problems, an embodiment of the present invention provides a DRAM array layout, including: word line patterns arranged in parallel and extending in a first direction; bit line patterns arranged in parallel and extending in a second direction, where the first direction and the second direction are not parallel; a first memory cell contact pad pattern and a second memory cell contact pad pattern, with the first memory cell contact pad pattern and the second memory cell contact pad pattern located on both sides of the bit line pattern respectively, and the first memory cell contact pad pattern and the second memory cell contact pad pattern each having a partial overlapping area with the word line pattern; active region patterns arranged in parallel and extending in a third direction, with both ends of the active region pattern having a partial overlapping area with the first memory cell contact pad pattern and the second memory cell contact pad pattern respectively.

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will elaborate on each embodiment of the present invention in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in each embodiment of the present invention, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0019] Figure 1 and Figure 2 is a schematic diagram of a DRAM array layout provided by an embodiment of the present invention. Figure 2 is Figure 1 a schematic diagram of the repeating unit in

[0020] Referring to Figure 1 , the DRAM array layout includes word lines 101 arranged in parallel, with the word lines 101 extending in the first direction a, and also includes bit lines 102 arranged in parallel, with the bit lines 102 extending in the second direction b, where the a direction and the b direction are not parallel.

[0021] The word line pattern is used to define the position of the word line in the DRAM memory on the semiconductor substrate (not labeled), and the bit line pattern is used to define the position of the bit line in the DRAM memory on the semiconductor substrate. The extending directions of the word line pattern and the bit line pattern are not parallel. As Figure 1 shown in , the extending directions of the word line pattern 101 and the bit line pattern 102 are perpendicular. In other embodiments, the extending direction of the word line pattern 101 and the extending direction of the bit line pattern 102 can also be an angle with a certain degree.

[0022] Continuing to refer to Figure 1, further comprising a first memory cell contact pad pattern 103 and a second memory cell contact pad pattern 104. The first memory cell contact pad pattern 103 and the second memory cell contact pad pattern 104 are respectively located on both sides of the bit line pattern 102, and the first memory cell contact pad pattern 103 and the second memory cell contact pad pattern 104 respectively have partial overlapping regions with the word line pattern 101.

[0023] The memory cell contact pad pattern is used to define the positions of the contact pads of the capacitor and the active region in the memory cell. The memory cell contact pad pattern includes a first memory cell contact pad pattern 103 and a second memory cell contact pad pattern 104. Refer to Figure 2 , the first memory cell plug pattern 103 and the second memory cell plug pattern 104 are respectively located on both sides of the bit line pattern 102, and the first memory cell plug pattern 103 and the second memory cell plug pattern 104 respectively have partial overlapping regions with the word line pattern 101. The situation where the memory cell contact pad pattern and the word line pattern have an overlapping region is not limited to Figure 1 or Figure 2 as shown in

[0024] Continue to refer to Figure 1 and Figure 2 , further comprising an active region pattern 106 arranged in parallel and extending along a third direction. The active region pattern 106 extends along the c direction, and both ends respectively have partial overlapping regions with the first memory cell contact pad pattern 103 and the second memory cell contact pad pattern 104.

[0025] The DRAM array layout is a repetition of the minimum repeating unit, so Figure 1 only the patterns in the minimum repeating unit are identified in Figure 1 . Those skilled in the art can understand that

[0026] It should be noted that a memory cell contact hole pattern 105 is further included between the active region pattern 106 and the memory cell contact pad pattern. The memory cell contact hole pattern 105 is used to define the contact position between the active region 106 and the capacitor.

[0027] In addition, in order to optimize the spatial layout of the DRAM array, achieve a compact structural design, and stack memory cells with higher density, the included angle θ formed by the line connecting the centers of the first memory cell contact pad pattern and the second memory cell contact plug and the extension direction of the bit line is less than or equal to 90 degrees, and the included angle β between the third direction and the second direction is tan -1 (sinθ / 3) degrees.

[0028] Refer to Figure 2, in the minimum repeating unit of the DRAM array layout, the angle θ between the line connecting the centers of the first memory cell contact pad pattern 103 and the second memory cell contact pad pattern 104 and the extending direction of the bit line pattern 102 is less than or equal to 90 degrees. It can be understood that the line connecting the centers of the first memory cell contact pad patterns between adjacent bit line patterns 102 is parallel to the extending direction of the bit line pattern 102. Therefore, the angle θ is equal to the angle less than or equal to 90 degrees formed by the line connecting the centers of the first memory cell contact pad pattern and the second memory cell contact pad pattern and the line connecting the centers of two adjacent first memory cell plug patterns.

[0029] The active region 106 extends in the third direction c direction, and the angle β between the c direction and the extending direction b direction of the bit line 102 is less than or equal to 90 degrees. In forming a compact layout structure, the geometric relationship between the angle β and the angle θ is satisfied: β is equal to tan -1 (sinθ / 3) degrees.

[0030] It should be noted that, in order to optimize the spatial layout within the DRAM array, improve the utilization rate of the array space, and achieve high-density stacking of memory cells under a reasonable structural design, in a compact structure design provided in this embodiment, the angle θ is 58 - 62 degrees, and the angle β is 15.78 - 16.4 degrees. For example, the angle θ is 60 degrees and the angle β is 16.1 degrees.

[0031] Reference Figure 2 , the angle θ between the line connecting the centers of the first memory cell contact pad pattern 103 and the second memory cell contact pad pattern 104 and the extending direction of the bit line pattern 102 is 60 degrees. At this time, the lines connecting the centers of three adjacent memory cell contact pad patterns form an equilateral triangle. The angle β less than or equal to 90 degrees between the extending direction c direction of the active region pattern 106 and the extending direction b direction of the bit line 102 is 16.1 degrees, and the geometric relationship between the angle θ and the angle β is satisfied: tanβ = sinθ / 3.

[0032] Compared with the existing DRAM array design where the angle between the extending direction of the active region pattern and the extending direction of the bit line pattern is 21.05 degrees, in the DRAM array design with the angle β of 16.1 degrees provided in the embodiment of the present invention under the same memory cell area, the word line pitch is increased by 15.4%, so it has better reduction.

[0033] It should be noted that, in order to make full use of the space on the semiconductor substrate and thus improve the stacking density of memory cells, in a compact layout design provided in the present invention, the ratio between the pitch of adjacent bit line patterns and the pitch of adjacent word line patterns is 0.85 - 0.88. For example, the ratio is

[0034] Reference Figure 2, the ratio of the pitch X between adjacent bit line patterns 102 and the pitch Y between adjacent word line patterns 101 is 0.85 to 0.88. For example, the ratio is

[0035] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages: The storage unit contact pad pattern and the word line have an overlapping area, forming a layout structure in which the storage unit contact pads are offset along the bit line direction, so that the pitch between the storage unit contact pad patterns is larger under the same storage unit area, thereby avoiding short circuits between storage units. At the same time, compared with the existing DRAM array design, in the DRAM array layout design provided by the embodiment of the present invention, the word line pitch is larger, which can better adapt to the next-generation memory manufacturing technology with a higher storage unit stacking density.

[0036] Correspondingly, another embodiment of the present invention provides a DRAM memory, including: a semiconductor substrate having a first plane and a second plane parallel to each other; word lines arranged in parallel on the first plane and extending along a first direction; bit lines arranged in parallel on the second plane and extending along a second direction, the first direction and the second direction not being parallel; a first storage unit contact pad and a second storage unit contact pad on the semiconductor substrate, the orthographic projections of the first storage unit contact pad and the second storage unit contact pad are respectively on both sides of the orthographic projection of the bit line, and the orthographic projections of the first storage unit contact pad and the second storage unit contact pad respectively have a partial overlapping area with the orthographic projection of the word line; active regions arranged in parallel on the semiconductor substrate and extending along a third direction, the orthographic projections of the active regions respectively have a partial overlapping area with the orthographic projections of the first storage unit contact pad and the second storage unit contact pad.

[0037] Reference Figure 3 , the DRAM memory includes a semiconductor substrate ( Figure 3 not labeled in the figure), the semiconductor substrate has a first plane and a second plane parallel to each other, and on the first plane there are word lines 201 arranged in parallel, and the word lines 201 extend along the first direction a. Bit lines 202 arranged in parallel on the second plane, and the bit lines 202 extend along the second direction b. The first direction and the second direction are not parallel, that is, the a direction and the b direction have an included angle. As Figure 3 shown in the figure, the a direction and the b direction are perpendicular to each other, but are not limited to being perpendicular.

[0038] Continue to refer to Figure 3, the DRAM memory further includes a first memory cell contact pad 203 and a second memory cell contact pad 204 located on a semiconductor substrate. In the orthographic projection of the DRAM memory, the first memory cell contact pad 203 and the second memory cell contact pad 204 are located on both sides of the bit line 202, and the first memory cell contact pad 203 and the second memory cell contact pad 204 respectively have overlapping regions with the word line 201.

[0039] Continuing to refer to Figure 3 , the DRAM memory further includes active regions 206 arranged in parallel and extending along the third direction c on the semiconductor substrate. The orthographic projections of the active regions 206 respectively have partial overlapping regions with the orthographic projections of the first memory cell contact pad 203 and the second memory cell contact pad 204.

[0040] It can be understood that since the DRAM array is a repetition of the minimum repeating unit, the final DRAM array structure can be obtained by simple replication transformation of the minimum repeating unit. Since the DRAM memory provided in this embodiment is manufactured through the DRAM array layout provided in an embodiment of the present invention, for the convenience of describing the structure, therefore, in the orthographic projection of the DRAM memory, reference can be made to Figure 2 .

[0041] Refer to Figure 2 , in a minimum repeating unit, the orthographic projection patterns of the first memory cell contact pad 203 and the second memory cell contact pad 204 are respectively located on both sides of the orthographic projection pattern of the bit line, and respectively have partial overlapping regions with the orthographic projection pattern of the word line 201. The size of the overlapping region is not limited to that shown in Figure 2 .

[0042] Refer to Figure 2 , at both ends of the orthographic projection pattern of the active region 206, there are overlapping regions with the orthographic projection patterns of the first memory cell contact pad 203 and the second memory cell contact pad 204 which are located on both sides of the bit line 202 and on different word lines respectively. It can be understood that when the area of the memory cell is different, the length of the active region is different. Therefore, the positions of the first memory cell contact pad and the second memory cell contact pad connected by the active region in the orthographic projection can change accordingly, and the extension direction of the active region also changes.

[0043] The size of the orthographic projection pattern of the active region 206 is related to the memory cell area of the DRAM memory. The memory cell area of the DRAM memory provided in this embodiment is 6F 2 , but not limited to 6F 2 .

[0044] It can be understood that a memory cell contact hole 205 is further included between the active region and the memory cell contact pad for connecting the active region and the memory cell contact pad.

[0045] In addition, in order to optimize the spatial layout of the DRAM array, achieve a compact structural design, and stack storage cells with higher density under the same area, in the orthographic projection of the DRAM memory, the orthographic projection patterns of the storage cell contact pads and the orthographic projection patterns of the active regions satisfy a certain geometric relationship in terms of positional relationship. The line connecting the center of the orthographic projection of the first storage cell contact pad and the center of the orthographic projection of the adjacent second storage cell contact pad forms an angle θ less than or equal to 90 degrees with the second direction, and the angle β between the third direction and the second direction is tan -1 (sinθ / 3) degrees.

[0046] Refer to Figure 2 , the line connecting the centers of the orthographic projection patterns of the first storage cell contact pad 203 and the second storage cell contact pad 204, which are located on both sides of the orthographic projection pattern of the bit line 202 and on the same word line 201, and the extension direction b of the bit line 202 have an angle θ. Since the line connecting the centers of the orthographic projection patterns of the storage cell contact pads between the orthographic projection patterns of adjacent bit lines 202 is parallel to the extension direction b of the bit line 202, therefore, Figure 2 the angle θ in

[0047] Continue to refer to Figure 2 , the angle β less than or equal to 90 degrees formed by the extension direction of the orthographic projection pattern of the active region 206 and the extension direction of the bit line 202, and the relationship between the angle β and the angle θ satisfies tan -1 (sinθ / 3).

[0048] It should be noted that, in order to optimize the spatial layout within the DRAM array, improve the utilization rate of the array space, and achieve high-density stacking of storage cells under a reasonable structural design, in a DRAM memory provided by an embodiment of the present invention, the angle θ is 58 to 62 degrees, and the angle β is 15.78 to 16.4 degrees. For example, the angle θ is 60 degrees and the angle β is 16.1 degrees.

[0049] Compared with the design in the existing DRAM memory where the angle between the extension direction of the active region and the extension direction of the bit line is 21.05 degrees, in a DRAM memory provided by an embodiment of the present invention under the same storage cell area, with the angle β being 16.1 degrees, the word line pitch is increased by 15.4%, and thus it has better shrinkability.

[0050] In addition, in order to make full use of the space on the semiconductor substrate and increase the stacking density of memory cells, the ratio between the pitch of adjacent bit lines and the pitch of adjacent word lines is 0.85 to 0.88. For example, the ratio is

[0051] Reference Figure 2 , in the orthographic projection direction, the ratio between the pitch X of adjacent bit lines 202 and the pitch Y of adjacent word lines 201 is 0.85 to 0.88. For example, the ratio is

[0052] In the DRAM memory provided by the present invention, the bit line pitch is smaller. Therefore, in order to reduce unnecessary parasitic capacitance generated between bit lines, dielectric layers are provided on both sides of the bit lines, and the material of the dielectric layers is a low dielectric constant material.

[0053] Reference Figure 4 , Figure 4 For the cross-sectional structure diagram along the Figure 3 AA1 direction in

[0054] The DRAM memory provided in this embodiment has a larger memory cell contact pad pitch under the same memory cell stacking density, avoiding short circuits between memory cells. And under the same memory cell area, the word line pitch is larger, having better scalability and can meet the requirements of next-generation memory manufacturing technology.

[0055] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A DRAM array layout, characterized in that, it includes: Word line patterns arranged in parallel and extending along a first direction; Bit line patterns arranged in parallel and extending along a second direction, where the first direction and the second direction are not parallel; A first memory cell contact pad pattern and a second memory cell contact pad pattern located above the memory cell contact holes, the first memory cell contact pad pattern and the second memory cell contact pad pattern are respectively located on both sides of the bit line pattern and do not overlap with the orthographic projection of the bit line pattern on the semiconductor substrate plane, and the first memory cell contact pad pattern and the second memory cell contact pad pattern respectively have partial overlapping regions with the word line pattern; Active region patterns arranged in parallel and extending along a third direction, and both ends of the active region pattern respectively have partial overlapping regions with the first memory cell contact pad pattern and the second memory cell contact pad pattern.

2. The DRAM array layout according to claim 1, characterized in that, The included angle θ between the line connecting the center of the first memory cell contact pad pattern and the center of the adjacent second memory cell contact pad pattern and the second direction is less than or equal to 90 degrees, and the included angle β between the third direction and the second direction is tan -1 (sinθ / 3) degrees.

3. The DRAM array layout according to claim 2, characterized in that, The included angle θ is 58 degrees to 62 degrees, and the included angle β is 15.78 degrees to 16.4 degrees.

4. The DRAM array layout according to claim 3, characterized in that, The included angle θ is 60 degrees, and the included angle β is 16.1 degrees.

5. The DRAM array layout according to claim 1, characterized in that, The ratio between the pitch of adjacent bit line patterns and the pitch of adjacent word line patterns is 0.85 to 0.

88.

6. The DRAM array layout according to claim 5, characterized in that, The ratio between the pitch of adjacent bit line patterns and the pitch of adjacent word line patterns is 7. A DRAM memory, characterized in that, it includes: A semiconductor substrate having a first plane and a second plane that are parallel to each other; Word lines arranged in parallel and extending along a first direction on the first plane; Bit lines arranged in parallel and extending along a second direction on the second plane, where the first direction and the second direction are not parallel; A first memory cell contact pad and a second memory cell contact pad located above the memory cell contact holes on the semiconductor substrate, the orthographic projections of the first memory cell contact pad and the second memory cell contact pad are respectively located on both sides of the orthographic projection of the bit line and do not overlap with the orthographic projection of the bit line, and the orthographic projections of the first memory cell contact pad and the second memory cell contact pad respectively have partial overlapping regions with the orthographic projection of the word line, and the orthographic projection is the orthographic projection on the first plane or the second plane of the semiconductor substrate; Active regions arranged in parallel and extending along a third direction on the semiconductor substrate, and the orthographic projections of the active regions respectively have partial overlapping regions with the orthographic projections of the first memory cell contact pad and the second memory cell contact pad.

8. The DRAM memory according to claim 7, characterized in that, The line connecting the center of the orthographic projection of the first memory cell contact pad and the center of the orthographic projection of the adjacent second memory cell contact pad forms an angle θ less than or equal to 90 degrees with the second direction, and the angle β between the third direction and the second direction is tan -1 (sinθ / 3) degrees.

9. The DRAM memory according to claim 8, characterized in that, The included angle θ is 58 degrees to 62 degrees, and the included angle β is 15.78 degrees to 16.4 degrees.

10. The DRAM memory according to claim 9, characterized in that, The included angle θ is 60 degrees, and the included angle β is 16.1 degrees.

11. The DRAM memory according to claim 7, wherein, the ratio between the pitch of adjacent bit lines and the pitch of adjacent word lines is 0.85 to 0.

88.

12. The DRAM memory according to claim 11, wherein, The ratio between the pitch of adjacent bit lines and the pitch of adjacent word lines is 13. The DRAM memory according to claim 7, wherein, dielectric layers are provided on both sides of the bit line, and the material of the dielectric layer is a low dielectric constant material.

14. The DRAM memory according to claim 7, wherein, It further includes a storage unit, and the area of the storage unit is 6F 2 .

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