Semiconductor structure and method for forming the same

Abstract

A semiconductor structure comprises: a transistor, comprising a first source / drain region; a source / drain contact plug, located above the first source / drain region and electrically connected to the first source / drain region; and a through hole, located above the source / drain contact plug and contacting the source / drain contact plug. The through hole comprises: a bottom portion, having a first length; and an upper portion, having a second length. The first length is greater than the second length. The first length and the second length are measured along the same direction parallel to the top surface of the source / drain contact plug. Another aspect of an embodiment of the present application provides a method for forming a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductors, and in particular, to semiconductor structures and methods for forming the same. Background Art

[0002] As the size of integrated circuits continues to decrease, new challenges emerge. For example, the contact resistance between conductive components begins to dominate the resistance of the integrated circuit. An example is the contact resistance between the source / drain contact plug and the corresponding via above, which can be high due to the small contact area between the source / drain contact plug and the via. High contact resistance values ​​significantly affect the drive current of the transistor. Summary of the invention

[0003] An embodiment of the present application provides a semiconductor structure, comprising: a transistor, comprising a first source / drain region; a source / drain contact plug, located above the first source / drain region and electrically connected to the first source / drain region; and a through-hole, located above the source / drain contact plug and in contact with the source / drain contact plug, the through-hole comprising: a bottom portion, having a first length; and an upper portion, having a second length, wherein the first length is greater than the second length, and the first length and the second length are measured along a first direction parallel to a top surface of the source / drain contact plug.

[0004] An embodiment of the present application provides a semiconductor structure, comprising: a first conductive component, wherein, in a plan view, the first conductive component has a first length along a first direction, and a first width along a second direction perpendicular to the first direction, and the first width is smaller than the first length; and a conductive via, located above the first conductive component and in contact with the first conductive component, wherein the conductive via comprises: a bottom, wherein the bottom is elongated and has a second length measured along the first direction, and a second width measured along the second direction, and the second width is smaller than the second length; and an upper portion, located above the bottom and connected to the bottom, wherein the upper portion has a third length measured along the first direction, and a third width measured along the second direction, and the third length is substantially equal to the third width.

[0005] An embodiment of the present application provides a method for forming a semiconductor structure, comprising: depositing a first dielectric layer over a first conductive component; depositing a second dielectric layer over the first dielectric layer; performing a first etching process to etch through the first dielectric layer and the second dielectric layer and form an opening, wherein the opening comprises: a bottom portion located in the first dielectric layer; and an upper portion located in the second dielectric layer; performing a second etching process to extend the bottom portion beyond an edge of the upper portion; and filling a conductive material into the opening to form a second conductive component.

[0006] Embodiments of the present application provide a contact interface design for reducing contact resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1-Figure 6 , Fig. 7A , Figure 7B ,as well as Figure 8-Figure 11 shows perspective and cross-sectional views of intermediate stages in the formation of a fin field effect transistor (FinFET) and corresponding source / drain contact plugs according to some embodiments;

[0009] Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig. 20A ,as well as Fig. 20B perspective and cross-sectional views showing intermediate stages in the formation of a through hole according to some embodiments;

[0010] Fig.19 shows a plan view of a through hole according to some embodiments;

[0011] Fig.21A , Fig. 21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A , Fig. 24B , Fig.25A ,as well as Fig.25B shows a cross-sectional view of an intermediate stage in the formation of a through-hole according to some embodiments;

[0012] Fig.26 shows a plan view of a through hole according to some embodiments;

[0013] Fig.27A , Fig.27B , Fig.28A , Fig.28B , Fig.29A , Fig.29B , Fig. 30A ,as well as Fig. 30B shows a cross-sectional view of an intermediate stage in the formation of a through-hole according to some embodiments;

[0014] Fig.31 and Fig.32 shows a plan view of a through hole according to some embodiments;

[0015] Fig.33 , Fig.34 ,as well as Fig.35 shows a perspective view of a via and underlying source / drain contact plugs according to some embodiments;

[0016] Fig.36 and Fig.37 illustrates various layers of a transistor according to some embodiments;

[0017] Fig.38 A process flow for forming FinFETs and vias is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or structures discussed.

[0019] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0020] According to various embodiments, a transistor including a source / drain contact plug, a through hole thereon, and a method for forming the same are provided. According to some embodiments, an intermediate stage of forming a transistor and a through hole is shown. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, similar reference numerals are used to indicate similar elements. In the illustrated embodiment, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concept of the present invention. Other types of transistors such as nanowire transistors, nanosheet transistors, planar transistors, etc. may also employ the concept of the present invention. Although method embodiments may be discussed as being implemented in a particular order, other method embodiments may be implemented in any logical order. According to some embodiments of the present invention, a through hole is formed above the source / drain contact plug of the transistor and contacts the source / drain contact plug of the transistor. The bottom of the through hole is laterally expanded to increase the contact area between the through hole and the source / drain contact plug, thereby reducing the contact resistance. The top of the through hole may also be laterally expanded to increase the contact area between the through hole and the conductive component (e.g., metal line) thereon to reduce the corresponding contact resistance.

[0021] Figure 1-Figure 6 , Fig. 7A , Figure 7B , Figure 8-Figure 13 , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig. 20A ,as well as Fig. 20B 3D and cross-sectional views of intermediate stages in the formation of FinFETs and corresponding vias according to some embodiments of the present invention are shown. The processes shown in these figures are also schematically reflected in FIG. Fig.38 In the process flow 400 shown.

[0022] exist Figure 1In the embodiment, a substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a P-type or N-type dopant) or undoped. The substrate 20 may be a portion of a wafer 10 (e.g., a silicon wafer). Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 includes: silicon; germanium; compound semiconductors, including silicon carbide, SiPC, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0023] Further references Figure 1 , a well region 22 is formed in the substrate 20. Fig.38 In the process flow 400 shown, the corresponding process is shown as process 402. According to some embodiments of the present invention, the well region 22 is a p-type well region formed by injecting p-type impurities such as boron, indium, etc. into the substrate 20. According to other embodiments of the present invention, the well region 22 is an n-type well region formed by injecting n-type impurities such as phosphorus, arsenic, antimony, etc. into the substrate 20. The resulting well region 22 may extend to the top surface of the substrate 20. The n-type or p-type impurity concentration may be equal to or less than 10 18 cm -3 , for example, at about 10 17 cm -3 and about 10 18 cm -3 in the range between.

[0024] refer to Figure 2 , forming an isolation region 24 that extends from the top surface of the substrate 20 into the substrate 20. Hereinafter, the isolation region 24 may alternatively be referred to as a shallow trench isolation (STI) region. Fig.38In the process flow 400 shown, the corresponding process is shown as process 404. The portion of the substrate 20 located between adjacent STI regions 24 is called a semiconductor strip 26. In order to form the STI region 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, and then the pad oxide layer 28 and the hard mask layer 30 are patterned. The pad oxide layer 28 can be a thin film formed by silicon oxidation. According to some embodiments of the present invention, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 acts as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 can also act as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the present invention, the hard mask layer 30 is formed by silicon nitride, for example, using low pressure chemical vapor deposition (LPCVD). According to other embodiments of the present invention, the hard mask layer 30 is formed by thermal nitridation of silicon or plasma enhanced chemical vapor deposition (PECVD). A photoresist (not shown) is formed on the hard mask layer 30 and then patterned. Then, the hard mask layer 30 is patterned using the patterned photoresist as an etching mask to form a Figure 2 A hard mask 30 is shown.

[0025] Next, the patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, and then the resulting trenches in the substrate 20 are filled with (some) dielectric material. A planarization process such as a chemical mechanical polishing (CMP) process or a mechanical grinding process is performed to remove excess portions of the dielectric material, and the remaining portions of (some) dielectric material become the STI region 24. The STI region 24 may include a pad dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The pad dielectric may also be a deposited silicon oxide layer, a silicon nitride layer, etc. formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 24 may also include a dielectric material above the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material above the pad dielectric may include silicon oxide.

[0026] The top surface of hard mask 30 and the top surface of STI region 24 may be substantially flush with each other. Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments of the present invention, semiconductor strips 26 are a portion of the original substrate 20, and thus the material of semiconductor strips 26 is the same as the material of substrate 20. According to an alternative embodiment of the present invention, semiconductor strips 26 are replacement strips formed by etching a portion of substrate 20 between STI regions 24 to form a groove, and performing epitaxy to grow another semiconductor material in the groove. Therefore, semiconductor strips 26 are formed by a semiconductor material different from the semiconductor material of substrate 20. According to some embodiments, semiconductor strips 26 are formed by silicon germanium, silicon carbon, or III-V compound semiconductor materials.

[0027] refer to Figure 3 , the STI region 24 is recessed, so that the top of the semiconductor strip 26 protrudes higher than the top surface 24A of the remaining portion of the STI region 24 to form a protruding fin 36. Fig.38 In the illustrated process flow 400, the corresponding process is shown as process 406. Etching can be performed using a dry etching process, wherein, for example, HF3 and NH3 are used as etching gases. During the etching process, plasma may be generated. Argon gas may also be included. According to an alternative embodiment of the present invention, a wet etching process is used to implement the recessing of the STI region 24. The etching chemical may include, for example, HF.

[0028] The protruding fin 36 may be formed by other semiconductor materials or replaced by other semiconductor materials. For example, for an NMOS transistor, the protruding fin 36 may be formed by Si, SiP, SiC, SiPC, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.), or may include Si, SiP, SiC, SiPC, or a III-V compound semiconductor (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc.). For a PMOS transistor, the protruding fin 36 may be formed by Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InSb, GaSb, InGaSb, etc.), or may include Si, SiGe, SiGeB, Ge, or a III-V compound semiconductor (e.g., InSb, GaSb, InGaSb, etc.).

[0029] In the above embodiments, the fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multi-patterning processes. Typically, double patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with smaller pitches, for example, than can be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may then be used to pattern the fins.

[0030] refer to Figure 4 , forming a dummy gate stack 38 that extends over the top surface and sidewalls of the (protruding) fin 36. Fig.38 In the process flow 400 shown, the corresponding process is shown as process 408. The dummy gate stack 38 may include a dummy gate dielectric 40 and a dummy gate electrode 42 located above the dummy gate dielectric 40. The dummy gate electrode 42 may be formed, for example, using polysilicon, or other materials may be used. Each dummy gate stack 38 may also include a layer (or multiple layers) of hard mask layer 44 located above the dummy gate electrode 42. The hard mask layer 44 may be formed by silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 may span a single or multiple protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a length direction perpendicular to the length direction of the protruding fins 36.

[0031] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. Fig.38 In the process flow 400, the corresponding process is also shown as process 408. According to some embodiments of the present invention, the gate spacer 46 is formed by dielectric materials such as silicon nitride, silicon carbonitride, etc., and can have a single layer structure or a multi-layer structure including multiple dielectric layers.

[0032] Then, an etching process is performed to etch the portion of the protruding fin 36 that is not covered by the dummy gate stack 38 and the gate spacer 46, thereby obtaining Figure 5 The structure shown. Fig.38 In the illustrated process flow 400, the corresponding process is shown as process 410. The recess may be anisotropic so that the portion of the fin 36 directly below the dummy gate stack 38 and the gate spacer 46 is protected from being etched. According to some embodiments, the top surface of the recessed semiconductor strip 26 may be lower than the top surface 24A of the STI region 24. Thus, a recess 50 is formed. The recess 50 includes portions on opposite sides of the dummy gate stack 38 and portions between the remaining portions of the protruding fin 36.

[0033] Next, epitaxial regions (source / drain regions) 54 are formed by selectively growing semiconductor material in the recesses 50 (by epitaxy). Figure 6 The structure of Fig.38 In the process flow 400 shown, the corresponding process is shown as process 412. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, as the epitaxy proceeds, p-type impurities or n-type impurities can be in-situ doped. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP) or silicon carbon phosphorus (SiCP) can be grown. According to an alternative embodiment of the present invention, the epitaxial region 54 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, a combination thereof, or a multilayer thereof. After the recess 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to expand horizontally, and facets can be formed. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. A void (air gap) 56 may be generated. According to some embodiments of the present invention, the formation of the epitaxial region 54 may be completed when the top surface of the epitaxial region 54 is still wavy, or when the top surface of the fused epitaxial region 54 has become flat, which is achieved by Figure 6 This is achieved by further growth on the epitaxial region 54 as shown.

[0034] After the epitaxy step, the epitaxy region 54 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also indicated by reference numeral 54. According to an alternative embodiment of the present invention, when the epitaxy region 54 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation step is skipped.

[0035] Fig. 7A FIG. 4 shows a perspective view of the structure after the formation of a contact etch stop layer (CESL) 58 and an interlayer dielectric (ILD) 60. Fig.38In the process flow 400 shown, the corresponding process is shown as process 414. CESL 58 can be formed by silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, etc., and can be formed using CVD, ALD, etc. ILD 60 may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 60 may be formed by an oxygen-containing dielectric material, which may be a silicon oxide-based material, such as silicon oxide, phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), silicon oxycarbide, high-k dielectric material (e.g., zirconium oxide, hafnium oxide), or low-k dielectric material. A planarization process such as a CMP process or a mechanical grinding process may be performed to make the top surfaces of ILD 60, dummy gate stack 38, and gate spacer 46 flush with each other.

[0036] Figure 7B Shows Fig. 7A 7B-7B in FIG. 7B, which shows a dummy gate stack 38. Next, as shown in FIG. Figure 8 As shown, the dummy gate stack 38 including the hard mask layer 44, the dummy gate electrode 42, and the dummy gate dielectric 40 is etched to form a trench 62 between the gate spacers 46. Fig.38 In the process flow 400 shown in FIG. 4 , the corresponding process is shown as process 416. The top surface and sidewalls of the protruding fin 36 are exposed to the trench 62. Next, as shown in FIG. Fig. 9 As shown, in the groove 62 ( Figure 8 ) to form a replacement gate stack 68. Fig.38 In the illustrated process flow 400 , the corresponding process is shown as process 418 . The replacement gate stack 68 includes a gate dielectric 64 and a corresponding gate electrode 66 .

[0037] According to some embodiments of the present invention, the gate dielectric 64 includes an interfacial layer (IL) as its lower portion. The IL is formed on the exposed surface of the protruding fin 36. The IL may include an oxide layer such as a silicon oxide layer, which is formed by thermal oxidation, chemical oxidation process, or deposition process of the protruding fin 36. The gate dielectric 64 may also include a high-k dielectric layer formed above the IL. The high-k dielectric layer includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0, sometimes up to 21.0 or higher. The high-k dielectric layer is above the IL and may contact the IL. According to some embodiments of the present invention, the high-k dielectric layer is formed using ALD, CVD, PECVD, molecular beam deposition (MBD), etc.

[0038] A gate electrode 66 is formed on the gate dielectric 64. The gate electrode 66 may include: a plurality of stacked layers, which may be formed as a conformal layer; and a filling metal region, which fills the remaining portion of the trench 62 not filled by the plurality of stacked layers. The stacked layers may include a barrier layer, a work function layer above the barrier layer, and one or more metal capping layers above the work function layer. The filling metal region may be formed of tungsten, cobalt, etc. According to an alternative embodiment, the barrier layer may not be formed, the capping layer may completely fill the trench, and no filling metal region may be formed.

[0039] Fig.10 The formation of a self-aligned hard mask 70 is shown in accordance with some embodiments. Fig.38 In the illustrated process flow 400, the corresponding process is shown as process 420. The formation of the hard mask 70 may include performing an etching process to recess the replacement gate stack 68, thereby forming a groove between the gate spacers 46, filling the groove with a dielectric material, and then performing a planarization process such as a CMP process or a mechanical grinding process to remove excess portions of the dielectric material. The hard mask 70 may be formed of silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc.

[0040] Fig.11 The formation of source / drain contact plugs 72 is shown. Fig.38In the process flow 400 shown, the corresponding process is shown as process 422. The formation of the source / drain contact plug 72 includes etching the ILD 60 to expose the portion below the CESL 58, and then etching the exposed portion of the CESL 58 to expose the source / drain region 54. In a subsequent process, a metal layer is deposited and extends into the contact opening. The metal layer can be formed by Ti, Co, Ni, NiCo, Pt, Ni(Pt), Ir, Pt(Ir), Er, Yb, Pd, Rh, etc. or their alloys, or can include Co, Ni, NiCo, Pt, Ni(Pt), Ir, Pt(Ir), Er, Yb, Pd, Rh, etc. or their alloys. A metal nitride capping layer can be formed. An annealing process is then performed to react the metal layer with the top of the source / drain region 54 to form a silicide region 74. Next, either the previously formed metal nitride layer is retained without removal, or the previously formed metal nitride layer is removed, and then a new metal nitride layer (e.g., a titanium nitride layer) is deposited. The metal nitride layer may be referred to as a barrier layer, and is shown as a barrier layer 72A. A filling metal material 72B such as W, Co, Ru, Ir, Ni, Os, Rh, Al, Mo, alloys thereof, etc. is then filled into the contact opening, followed by a planarization process to remove excess material, thereby obtaining a source / drain contact plug 72. The deposition method of the barrier layer 72A and the filling metal material 72B may include CVD, PVD, chemical deposition (ELD), electrochemical plating (ECP), or ALD. Thus, a FinFET 75 is formed, which can be connected in parallel as one FinFET.

[0041] According to some embodiments of the present invention, for example, when the filling metal material 72B includes cobalt, the source / drain contact plug 72 may be slightly recessed, and another metal such as tungsten may be selectively deposited on the recessed source / drain contact plug 72. Fig. 20A ) includes ruthenium, which is incompatible with cobalt, so that tungsten or a similar material is used as a buffer.

[0042] Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig. 20A ,as well as Fig. 20BPerspective and cross-sectional views are shown of intermediate stages in the formation of vias according to some embodiments. The vias are formed over and land on source / drain contact plugs 72 .

[0043] refer to Fig.12 , forming an etch stop layer 76. According to some embodiments of the present invention, the etch stop layer 76 is formed by a dielectric material, which may include silicon nitride, aluminum oxide, etc. The thickness T1 of the etch stop layer 76 may be in the range between about 1 nm and about 5 nm. A dielectric layer 78 is deposited over the etch stop layer 76. Fig.38 In the illustrated process flow 400, the process for forming the etch stop layer 76 and the dielectric layer is shown as process 424. According to some embodiments, the dielectric layer 78 is formed by a low-k dielectric material, which may be a silicon oxide-based dielectric material, which may be formed by silicon oxide, PSG, BSG, BPSG, fluorine-doped silicate glass (FSG), a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc., or may include silicon oxide, PSG, BSG, BPSG, fluorine-doped silicate glass (FSG), a carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. The thickness T2 of the dielectric layer 78 may be in a range between about 10 nm and about 150 nm.

[0044] refer to Fig.13 , a via opening 84 is formed by etching through the dielectric layer 78 and the etch stop layer 76. The via opening 84 includes a lower portion 84A and an upper portion 84B, and the lower portion 84A is wider than the corresponding upper portion 84B. Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A ,as well as Fig. 16B 84 according to some example embodiments. In the following figures, when a reference numeral includes a number followed by the letter "A", the figure represents a through hole opening 84 formed in accordance with some example embodiments. Fig.13 The cross-sectional view obtained from the reference section AA in FIG. 1 is also called an X-cut cross-sectional view because the cut is parallel to Fig.13 When a reference numeral contains a number followed by the letter "B", the figure represents the direction from Fig.13 The cross-sectional view is obtained from the reference cross-sectional view BB in FIG. 1 , which is also called a Y-cut cross-sectional view because the cut is parallel to Fig.13 The X direction and the Y direction are also shown in the figures discussed later.

[0045] Fig.14A and Fig. 14B A first etching process 83 is shown for etching through the dielectric layer 78 and the etch stop layer 76 to form an opening 84. Fig.38 In the process flow 400 shown, the corresponding process is shown as process 426. The first etching process is an anisotropic etching process and can be a dry etching process. An etching mask 82 such as a patterned photoresist is formed to define an opening 84. The first etching process can be implemented using a first etching gas to etch through the dielectric layer 78 and stop on the etching stop layer 76. The etching gas is then changed to etch through the etching stop layer 76. The etching gas is selected according to the materials of the dielectric layer 78 and the etching stop layer 76. For example, a mixed gas of NF3 and NH3, a mixed gas of HF and NH3, etc. can be used to etch the dielectric layer 78. The etching stop layer 76 can be etched using a mixed gas of CF4, O2 and N2, a mixed gas of NF3 and O2, a mixed gas of SF6 and O2, etc. After etching the etching stop layer 76, the polymer generated in the etching process can be removed by implementing a cleaning process. The cleaning process can be implemented using oxygen (O2) or a mixture of H2 and N2, and plasma is generated, and then a wet cleaning process is performed using deionized water. The cleaning process may result in etching of the opening 84 , such that the opening 84 extends slightly downward into the source / drain contact plug 72 .

[0046] After the first etching process, the etching mask 82 may be removed. The opening 84 formed in the first etching process may have straight edges, which may be vertical or substantially vertical, for example, with an inclination angle α ranging between about 88 degrees and 90 degrees.

[0047] Next, if Fig. 15B As shown, a tilted implantation 87 is performed. Fig.38 In the process flow 400 shown, the corresponding process is shown as process 428. Fig. 15BIn the plan view of the structure shown, an inclined implant 87 is implemented with a component parallel to the Y direction (parallel to the source to drain direction). The inclined implant 87 includes a first implant inclined to the +Y direction and a second implant inclined to the -Y direction. The tilt angle β is selected to ensure that the implant is implanted into the sidewall of the etch stop layer 76 and the dielectric layer 78 does not create a barrier. According to some embodiments, the tilt angle β is in a range between about 40 degrees and about 75 degrees. The implanted portions of the dielectric layer 78 and the etch stop layer 76, which now include the implanted elements, are referred to as implanted portions 78' and implanted portions 76', respectively. The implanted elements are selected so that the implanted portions 78' and implanted portions 76' are not etched in the second etching process that is subsequently implemented. According to some embodiments, silicon, germanium, carbon, boron, oxygen, or a combination thereof are implanted, and the specific element is selected based on the material of the etch stop layer 76. For example, when the etch stop layer 76 is formed by or includes silicon nitride, the implanted elements include oxygen, carbon, silicon, boron, phosphorus, or a combination thereof. When the etch stop layer 76 is formed by aluminum oxide, the implanted element includes, for example, nitrogen (using N2 gas). According to some example embodiments, silicon is implanted at an energy of about 0.5 KeV to about 5 KeV, with a dose of about 1E15 / cm 2 to about 5E15 / cm 2 After implantation, the atomic percentage of the implanted element in the implanted portion 78' and the implanted portion 76' may be in the range between about 10% and about 50%.

[0048] The tilted implant 87 has no component parallel to the X direction (in plan view), and there may be no tilted implant parallel to directions other than the X and Y directions. Fig.15A In the cross-sectional view shown, the implant 87 appears vertical. As a result, Fig.15A As shown, no implanted portions are formed on the shown sidewalls of etch stop layer 76 and dielectric layer 78 .

[0049] After injection, Fig.16A and Fig. 16B As shown, a second etching process 85 is performed. Fig.38In the process flow 400 shown, the corresponding process is shown as process 430. The second etching process includes an isotropic component and may or may not include an anisotropic component. When both anisotropic and isotropic components are present, the main effect is isotropic. The second etching process may include a dry etching process or a wet etching process. The etching chemical is selected to etch the unimplanted portion of the etch stop layer 76 without etching the implanted portion 76', the implanted portion 78', and the unimplanted portion of the dielectric layer 78. For example, when the etch stop layer 76 is formed by silicon nitride, and when wet etching is used, the etching chemical may include a phosphoric acid solution (H3PO4:H2O). The temperature of the phosphoric acid solution may be in a range between about 135°C and about 155°C. According to some embodiments, where the etch stop layer 76 is formed by silicon nitride, and when dry etching is used, the etching gas may include a mixture of CF4 and H2, and a plasma is generated. According to some embodiments, where etch stop layer 76 is formed of aluminum oxide, and when wet etching is used, the etching chemistry may include an ammonia solution (NH 4 OH:H 2 O 2 :H 2 O) including ammonia dissolved in hydrogen peroxide and water.

[0050] refer to Fig.16A In the second etching process 85, the non-implanted portion of the etch stop layer 76 is etched, and thus, the lower portion 84A of the opening 84 in the etch stop layer 76 is expanded to be wider than the corresponding upper portion 84B in the dielectric layer 78. Fig. 16B As shown, the expansion is along the X direction, not along the Y direction, because the implanted portion 76' blocks the expansion. According to some embodiments, the length L1' of the upper portion 88B of the through hole can be in the range between about 10nm and about 18nm. The length L1 of the bottom 88A of the through hole can be in the range between about 12nm and about 20nm, or it can be equal to the width of the interface between the conductive through hole 88 and the source / drain contact plug 72. The expansion amount (L1-L1') can be in the range between about 2nm and about 10nm. The expansion ratio (L1-L1') / L1' should not be too large or too small, which reflects the extent to which the bottom 88A expands beyond the upper portion 88B. When the expansion ratio (L1-L1') / L1' is too large, the through hole 88 may also expand along the Y direction, and the through hole 88 may be at risk of electrical short circuit (leakage) with the gate contact plug. When the expansion ratio is too small, the purpose of reducing the contact resistance cannot be achieved. According to some embodiments, the expansion ratio (L1-L1') / L1' is in a range between about 0.2 and about 0.5. Fig. 16B As shown, in the second etching process 85 , the opening 84 does not expand along the Y direction due to the protection of the implanted portion 76 ′ and the implanted portion 78 ′.

[0051] After the second etching process 85 , a pre-cleaning process may be performed, for example, using a process gas such as hydrogen, argon, WF 6 , and / or the like.

[0052] refer to Fig.17A and Fig. 17B , fill the metal material 86 into Fig.16A and Fig. 16B In the opening 84 shown. Fig.38 In the process flow 400 shown, the corresponding process is shown as process 432. According to some embodiments, the metal material 86 includes a metal such as Ru, Co, Ni, Cu, Al, Pt, Mo, W, Al, Ir, Os, or a combination thereof. The metal material 86 is deposited using a bottom-up deposition process, which can be implemented using a thermal chemical vapor deposition (CVD) process. The temperature of the wafer 10 can be in a range between 200° C. and about 400° C. The bottom-up deposition process can be implemented using WF6 and H2 as process gases (when tungsten is to be deposited), or other process gases when other materials are used. Using bottom-up deposition, the opening 84 can be filled without generating an air gap therein. The deposition method can also include CVD, ALD, PVD, ECP, ELD, etc.

[0053] According to some embodiments, the deposition of the metal material 86 may be performed at a temperature range between about 50° C. and about 500° C., with a carrier gas including argon or nitrogen at a flow rate of about 10 sccm to about 500 sccm. According to some embodiments, a reaction gas such as a metal-containing precursor, H2, O2, NH3, etc. may be added at a flow rate of about 10 sccm to about 500 sccm, and a pressure in a range between about 0.00001 Torr and about 10 Torr.

[0054] According to some embodiments, metal material 86 is formed of a homogeneous material and does not include a barrier layer. According to alternative embodiments, metal material 86 is formed of a homogeneous material and a conformal barrier layer (not shown) is formed before depositing metal material 86. The conformal barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0055] Fig.18A and Fig.18B A planarization process is shown for removing excess portions of metal material 86, and thereby forming conductive vias 88. Fig.38 In the illustrated process flow 400, the corresponding process is shown as process 434. The conductive via 88 includes a bottom (extended) portion 88A extending into the etch stop layer 76, and an upper portion 88B located in the dielectric layer 78. Fig.18A In the cross-sectional view shown, the through-hole bottom 88A extends laterally beyond the corresponding upper portion 88A above. Fig.18AIn the cross-sectional view shown, there is no injection portion 76' and injection portion 78'. Fig.18A In the cross-sectional view of FIG. 7 , substantially no implanted portion ( 76 ′ / 78 ′) is formed, for example, the atomic percentage of the implanted element in the sidewall portion of the etch stop layer 76 and the dielectric layer 78 is less than about 5% or about 2%. Fig.18B In the embodiment, the bottom portion 88A of the via does not extend laterally beyond the corresponding upper portion 88B above. The sidewalls of the bottom portion 88A of the via and the sidewalls of the upper portion 88B form a continuous straight sidewall extending from the dielectric layer 78 to the etch stop layer 76. Therefore, Fig.18B The portion of the conductive via 88 shown in FIG. 8 is in contact with the implanted portion 76′ of the etch stop layer 76 and the implanted portion 78′ of the dielectric layer 78, while Fig.18A The portion of conductive via 88 shown in FIG. 8 is in contact with the non-implanted portions of dielectric layer 78 and etch stop layer 76 .

[0056] Fig.19 1 shows a plan (top) view of the conductive via 88 and the underlying source / drain contact plug 72. The figure shows that the bottom portion 88A extends laterally along the +X direction and the -X direction, which are the length directions of the source / drain contact plug 72. Along the +Y direction and the -Y direction, the bottom portion 88A does not extend beyond the upper portion 88B. The +Y direction and the -Y direction extend toward the adjacent gate contact plug 94 (such as Fig.36 and Fig.37 ). Therefore, limiting the extension of the conductive via 88 along the +Y direction and the -Y direction can prevent the conductive via 88 from being electrically shorted with the adjacent gate contact plug 94. On the other hand, extending the size of the conductive via 88 along the +X direction and the -X direction can increase the contact area between the conductive via 88 and the source / drain contact plug 72, and thus achieve the desired reduction in contact resistance. According to some embodiments, in a plan view, along the +Y direction and the -Y direction, the conductive via 88 does not extend beyond the edge 72' of the source / drain contact plug 72.

[0057] According to some embodiments, in plan view, the dimensions of the upper portion 88B are non-elongated, for example, the length L1' and the width W1' are equal to each other, or substantially equal to each other. Throughout the specification, unless otherwise specified, when a first dimension is referred to as being substantially equal to a second dimension, the difference between the first dimension and the second dimension is less than about 5 percent of the first dimension and less than about 5 percent of the second dimension. The bottom portion 88A is elongated, and the length L1 and the width W1 have a ratio L1 / W1 greater than 1.0 and greater than about 1.05. The ratio L1 / W1 can be in the range between about 1.2 and about 2. Fig.19 Also schematically shown are implanted portions 76 ′ of etch stop layer 76 and implanted portions 78 ′ of dielectric layer 78 .

[0058] Fig.33 FIG. 8 is a perspective view of a conductive via 88 and a source / drain contact plug 72. According to some embodiments, the width W of the source / drain contact plug 72 is MD The height H of the through hole 88 is in the range between about 12 nm and about 20 nm. via The aspect ratio of the source / drain contact plug 72 (ie, the ratio H) may be in the range between about 10 nm and about 100 nm. MD / W MD ) may be in the range between about 5 and 30, where H MD is the height of the source / drain contact plug 72. The aspect ratio H of the conductive via 88 is via / L1' may be in the range between about 2 and 15. The ratio H exp / H via can be in the range between about 0.03 and about 0.2, where H exp is the height of the bottom 88A of the through hole.

[0059] Fig. 20A and Fig. 20B A cross-sectional view of a metal line 90 and a dielectric layer 92 is shown. The metal line 90 may include a barrier layer 90A and a metal material 90B. The barrier layer 90A may be formed of Ti, TiN, Ta, TaN, etc., and the metal material 90B may be formed of copper, a copper alloy, etc. The formation of the metal line 90 may adopt a damascene process. The dielectric layer 92 may be an intermetallic dielectric (IMD) and may be formed of a low-k dielectric material.

[0060] Fig.21A and FIG. 21B to FIG. 25A and Fig.25B 1 shows a cross-sectional view of an intermediate stage in the formation of a through hole 88 according to an alternative embodiment of the present invention. Unless otherwise specified, the materials and formation processes of the components in these embodiments are the same as those in Fig.14A and FIG. 14B to FIG. 20A and Fig. 20B Similar components in the aforementioned embodiments shown and indicated by similar reference numerals are substantially the same. Fig.21A and FIG. 21B to FIG. 25A and Fig.25B (as well as Fig.27A and FIG. 27B to FIG. 30A and Fig. 30B ) as shown in the details of the formation process and materials of the components. The initial steps of these embodiments are similar to Figure 1-Figure 6 , Fig. 7A , Figure 7B ,as well as Figure 8-Figure 12 Basically the same as shown.

[0061] Fig.21A and FIG. 21B to FIG. 25A and Fig.25B The embodiment shown is Fig.14A and FIG. 14B to FIG. 20A and Fig. 20B The embodiment shown is similar to that shown, except that the Fig.15A and Fig. 15B The implantation process 87 is shown, so that the bottom 88A of the via hole expands in both the X direction and the Y direction. Fig.21A and Fig. 21B , depositing a dielectric layer 78 and an etch stop layer 76. Then, in a first etching process 83, the dielectric layer 78 and the etch stop layer 76 are etched to expose the source / drain contact plugs 72. The etching is anisotropic. Next, as Fig.22A and Fig. 22B As shown, a second etching process 85 is performed. The first etching process can be Fig.14A and Fig. 14B The first etching process 83 shown is similar or the same as the second etching process 83. Fig.16A and Fig. 16B The second etching process 85 shown is similar or identical to the first etching process 85. Therefore, the details of the first etching process and the second etching process are not repeated here. Since no implantation is performed, there is no implanted portion 76' to prevent the etching of the etch stop layer 76 along the Y direction. Therefore, as shown in FIG. Fig.22A and Fig. 22B As shown, the lower portion 84A extends beyond the edge of the upper portion 84B in both the X-direction and the Y-direction.

[0062] Next, if Fig.23A and Fig. 23B As shown, the opening 84 is filled with a metal material 86, and then a planarization process is performed to remove the excess portion of the metal material 86, as shown in FIG. Fig.24A and Fig. 24B As shown, a through hole 88 is formed. Fig.25A and Fig.25B The formation of dielectric layer 92 and metal line 90 is shown where, for example, a damascene process is used.

[0063] Fig.26 88 is shown in a plan view. According to some embodiments of the present invention, the upper portion 88B of the via 88 has a length L1' and a width W1' that are less than the length L1 and width W1 of the corresponding bottom portion 88A. The width W1 is also equal to, substantially equal to, or less than the width W1 of the underlying source / drain contact plug 72. MD When the width W1 is equal to or substantially equal to the width W of the source / drain contact plug 72 MD When the contact area is maximized, the risk of shorting to the gate contact plug is not increased.

[0064] The length L1 may be equal to or substantially equal to the width W1, and the length L1' may be equal to or substantially equal to the width W1'. Fig.26 As shown, in plan view, the bottom portion 88A may extend beyond the upper portion 88B in all directions. Fig.34 Schematically shows the corresponding Fig.26 88 and source / drain contact plugs 72.

[0065] Fig.27A and FIG. 27B to FIG. 30A and Fig. 30B 88 according to alternative embodiments are shown. These embodiments are similar to the embodiments shown in the previous figures, except that the top of the via 88 is also expanded so that the contact area between the via 88 and the metal line 90 above is also increased. In addition, in some of the illustrated embodiments, the implantation process ( Fig. 15B ), and according to an alternative embodiment, an implantation process may also be performed.

[0066] refer to Fig.27A and Fig.27B , forming an etch stop layer 76 and a dielectric layer 78. In addition, a dielectric layer 79 is formed over the dielectric layer 78. The material of the dielectric layer 79 may have similar properties to the material of the etch stop layer 76, so that when the etch stop layer 76 is etched in the second etching process, the dielectric layer 79 is also etched. The material of the dielectric layer 79 may be selected from the same candidate material group of the etch stop layer 76, and may be the same as or different from the material of the etch stop layer 76.

[0067] Fig.27A and Fig.27B Further shown is a first etching process 83 for forming a via opening 84 that passes through dielectric layer 79, dielectric layer 78, and etch stop layer 76. Next, as shown in FIG. Fig.28A and Fig.28B As shown, the second etching process 85 is performed to expand the portion of the opening 84 in the etching stop layer 76. In addition, since the dielectric layer 79 has similar etching characteristics to the etching stop layer 76, the portion 84C of the opening 84 in the dielectric layer 79 is also laterally expanded. Between the first etching process 83 and the second etching process 85, an implantation process may or may not be performed (see FIG. Fig.15A and Fig. 15B ). When no injection is performed, such as Fig.28B As shown, the opening portion 84C extends laterally along the Y direction. When the implantation is performed, the etch stop layer 76, the dielectric layer 78, and the dielectric layer 79 will have an implanted portion 76', an implanted portion 78', and an implanted portion 79', as shown in FIG. Fig.27BThe injection portion 76', the injection portion 78', and the injection portion 79' will prevent the opening 84 from expanding laterally along the Y direction. The opening 84 obtained in the Y-cut will be similar to Fig.27B shown.

[0068] Next, if Fig.29A and Fig.29B As shown, a metal material 86 is deposited to fill the opening 84, and then a planarization process is performed to remove excess portions of the metal material 86. Fig. 30A and Fig. 30B As shown. Thus, a through hole 88 is formed. The through hole 88 also includes a top portion 88C, and both the bottom portion 88A and the top portion 88C extend laterally beyond the upper portion (also referred to as the middle portion) 88B. According to some embodiments, the lateral extension ratio (L4-L3) / L3 can be in the range between about 0.3 and about 1.2, wherein the length L3 is the top length of the middle portion 88B, and the length L4 is the top length of the top portion 88C. Fig. 30A and Fig. 30B Also shown is the formation of dielectric layer 92 and metal lines 90 , where, for example, a damascene process is used.

[0069] Fig.31 A plan view of via 88 is shown when no implantation is performed between the first and second etching processes. Fig.31 It is schematically shown that both top portion 88C and bottom portion 88A extend laterally beyond the edge of middle portion 88B in all lateral directions when no implantation is performed. A top view of bottom portion 88A, middle portion 88B, and top portion 88C may be circular with a length equal to the corresponding width.

[0070] Fig.32 The implantation is performed between the first etching process and the second etching process (eg Fig.15A and Fig. 15B 88 as shown). Fig.32 It is schematically shown that both the top portion 88C and the bottom portion 88A extend beyond the respective edges of the middle portion 88B in the X direction and do not extend in the Y direction. Fig.35 Schematically shows Fig.32 88 and a perspective view of the source / drain contact plugs 72 corresponding to the through-hole 88 shown in FIG.

[0071] Fig.36 and Fig.37 Schematically illustrates a gate contact plug 94 and its relationship to the via 88 and other features according to some embodiments. Fig.36 As shown, an ILD 96 is formed over the ILD 60, and the source / drain contact plugs 72 pass through the ILD 60 and the ILD 96. According to an alternative embodiment, as shown in FIG. Fig.37As shown, source / drain contact plugs 72 are formed in ILD 60, and as shown in FIG. Fig.36 The ILD 96 shown is not formed on Fig.37 middle.

[0072] Embodiments of the present invention have some advantageous features. By extending the bottom of the via, the contact area between the via and the conductive component below, such as the source / drain contact plug, can be increased, and thus the contact resistance is reduced. By extending the top of the via, the contact area between the via and the conductive component above, such as the metal line, can be increased to reduce the contact resistance. The effect of reducing the contact resistance is very obvious in vias with a length and width of less than 10nm.

[0073] According to some embodiments of the present invention, a structure includes: a transistor, the transistor including a first source / drain region; a source / drain contact plug, the source / drain contact plug is located above the first source / drain region and electrically connected to the first source / drain region; and a through hole, the through hole is located above the source / drain contact plug and contacts the source / drain contact plug; the through hole includes: a bottom, the bottom has a first length; and an upper portion, the upper portion has a second length, wherein the first length is greater than the second length, and the first length and the second length are measured along a first direction parallel to the top surface of the source / drain contact plug. In one embodiment, the transistor also includes: a gate stack; and a second source / drain region; wherein the first source / drain region and the second source / drain region are located on opposite sides of the gate stack, and the first direction is perpendicular to a direction pointing from the first source / drain region to the second source / drain region. In one embodiment, the bottom has a first width, the upper portion has a second width less than the first width, and the first width and the second width are measured along a second direction perpendicular to the first direction. In one embodiment, the bottom portion has a first width, the upper portion has a second width substantially equal to the first width, and the first width and the second width are measured along a second direction perpendicular to the first direction. In one embodiment, the structure further comprises: an etch stop layer, wherein the bottom of the via is located in the etch stop layer; and a dielectric layer, the dielectric layer being located above the etch stop layer, wherein the upper portion of the via is located in the dielectric layer. In one embodiment, the via further comprises a top portion, the top portion extending laterally beyond the upper portion, and wherein the length of the via from the upper portion to the top portion changes abruptly. In one embodiment, the structure further comprises: an etch stop layer, wherein the bottom portion is located in the etch stop layer; a first dielectric layer, the first dielectric layer being located above the etch stop layer, wherein the upper portion is located in the first dielectric layer; and a second dielectric layer, the second dielectric layer being located above the first dielectric layer, wherein the top portion is located in the second dielectric layer. In one embodiment, the upper portion has substantially straight and vertical sidewalls, and the bottom portion extends laterally beyond the substantially straight and vertical sidewalls.

[0074] According to some embodiments of the present invention, a structure includes: a first conductive component, wherein, in a plan view, the first conductive component has a first length along a first direction, and a first width along a second direction perpendicular to the first direction, and the first width is less than the first length; and a conductive via, the conductive via being located above the first conductive component and contacting the first conductive component; wherein the conductive via includes: a bottom, wherein the bottom is elongated, has a second length measured along the first direction, and a second width measured along the second direction, the second width is less than the second length; and an upper portion, the upper portion being located above the bottom portion and connected to the bottom portion, wherein the upper portion has a third length measured along the first direction, and a third width measured along the second direction, the third length being substantially equal to the third width. In one embodiment, the bottom portion and the upper portion of the conductive via include the same homogeneous material. In one embodiment, the upper portion has straight sidewalls. In one embodiment, the second length is greater than the third length by a difference, and the ratio of the difference to the first length is in a range between about 0.2 and about 0.5. In one embodiment, the structure further comprises: an etch stop layer, wherein the bottom portion is located in the etch stop layer; and a dielectric layer, the dielectric layer being located above the etch stop layer, wherein the upper portion is located in the dielectric layer. In one embodiment, the conductive via further comprises a top portion, the top portion being located above the upper portion and connected to the upper portion, wherein the top portion is elongated in plan view.

[0075] According to some embodiments of the present invention, a method includes: depositing a first dielectric layer over a first conductive component; depositing a second dielectric layer over the first dielectric layer; performing a first etching process to etch through the first dielectric layer and the second dielectric layer and form an opening, wherein the opening includes: a bottom portion, the bottom portion is located in the first dielectric layer; and an upper portion, the upper portion is located in the second dielectric layer; performing a second etching process to extend the bottom portion beyond the edge of the upper portion; and filling a conductive material into the opening to form the second conductive component. In one embodiment, the first etching process includes an anisotropic etching process, and the second etching process includes an isotropic etching process. In one embodiment, in the second etching process, the bottom of the opening extends along all directions parallel to the main top surface of the first dielectric layer. In one embodiment, in the second etching process, the bottom of the opening extends along a first direction and does not extend along a second direction perpendicular to the first direction, wherein the first direction and the second direction are parallel to the main top surface of the first dielectric layer. In one embodiment, the method further includes performing a tilted implantation after the first etching process and before the second etching process to implant sidewall portions of the first dielectric layer and the second dielectric layer, wherein the sidewall portions face the opening. In one embodiment, the sidewall portion is not substantially etched during the second etching process.

[0076] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: a transistor including a first source / drain region; a source / drain contact plug, located above the first source / drain region and electrically connected to the first source / drain region; as well as A through hole is located above the source / drain contact plug and contacts the source / drain contact plug, the through hole comprising: a base having a first length; and an upper portion having a second length, wherein the first length is greater than the second length, and the first length and the second length are measured along a first direction parallel to a top surface of the source / drain contact plug; An etch stop layer, wherein the bottom of the through hole is located in the etch stop layer; wherein a portion of the through hole is in contact with an implanted portion of the etch stop layer.

2. The semiconductor structure according to claim 1, wherein: The transistor further comprises: a gate stack; and A second source / drain region, wherein the first source / drain region and the second source / drain region are located on opposite sides of the gate stack, and the first direction is perpendicular to a direction pointing from the first source / drain region to the second source / drain region.

3. The semiconductor structure according to claim 1, wherein: The bottom portion has a first width, the upper portion has a second width smaller than the first width, and the first width and the second width are measured along a second direction perpendicular to the first direction.

4. The semiconductor structure according to claim 1, wherein: The bottom portion has a first width, the top portion has a second width substantially equal to the first width, and the first width and the second width are measured along a second direction perpendicular to the first direction.

5. The semiconductor structure according to claim 1, further comprising: A dielectric layer is located above the etch stop layer, wherein the upper portion of the through hole is located in the dielectric layer.

6. The semiconductor structure according to claim 1, wherein: The through hole further includes a top portion extending laterally beyond the upper portion, and wherein a length of the through hole from the upper portion to the top portion changes abruptly.

7. The semiconductor structure according to claim 6, further comprising: a first dielectric layer located above the etch stop layer, wherein the upper portion is located in the first dielectric layer; and A second dielectric layer is located above the first dielectric layer, wherein the top portion is located in the second dielectric layer.

8. The semiconductor structure according to claim 1, wherein: The upper portion has substantially straight and vertical side walls, and the bottom portion extends laterally beyond the substantially straight and vertical side walls.

9. A semiconductor structure comprising: a first conductive component, wherein, in a plan view, the first conductive component has a first length along a first direction, and a first width along a second direction perpendicular to the first direction, and the first width is smaller than the first length; and a conductive via located above the first conductive component and in contact with the first conductive component, wherein the conductive via comprises: a base, wherein the base is elongated and has a second length measured along the first direction, and a second width measured along the second direction, the second width being smaller than the second length; and an upper portion located above the bottom portion and connected to the bottom portion, wherein the upper portion has a third length measured along the first direction and a third width measured along the second direction, the third length being substantially equal to the third width; An etch stop layer, wherein the bottom portion is located in the etch stop layer; wherein a portion of the conductive via is in contact with an implanted portion of the etch stop layer.

10. The semiconductor structure according to claim 9, wherein: The bottom portion and the upper portion of the conductive via include the same homogeneous material.

11. The semiconductor structure according to claim 9, wherein: The upper portion has straight side walls.

12. The semiconductor structure according to claim 9, wherein: The second length is greater than the third length by a difference, and a ratio of the difference to the first length is in a range between about 0.2 and about 0.

5.

13. The semiconductor structure of claim 9, further comprising: A dielectric layer is located above the etch stop layer, wherein the upper portion is located in the dielectric layer.

14. The semiconductor structure according to claim 13, wherein: The conductive via further includes a top portion located above the upper portion and connected to the upper portion, wherein the top portion is elongated in the plan view.

15. A method of forming a semiconductor structure, comprising: depositing a first dielectric layer over the first conductive feature; depositing a second dielectric layer over the first dielectric layer; Performing a first etching process to etch through the first dielectric layer and the second dielectric layer and form an opening, wherein the opening comprises: a bottom portion located in the first dielectric layer; and an upper portion, located in the second dielectric layer; Performing a second etching process to extend the bottom portion beyond the edge of the upper portion; and filling a conductive material into the opening to form a second conductive member; Wherein, in the second etching process, the bottom of the opening expands along a first direction and does not expand along a second direction perpendicular to the first direction, wherein the first direction and the second direction are parallel to the main top surface of the first dielectric layer.

16. The method according to claim 15, wherein: The first etching process includes an anisotropic etching process, and the second etching process includes an isotropic etching process.

17. The method according to claim 15, wherein: The first dielectric layer is located above an etch stop layer, wherein in the second etching process, an expansion of the bottom of the opening along the second direction parallel to the main top surface of the first dielectric layer is prevented by an implanted portion of the etch stop layer.

18. The method according to claim 15, wherein: The second dielectric layer is formed of silicon nitride.

19. The method according to claim 15, further comprising: After the first etching process and before the second etching process, an inclined implantation is performed to implant sidewall portions of the first dielectric layer and the second dielectric layer, wherein the sidewall portions face the opening.

20. The method according to claim 19, wherein: The sidewall portion is substantially not etched in the second etching process.

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