Air spacer structure

Abstract

The present disclosure relates generally to semiconductor structures, and more particularly to air spacer structures and methods of manufacturing the same. The structure includes: a plurality of gate structures including active regions; contacts extending to the active regions; a plurality of anchor structures located between the active regions; and air spacer structures adjacent to the contacts.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor structures and, more particularly, to air spacer structures and methods of fabricating. Background Art

[0002] As semiconductor processes continue to scale down (e.g., shrink), the desired spacing (i.e., pitch) between features is also getting smaller. As a result, it becomes increasingly difficult to manufacture features in smaller technology nodes due to critical dimension (CD) scaling and process capabilities.

[0003] In radio frequency (RF) applications, device performance is limited by gate-to-source / drain (S / D) parasitic capacitance. This is because high-frequency performance metrics of RF transistors (e.g., Ft and Fmax) are closely related to the gate structure to S / D contact capacitance (i.e., gate-to-drain capacitance (C gd ) and the gate-to-source capacitance (C gs The gate-to-S / D parasitic capacitance may come from: (i) the spacer material of the gate structure; and (ii) the relatively low-quality oxide flowing chemical vapor deposition (FCVD) between the metal stack of the gate structure and the metal fill of the S / D contacts.

[0004] Conventional devices that attempt to address gate to S / D parasitic capacitance involve a self-aligned contact (SAC) integration flow. However, the SAC flow is not necessarily the integration of choice for technology nodes with relatively large contact pitches (CPP) because the space between the gate structures is large enough that trench contacts can be reliably formed using only patterning and etching processes. Thus, the requirement to self-align the trench contacts with the gate structures is bypassed. Examples of such relaxed CPP devices can be found in RF technology, where the space between adjacent gate structures remains large enough that a SAC integration flow is not required. For RF devices, the trench contacts are etched directly into low-quality FCVD oxide. However, most proposed air gap spacer integrations are derived from the SAC flow and are not necessarily compatible with relaxed CPP integration. The present invention provides a solution to this problem. Summary of the invention

[0005] In one aspect of the disclosure, a structure includes: a plurality of gate structures including active regions; contacts extending to the active regions; a plurality of anchor structures located between the active regions; and air spacer structures adjacent to the contacts.

[0006] In one aspect of the present disclosure, a structure includes: a plurality of gate structures including source and drain (S / D) regions; contacts extending to the S / D regions; a plurality of anchor structures located between the S / D regions; and air spacer structures adjacent to the contacts and the anchor structures.

[0007] In one aspect of the present disclosure, a method includes: forming at least one gate structure; forming a plurality of active regions adjacent to the at least one gate structure; forming a double liner that seals the at least one gate structure and the active regions; depositing an insulator material over the double liner; forming a plurality of anchor structures between the active regions; forming a plurality of contacts that are electrically in contact with the active regions; etching at least one liner in the double liner; etching selected portions of the insulator material to form at least one air gap; and depositing a second liner within the air gap to form an air spacer structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the following detailed description, the present disclosure is described by way of non-limiting examples of exemplary embodiments of the present disclosure with reference to the several accompanying drawings mentioned.

[0009] Figures 1A to 1C A dummy gate structure and corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0010] Figure 2A and 2B Bottom and top contact etch stop liners (CESLs) and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0011] Figure 3A and 3B An anchoring structure and corresponding manufacturing process according to, among other features, aspects of the present disclosure are shown.

[0012] Figure 4A and 4B A replacement gate structure and corresponding fabrication process are shown, among other features, in accordance with aspects of the present disclosure.

[0013] Figure 5A and 5B An air gap capping layer and corresponding manufacturing process are shown, among other features, according to aspects of the present disclosure.

[0014] Fig. 6A and 6B Source / drain (S / D) metallization features and corresponding fabrication processes are shown, among other features, in accordance with aspects of the present disclosure.

[0015] Fig. 7A and7B An air gap and corresponding manufacturing process are shown, among other features, in accordance with aspects of the present disclosure.

[0016] Fig. 8A and 8B An air spacer structure and corresponding manufacturing process are shown, among other features, according to aspects of the present disclosure.

[0017] Figures 9A to 10B Alternative structures and corresponding manufacturing processes according to aspects of the present disclosure are shown. DETAILED DESCRIPTION

[0018] The present disclosure relates generally to semiconductor structures, and more specifically to air spacer structures and methods of manufacturing. In an embodiment, the methods and structures provided herein use liners and anchors to form an air gap of an air spacer structure between a gate structure and a source / drain (S / D) contact. Advantageously, by forming an air spacer structure, gate-to-S / D parasitic capacitance can be reduced due to the low-k nature of air, thereby improving radio frequency (RF) device performance.

[0019] The methods and structures described herein allow the dielectric constant of the spacer between the gate structure and the S / D contacts to be designed in a specific way to reduce the gate-to-S / D parasitic capacitance to the target value required for RF technology, i.e., to reduce the gate-to-drain capacitance (C gd ) and the gate-to-source capacitance (C gs In an embodiment, forming a relatively large air spacer structure allows achieving these RF target values, such as Ft and Fmax of the RF transistor, because Ft and Fmax are related to the capacitance of the gate structure to the S / D contact (i.e., C gd and C gs ) is inversely proportional to the value of ). In further embodiments, the methods and structures described herein are compatible with non-self-aligned contact (SAC) processes and can be applied to any contact pitch (CPP) that is critical to RF FinFETs. In this way, the structures and methods described herein improve the overall performance of RF devices at any CPP.

[0020] A method includes forming a dual (bottom liner and top liner) contact etch stop liner (CESL) to encapsulate the gate structure of the device. An anchor structure is formed between the active regions (i.e., S / D regions) of the device, and an interlayer dielectric cap is formed on top of the CESL liner from the same material as the anchor structure. The method also includes selective etching to etch the top liner of the dual CESL liner to access the interlayer dielectric. The interlayer dielectric is selectively etched to remove the interlayer dielectric between the gate structure and the S / D contacts, thereby forming an air gap. A relatively large air spacer structure is formed from the air gap by depositing a conformal low-k liner within the air gap.

[0021] A structure includes an air spacer structure having a relatively large air gap between the spacer of the gate structure and the S / D contact. The structure has no air gap in the spacer of the gate structure. In addition, the air gap cap contacts the S / D contact and the spacer of the gate structure. In an embodiment, the structure includes a single air gap or a double air gap sealed between a dielectric post of an anchoring structure, an S / D region, and the S / D contact. In addition, the S / D contact is anchored by a dielectric post of an anchoring structure, wherein the anchoring structure is located between the active regions.

[0022] The structures disclosed herein can be manufactured in a variety of ways using a variety of different tools. However, in general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods (i.e., techniques) for manufacturing the structures disclosed herein have been adopted based on integrated circuit (IC) technology. For example, these structures are built on wafers and implemented in a film of material patterned on top of the wafer by photolithography. Specifically, the manufacture of the structure uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film to the mask.

[0023] Figures 1A to 1C The access structure and the corresponding manufacturing process according to aspects of the present disclosure are shown. Specifically, Figure 1A shows a top view of the structure 100, Figure 1B The structure 100 is shown along the X-axis, Figure 1C The structure 100 is shown along the Y-axis. Figures 1A to 1C The structure 100 includes a fin structure 110 formed of a suitable semiconductor material 105. For example, the fin structure 110 may be formed of any suitable semiconductor material 105, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, etc.

[0024] The fin structure 110 may be manufactured using a sidewall image transfer (SIT) technique. In an example of the SIT technique, a mandrel material (e.g., SiO2) is deposited on a substrate using a conventional chemical vapor deposition (CVD) process. A resist is formed on the mandrel material and exposed to light to form a pattern (opening). Reactive ion etching (RIE) is performed through the opening to form the mandrel. In an embodiment, the mandrel may have different widths and / or spacings depending on the desired size of the fin structure. Spacers are formed on the sidewalls of the mandrel, the material of the spacer preferably being different from the mandrel, and are formed using conventional deposition processes known to those skilled in the art. The width of the spacer may, for example, match the size of the fin structure. The mandrel is removed or stripped using a conventional etching process that is selective to the mandrel material. Etching is then performed within the spacing of the spacer to form a sub-lithographic feature, such as a fin structure. The sidewall spacer may then be stripped.

[0025] Still refer to Figures 1A to 1C , the gate structure 120 is formed on the fin structure 110 and the shallow trench isolation (STI) region 115. The STI region 115 can be formed by conventional etching and deposition processes, followed by a planarization process (e.g., chemical mechanical planarization (CMP)). In an embodiment, the gate structure 120 is composed of a dummy gate material 125 (e.g., amorphous Si (α-Si)) and a cap layer 130. The cap layer 130 can be formed of any suitable hard mask material (e.g., SiN and other examples).

[0026] The dummy gate material 125 and the cap layer 130 are deposited by CVD and then subjected to conventional patterning steps. The gate structure 120 also includes sidewall spacers 135 (e.g., low-k dielectrics) that can be deposited on the sidewalls of the patterned materials 125, 130. The sidewall spacers 135 can be deposited by conventional chemical vapor deposition (CVD) processes and then subjected to patterning processes (e.g., anisotropic etching processes) to remove any material from the horizontal surfaces of the structure 100.

[0027] Source and drain (S / D) regions 140 are formed on the sides of the gate structure 120 (e.g., the sides of the sidewall spacers 135) on the fin structure 110 using, for example, any conventional method. For example, the S / D regions 140 may be raised S / D regions formed by doping epitaxial growth of materials on the surface of the fin structure 110, which are located in the openings between the gate structures 120. In other embodiments, the S / D regions 140 may be formed by ion implantation processes, doping processes, or diffusion processes known to those skilled in the art, and therefore no further explanation is required to understand the present disclosure.

[0028] Figure 2A and 2BA double contact etch stop liner (CESL) 145 is shown deposited over the gate structure 120 and the S / D region 140. In an embodiment, the double CESL liner 145 may include a bottom liner 150 and a top liner 155. In this way, the etch stop liner is a double etch stop liner, i.e., a double CESL liner 145, which includes a bottom liner 150 and a top liner 155. The bottom liner 150 may be composed of any suitable low-k material (e.g., SiBCN). In further embodiments, the bottom liner 150 may be composed of the same low-k material as the sidewall spacer 135. The top liner 155 may also be composed of a low-k material (e.g., SiN). Therefore, the bottom liner and the top liner are composed of low-k materials. The bottom liner 150 and the top liner 155 may be deposited by an ALD or CVD process.

[0029] The bottom liner 150 and the top liner 155 may each have a thickness in the range of 2 nm to 5 nm. In this way, the dual CESL liner 145 may be formed to have a thickness in the range of about 4 nm to 10 nm; however, other dimensions are also contemplated herein. An interlayer dielectric (ILD) 160 is deposited over the S / D regions 140 and the dual CESL liner 145. The ILD 160 may be deposited by a CVD process and, for example, may be composed of an oxide. After deposition, the ILD 160 is planarized to the level of the cap layer 130 by a CMP process, thereby removing the dual CESL liner 145 directly above the cap layer 130.

[0030] Figure 3A and 3B An anchor structure 165 is shown formed between active regions of the device. In an embodiment, an organic planarization layer (OPL) is applied by a spin coating process to blanket deposit the OPL material on the top surface of the ILD 160 and the top surface of the cap layer 130. A selective etching process (e.g., RIE) patterns the ILD 160 to form trenches in the ILD 160. The OPL material is etched away by a conventional etching process (e.g., an oxygen ashing process).

[0031] An anchor structure 165 is formed in the trench of the ILD 160 between the active regions (i.e., S / D regions 140) and above the double CESL liner 145 by depositing a filling material 170 in the trench using an ALD or CVD process. In this way, the structure includes an etch stop liner, i.e., the double CESL liner 145, below the anchor structure 165. In an embodiment, the filling material 170 may be composed of SiC and may be polished by a CMP process, which stops on the ILD 160 due to the selectivity between the filling material 170 and the ILD 160.

[0032] In an embodiment, the anchor structure 165 prevents the structure 100 from collapsing during subsequent etching of the bottom liner 150, the top liner 155, and / or the ILD 160. After forming the anchor structure 165, the cap layer 130 is etched (removed) using conventional etching techniques (e.g., RIE process). In this way, the dummy gate material 125 is exposed. In an alternative embodiment, the anchor structure 165 can be formed after forming the replacement gate structure.

[0033] Figure 4A and 4B A replacement gate structure 175 is shown formed over the fin structure 110. In an embodiment, the dummy gate material 125 is removed by conventional etching techniques (e.g., RIE process). In this manner, the gate structure 175 includes the sidewall spacers 135 and an etch stop liner adjacent to the sidewall spacers 135, i.e., the double CESL liner 145. The replacement gate structure 175 includes a gate stack 180, which includes a dielectric material and a gate metal.

[0034] The gate dielectric material may be, for example, a high-k gate dielectric material, such as a hafnium-based dielectric. In an embodiment, the high-k dielectric material may include, but is not limited to, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations including multiple layers of the above materials. Depending on the specific application and design parameters, the gate metal of the gate stack 180 may include any metal or any combination of metals, such as TiN, TiC, tungsten (W). The gate cap 185 is deposited over the gate stack 180. In an embodiment, the gate stack 180 and the gate cap 185 may be deposited between the sidewall spacers 135 using a CVD process, followed by a CMP process.

[0035] Figure 5A and 5B An air gap cap 190 is shown deposited over the ILD 160 and the anchoring structure 165. In an embodiment, the ILD 160 is recessed by a selective RIE process to form a trench before depositing the air gap cap 190. The trench is filled with a material 195, which is deposited by a CVD process and then subjected to a CMP process, to form the air gap cap 190. In an embodiment, the material 195 is the same as the filling material 170 of the anchoring structure 165, i.e., SiC. In this way, the cap (i.e., the air gap cap 190) is composed of the same material as the anchoring structure 165.

[0036] Fig. 6A and 6BThe S / D contacts 200 and other features are shown. In an embodiment, a trench is formed in the ILD 160 using conventional photolithography and etching techniques (e.g., RIE process). In an embodiment, the trench formation can be a maskless process due to the materials implemented. The etch exposes the dual CESL liner 145 over the S / D region 140 so that the S / D region 140 can be subsequently etched by a selective chemical process.

[0037] In an embodiment, a trench is formed by selectively etching the air gap cap 190 and the ILD 160 using a RIE process, thereby exposing the dual CESL liner 145. The dual CESL liner 145 is then etched from the top surface of the S / D region 140, thereby exposing the S / D region 140. The removal of the dual CESL liner 145 can be a maskless process performed by wet etching or dry etching, which, for example, uses a chemical process to remove the material of the liner 150, 155 (e.g., selective to the remaining materials). The S / D contact 200 will be formed to contact the exposed portion of the S / D region 140. More specifically, the metal material 205 of the S / D contact 200 will directly contact the S / D region 140.

[0038] The silicide liner is deposited in the trench above the S / D region 140 and then subjected to silicide processing. It will be appreciated by those skilled in the art that the silicide processing begins with the deposition of a thin transition metal layer (e.g., nickel, cobalt, or titanium) on top of a fully formed and patterned semiconductor device (e.g., S / D region 140). After the material is deposited, the structure is heated so that the transition metal reacts with the exposed silicon (or other semiconductor materials described herein) in the active regions (e.g., source regions, drain regions, gate contact regions) of the semiconductor device to form a low resistance transition metal silicide. After the reaction occurs, any residual transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device. It will be appreciated by those skilled in the art that when the gate structure is composed of a metal material, no silicide contacts are required on the device.

[0039] The self-aligned silicide liner can be deposited using a physical vapor deposition (PVD) or CVD process. After the silicide treatment, a metal material 205 is deposited on the transition metal silicide to form an S / D contact 200. The S / D contact 200 is formed to contact the exposed portion of the S / D region 140. More specifically, the metal material 205 of the S / D contact 200 directly contacts the S / D region 140. The metal material 205 can be composed of, for example, cobalt (Co) or tungsten (W) or ruthenium (Ru).

[0040] After depositing the metal material 205, a CMP process is performed on the material of the gate cap 185. In this way, the formation of the S / D contact 200 is a non-self-aligned contact (SAC) process. In an embodiment, the S / D contact 200 is anchored by the anchor structure 165, thereby providing further stability to the S / D contact 200 during subsequent etching processes. Specifically, the contact 200 is anchored into the anchor structure 165.

[0041] Fig. 7A and 7B An air gap 210 is shown formed by removing selected portions of the top liner 155 and the ILD 160 of the dual CESL liner 145. In an embodiment, the removal of the top liner 155 is a maskless process performed by vapor etching, for example, using a selective chemical process to remove the material of the top liner 155 (selective to the SiO2 material of the ILD 160, the SiC material of the anchor structure 165, and the low-k material SiBCN of the bottom liner 150).

[0042] The SiO2 material of the ILD 160 is removed using a selective etch (e.g., vapor phase etch) that is selective to the SiC material of the anchor structure 165 and the low-k material SiBCN of the bottom liner 150. Specifically, a selected portion of the ILD 160 located between the replacement gate structure 175 and the S / D contact 200 is etched away while other portions of the ILD 160 are retained. In this way, an air gap 210 is formed between the replacement gate structure 175 and the S / D contact 200, while the bottom liner 150 of the double CESL liner 145 remains intact. In an embodiment, a portion of the top liner 155 and a portion of the bottom liner 150 are both covered by the anchor structure 165 and thus remain located below the anchor structure 165. In this way, the etch stop liner (i.e., the double CESL liner 145) extends below the anchor structure 165.

[0043] In an embodiment, the dielectric pillars of the anchoring structure 165 provide stability to the structure 100 by anchoring the S / D contacts 200 in the anchoring structure, thereby preventing the device layer from collapsing. Thus, when selected portions of the ILD 160 are removed, the structure 100 does not collapse due to the weight of the S / D contacts 200.

[0044] Fig. 8A and 8B The formation of an air spacer structure 220 (i.e., a single air gap structure or a double air gap structure) is shown. Thus, the structure and method described herein include: a plurality of gate structures 175 including active regions (i.e., S / D regions 140); and contacts 205 extending to the active regions. In addition, the structure includes a plurality of anchor structures 165 located between the active regions, and air spacer structures 220 adjacent to the contacts 205.

[0045] The air spacer structure 220 is formed by depositing a low-k liner 215 on the sidewalls of the air gap 210 to form the air spacer structure 220, and then performing an isotropic etch-back process. In this way, the air spacer structure 220 includes a liner (i.e., a low-k liner 215) and an air gap 210. For example, the low-k liner 215 can be composed of any suitable low-k material (e.g., SiBCN) deposited by CVD. In an embodiment, the deposition of the low-k liner 215 seals the air gap 210 to form the air spacer structure 220. Therefore, the air spacer structure 220 includes an air gap 210 located between the gate structure 175 and the contact 200. In an embodiment, the low-k liner 215 lines the anchor structure 165, and the air gap cap 190 is located above the air spacer structure 220.

[0046] The low-k nature of the air contained in the air spacer structures 220 allows for reduced gate to S / D parasitic capacitance, thereby improving RF device performance. In addition, the air gap cap 190 above the air spacer structures 220 allows for making the air spacer structures 220 more complete. In this manner, the structure includes a plurality of gate structures 175 including source and drain (S / D) regions 140, wherein the contacts 200 extend to the S / D regions 140. In addition, a plurality of anchor structures 165 are located between the S / D regions 140, wherein the air spacer structures 220 are adjacent to the contacts 205 and the anchor structures 165.

[0047] The methods and structures described herein allow the dielectric constant of the spacer structure between the replacement gate structure 175 and the S / D contact 200 to be designed to reduce the gate-to-S / D parasitic capacitance to a target value required for RF technology, i.e., to reduce the gate-to-drain capacitance (C gd ) and the gate-to-source capacitance (C gs In an embodiment, forming a relatively large air spacer structure 220 allows these RF target values ​​(e.g., Ft and Fmax of the RF transistor) to be achieved because Ft and Fmax are proportional to the capacitance C of the gate structure to the S / D contact. gd and C gs The value of is inversely proportional to . Further, the methods and structures described herein are compatible with non-self-aligned contact (SAC) processes and can be applied to any contact pitch (CPP) that is critical to, for example, RF FinFETs. In this way, the structures and methods described herein improve the overall performance of RF devices at any CPP.

[0048] The structures and methods described herein are generally compatible with processes of record integration flows and relatively large CPPs. In addition, the structures and methods described herein address gate-to-S / D parasitic capacitance caused by flow chemical vapor deposition (FCVD) of relatively low-quality oxides between the gate stack 180 and gate cap 185 of the replacement gate structure 175 and the metal material 205 of the S / D contact 200. By removing these low-quality FCVD oxides of RF devices with relaxed CPPs and forming air gaps instead, parasitic capacitance can be significantly reduced and overall RF performance improved. In addition, the structures and methods described herein are not limited to forming only small air gaps within the sidewall spacers 135 of the replacement gate structure 175; rather, the structures and methods described herein allow for relatively large air spacer structures 220 adjacent to the sidewall spacers 135 of the replacement gate structure 175.

[0049] Figures 9A to 10B An alternative structure according to aspects of the present disclosure is shown. Figures 1A to 8B Similar to the process described in, Fig.9A and 9B In addition to removing Fig. 7A and 7B In addition to the top liner 155 shown, the bottom liner 150 and the sidewall spacers 135 of the replacement gate structure 175 are removed. Therefore, the air gap 210a is larger than Fig. 7A and 7B In this way, due to the increased size of the air gap 210 generated by removing the bottom liner 150 and the sidewall spacer 135, Fig. 8A and 8B Compared with the air spacer structure 220, Fig. 10A and Fig. 10B The air spacer structure 220a is shown to be relatively large. In this manner, the method described herein includes forming at least one gate structure 175 and forming a plurality of active regions (i.e., S / D regions 140) adjacent to the at least one gate structure 175. In addition, the method includes forming a dual liner (i.e., dual CESL liner 145) that seals the at least one gate structure and the active regions, and depositing an insulator material (i.e., ILD 160) over the dual liner.

[0050] In addition, the method includes forming a plurality of anchor structures 165 between the active regions and forming a plurality of contacts 200 that are electrically contacted with the active regions. In an embodiment, the method ends by etching at least one liner of the dual liner (i.e., the bottom liner 150 or the top liner 155), etching a selected portion of the insulator material to form at least one air gap 210, and depositing a second liner (i.e., low-k liner 215) within the air gap 210 to form an air spacer structure. In a further embodiment, the at least one liner etched is the top liner 155 of the dual liner.

[0051] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0052] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the various embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure comprising: A plurality of gate structures are disposed above the active region; a contact extending to the active region; a plurality of anchoring structures for anchoring the contacts and located only between the active regions in the extension direction of the gate structure, wherein the upper surfaces of the anchoring structures are lower than the upper surfaces of the contacts and the gate structure; and an air spacer structure adjacent to the contact, wherein the air spacer structure comprises an air gap and a liner on a sidewall of the air gap for sealing the air gap, Wherein, the air gap is partially located between the anchor structure and the active region in the extension direction of the gate structure.

2. The semiconductor structure of claim 1, wherein the liner is a low-k liner.

3. The semiconductor structure of claim 2, wherein the low-k liner lines the anchor structure. 4 . The semiconductor structure of claim 1 , further comprising an etch stop liner beneath the anchor structure. 5 . The semiconductor structure of claim 4 , wherein the etch stop liner is a double etch stop liner including a bottom liner and a top liner.

6. The semiconductor structure of claim 5, wherein the bottom liner and the top liner are composed of a low-k material.

7. The semiconductor structure of claim 1, further comprising a cap located over the air spacer structure.

8. The semiconductor structure of claim 7, wherein the cap is made of the same material as the anchor structure.

9. A semiconductor structure comprising: a plurality of gate structures disposed on the source and drain S / D regions, wherein the S / D regions are disposed on the sides of the gate structures; a contact extending to the S / D region; a plurality of anchoring structures for anchoring the contacts and located only between the S / D regions in the extension direction of the gate structure, wherein the upper surfaces of the anchoring structures are lower than the upper surfaces of the contacts and the gate structure; as well as an air spacer structure adjacent to the contacting and anchoring structures, wherein the air spacer structure comprises a liner and an air gap contacting the liner, Wherein, the air gap is partially located between the anchor structure and the S / D region in the extension direction of the gate structure.

10. The semiconductor structure of claim 9, wherein the air gap is located between the gate structure and the contact. The semiconductor structure of claim 9 , wherein the liner is a low-k liner.

12. The semiconductor structure of claim 10, wherein the gate structure comprises a sidewall spacer and an etch stop liner adjacent to the sidewall spacer.

13. The semiconductor structure of claim 12, wherein the etch stop liner extends below the anchor structure.

14. The semiconductor structure of claim 13, wherein the etch stop liner is a double etch stop liner including a bottom liner and a top liner.

15. A method for manufacturing a semiconductor structure, comprising: forming at least one gate structure; forming a plurality of active regions adjacent to the at least one gate structure; forming a double liner encapsulating the at least one gate structure and the active area; depositing an insulator material over the dual liner; forming a plurality of anchor structures between the active regions only in the extension direction of the gate structure, the anchor structures anchoring a plurality of contacts electrically contacting the active regions; forming the plurality of contacts; etching at least one of the dual liners; etching portions of the insulator material adjacent the anchor structure and the contact to form at least one air gap; as well as depositing a second liner for sealing the at least one air gap on a sidewall of the at least one air gap to form an air spacer structure, wherein the air spacer structure comprises the at least one air gap and the second liner, Wherein, an upper surface of the anchoring structure is lower than an upper surface of the contact and the at least one gate structure, and wherein the at least one air gap is partially located between the anchoring structure and the active region in the extension direction of the gate structure.

16. The method of claim 15, wherein etching the at least one liner comprises etching a top liner of the dual liner.

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